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synchronous buck controller with constant on - time and valley current mode data sheet ADP1874 / adp1875 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringement s of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered tr ademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 C 2012 analog devices, inc. all rights reserved. features power input voltage range: 2.9 5 v to 20 v on - board bias regulator minimum output voltage : 0.6 v 0.6 v reference voltage with 1.0% a ccuracy suppo rts all n - channel mosfet power s tage s available in 300 k hz, 600 k hz , and 1.0 mhz options no current - se nse resistor required power saving mode (psm) for light loads ( adp1875 only) resistor programmable current l imit power g ood with internal pull - up resistor externally p rogrammable soft start thermal overload pr otection s hort - circuit protection stand alone p recision enable input integrated boot strap diode for high - side drive starts into a pre charged output available in a 16 - lead qsop package applications telecom and networking systems mid - t o high - end servers set - top boxes dsp core power supplies general description the ADP1874 / adp1875 are versatile current mode, synchronous step - down controllers . they provide superior tra nsient response, optimal stability, and current - limit protection by using a constant on - time, pseudo fixed frequency with a programmable current limit , current control scheme. in addition, these devices offer optimum performance at low duty cycles by u sing a valley, current mode control architecture. this allows the ADP1874 / adp1875 to drive all n - channel power stages to regulate output voltages to as low as 0.6 v. the adp1875 is the power saving mode (psm) version of the device and is capable of pulse skipping to maintain output regulation while achieving improved system efficiency at light loads (see the adp1875 power saving mode ( psm ) section for more information). available in three frequency options (300 khz, 600 khz, and 1.0 mhz, plus the psm option), the ADP1874 / adp1875 are well suited for a wide range of applications that require a single - input power supply rang e from 2.9 5 v to 20 v. low voltage biasing is supplied via a 5 v internal low dropout regulator ( ldo ) . typical applicati ons circuit comp bst fb drvh gnd sw vreg vreg_in res drvl ss c ss pgnd vin c c c vreg c vreg2 c c2 r c r bot r top v out en 10k? vreg q1 q2 l c out v out c bst load c in v in = 2.95v to 20v ADP1874/ adp1875 r res r trk1 pgood r pgd v ext track r trk2 v master 09347-001 figure 1. typical applications circuit 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 1.8v f sw = 300khz wrth inductor: 744325120, l = 1.2h, dcr = 1.8m infineon fets: bsc042n03ms g (upper/lower) v in = 5v (psm) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09347-102 figure 2 . ADP1874 / adp1875 efficiency vs. load current (v out = 1.8 v, 300 khz) in addition, soft start programmability is included to limit input in - rush current from the input supply during startup and to provide reverse current protection during p recharged output conditions . the low - side current sense, curren t gain scheme , and integration of a boost diode, along with the psm/forced pulse - width modulation (pwm) option, reduce the external part count and improve efficiency. the ADP1874 / adp1875 operate over the ?40c to +125c junction temperature range and are available in a 16- lead qsop package .
ADP1874/adp1875 data sheet rev. a | page 2 of 44 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical applications circuit ............................................................ 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 boundary condition .................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 ADP1874/adp1875 bloc k digram ............................................... 18 theory of operation ...................................................................... 19 startup .......................................................................................... 19 soft start ...................................................................................... 19 precision enable circuitry ........................................................ 19 undervoltage lockout ............................................................... 19 on - board low d ropout regulator .......................................... 20 thermal shutdown ..................................................................... 20 programming resistor (res) detect circuit .......................... 20 valley current - limit setting .................................................... 20 hiccup mode during short circuit ......................................... 22 synchronous rectifier ................................................................ 22 adp1875 power saving mode (psm) ...................................... 22 timer operation ........................................................................ 23 pseudo - fixed frequency ........................................................... 24 power good monitoring ........................................................... 24 voltage tracking ......................................................................... 25 applications info rmation .............................................................. 27 feedback resistor divider ........................................................ 27 inductor selection ...................................................................... 27 ou tput ripple voltage (v rr ) .................................................. 27 output capacitor selection ....................................................... 27 compensation network ............................................................ 28 efficiency consideration ........................................................... 29 input capacitor selection .......................................................... 30 thermal considerations ............................................................ 31 design example .......................................................................... 32 external component recommendations .................................... 34 layout considerations ................................................................... 36 ic section (left side of evaluation board) ............................. 38 power section ............................................................................. 38 different ial sensing .................................................................... 39 typical application circuits ......................................................... 40 12 a, 300 khz high current application circuit .................. 40 5.5 v input, 600 khz application circuit ............................... 40 300 khz high current application circuit ............................ 41 outline dimensions ....................................................................... 42 ordering guide .......................................................................... 42 revision history 7 /12 rev. 0 to rev. a changes to table 7 .......................................................................... 21 3 / 1 1 rev ision 0: initial version
data sheet ADP1874/adp1875 rev. a | page 3 of 44 specifications all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). vreg = 5 v, bst ? sw = vreg ? v rect_drop ( s ee figure 40 to figure 42 ). v in = 1 2 v . the specifications are valid for t j = ? 40c to +12 5c, unless otherwise specified. table 1 . parameter symbol test conditions /comments min typ max unit power supply characteristics high input voltage range vi n c vin = 22 f(25 v rating) to pgnd (at pin 1) ADP1874arqz - 0.3/adp1875arqz - 0.3 (300 khz) 2.95 12 20 v ADP1874arqz - 0.6/adp1875arqz - 0.6 (600 khz) 2.95 12 20 v ADP1874arqz - 1.0/adp1875arqz - 1.0 (1.0 mhz) 3.25 12 20 v quiescent current i q_reg + i q_ bst fb = 1.5 v, no switching 1.1 ma shutdown current i reg,sd + i bst,sd en < 600 mv 140 225 a undervoltage lockout uvlo rising v in (see figure 35 for temperature variation) 2.65 v uvlo hysteresis falling v in from operational state 190 mv internal regulator characteristics vreg and vreg_in tied together and should not be loaded externally because they are intended to only bias internal circuitry vreg operational output voltage vreg c vreg = 4.7 f t o pgnd, 0.22 f to gnd, v in = 2.95 v to 20 v ADP1874arqz - 0.3/adp1875arqz - 0.3 (300 khz) 2.75 5 5.5 v ADP1874arqz - 0.6/adp1875arqz - 0.6 (600 khz) 2.75 5 5.5 v ADP1874arqz - 1.0/adp1875arqz - 1.0 (1.0 mhz) 3.05 5 5.5 v vreg output in regulation v in = 7 v, 100 ma 4.82 4.981 5.16 v v in = 12 v, 100 ma 4.83 4.982 5.16 v load regulation 0 ma to 100 ma, v in = 7 v 32 mv 0 ma to 100 ma, v in = 20 v 34 mv line regulation v in = 7 v to 20 v, 20 ma 2.5 mv v in = 7 v to 20 v, 100 ma 2 mv vin to vreg dropout voltage 100 ma out of vreg, v in 5 v 300 415 mv short vreg to pgnd v in = 20 v 229 320 ma soft start soft start period calculation connect external capacitor from ss pin to gnd, c ss = 10 nf/ms 10 n f/ms error amplifer fb regulation voltage v fb t j = 25c 600 mv t j = ?40c to +85c 596 600 604 mv t j = ?40c to +125c 594.2 600 605.8 mv transconductance g m 320 496 670 s fb input leakage current i fb, leak fb = 0.6 v, en = vreg 1 50 na current - sense amplifier gain programming resistor (res) value f rom res to pgnd res = 47 k 1% 2.7 3 3.3 v/v res = 22 k 1% 5.5 6 6.5 v/v res = none 11 12 13 v/v res = 100 k 1% 22 24 26 v/v switching frequency typical values measured at 50% time points with 0 nf at drvh and drvl; maximum values a re guaranteed by bench evaluation 1 ADP1874arqz - 0.3/ adp1875arqz - 0.3 (300 khz) 300 khz on - time vin = 5 v, v out = 2 v, t j = 25c 1120 1200 1280 ns minimum on - time vin = 20 v 145 190 ns minimum off - time 84% duty cycle (maximum) 340 400 ns
ADP1874/adp1875 data sheet rev. a | page 4 of 44 parameter symbol test conditions /comments min typ max unit a dp1874arqz - 0.6/ adp1875arqz - 0.6 (600 khz) 600 khz on - time vin = 5 v, v out = 2 v, t j = 25c 500 540 580 ns minimum on - time vin = 20 v, v out = 0.8 v 82 110 ns minimum off - time 65% duty cycle (maximum) 340 400 ns ADP1874arqz - 1.0/ adp1875arqz - 1. 0 (1.0 mhz) 1.0 mhz on - time vin = 5 v, v out = 2 v, t j = 25c 285 312 340 ns minimum on - time vin = 20 v 52 85 ns minimum off - time 45% duty cycle (maximum) 340 400 ns output driver characteristics high - side driver output source res istance 2 i source = 1.5 a, 100 ns, positive pulse (0 v to 5 v) 2.25 3 .5 output sink resistance 2 i sink = 1.5 a, 100 ns, negative pulse (5 v to 0 v) 0.70 1 rise time 3 t r, drvh bst ? sw = 4.4 v, c in = 4.3 nf (see figure 59) 25 ns fall time 3 t f, drvh bst ? sw = 4.4 v, c in = 4.3 nf (see figure 60) 11 ns low - side driver output source resistance 2 i source = 1.5 a, 100 ns, positive pulse (0 v to 5 v) 1.6 2. 4 output sink resistance 2 i sink = 1.5 a, 100 ns, negative pulse (5 v to 0 v) 0.7 1 rise time 3 t r,drvl vreg = 5.0 v, c in = 4.3 nf (see figure 60) 18 ns fall time 3 t f,drvl vreg = 5.0 v, c in = 4.3 nf (see figure 59) 16 ns propagation delays drvl fall to drvh rise 3 t tpdhdrvh bst ? sw = 4.4 v (see figure 59) 15.4 ns drvh fall to drvl rise 3 t tpdhdrvl bst ? sw = 4.4 v (see figure 60) 18 ns sw leakage current i swleak bst = 25 v, sw = 20 v, vreg = 5 v 110 a integrated rectifier channel impedance i sink = 10 ma 22 precision enable threshold logic high level vin = 2.9 v to 20 v, vreg = 2.75 v to 5.5 v 570 630 6 80 mv enabl e hysteresis vin = 2.9 v to 20 v, vreg = 2.75 v to 5.5 v 31 mv comp voltage comp clamp low voltage v comp(low) tie en pin to vreg to enable device ( 2.75 v vreg 5.5 v) 0.47 v comp clamp high voltage v comp(high) ( 2.75 v vreg 5.5 v) 2. 55 v comp zero current threshold v comp_zct ( 2.75 v vreg 5.5 v) 1.15 v thermal shutdown t tmsd thermal shutdown threshold rising temperature 155 c thermal shutdown hysteresis 15 c current limit hiccup current limit timing co mp = 2.4 v 6 ms overvoltage and power good thresholds pgood fb power good threshold fb pgd v fb rising during system power -up 542 568 mv fb power good hysteresis 30 mv fb overvoltage threshold fb ov v fb rising during overvoltage event, i pgood = 1 ma 691 710 mv fb overvoltage hysteresis 30 mv pgood low voltage d uring sink v pgood i pgood = 1 ma 143 200 mv pgood leakage current pgood = 5 v 1 400 na
data sheet ADP1874/adp1875 rev. a | page 5 of 44 parameter symbol test conditions /comments min typ max unit tracking track input voltage rang e 0 5 v fb -to - tracking offset voltage 0.5 v < track < 0.6 v, offset = v fb ? v track 63 mv leakage current v track = 5 v 1 50 na 1 the maximum specified value s are with the closed loop measured at 10% to 90% time points (see figure 59 and figure 60 ), c gate = 4.3 nf, and the upper side and lower side mosfets being infineon bsc042n03ms g. 2 guaranteed by design. 3 not automatic test equipment (ate) tested.
ADP1874/adp1875 data sheet rev. a | page 6 of 44 a bsolute maximum rati ngs table 2 . parameter rating vreg , vreg_in , track to p gnd , gnd ?0.3 v to +6 v vin , en, pgood to p gnd ?0.3 v to +28 v fb, comp, res, ss to gnd ?0.3 v to ( vreg + 0.3 v) drvl to pgnd ?0.3 v to ( vreg + 0.3 v) sw to pgnd ?2.0 v to +28 v bst to sw ?0.6 v to ( vreg + 0.3 v) bst to pgnd ?0.3 v to + 2 8 v drvh to sw ?0.3 v to vreg pgnd to gnd 0.3 v pgood input current 20 ma ja (1 6 - lead q sop) 4 - layer board 104c/w operating junction temperature range ?40c to +125c storage temperature range ?65c to +150c soldering conditions jedec j - std -020 maximum soldering lead temperature (10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified , all other voltages are referenced to p gnd. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3 . thermal resistance package type ja un it ja (16 - lead qsop) 4 - layer board 104 c/w boundary condition in determin ing the values given in table 2 and table 3 , natural convection is used to transfer heat t o a 4 - layer evaluation board. esd caution
data sheet ADP1874/adp1875 rev. a | page 7 of 44 pin configuration and fu nction descriptions vin 1 comp 2 en 3 fb 4 bst 16 sw 15 drvh 14 pgnd 13 gnd 5 drvl 12 res 6 pgood 11 vreg 7 ss 10 vreg_in 8 track 9 ADP1874/ adp1875 top view (not to scale) 09347-003 figure 3. pin configuration table 4 . pin function descriptions pin o. mnemonic description 1 vin high -s i de input voltage. connect vin to the drain of the upper side mosfet. 2 comp output of the error am plifier. connect the compensation network between this pin and agnd to achieve stability ( s ee the compensation netwo rk s ection). 3 en connect to vreg to e nable ic. when pulled down to agnd externally, disables the ic. 4 fb noninverting input of the internal error amplifier. this is the node where the feedback resistor is connected. 5 gnd analog ground reference pin of the ic. all sensitive analog components should be connected to this ground plane (see the layout considerations section). 6 res current sense gain resistor (e xternal). connect a res istor between the res pin and gnd (p in 5). 7 vreg internal regulator supply bias voltage for the ADP1874 / adp1875 controller ( i ncludes the output gate drivers ). a bypass capacitor of 1 f dir ectly from this pin to pgnd and a 0.1 f across vreg and gnd are recommended. 8 vreg_in input to the internal ldo. tie this pin directly to p in 7 (vreg) . 9 track tracking input. if the tracking function is not used, it is recommended to connect track to vreg through a resistor higher than 1 m or simply connect track between 0.7 v and 2 v to reduce the bias current going into the pin. 10 ss soft start input. connect an external capacitor to gnd to program the soft start period. capacitance value of 10 nf for every 1 ms of soft start delay. 11 p good open - drain power good output. sinks current when fb is out of regulation or during thermal shutdown. connect a 3 k resistor between p good and vreg . leave unconnected if not used. 12 drvl driv e output for th e external lower side, n - channel mosfet. this pin also serves as the current - sense gain setting pin (see figure 69 ). 13 pgnd power gnd. ground for the lower side gate driver and lower side, n - channel mosfet. 14 drvh drive output for the external uppe r side, n - channel mosfet. 15 sw switch node connection. 1 6 bst bootstrap for the upper side mosfet gate drive circuitry. an internal boot rectifier (diode) is connected between vreg and bst. a capacitor from bst to sw is required. an external schottky diode can also be connected between vreg and bst for increased gate drive capability.
ADP1874/adp1875 data sheet rev. a | page 8 of 44 typical performance characteristics 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 0.8v f sw = 300khz wrth inductor: 744325072, l = 0.72h, dcr = 1.3m infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09347-104 figure 4. efficiency 300 kh z , v out = 0.8 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 1.8v f sw = 300khz wrth inductor: 744325120, l = 1.2h, dcr = 1.8m infineon fets: bsc042n03ms g (upper/lower) v in = 5v (psm) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09347-105 figure 5. efficiency 300 kh z , v out = 1.8 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 7v f sw = 300khz wrth inductor: 7443551200, l = 2.0h, dcr = 2.6m infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09347-106 figure 6. efficiency 300 kh z , v out = 7 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 0.8v f sw = 600khz wrth inductor: 744355147, l = 0.47h, dcr = 0.67m infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09347-107 figure 7. efficiency 600 kh z , v out = 0.8 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 1.8v f sw = 600khz wrth inductor: 744325072, l = 0.72h, dcr = 1.3m infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09347-108 figure 8. efficiency 600 kh z , v out = 1.8 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 5v f sw = 600khz wrth inductor: 744318180, l = 1.4h, dcr = 3.2m infineon fets: bsc042n03ms g (upper/lower) v in = 20v (psm) v in = 13v (psm) v in = 16.5v (psm) v in = 20v v in = 16.5v 09347-109 figure 9. efficiency 600 kh z , v out = 5 v
data sheet ADP1874/adp1875 rev. a | page 9 of 44 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 0.8v f sw = 1.0mhz wrth inductor: 744303012, l = 0.12h, dcr = 0.33m infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09347-110 figure 10 . efficiency 1.0 m hz , v out = 0.8 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 1.8v f sw = 1.0mhz wrth inductor: 744303022, l = 0.22h, dcr = 0.33m infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09347-111 figure 11 . efficiency 1.0 m hz , v out = 1.8 v 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 10 100 1k 10k 100k efficiency (%) load current (ma) t a = 25c v out = 5v f sw = 1.0mhz wrth inductor: 744355090, l = 0.9h, dcr = 1.6m infineon fets: bsc042n03ms g (upper/lower) v in = 13v (psm) v in = 16.5v (psm) v in = 13v v in = 16.5v 09347-112 figure 12 . efficiency 1.0 m hz , v out = 5 v 0.807 0.806 0.805 0.804 0.803 0.802 0.801 0.800 0.799 0.798 0.797 0.796 0.795 0.794 0.793 0.792 0 2000 4000 6000 8000 10,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 09347-013 figure 13 . output voltage accuracy 300 kh z , v out = 0.8 v 1.821 1.816 1.811 1.806 1.801 1.796 1.791 1.786 0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 5.5v +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 09347-014 figure 14 . output voltage accuracy 300 kh z , v out = 1.8 v 7.100 7.095 7.090 7.085 7.080 7.075 7.070 7.065 7.060 7.055 7.050 7.045 7.040 7.035 7.030 7.025 7.020 7.015 7.010 7.005 7.000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v v in = 16.5v 09347-015 figure 15 . output voltage accuracy 300 kh z , v out = 7 v
ADP1874/adp1875 data sheet rev. a | page 10 of 44 0.808 0.792 0.794 0.796 0.798 0.800 0.802 0.804 0.806 0 1000 2000 3000 4000 5000 6000 7000 8000 10,000 9000 frequency (khz) load current (ma) +125c +25c ?40c v in = 13v v in = 16.5v 09347-115 figure 16 . output voltage accuracy 600 khz, v out = 0.8 v 1.818 1.770 1.772 1.774 1.776 1.778 1.780 1.782 1.784 1.786 1.788 1.790 1.792 1.794 1.796 1.798 1.800 1.802 1.804 1.806 1.808 1.810 1.812 1.814 1.816 0 12,000 10,500 9000 7500 6000 4500 3000 1500 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 09347-016 figure 17 . output voltage accuracy 600 kh z , v out = 1.8 v 5.030 5.025 5.005 5.010 5.015 5.020 5.000 4.995 4.990 4.985 4.980 4.975 4.970 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v v in = 16.5v v in = 20v 09347-017 figure 18 . output voltage accuracy 600 kh z , v out = 5 v 0 2000 4000 6000 8000 10,000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 0.787 0.789 0.791 0.793 0.795 0.797 0.799 0.801 0.803 0.805 0.807 09347-118 figure 19 . output voltage accuracy 1.0 m hz , v out = 0.8 v 1.820 1.815 1.810 1.805 1.800 1.795 1.790 0 10,000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 09347-019 figure 20 . output voltage accuracy 1.0 m hz , v out = 1.8 v 7200 6400 5600 4800 4000 2400 1600 3200 0 9600 8800 8000 800 5.04 4.90 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 output voltage (v) load current (ma) +125c +25c ?40c v in = 13v +125c +25c ?40c v in = 16.5v 09347-020 figure 21 . output voltage accuracy 1.0 m hz , v out = 5 v
data sheet ADP1874/adp1875 rev. a | page 11 of 44 601.0 600.5 600.0 599.5 599.0 598.5 598.0 597.5 597.0 ?40.0 ?7.5 25.0 57.5 90.0 122.5 feedback voltage (v) temperature (c) vreg = 5v, v in = 13v vreg = 5v, v in = 20v 09347-121 figure 22 . feedback voltage vs. temperature 325 315 305 295 285 275 265 255 10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2 switching frequency (khz) v in (v) +125c +25c ?40c no load 09347-022 figure 23 . switching frequency vs. high input voltage , 300 khz, 10% of 12 v 650 600 550 500 450 400 13.0 13.4 13.8 14.2 14.6 15.0 15.4 15.8 16.2 16.5 switching frequency (khz) v in (v) +125c +25c ?40c no load 09347-123 figure 24 . switching frequency vs. high input voltage, 600 khz, v out = 1.8 v, v in range = 13 v to 16.5 v 900 880 860 840 820 800 780 760 740 720 700 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 switching frequency (khz) v in (v) +125c +25c ?40c 09347-124 figure 25 . switching frequency vs. high input voltage, 1.0 mhz, v in range = 13 v to 16.5 v 280 190 205 220 235 250 265 0 10,000 8000 6000 4000 2000 frequency (khz) load current (ma) v in = 13v v in = 20v v in = 16.5v +125c +25c ?40c 09347-025 figure 26 . frequency vs. load current, 300 khz, v out = 0.8 v 330 240 250 260 270 280 290 300 310 320 0 15,000 12,000 13,500 10,500 9000 7500 6000 4500 3000 1500 frequency (khz) load current (ma) v in = 20v v in = 13v v in = 16.5v +125c +25c ?40c 09347-026 figure 27 . frequency vs. load current, 300 khz, v out = 1.8 v
ADP1874/adp1875 data sheet rev. a | page 12 of 44 338 298 302 306 310 314 318 322 326 330 334 0 6400 7200 8000 8800 5600 4800 4000 3200 2400 1600 800 frequency (khz) load current (ma) v in = 13v v in = 16.5v +125c +25c ?40c 09347-027 figure 28 . frequency vs. load current, 300 khz, v out = 7 v 300 330 360 390 420 450 480 510 540 0 12,000 1200 2400 3600 4800 6000 7200 8400 9600 10,800 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 09347-028 figure 29 . frequency vs. load current, 600 khz, v out = 0.8 v 675 495 515 535 555 575 595 615 635 655 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 09347-029 figure 30 . frequency vs. load current, 600 khz, v out = 1.8 v 740 621 628 635 642 649 656 663 670 677 684 691 698 705 712 719 726 733 0 9600 8800 8000 7200 6400 5600 4800 4000 3200 2400 1600 800 frequency (khz) load current (ma) v in = 13v v in = 16.5v +125c +25c ?40c 09347-030 figure 31 . frequency vs. load current, 600 khz, v out = 5 v 850 775 700 625 550 475 400 0 12,000 10,000 8000 6000 4000 2000 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 09347-031 figure 32 . frequency vs. load current, v out = 1.0 mhz, 0.8 v 550 625 700 775 850 925 1000 1075 1150 1225 0 12,000 9600 10,800 8400 7200 6000 4800 3600 2400 1200 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 09347-032 figure 33 . frequency vs. load current, 1.0 mhz, v out = 1.8 v
data sheet ADP1874/adp1875 rev. a | page 13 of 44 1000 1450 1400 1350 1300 1250 1200 1150 1100 1050 0 8000 800 1600 2400 3200 4000 4800 5600 6400 7200 frequency (khz) load current (ma) v in = 16.5v v in = 13v +125c +25c ?40c 09347-033 figure 34 . frequency vs. load curr ent, 1.0 mhz, v out = 5 v 2.649 2.658 2.657 2.656 2.655 2.654 2.653 2.652 2.651 2.650 ?40 120 100 80 60 40 20 0 ?20 uvlo (v) temperature (c) 09347-034 figure 35 . uvlo vs. temperature 55 60 65 70 75 80 85 90 95 300 400 500 600 700 800 900 1000 maximum duty cycle (%) frequency (khz) +125c +25c ?40c 09347-035 figure 36 . maximum duty cycle vs. frequency 62 64 66 68 70 72 74 76 78 80 82 5.5 6.7 7.9 9.1 10.3 11.5 12.7 13.9 15.1 16.3 maximum duty cycle (%) v in (v) +125c +25c ?40c 09347-036 figure 37 . maximum duty cycle vs. high voltage input (v in ) 180 680 630 580 530 480 430 380 330 280 230 ?40 120 100 80 60 40 20 0 ?20 minumum off-time (ns) temperature (c) vreg = 2.7v vreg = 5.5v vreg = 3.6v 09347-037 figure 38 . minimum off - tim e vs. temperature 180 680 630 580 530 480 430 380 330 280 230 2.7 5.5 5.1 4.7 4.3 3.9 3.5 3.1 minumum off-time (ns) vreg (v) +125c +25c ?40c 09347-038 figure 39 . minimum off - time vs. vreg (low input voltage)
ADP1874/adp1875 data sheet rev. a | page 14 of 44 80 800 720 640 560 480 400 320 240 160 300 400 500 600 700 800 900 1000 rectifier drop (mv) frequency (khz) vreg = 2.7v vreg = 5.5v vreg = 3.6v +125c +25c ?40c 09347-039 figure 40 . internal rectifier drop vs. frequency 80 1280 720 640 560 480 1040 1120 1200 960 880 800 400 320 240 160 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 rectifier drop (mv) vreg (v) v in = 5.5v v in = 16.5v v in = 13v 1mhz 300khz t a = 25c 09347-040 figure 41 . internal boost rectifier drop vs. vreg (low input voltage) over v in variation 80 720 640 560 480 400 320 240 160 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 rectifier drop (mv) vreg (v) 1mhz 300khz +125c +25c ?40c 09347-041 figure 42 . internal boost rectifier drop vs. vreg 8 80 64 72 56 48 40 32 24 16 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 body diode conduction time (ns) vreg (v) 1mhz 300khz +125c +25c ?40c 09347-042 figure 43 . lower side mosfet body diode conducti on time vs. vreg ch1 50mv b w ch2 5a ? ch3 10v b w ch4 5v m400ns a ch2 3.90a t 35.8% 1 2 3 4 output voltage inductor current sw node low side 09347-043 figure 44 . power saving mode (psm) operational waveform , 10 0 ma ch1 50mv b w ch2 5a ? ch3 10v b w ch4 5v m4.0s a ch2 3.90a t 35.8% 1 2 3 4 output voltage inductor current sw node low side 09347-044 figure 45 . psm waveform at light load , 500 ma
data sheet ADP1874/adp1875 rev. a | page 15 of 44 ch1 5a ? ch3 10v ch4 100mv b w m400ns a ch3 2.20v t 30.6% 1 3 4 output voltage inductor current sw node 09347-045 figure 46 . ccm operation at heavy load , 12 a ( see figure 99 for application circuit ) ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m2ms a ch1 3.40a t 75.6% 1 2 3 4 output voltage 12a step sw node low side 09347-046 figure 47 . load transient step psm enabled , 12 a (see figure 99 application circuit ) ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m20s a ch1 3.40a t 30.6% 1 2 3 4 output voltage 12a positive step sw node low side 09347-047 figure 48. positive step during heavy load transient behavior psm enabled , 12 a, v out = 1.8 v (see figure 99 application circuit ) ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m20s a ch1 3.40a t 48.2% 1 2 3 4 output voltage 12a negative step sw node low side 09347-048 figure 49 . negative step during heavy load transient behavior psm enabled , 12 a (see figure 99 application circuit ) ch1 10a ? ch2 5v ch3 20v ch4 200mv b w m2ms a ch1 6.20a t 15.6% 1 2 3 4 output voltage 12a step sw node low side 09347-049 figure 50 . load transient step forced pwm at light load , 12 a (see figure 99 application circuit ) ch1 10a ? ch2 5v ch3 20v ch4 200mv b w m20s a ch1 6.20a t 43.8% 1 2 3 4 output voltage 12a positive step sw node low side 09347-050 figure 51 . positive step during heavy load transient behavior forced pwm at light load , 12 a, v out = 1.8 v (see figure 99 application circuit )
ADP1874/adp1875 data sheet rev. a | page 16 of 44 ch1 10a ? ch2 200mv b w ch3 20v ch4 5v m10s a ch1 5.60a t 23.8% 1 2 3 4 output voltage 12a negative step sw node low side 09347-051 figu re 52. negative step during heavy load transient behavior forced pwm at light load , 12 a (see figure 99 application circuit ) ch1 2v b w ch2 5a ? ch3 10v ch4 5v m4ms a ch1 920mv t 49.4% 1 2 3 4 output voltage inductor current sw node low side 09347-052 figure 53 . output short - circuit beh avior leading to hiccup mode ch1 5v b w ch2 10a ? ch3 10v ch4 5v m10s a ch2 8.20a t 36.2% 1 2 3 4 output voltage inductor current sw node low side 09347-053 figure 54 . magnified waveform during hiccup mode ch1 2v b w ch2 5a ? ch3 10v ch4 5v m2ms a ch1 720mv t 32.8% 1 2 3 4 output voltage inductor current sw node low side 09347-054 figure 55 . start - up behavior at heavy load, 12 a , 300 kh z (see figure 99 ap plication circuit ) ch1 2v b w ch2 5a ? ch3 10v ch4 5v m4ms a ch1 720mv t 41.6% 1 2 3 4 output voltage inductor current sw node low side 09347-055 figure 56 . power - down waveform during heavy load ch1 50mv b w ch2 5a ? ch3 10v b w ch4 5v m2s a ch2 3.90a t 35.8% 1 2 3 4 output voltage inductor current sw node low side 09347-056 figure 57 . output voltage ripple waveform during psm operation at light load , 2 a
data sheet ADP1874/adp1875 rev. a | page 17 of 44 2 ch2 5v ch3 5v math 2v 40ns ch4 2v m40ns a ch2 4.20v t 29.0% 3 m 4 high side hs minus sw sw node low side t a = 25c 09347-058 figure 58 . output drivers and sw node waveforms 2 ch2 5v ch3 5v math 2v 40ns ch4 2v m40ns a ch2 4.20v t 29.0% 3 m 4 high side hs minus sw sw node low side 16ns ( t f ,drvl ) 25ns ( t r ,drvh ) 22ns ( t pdh drvh ) t a = 25c 09347-059 figure 59 . upper side driver rising and low er side falling edge waveform s (c in = 4.3 nf ( upper side /low er side mosfet ), q total = 27 nc (v gs = 4.4 v (q1), v gs = 5 v (q3) ) 2 ch2 5v ch3 5v math 2v 20ns ch4 2v m20ns a ch2 4.20v t 39.2% 3 m 4 high side hs minus sw sw node low side 18ns ( t r ,drvl ) 24ns ( t pdh ,drvl ) 11ns ( t f ,drvh ) t a = 25c 09347-060 figure 60 . upper side dri ver falling and low er side rising edge waveforms (c in = 4.3 nf ( upper side /low er side mosfet), q total = 27 nc (v gs = 4.4 v (q1), v gs = 5 v (q3) ) 570 550 530 510 490 470 450 430 ?40 ?20 120 100 80 60 40 20 0 transconductance (s) temperature (c) vreg = 5.5v vreg = 3.6v vreg = 2.7v 09347-061 figure 61 . transconductance (g m ) vs . temperature 680 330 380 430 480 530 580 630 2.7 3.0 5.4 4.8 5.1 4.5 4.2 3.9 3.6 3.3 transconductance (s) vreg (v) +125c +25c ?40c 09347-062 figure 62 . transconductance (g m ) vs . vreg 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 0.75 0.70 2.7 5.5 5.1 4.7 4.3 ?40c +25c +125c 3.9 3.5 3.1 quiescent current (ma) vreg (v) 09347-163 figure 63 . quiescent current vs. vreg
ADP1874/adp1875 data sheet rev. a | page 18 of 44 ADP1874 / adp1875 blo ck digram 09347-063 drvh gnd irev comp ADP1874/adp1875 c r (trimmed) vreg t on timer t on = 2rc(v out /v in ) i sw information sw filter state machine ton bg_ref in_psm in_ss pwm hs_o hs sw ls ls_o irev level shift hs vreg ls vreg 300k? 800k? 8k? sw drvl pgnd bst vin psm ref_zero in_hicc ss comp error amp ss_ref 0.6v lower comp clamp ref_zero cs amp pwm fb track comp vreg vreg_in i ss ss 0.4v adc res detect and gain set cs gain set bias block and reference ref ldo precision enable en_ref to enable all blocks en res 530mv 690mv fb 600mv pgood figure 64 . ADP1874 / adp1875 block diagram
data sheet ADP1874/adp1875 rev. a | page 19 of 44 theory of operation the ADP1874 / adp1875 are versatile current mode, synchronous step - down controllers that provide superior transient response, optimal stability, and current limit protection by using a constant on - time, pseudo - fixed freque ncy with a programmable current - sense gain, current - control scheme. in addition, these devices offer optimum performance at low duty cycles by u s ing a valley , curre nt mode control architecture. this allows the ADP1874 / adp1875 to drive all n - channel power stages to regulate output voltages to as low as 0.6 v. startup the ADP1874 / adp1875 ha ve an internal regulator ( vreg ) for biasing and supplying power for the integrated mosfet drivers . a bypass capacitor should be located directly across the vreg (pin 7 ) and pgnd (pin 13) pins . in cluded in th e power - up sequenc e is the biasin g of the current - sense amplifier , the current - sense gain circuit (see the programming resistor (res) detect circuit section ), the soft start circuit, and the error amplifier . the current - sense blocks provide valle y current information (see the programming resistor (res) detect circuit section) and are a variable of the compensation equation for loop stability (see the compensation ne twork section ). the valley current information is extracted by forcing a voltage across the res and pgnd pin s , which generates a current depen ding on the resistor value across res and pgnd . the current through the resistor is used to set the current - sense amplifier gain. this process takes approximately 800 s, after which the drive signal pulses appear at the drvl and drvh pins synchronously , and the output voltage begins to rise in a controlled manner through the soft start sequence. the rise time of the output voltage is determined by the soft start and error amplifier blocks ( see the soft start section ). at the beginning of a soft start, the error amplifier charge s the e xter nal compensation capacitor , cau s ing th e comp pin to begin to rise (s ee figure 66). tying the vreg pin to the en pin via a pull - up resistor causes the voltage at this pin to rise above the enable threshold of 630 mv to enable the ADP1874 / adp1875 . soft start the ADP1874 employs externally programmable , so ft start circuitry that charges up a capacitor tied to the ss p in to gnd . this prevents input in - rush current through the external mosfet from the input supply (v in ). the output track s th e ramping voltage by producing pwm output pulses to the upper side mosfet . the purpose is to limit the in - rush curr ent from the high voltage input supply (v in ) to the output (v out ) . precision enable cir cuitry the ADP1874 / adp1875 ha ve precision enable circuitry. the precision enable thresho ld is 630 mv with 3 0 mv of hysteresis (see figure 65) . connecting th e en pin to gnd disables the ADP1874 / adp1875 , reduci ng the supply current of the device to approximately 1 40 a. precision enable comp. to enable all blocks en 630mv vreg 10k? 09347-064 figure 65 . connecting en p in to vreg via a pull - up resistor to e nable the ADP1874 / adp1875 comp 2.4v 1.0v 500mv 0v maximum current (upper clamp) zero current usable range only after soft start period if contunuous conduction mode of operation is selected. lower clamp 09347-065 figure 66 . comp voltage range undervoltage lockout the undervoltage lockout (uvlo) feature prevents the part from operating both the upper side and low er side mosfets at extremely low or undefined input voltage ( v in ) ran ges. operation at an undefined bias voltage may result in the incorrect propagation of signals to the hig h - side power switches . this , in turn , result s in invalid output behavior that can cause damage to the output devices , ultimately destroying the device tied at the output . the uvlo level is set at 2.65 v (nominal) .
ADP1874/adp1875 data sheet rev. a | page 20 of 44 on - board low dropout re gulator the ADP1874 / adp1875 use an on - board ldo to bias the internal digital and analog circuitry. connect the vreg and vreg_in pins together for normal ldo operation for low voltage internal block biasing (see figure 67) . 09347-168 vreg_in ref vreg vin on-board regulator figure 67 . conne cting vr eg and vreg_in together with proper bypass capacitors connected to the vreg pin ( output o f the internal ldo), this pin also provides power for the internal mosfet drivers. it is recommended to float vreg /vreg_in if vin is u s ed for greater than 5.5 v opera tion. the minimum voltage where bias is guaranteed to operate is 2.75 v at vreg. for application s where vin is decoupled from vreg, the minimum voltage at vin must be 2.9 v. it is recommended to tie vin and vreg together if the vin pin is subjected to a 2. 75 v rail. table 5 . power input and ldo output configurations vin vreg /vreg_in comments > 5.5 v float must use the ldo . <5.5 v connect to vin ldo dro p voltage is not realized ( that is, if vin = 2.75 v, then vreg = 2.7 5 v) . < 5.5 v float ldo drop is realized . vin ranging abov e and b elow 5.5 v float ldo drop is realized, minimum vin recommendation is 2.9 5 v. thermal shutdown the thermal shutdown is a self - protection feature to prevent the ic from damage due to a very high operati ng junction temperature. if the junction temperature of the device exceed s 155 c, the part ente rs the thermal shutdown state. in this state, the device shut s off both the upper side and low er side mosfets and disable s the entire controller immediately, thu s reducin g the power consumption of the ic. the part resume s operation after the junctio n temperature of the part cools to less than 140 c. programming resistor ( res ) detect circuit upon startup , one of the first blocks to become activ e is the res detect c ircuit. this block powers up before soft start begins. it forces a 0.4 v reference value at the res pin ( se e figure 68 ) and is programmed to identify four possible resistor val ues: 47 k?, 22 k ? , open, and 100 k?. the res detect circuit digitizes the value of the resistor at the res pin (pin 6) . an internal adc outputs a 2 - bit digital code that is used to program four separate gain configurations in the current - sense amplifier ( se e figure 69) . each configur ation corre - s pond s to a current - sense gain ( a cs ) of 3 v/v , 6 v/v , 12 v/v , or 24 v/v , respectively (see table 6 and table 7 ) . this variable is used for the valley current - limit setting, which set s up the appropriate current - sense gain for a given application and set s the compensation necessary to achieve loop stability ( see the valley current - limit setting section and the compensation network section ) . drvh drvl q1 sw q2 res cs gain programming 09347-066 figure 68 . programming resistor locati on sw pgnd cs gain set cs amp adc res 0.4v 09347-067 figure 69 . res detect circuit for current - sense gain programming table 6 . current - sense gain programmin g resistor a cs 47 k 3 v/v 22 k 6 v/v open 12 v/v 100 k 24 v/v valley current - limit setting the architecture of the ADP1874 / adp1875 is based on valley current - mode control. th e current limit is d etermined by three components: the r on of the l ow er side mosfet , the current - sense amplifier output voltage swing, and the current - sense gain. the c s output voltage range is internally fixed at 1.4 v. the current - sense gain is programma ble via an external resistor at th e res pin ( see the programming resistor (res) detect circuit section ). the r on of the low er side mosfet can vary over temperature and usually has a positive t c ( meaning that it inc rease s with temperature ) ; therefore, it is recommended to program the current - sense gain resistor based on the rated r on of the mosfet at 1 25c.
data sheet ADP1874/adp1875 rev. a | page 21 of 44 because the ADP1874 / adp1875 are based on valley current control, the relationship between i clim and i load is ? ? ? ? ? ? ? = 2 1 i load clim k i i where: k i is the ratio between the inductor ripple current and the desired average load current ( see figure 70). i clim is the desired valley current limit. i load is the current load. establishing k i helps to determine the inductor value (see the inductor selection section), but in most cases k i = 0.33 . load current valley current limit ripple current = i load 3 09347-068 figure 70 . valley current limit to average current relation when the desired valley current limit (i clim ) has been deter mined, the current - se nse gain can be calculated as follows : on cs clim r a i = v 4 . 1 where: r on is the channel impedance of the low er side mosfet . a cs is the current - sense gain multiplier (see table 6 and table 7 ) . although the ADP1874 / adp1875 ha ve only four discrete current - sense gain settings for a given r on variable , table 7 and figure 71 outline several available options for the valley current setpoint based on various r on value s. table 7 . valley current limit program (see figure 71) r on (m) valley current level 47 k 22 k open 100 k a cs = 3 v/v a cs = 6 v/v a cs = 12 v/v a cs = 24 v/v 1.5 38.9 2 29.2 2.5 23.3 3 39.0 19.5 3.5 33.4 16.7 4.5 26.0 13 5 23.4 11.7 5.5 21.25 10.6 10 23.3 11.7 5.83 15 31.0 15.5 7.75 3.87 18 26.0 13.0 6.5 3.25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 valley current limit (a) r on p? 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 5(6 n? a cs = 3v/v 5(6 n? a cs = 6v/v res = no res a cs = 12v/v 5(6 n? a cs = 24v/v 09347-069 figure 71 . valley current - limit value vs. r on of the low er side mosfet for each programming resistor (res) t he valley current limit is programmed as outlined in table 7 and figure 71. the inductor chosen must be rated to handle the peak current, which is equal to the valley current from table 7 plus the peak - to - peak inductor ripple current ( see the inductor selection section ). in addition , the peak curren t value must be used to comput e the worst - case power dissipation in the mosfets ( see figure 72) . inductor current valley current-limit threshold (set for 25a) ?, of 30a cs amplifier output swing cs amplifier output 2.4v 1v 0a 35a 37a 49a 39.5a ?, of 32.25a ?, of 37a maximum dc load current 09347-070 32.25a 30a figure 72 . vall ey current - limit threshold in relation to inductor ripple curren t
ADP1874/adp1875 data sheet rev. a | page 22 of 44 hs clim zero current repeated current-limit violation detected a predetermined number of pulses is counted to allow the converter to cool down soft start is reinitialized to monitor if the violation still exists 09347-071 figure 73 . idle mode entry sequence du e to current - limit violation hiccup mode during s hort circuit a current - limit violation occurs when the current a cross the source and drain of the lower side mosfet exceeds the current - limit setpoint. when 16 current - limit violations are detected, the controller enters idle mode and turns off the mosfets for 6 ms, allowing the converter to cool down. then, the contro ller rees tablishes soft start and begins to cause the output to ramp up again (see figure 73 ). while the output ramps up, c s amplifier output is monitored to determine if the violation is still present. if it is st ill present, the idle event occurs again, followed by the full chip, power - down sequence. this cycle continues until the violation no longer exists. if the violation disappears, the converter is allowed to switch normally, maintaining regulation. synchrono us rectifier the ADP1874 / adp1875 employ internal mosfet driver s for the external upper side and low er side mosfets. the low - side synchronous rectifier not only i mproves overall conduction efficiency but it also ensures proper charging of the bootstra p capacitor located at the upper side driver input. this is beneficial during start up to provide sufficient drive signal to the external upper side mosfet and to attai n fast turn - on response , which is essential for minimizing switching loss es . the integrated upper side and lower side mosfet drivers operate in com plementary fashion with built - in anti cross - conduction circuitry to prevent unwanted shoot - through current th at may potentially damage the mosfet s or reduce efficiency because of excessive power loss . adp1875 power saving mode ( psm ) a power saving mode is provided in the adp1875 . the adp1875 operates in the discontinuous conduction mode (dcm) and pulse skip s at light load to medium load currents. the controller output s pulses as necessary to maintain output regula tion. unlike the continuous conduction mode (ccm), dcm operation prevents negative current , thus allowing improved system efficiency at light load s . c urrent in the reverse direction through this pathway , however, result s in power dissipation and therefore a decrease in efficiency. hs hs and ls are off or in idle mode ls 0a i load as the inductor current approaches zero current, the state machine turns off the lower-side mosfet. t on t off 09347-072 figure 74 . discon tinuous mode of operation (dcm) to minimize the chance of negative inductor current build up, an on - board zero - cross comparator turns off all upper side and lower side switching activitie s when the inductor current approaches the zero current line , causing the system to enter idle mode , where the upper side and lower side mo sf e ts a re turned off. to e nsure idle mode entry, a 10 mv offset, connected in series at the sw node , is implemented ( see figure 75 ). 10mv zero-cross comparator q2 ls sw i q2 09347-073 figure 75 . zero - cross comparator with 10 mv of offset
data sheet ADP1874/adp1875 rev. a | page 23 of 44 as soon as the forward current through the lower side mosfet decreases to a level where 10 m v = i q2 r on(q2) th e zero - cross comparator (or i rev comparator) emi ts a signal to turn off the low er side mos f e t. from this point, the slope of the inductor current ra mp ing down becomes steeper ( see figure 76) as the body diode of th e low er side mos fet begins to conduct current and continue s conduct ing current until the remaining energy stored in the inductor has been depleted. hs and ls in idle mode 10mv = r on i load zero-cross comparator detects 10mv offset and turns off ls sw ls 0a i load t on another t on edge is triggered when v out falls below regulation 09347-074 figure 76 . 10 mv offset to ensure prevention of negative inductor current the sys tem remain s in idle mode until the output v oltage drops below regulation. a pwm pulse is then produced , turning on the upper side mosfet to maintain system regulation. the adp1875 does not have an internal clo ck, so it switches purely as a hysteretic controller as described in this section . timer operation the ADP1874 / adp1875 employ a constant on - time architecture , whi ch provides a variety of benefits , including improved load and line transient response when compared with a constant ( fixed ) frequency current - mode contr ol loop of comparable loop design. the constant on - time timer , or t on timer, senses the high - side input voltage (v in ) and the output voltage ( v out ) using sw waveform informati on to produce an adjustable one - shot pwm pulse . the pulse varies the on - time of the upper side mosfet in response to dynamic changes in input voltage, output voltage, and load current conditions to maintain output regulation . the timer generates an on - time ( t on ) pulse that is inversely proportional to v in . in out on v v k t = where k is a constant that is trimmed using an rc timer product for the 300 k hz, 600 k hz , and 1 .0 mhz frequ ency options. c r (trimmed) vreg t on v in i sw information 09347-075 figure 77 . constan t on - time time the constant on - time ( t on ) is not strictly constant because it varies with v in and v out . however , this variation occurs in such a way as to keep the switching frequency virtually ind ependent of v in and v out . the t on timer uses a feedforward technique , which when applied to the constant on - time control loop mak es it a pseudo - fixed frequency to a first - order approximation . second - order effects , such as dc losses in the external power m osfet s ( see the efficiency consideration section ) , caus e some variation in frequency v s. load current and lin e voltage. these effec ts are shown in figure 23 to figure 34. the variations in frequency are much reduced compared with the variations generated if the feedforward technique is not u s ed. the f eedforward technique establishes the following relationship : k f sw 1 = where f sw is the controller switching frequency (300 khz, 600 khz, and 1.0 mhz) . the t on timer senses v in and v out to minimize frequency variation as previously explained. this provides pseudo - fixed frequency as explained in the pseudo - fixed frequency section. to allow headroom for v in and v out sensing, adhere to the following equations : vreg v in /8 + 1.5 vreg v out /4 for typical applications where vreg is 5 v, these equations are not relevant; however, care may be required for lower vreg /vin inputs.
ADP1874/adp1875 data sheet rev. a | page 24 of 44 pseudo - fixed frequency t he ADP1874 / adp1875 employ a constant on - time control scheme. during steady state operation, the switching frequency stays relative ly constant , or pseudo - fixed . this is due to the one - shot t on timer that produces a high - side pwm pulse with a fixed duration , given that external conditions such as input voltage, output voltage , and load current are also at steady state . during load transients , the frequency momentarily change s for the duration of the transient event so that the output comes back within regulation more quick ly than if the frequency w ere fixed or if it w ere to remain unc hange d . after the transient event is complete , the frequency returns to a pseudo - fixed value. to illustrate this feature more clearly , this s ection describe s one such load transient event a positive load step in detail. during load transient events, the high - side d river output pulse - width stays relatively c onsistent from cycle to cycle ; however, the off - time ( drvl on - time ) dynamically adjusts according to the instantaneous changes in the external conditions mentioned. when a positive load step occurs, the error amplifier (out of phase with the output, v out ) produces new voltage in formation at its output (comp). in addition, the current - sense a mplifier senses new inductor current information during this positive load transient event. the error amplifiers output voltage reaction is compared with the new inductor current information that sets the start of the next switching cycle. because current information is produced from valley current sensing, it is sensed at the down ramp of the inductor current , whereas the voltage loop information is sense d through the counter action up swing of the error amplifier s output (comp) . the result is a converge nce of these two signals ( see figure 78) , which allows an instantaneous increase in switching frequency during th e positive load transient event . in summary, a positive load step causes v out to transient down , whic h causes comp to transient up and , therefore , shortens the off time. this result ing increase in frequency during a positive load transient helps to quickly bring v out back up in value and within the regulation window . similarly , a negati ve load step cause s the off time to lengthen in response to v out rising. this effect ively increases the inductor de magnetizing phase , help ing to bring v out within regulation. in this case, the switching frequency decreases , or experiences a foldback, to help facilitate outp ut voltage recovery . because the ADP1874 / adp1875 ha ve the ability to respond rapidly to sudden changes in load demand, the recovery period in which the output vo ltage settles back to its original steady state operating point is much quicker than it would be for a fixed - frequency equivalent . therefore, using a pseudo - fixed frequency results in significantly better load - transient performance compared to using a fixe d frequency. valley trip points load current demand error amp output pwm output f sw > f sw cs amp output 09347-076 figure 78 . load transient response operation power g ood m onitoring the ADP1874 / adp1875 power good circuitry monitors the o utput voltage via the fb pin. the pgood pin is an open - drain output that can be pulled up by an external resistor t o a voltage rail that does not necessarily have to be vreg. when the internal nmos switch is in high impedance ( off state ), this means that t he pgoo d pin is logic high , and the ou t put voltage via the fb pin is within the specified regulation window. when the internal switch is turned on, pgood is internally pulled low when the output voltage via the fb pin is outside this regulation window. the p ower good window is defined with a typical upper specification of +90 mv and a lower specification of ? 70 mv below the fb voltage of 600 mv. when an overvoltage event occurs at the output, there is a typical propagation delay of 12 s prior to the pgood pin deassertion (logic low). when the output voltage re - enters the regulation window, there is a propaga tion delay of 12 s prior to pgood reasserting back to a logic high state . when the output is outside the regulation window , the pgood open drain switch is capable of sinking 1ma of current and provides 140 mv of drop across this switch. the user is free t o tie the external pull - up resistor (r res ) to any voltage rail up to 20 v. the following equation provide s the proper external pull - up resistor value: ma 1 mv 140 ? = ext pgd v r where: r pgd is the pgood external resistor . v ext is a user - chosen voltage rail . 09347-180 530mv 690mv fb 600mv pgood 1ma ? 140mv + v ext r pgd figure 79 . power good, output voltage monitoring circuit
data sheet ADP1874/adp1875 rev. a | page 25 of 44 09347-181 690mv 640mv 600mv 530mv fb hysteresis (50mv) output overvoltage pgood deassert pgood reassert pgood assertion at power-up pgood deassertion at power down soft-start v ext pgood 0v 0v t pgd t pgd t pgd t pgd figure 80 . power good timing diagram, t pgd = 12 s (diagram may look disproportionate for illustration purposes.) 09347-182 slave r trk2 1k? r trk1 1k? r pgd v ext c ss 10k? r top2 1k? r bot2 1k? vreg 1.2v v out2 (slave) en fb gnd pgood ss track pgnd master 10k? r top1 r bot1 vreg 1.8v v out1 (master) en fb gnd pgnd 0.9v figure 81 . coincident tracking circuit implementation 09347-184 slave r trk2 500? r trk1 1k? r pgd v ext c ss 10k? r top2 1k? r bot2 1k? vreg 1.2v v out2 (slave) en fb gnd pgood ss track pgnd master 10k? r top1 r bot1 vreg 2.5v v out1 (master) en fb gnd pgnd 1.7v figure 82 . ratiometric tracking circuit implementation v oltage t racking the ADP1874 / adp1875 feature a voltage - tracking function that facilitates proper power - up sequencing in applications that require tracking a master voltage. in this manner, the user is free to impose a master voltage that typically comes with a selectable or prog rammable ramp rate on slave or secondary power rails . t o impose any voltage tracking relationship, the master voltage rise time must be longer than the slave voltage soft start period . this is particularly important i n applications such as i/o voltage sequ encing and core voltage applications where specific power sequencing is required . tracking is made possible by four inputs to the error amplifier, three of which are input pins to the ic . the track and ss pins are positive inputs , and the fb pin provides t he negative feedback from the output voltage via the divide r network . the fourth input to the amplifier is the reference voltage of 0.6 v. the negative feedback pin (fb pin) regulates the output voltage to the lowest of the three positive inputs (track, ss , and 0.6 v reference). in all tracking configurations, the slave output can be set to as low as 0.6 v for a given operating condition. the master voltage must have a longer rise time than the slaves programmed soft s tart period ; otherwise , the tracking re lationship will not be observed at the slave output. coincident and r atiometric tracking are two possible tracking configuration options offered by the ADP1874 / adp 1875 . coincid ent tracking is the most commonly used tracking technique. it is primarily used in core and i/o sequencing applications. the ramp rate of the master voltage is fully imposed onto the ramp rate of the slave output voltage until it has reached its regulation setpoint. connecting the track pin , by differentially tapping onto the master voltage via a resist ive divider of similar ratio to the slave feedback divider network , is depicted in figure 83. 09347-083 master voltage slave voltage time (ms) output voltage (v) figu re 83 . coincident tracking: master voltage slav e voltage tracking relationship
ADP1874/adp1875 data sheet rev. a | page 26 of 44 the s lave output track s the m aster output dv/dt until the slave outpu t regulation point is reached. any i nfluence by the master vol tage thereafter wi ll no longer be in effect. ensure that the voltage forced on the slave track pin is above 0.7 v at the end of track phase . voltages imposed on the track pin below 0.7 v, once that tracking period has expired (steady state), may result in regulation inaccur acies due to the internal offsets of the error amplifier between track and fb . ratio metric tracking can be achieved by assigning the slave output to rise more quickly than the master voltage. the simplest way to perform ratiometric tracking is to different ially connect the slave track pin to the fb pin of the master voltage ic. the slave output, however, must be limited to a fraction of the master voltage. in this tracking configuration, it is not recommended for the slave track pin to terminate at a voltag e lower than 0.6 v due to inaccuracies between the track and fb inputs previously mentioned. it is not recommended to force any voltage on the slave track pin lower than 0.6 v. figure 84 illustrates a circuit with a ratiometric tracking configuration. setting r trk1 > r trk2 ensures that the slave track voltage will rise up more quickly (to the regulation point ) than the master voltage. 09347-085 master voltage slave voltage time (ms) output voltage (v) figure 84 . ratiometric tracking: master voltage slave voltage tracking relationship
data sheet ADP1874/adp1875 rev. a | page 27 of 44 application s i nformation feedback resistor di vider the required resistor divider network can be determine d for a given v out value because t he internal band gap reference (v ref ) is fixed at 0.6 v . s electing values for r t and r b determine s the minimum output load current of the converter . therefore, f or a given value of r b , the r t value can be determined through the following expression: v 6 . 0 v) 6 . 0 ( ? = out b t v r r inductor selection the inductor value is inversely proportional t o th e inductor ripple current. the peak - to - peak ripple current is given by 3 load load i l i i k i = ? where k i is typically 0.33 . the equation for the inductor value is given by in out sw l out in v v f i v v l ? ? = ) ( where: v in is the high voltage input. v out is the desire d output voltage . f sw is the c ontroller switching frequency ( 300 khz , 600 kh z , or 1 .0 m h z) . when selecting the inductor, choose an inductor saturation rating that is above the peak current level , and then calculate the inductor current ripple ( see the valley current - limit setting section and figure 85) . 52 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 6 8 10 12 14 16 18 20 22 24 26 28 30 peak inductor current (a) valley current limit (a) ?, ?, ?, 09347-077 figure 85 . peak inductor current vs. vall ey current limit for 33%, 40% , and 50 % of inductor rip ple current table 8 . recommended inductors l (h) dcr (m) i sat (a) dimensions (mm) manufacturer model number 0.12 0.33 55 10.2 7 w rth elek. 744303012 0.22 0.33 30 10.2 7 w rth elek. 744303022 0.47 0.8 50 14.2 12.8 w rth elek. 744355147 0.72 1.65 35 10.5 10.2 w rth elek. 744325072 0.9 1. 6 32 14 12.8 w rth elek. 744318120 1. 2 1.8 25 10.5 10.2 w rth elek. 744325120 1.0 3. 8 16 10.2 10.2 w rth elek. 7443552100 1.4 3.2 24 14 12.8 w rth elek. 744318180 2.0 2.0 23 10.2 10.2 w rth elek. 7443551200 0.8 27.5 sumida cep125u - 0r8 ou tput ripple voltage ( v rr ) the output ripple voltage is the ac component of the dc output voltage during steady state. for a ripple error of 1.0%, the output capacitor value needed to achieve this tolerance can be determined using the following equation . ( note that an accuracy of 1.0% is only possible during steady state conditions , not during load transients . ) v rr = (0.01) v out output capacitor sel ection the primary objective of the outp ut capacitor is to fa cilitate the reduction of the output voltage ripple ; however, the o utput capacitor also assist s in the output voltage recovery during load transient events. for a given load current step, the output voltage ripple generated during this step event is inversely proportional to the value chosen for the output capacitor. the speed at which the o utput voltage settles during this recovery period depend s on where the crossove r frequency (loop bandwidth) is set . this crossover frequency is determined by the output capacitor, the equivalent series resistance (esr) of the capacitor , and the compensation network. to c alculat e the small signal voltage ripple ( output ripple voltage ) at the steady state operating point , use the following equation: [ ] ? ? ? ? ? ? ? ? ? ? ? ? = ) ( 8 1 esr i v f i c l ripple sw l out where esr is the equivalent series resistance of the output capaci tors. to calculate the output load step , use the following equation : )) ( ( 2 esr i v f i c load droop sw load out ? ? ? ? = where v droop is the amount that v out is allowed to deviate for a given positive load current step ( i load ).
ADP1874/adp1875 data sheet rev. a | page 28 of 44 ceramic capacitors are known to have low esr. however, the re is a trade - off in using the popular x5r capacitor technology because up to 80% of its capa citance m ay be lost due to derating as the voltage applied across the capacitor is increased (see figure 86) . although x7r series capacitors can also be used, the available selection is limited to 22 f max imum . 20 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 0 5 10 15 20 25 30 capacitance charge (%) dc voltage (v dc ) x7r (50v) x5r (25v) x5r (16v) 10f tdk 25v, x7r, 1210 c3225x7r1e106m 22f murata 25v, x7r, 1210 grm32er71e226ke15l 47f murata 16v, x5r, 1210 grm32er61c476ke15l 09347-078 figure 86 . capacitance vs. dc voltage characteristics f or ceramic capacitors electrolytic capacitors satisfy the bulk capacitance requirements for most high current application s . however, b ecause the esr of electrolytic capacitor s is much higher than that of ceramic cap a citors , several mlccs should be mounted in parallel with the electrolytic capacitors to reduce the overall series resistance . compensation network due to its current - mode architecture, the ADP1874 / adp1875 require type ii compensation. t o determine the component values needed for compensation (resistance and capacitance value s), it is necessary to examine th e converters ov erall loop gain ( h ) at the unity gain frequency ( f sw /10) when h = 1 v/v . filt comp out ref cs m z z v v g g h = = v/v 1 ex amining each variable at high frequency enables the unity - gain transfer function to be s implified to provide expression s for the r comp and c comp component va lues. output filter impedance (z filt ) examining the filters transfer function at high frequencies simplifies to out l out l filter c esr r s c esr s r z ) ( 1 1 + + + = at the crossover frequency (s = 2f cross ). esr is the equivalent series resistance of the output capacitor s. error amplifier output impedance (z comp ) assuming that c c 2 is significantly smaller than c comp , c c 2 can be omitted from the output impedance equation of the error amp lifier . the transfer function simplif ies to 2 2 zero cross cross comp comp f f f r z + = and sw cross f f = 12 1 where f zero , the zero frequency , is set to be 1/4 the c ross over frequency for the ADP1874 . error amplifier gain (g m ) the er ror amplifier gain (transconductance) is g m = 500 a /v ( s) current - sense loop gain ( g cs ) the curr ent - sense loop - gain is on cs cs r a g = 1 (a/v) w here : a cs (v/v) is programmable for 3 v/v , 6 v/v , 12 v / v, and 24 v/v (see the programming resistor (res) detect circuit and valley current - limit setting sections ) . r on is the channel impedance of the low er side mosfet . crosso ver frequency the crossover frequency is the f requ ency at which the overall loop (system) gain is 0 db (h = 1 v/v). it is recommended for current - mode converters , such as the ADP1874 , that the user set the cross over frequency between 1/10 and 1/15 the switching frequency. sw cross f f 12 1 = the relat ionship between c comp and f zero (zero frequency ) is as follows : comp comp zero c r f = 2 1 the zero frequency is set to 1/4 the cross over frequency. combining all of the above parameters result s in ( ) ( ) 1 1 1 ) ( 1 2 2 2 2 2 2 + + + + = where esr is the equivalent series r esistance of the output capacito rs. zero comp comp f r c = 2 1
data sheet ADP1874/adp1875 rev. a | page 29 of 44 efficiency considera tion one of the important criteria to consider in constructing a dc - to - dc converter is efficiency. by definition , efficiency is the ratio of the output power to the input power . for high power application s at load currents up to 20 a , t he following are important mosfet parameters that aid in the selection process: ? v gs (th) is the mosfet voltage applied between the gate and the source that starts channel co n duction . ? r ds (on) is t he mosfet on r esistance during channel conduction. ? q g is the total gate charge . ? c n1 is the input capacitance of the upper side switch . ? c n2 is the input capacitance of the lower side switch . the following are the losses experienced thro ugh the external comp onent during normal switching operation: ? channel conduction loss (both the mosfets) ? mosfet driver loss ? mosfet switching loss ? body diode conduction loss (low er side mosfet) ? inductor loss (copper and core loss) channel conduction loss during normal operatio n, the bulk of the loss in efficiency is due to the power dissipated through mosfet channel conduction. power loss through the upper side mosfet is directly pro - portional to the duty - cycle (d) for each switching period, and the power loss through the low er side mosfet is directly proportional to 1 ? d for each switching period. the selection of mosfet s is governed by the maximum dc load current that the converter is expected to deliver. in particular, the selection of the low er side mosfet is dictated by th e maximum load current because a typical high current application employ s duty cycles of less than 50%. therefore , the low er side mosfet is in the on state for most of the switching period. ( ) [ ] 2 1 load n2(on) n1(on) n1,n2(cl) i r d r d p ? + = mosfet driver loss o ther dis sipative element s are the mosfet drivers. the con - tributing factors are the dc current flowing through a driver during operation and the q gate parameter of the external mosfet s. ( ) [ ] ( ) [ ] + + + = ) ( where: c upperfet is the input gate capacitance of the upper side mosfet . c lowerfet is the input gate capacitance of the lower side mosfet . i bias is the dc current flowing into the upper side and lower side drivers. v dr is the driver bias voltage (that is, the low input voltage ( vreg ) minus the rectifier drop (see figure 87) ) . vreg is the bias voltage. 800 720 640 560 480 400 320 240 160 80 300 1000 900 800 700 600 500 400 rectifier drop (mv) switching frequency (khz) +125c +25c ?40c vreg = 2.7v vreg = 3.6v vreg = 5.5v 09347-079 figure 87 . internal rectifier voltage drop vs. switching frequency switching loss the sw node transitions due to the switching activities of th e upper side and lower side mosfet s. this causes removal and replenishing of charge to and from the gate oxide layer of the mosfet , as well as to and from the parasitic capacitance associated with the gate oxide edge overlap and the drain and source termin als. the current that enters and exi ts these charge paths presents additional loss during these transition times. this can be approximately quantified by using the following equation, which represents the time in which charge enters and exits these capacit ive regions : t sw - trans = r gate c total where : c total is the c gd + c gs of the external mosfet . r gate is the g ate input resistance of the external mosfet . the ratio of this time constant to the period of one switching cycle is the multiplying factor to be used in the following expression: 2 - ) ( = or p sw(loss) = f sw r gate c total i load v in 2
ADP1874/adp1875 data sheet rev. a | page 30 of 44 diode conduction loss the ADP1874 / adp1875 employ anti cross - conduction circuitry that prevents the upper side and lower side mosfet s from conducting current simultaneously. this overlap control is beneficial, avoiding large current flow that may lead to irreparable damage to the external components of th e power stage . however , this blanking period comes with the trade - off of a diode conduction loss occurring immediately after the mosfet change states and continuing well into i dle mode. the amount of loss through the body diode of the lower side mosfet dur ing the anti - overlap state is given by the following expression: 2 ) ( ) ( = f load sw loss body loss body v i t t p w here : t body(loss) is the body conduction time ( see figure 88 for dead time periods ) . t sw is the period per switching cycle. v f is the forward drop of the body diode during conduction . ( see the selected external mosfet data sheet for more information about the v f parameter.) 80 72 64 56 48 40 32 24 16 8 2.7 5.5 4.8 4.1 3.4 body diode conduction time (ns) vreg (v) +125c +25c ?40c 1mhz 300khz 09347-080 figure 88 . body diode conduction time vs. low voltage input ( vreg ) inductor lo ss during normal conduction mode, further power loss is caused by the conduction of current thr ough the inductor winding s, which ha ve dc resistance (dcr). typically, larger sized in ductors have smaller dcr values. the inductor core loss is a result of the eddy currents generated within the core material . these eddy currents are induced by the changing flux, which is produced by the current flowing through the windings . the amount of inductor core loss depends on the core material, the flux swing, the freque ncy , and the core volume. ferrite inductors have the lowest core losses , whereas powdered iron inductors have higher core losses. it is recommended to use shielded ferrite core material type inductors with the ADP1874 / adp1875 for a high current , dc - to - dc switching application t o achieve minimal loss and negligible electromagnetic interference (emi) . 2 ) ( load loss dcr i dcr p = + core loss input capacitor sele ction the g oal in selecting an input capacitor is to reduce or minimize input voltage ripple and to reduce the high frequency source impedance, which is essential for a chieving predictable loop stability and transient performance . the problem with using bulk capacit ors , other than their physical geometries , is their lar ge equivalent series resistance (esr) a nd large equivalent series inductance (esl). aluminum electrolytic capacitors have such high esr that they cause undesired input voltage ripple magnitudes and are generally not effective at high switching frequencies . if bulk electrolytic capacitors are used, it is recommended to u se mul t i layered ceramic capacitors (mlcc) in parallel due to their low es r values. this dramatically reduce s the input volta ge ripple a mplitude as long as the mlccs are mounted directly across the drain of the upper side mosfet and the source terminal of the low er side mosfet (see the layout considerations section) . improper placement and mounting of these mlccs may cancel their effectiveness due to stray inductance and an increase in trace impedance . ( ) out out in out max load rms cin v v v v i i ? = , , the m aximum input voltage ripple and maximum input capacitor rms current occur at the end of the duration of 1 ? d while the upper side mosfet is in the off state . t he input capacit or rms current reach es its maximum at t ime d . when calculating the maximum input voltage ripple, account for the esr of the input capacitor as follows : v max,ripple = v ripp + ( i load,max esr ) w here : v ripp is usually 1% of the minimum voltage input. i load,max is the maximum load current . esr is the equivalent series resistance rating of the input capacitor. inserting v max,ripple into the charge balance equation to calculate the mini mum input capacito r requirement gives sw ripple max max load in,min f d d v i c ) 1 ( , , ? = or ripple max sw max load in,min v f i c , , 4 = where d = 50% .
data sheet ADP1874/adp1875 rev. a | page 31 of 44 thermal consideratio ns the ADP1874 / adp1875 are used for dc - to - dc , step down, high current applications that have an on - board controller , an on - board ldo , and on - board mosfet drivers. because applications may requir e up to 20 a of load current and be subjected to high ambient temperature , the selection of external upper side and lo wer side mosfet s must be associated with careful thermal consideration to not exceed the maximum allowable junction temperature of 125c . to avoid permanent or irreparable damage , i f the junction temperature reaches or exceeds 155c , the part enter s therma l shutdown , turning off both external mosfets and is not re - enable d until the junction temperature cools to 140c ( see the on - board low dropout regulator section). in addition, it is important to consider the the r mal impedance of the package. because the ADP1874 / adp1875 employ an on - board ldo, the ac current (fxcxv) consumed by the internal drivers to drive the external m osfets, adds another element of power dissip ation across the internal ldo . equation 3 shows t he power dissipation calculations for the integrated drivers and for the internal ldo. table 9 lists the thermal impedan ce for t he ADP1874 / adp1875 , which are available in a 1 6 - lead q sop . table 9 . thermal impedance for 1 6 - lead q sop parameter thermal impedance 1 6 - lead q sop ja 4 - layer board 104c/w figure 89 specif ies the maximum allowable ambient temperature that can surround the ADP1874 / adp1875 ic for a specified high input voltage (v in ). figure 89 illustrate s the temperature derating conditions for each available switching frequenc y for low, typical , and high output setpoints for the 1 6 - lead q sop package . all temperature derating criteria are based on a maximum ic junction temperature of 125c. 150 30 40 50 60 70 80 90 100 110 120 130 140 5.5 19.0 17.5 16.0 14.5 13.0 11.5 10.0 8.5 7.0 maximum allowable ambient temperature (c) v in (v) v out = 0.8v v out = 1.8v v out = high setpoint 600khz 300khz 1mhz 09347-183 figure 89 . ambient temperature vs. v i n , 4- layer evb, c in = 4.3 nf (uppe r side /lower side mosfet) the maximum junction t emperature allowed for the ADP1874 / adp1875 ic s is 125c. this means that the sum of the ambient temperature (t a ) and the rise in package temperature (t r ), which is c aused by the thermal impedance of the package and the internal power dissipation , should not exceed 125c , as dictated by the following expression: t j = t r t a (1) w here : t j is the maximum junction temperature. t r is the rise in package temperature d ue to the power dissipated from within. t a is the ambient temperature. the rise in package temperature is directly proportional to its thermal impedance characteristics. the following equation represents this proportionality relationship: t r = ja p dr(lo ss) (2) w here : ja i s the thermal resistance of the package from the junction to the outside surface of the die , where it meets the surrounding air. p dr(loss) is the overall power dissipated by the ic. t he bulk of the power dissipated is due to the gate ca pa citance of the external mosfet s and current running through the on - board ldo . t he power loss equation s for the mosfet drivers and internal low dropout regulator ( see the mosfet driver loss section and the efficiency consideration section ) are p dr(loss) = [ v dr ( f sw c upperfet v dr + i bias )] + [ vreg ( f sw c lowerfet vreg + i bias )] (3) where: c upperfet is the input gate capacitance of the upper side mosfet . c lowerfet is the inp ut gate capacitance of the lower side mosfet . i bias is the dc current (2 ma) flowing into the upper side and lower side drivers. v dr is the driver bias voltage ( the low input voltage ( vreg ) minus the rectifier drop (see figure 87) ) . vreg is the ldo output/bias voltage. ) ( ) ( ) ( ) ( bias total sw in loss dr ldo diss i vreg c f vreg v p p + ? + = (4) where: p diss(ldo) is the power dissipated through the pass device in the ldo block across vin and vreg. p dr(loss) is the mosfet driver loss. v in is the high voltage input. vreg is the ldo output voltage and bias voltage. c total is the c gd + c gs of the external mosfet . i bias is the dc input bias current.
ADP1874/adp1875 data sheet rev. a | page 32 of 44 for example, if the external mosfet characteristics are ja ( 16 - lead qsop ) = 104 c / w, f sw = 300 khz, i bias = 2 ma, c upperfet = 3.3 nf, c lowerfet = 3.3 nf, v dr = 4.62 v, a n d vreg = 5.0 v, then the power loss is ( ) [ ] ( ) [ ] )) 002 . 0 0 . 5 10 3 . 3 10 300 ( 0 . 5 ( )) 002 . 0 62 . 4 10 3 . 3 10 300 ( 62 . 4 ( 9 3 9 3 ) ( + + + = + + + = ? ? bias lowerfet sw bias dr upperfet sw dr loss dr i vreg c f vreg i v c f v p = 57.12 mw ) 002 . 0 5 10 3 . 3 10 300 ( ) v 5 v 13 ( ) ( ) ( 9 3 ) ( + ? = + ? = ? bias total sw in ldo diss i vreg c f vreg v p = 55.6 mw mw 6 . 55 mw 13 . 77 ) ( ) ( ) ( + = + = loss dr ldo diss total diss p p p = 132.73 mw the rise in package temperature (for 16- lead qsop ) is mw 05 . 132 c 104 ) ( = = loss dr ja r p t = 13.7 c assuming a maximum ambient tem perature environment of 85c, t j = t r t a = 13.7c + 85c = 98.7c which is below the maximum junction temperature of 125c. design example the adp1 874 / adp1875 are easy to use, requiring only a few design criteria. for example, the example outlined in this section uses only four d esign criteria : v out = 1.8 v , i load = 15 a (pulsing) , v in = 12 v (typical) , and f sw = 300 kh z . input capacitor the maximum input voltage ripple is usually 1% of the minimum input voltage (11.8 v 0.01 = 120 mv). v ripp = 120 mv v max,ripple = v ripp ? ( i load,max esr ) = 120 mv ? (15 a 0.001) = 45 mv mv 105 10 300 4 a 15 4 3 , , = = ripple max sw max load in,min v f i c = 120 f choose five 22 f ceramic capacitors. the overall esr of five 22 f ceramic capacitors is less than 1 m. i rms = i load / 2 = 7.5 a p cin = ( i rms ) 2 esr = (7.5 a) 2 1 m = 56.25 mw inductor determin e inductor ripple current amplitude as follows : 3 load l i i ? = 5 a therefore, calculating for the inductor value v 2 . 13 v 8 . 1 10 300 v 5 ) v 8 . 1 v 2 . 13 ( ) ( 3 ? = ? ? = in,max out sw l out in,max v v f i v v l = 1.03 h the inductor peak current is approximately 15 a + (5 a 0.5) = 17.5 a therefore, an appropriate inductor selection is 1.0 h with dcr = 3.3 m ( wrth elektronik 7443552100) from table 10 with peak current handling of 20 a. 2 ) ( l loss dcr i dcr p = = 0.003 (15 a) 2 = 675 mw current limit programming the v alley current is approximately 15 a ? (5 a 0.5) = 12.5 a assuming a low er side mosfet r on of 4. 5 m and 13 a as the valley current limit from table 7 and figure 71 indicates , a programming resistor (res) of 100 k corr esponds to a n a cs of 24 v / v. choose a programmable resistor of r res = 100 k? for a current - sense gain of 24 v / v. output capacitor a ssum e that a load step of 15 a occurs at the output and no more than 5% output deviation is allowed from the steady state o perating point. in this case , t he ADP1874 advantage is that , because the frequency is pseudo - fixed, the converter is able to respond quickly because of the immediate, though temporary , increase in switching fr equency. v droop = 0.05 1.8 v = 90 mv assuming that the overall esr of the output capacitor ranges from 5 m to 10 m, ) mv 90 ( 10 300 a 15 2 ) ( 2 3 = ? ? = droop sw load out v f i c = 1.11 mf therefore, an appropriate i nductor selection is five 270 f polymer capacitors with a combined esr of 3.5 m.
data sheet ADP1874/adp1875 rev. a | page 33 of 44 assuming an over shoot of 45 mv , d etermine if the output capacitor that was calculated previously is adequate . ( ) ( ) 2 2 2 6 2 2 2 ) 8 . 1 ( ) mv 45 8 . 1 ( ) a 15 ( 10 1 ) ( ) ( ? ? = ? ? ? = ? out ovsht out load out v v v i l c = 1.4 mf choose five 270 f polymer capacitors. the rms current through the output capacitor is a 49 . 1 v 2 . 13 v 8 . 1 10 300 f 1 ) v 8 . 1 v 2 . 13 ( 3 1 2 1 ) ( 3 1 2 1 3 , , = ? = ? = max in out sw out max in rms v v f l v v i the power loss dissipated thro ugh the esr of the output capacitor is p cout = ( i rms ) 2 esr = (1.5 a) 2 1.4 m = 3.15 mw feedback resistor network setup choosing r b = 1 k as an example , c alculate r t as follows: k 2 v 6 . 0 v) 6 . 0 v 8 . 1 ( k 1 = ? = t r compensation network t o calculate r comp , c comp , and c par , the transconductance parameter and the current - sense gain variable are required. the t ransconductance parameter ( g m ) is 500 a/v , and the c urrent - sense loop gain is a/v 33 . 8 005 . 0 24 1 1 = = = on cs cs r a g where a cs and r on are taken from setting up the current limit ( see the programming resistor (res ) detect circuit section and the valley current - limit setting section ). the crossover f requency is 1/12 the switching frequency . 300 k h z/12 = 25 k h z the zero frequency is 1/4 the cross over frequency . 25 k h z/4 = 6 .25 k h z ( ) ( ) cs m ref out l out out l zero cross cross comp g g v v r c esr s c esr r s f f f r 1 1 1 ) ( 1 2 2 2 2 2 2 + + + + = ( ) ( ) 8 . 1 15 3 . 8 10 500 1 6 . 0 8 . 1 0011 . 0 0035 . 0 25 2 1 0011 . 0 ) 0035 . 0 ) 15 8 . 1 (( 25 2 1 25 . 6 25 25 6 2 2 2 2 2 2 + + + + = ? k k k k k r comp = 60.25 k zero comp comp f r c = 2 1 = 3 3 10 25 . 6 10 25 . 60 14 . 3 2 1 = 423 pf loss calculations d uty cycle = 1.8/12 v = 0.15 r on (n2) = 5 .4 m t body(loss) = 20 ns ( body conduction time) v f = 0.84 v ( mosfet f orward voltage ) c in = 3 .3 nf ( mosfet gate input capacitance ) q n1,n2 = 17 nc ( total mosfet gate charge ) r gate = 1.5 ( mosfet gate input resistance ) ( ) [ ] 2 1 load n2(on) n1(on) n1,n2(cl) i r d r d p ? + = = (0.15 0.0054 + 0.85 0.0054) (15 a) 2 = 1.21 5 w 2 ) ( ) ( = f load sw loss body loss body v i t t p = 20 n s 300 10 3 15 a 0.84 2 = 151.2 mw p sw(loss) = f sw r gate c total i load v in 2 = 300 10 3 1.5 ? 3.3 10 ?9 15 a 12 2 = 534.6 m w ( ) [ ] ( ) [ ] )) 002 . 0 0 . 5 10 3 . 3 10 300 ( 0 . 5 ( )) 002 . 0 62 . 4 10 3 . 3 10 300 ( 62 . 4 ( 9 3 9 3 ) ( + + + = + + + = ? ? bias lowerfet sw bias dr upperfet sw dr loss dr i vreg c f vreg i v c f v p = 57.12 mw mw 6 . 55 ) 002 . 0 5 10 3 . 3 10 300 ( ) v 5 v 13 ( ) ( ) ( 9 3 ) ( = + ? = + ? = ? bias total sw in ldo diss i vreg c f vreg v p p cout = ( i rms ) 2 esr = (1.5 a) 2 1.4 m = 3.15 mw 2 ) ( load loss dcr i dcr p = = 0.003 (15 a) 2 = 675 mw p cin = ( i rms ) 2 esr = (7.5 a) 2 1 m = 56.25 mw p loss = p n1,n2 + p body(loss) + p sw + p dcr + p dr + p diss(ldo) + p cout + p cin = 1.215 w + 151.2 mw + 534.6 mw + 57.12 mw + 55.6 + 3.15 mw + 675 mw + 56.25 mw = 2.655 w
ADP1874/adp1875 data sheet rev. a | page 34 of 44 external component r ecommendations the c onfigurations listed in table 10 are with f cross = 1/12 f sw , f zero = ? f cross , r res = 100 k , r bot = 1 k , r on = 5.4 m ? ( bsc042n03 ms g) , vreg = 5 v ( float) , and a maximum load current of 14 a. the adp1875 models listed in table 10 are the psm versions of the device. table 10. external component values marking code ( first line/ second l ine) sap model ADP1874 adp1875 v out (v) v in (v) c in (f) c out (f) l 1 (h) r c (k) c comp (pf) c par (pf) r top (k) ADP1874arqz - 0.3 - r7/ 1874/0.3 1875/0.3 0.8 13 5 22 2 5 560 3 0.72 56.9 620 6 2 0.3 adp1875arqz - 0.3 - r7 1874/0.3 1875/0.3 1.2 13 5 22 2 4 560 3 1.0 56.9 620 6 2 1.0 1874/0.3 1875/0.3 1.8 13 4 22 2 4 270 4 1.2 56.9 470 4 7 2.0 1874/0.3 1875/0.3 2.5 13 4 22 2 3 270 4 1.53 57.6 470 4 7 3.2 1874/0.3 1875/0.3 3.3 13 5 22 2 2 330 5 2.0 56.9 470 47 4.5 1874/0.3 1875/0.3 5 13 4 22 2 330 5 3.27 40.7 680 68 7.3 1874/0.3 1875/0.3 7 13 4 22 2 22 2 + ( 4 47 6 ) 3.44 40.7 680 68 10.7 187 4/0.3 1875/0.3 1.2 16.5 4 22 2 4 560 3 1.0 56.9 620 6 2 1.0 1874/0.3 1875/0.3 1.8 16.5 3 22 2 4 270 4 1.0 56.9 470 4 7 2.0 1874/0.3 1875/0.3 2.5 16.5 3 22 2 4 270 4 1.67 57.6 470 4 7 3.2 1874/0.3 1875/0.3 3.3 16.5 3 22 2 2 330 5 2.00 56.9 510 5 1 4.5 1874/0.3 1875/0.3 5 16.5 3 22 2 2 150 7 3.84 41.2 680 6 8 7.3 1874/0.3 1875/0.3 7 16.5 3 22 2 22 2 + 4 47 6 4.44 40.7 680 68 10.7 ADP1874arqz - 0.6 - r7/ 1874/0.6 1875/0.6 0.8 5.5 5 22 2 4 560 3 0.22 56.2 300 300 0.3 adp1875arqz - 0.6 - r7 1874/0.6 1875/0.6 1.2 5.5 5 22 2 4 270 4 0.47 56.9 2 70 2 7 1.0 1874/0.6 1875/0.6 1.8 5.5 5 22 2 3 270 4 0.47 56.9 2 20 22 2.0 1874/0.6 1875/0.6 2 .5 5.5 5 22 2 3 180 8 0.47 56.9 2 20 22 3.2 1874/0.6 1875/0.6 1.2 13 3 22 2 5 270 4 0.47 56.9 3 60 3 6 1.0 1874/0.6 1875/0.6 1.8 13 5 10 9 3 330 5 0.47 56.2 2 70 27 2.0 1874/0.6 1875/0.6 2.5 13 5 10 9 3 270 4 0.90 57.6 2 40 2 4 3.2 1874/0.6 1875/0.6 3.3 13 5 10 9 2 270 4 1.00 57.6 2 40 2 4 4.5 1874/0.6 1875/0.6 5 13 5 10 9 150 7 1.76 40.7 3 60 3 6 7.3 1874/0.6 1875/0.6 1.2 16.5 3 10 9 4 270 4 0.47 56.9 300 30 1.0 187 4/0.6 1875/0.6 1.8 16.5 4 10 9 2 330 5 0.72 53.6 270 2 7 2.0 1874/0.6 1875/0.6 2.5 16.5 4 10 9 3 270 4 0.90 57.6 2 70 2 7 3.2 1874/0.6 1875/0.6 3.3 16.5 4 10 9 330 5 1.0 53.0 2 70 2 7 4.5 1874/0.6 1875/0.6 5 16.5 4 10 9 4 47 6 2.0 41.2 3 60 3 6 7.3 1874/0.6 1875/0.6 7 16.5 4 10 9 3 47 6 2.0 40.7 3 00 3 0 10.7
data sheet ADP1874/adp1875 rev. a | page 35 of 44 marking code ( first line/ second l ine) sap model ADP1874 adp1875 v out (v) v in (v) c in (f) c out (f) l 1 (h) r c (k) c comp (pf) c par (pf) r top (k) ADP1874arqz - 1.0 - r7/ 1874/1.0 1875/1.0 0.8 5.5 5 22 2 4 270 4 0.22 54.9 200 20 0.3 adp1875arqz - 1.0 - r7 1874/1.0 1875/1.0 1.2 5.5 5 22 2 2 330 5 0.22 49.3 2 20 22 1.0 1874/1.0 1875/1.0 1.8 5.5 3 22 2 3 180 8 0.22 56.9 130 13 2.0 18 74/1.0 1875/1.0 2.5 5.5 3 22 2 270 4 0.22 54.9 130 13 3.2 1874/1.0 1875/1.0 1.2 13 3 10 9 3 330 5 0.22 53.6 200 20 1.0 1874/1.0 1875/1.0 1.8 13 4 10 9 3 270 4 0.47 56.9 1 80 1 8 2.0 1874/1.0 1875/1.0 2.5 13 4 10 9 270 4 0.47 54.9 1 80 1 8 3.2 1874/1.0 1875/1.0 3.3 13 5 10 9 270 4 0.72 56.2 1 80 1 8 4.5 1874/1.0 1875/1.0 5 13 4 10 9 3 47 6 1.0 40.7 220 22 7.3 1874/1.0 1875/1.0 1.2 16.5 3 10 9 4 270 4 0.47 56.9 2 70 2 7 1.0 1874/1.0 1875/1.0 1.8 16.5 3 10 9 3 270 4 0.47 56.9 2 2 0 2 2 2.0 1874/1.0 1875/1.0 2.5 16.5 4 10 9 3 180 8 0.72 56.9 200 20 3.2 1874/1.0 1875/1.0 3.3 16.5 4 10 9 270 4 0.72 56.2 180 18 4.5 1874/1.0 1875/1.0 5 16.5 3 10 9 3 47 6 1.2 40.7 220 22 7.3 1874/1.0 1875/ 1.0 7 16.5 3 10 9 22 2 + 47 6 1.2 40.7 180 18 10.7 1 see the inductor selection section and table 11. 2 22 f murata 25 v, x7r, 1210 grm32er71e226ke15l (3.2 mm 2.5 mm 2.5 mm). 3 560 f panasonic ( sp - series ) 2 v, 7 m , 3.7 a eefue0d561lr ( 4.3 mm 7.3 mm 4.2 mm ). 4 270 f panasonic (sp - series) 4 v, 7 m , 3.7 a eefue0g271lr ( 4.3 mm 7.3 mm 4.2 mm ). 5 330 f panasonic (sp - series) 4 v, 12 m , 3.3 a eefue0g331r ( 4.3 mm 7.3 mm 4.2 mm ). 6 47 f murata 16 v, x5r, 12 10 grm32er61c476ke15l (3.2 mm 2.5 mm 2.5 mm). 7 150 f panasonic (sp - series) 6.3 v, 10 m , 3.5 a eefue0j151xr ( 4.3 mm 7.3 mm 4.2 mm ). 8 180 f panasonic (sp - series) 4 v, 10 m , 3.5 a eefue0g181xr ( 4.3 mm 7.3 mm 4.2 mm ). 9 10 f tdk 25 v, x7r, 1 210 c3225x7r1e106m. table 11. recommended inductors l (h) dcr (m) i sat (a) dimension (mm) manufacturer model number 0.12 0.33 55 10.2 7 w rth elek tronik 744303012 0.22 0.33 30 10.2 7 w rth elektronik 744303022 0.47 0.8 50 14.2 12.8 w rth elektronik 744355147 0.72 1.65 35 10.5 10.2 w rth elektronik 74 4325072 0.9 1.6 32 14 12.8 w rth elektronik 744318120 1.2 1.8 25 10.5 10.2 w rth elektronik 744325120 1.0 3. 8 16 10.2 10.2 w rth elektronik 7443552100 1.4 3.2 24 14 12.8 w rth elektronik 744318180 2.0 2.6 23 10.2 10.2 w rth elektronik 74435 5 12 00 0.8 27.5 sumida cep125u - 0r8 table 12. recommended mosfet s v gs = 4.5 v r on (m) i d (a) v ds (v) c in (nf) q total (nc) package manufacturer model number upper side mosfet (q1/q2) 5.4 47 30 3.2 20 pg - tdson8 infineon bsc042n03 ms g 10.2 53 30 1.6 10 pg - tdson8 infineon bsc080n03 ms g 6.0 19 30 35 so -8 vishay si4842dy 9 14 30 2. 4 25 so -8 international rectifier irf7811 low er side mosfet (q3/q4) 5.4 47 30 3.2 20 pg - tdson8 infineon bsc042n03 ms g 10.2 82 30 1.6 10 pg - tdson8 infineon bsc080n03 ms g 6.0 19 30 35 so -8 vishay si4842dy
ADP1874/adp1875 data sheet rev. a | page 36 of 44 layout consideration s t he performance of a dc - to - dc converter depends highly on how the voltage and current paths are configured on the printed circuit board (pcb) . optimizing the placement of sensitive analog and power components is essential to minimize output ripple, maintain tight regulation sp ecifications , and reduce pwm jitter and electromagnetic interference. figure 90 shows the schematic of a typical ADP1874 / adp1875 used for a high current application. blue traces denote high current pathways. vin, pgnd , and v out tra ces should be wide and possibly replicated, descending down into the multiple layers. vias should populate , mainly around the positive and negat ive terminal s of the input and output capacitors , alongside the source of q1/q2, the drain of q3/q4, and the inductor . 10k? v reg murata: (high voltage input capacitors) 22f, 25v, x7r, 1210 grm32er71e226ke15l panasonic: (output capacitors) 270f, sp-series, 4v, 7m? eefue0g271lr infineon mosfets: bsc042n03ms g (lower side) bsc080n03ms g (upper side) wrth inductors: 1h, 3.8m?, 16a 7443552100 q3 q4 q1 q2 high voltage input v in = 12v c bst 100nf v out = 1.8v, 15a c3 22f c4 22f c5 22f c6 22f c7 22f c8 n/a c9 n/a c23 270f + c22 270f + c21 270f + c20 270f + c27 n/a c14 to c19 n/a + c26 n/a + c25 n/a + c24 n/a + 1.0h r snb 2? c snb 1.5nf r top 2k? r7 10k? r bot 1k? v out 1 vin 16 bst 2 comp 15 sw 3 en 14 drvh 5 gnd 12 drvl ADP1874/ adp1875 c c 430pf c par 53pf r c 57k? c1 1f c vin 22f c2 0.1f jp3 r res 100k? 4 fb 13 pgnd 6 res 11 pgood 7 vreg 10 ss 8 vreg_in 9 track 5k? v reg c ss 34nf v reg 09347-081 figure 90 . ADP1874 / adp1875 high current evaluation board schematic (blue traces indicate high current paths ) 09347-092 input capacitors are mounted close to drain of q1/q2 and source of q3/q4 separate analog ground plane for compensation and feedback resistors sensitive analog components located far from noisy power section output capacitors are mounted at rightmost area of evaluation board figure 91 . overall layout of the ADP1874 / adp1875 high current evaluation board
data sheet ADP1874/adp1875 rev. a | page 37 of 44 09347-093 figure 92 . layer 2 of ADP1874 / adp1875 evaluation board 09347-094 top resistor feedback tap vout sense tap line extending back to the top resistor in the feedback divider network. this overlaps with pgnd sense tap line extending to the analog ground plane figure 93 . layer 3 of ADP1874 / adp1875 evaluation board
ADP1874/adp1875 data sheet rev. a | page 38 of 44 09347-095 bottom resistor tap to analog ground plane pgnd sense tap from negative terminals of the output bulk capacitors. this track placement should be directly below the vout sense line of layer 3. figure 94 . layer 4 (bottom layer) of adp187 4 / adp1875 evaluation board ic section (left sid e of evaluation boar d) a dedicated plane for the analog ground plane (gnd) should be separate from the main power ground plane (pgnd). with the shortest path p ossible, connect the analog ground plane to the gnd pin (pin 5 ). this plane should be on only the top layer of the evaluation board. to avoid crosstalk interference, there should not be any other voltage or current pathway directly below this plane on laye r 2, layer 3, or layer 4. connect the negative terminals of all sensitive analog components to the analog ground plane. examples of such sensitive analog components include the resistor dividers bottom resistor, the high frequency bypass capacitor for bia sing (0.1 f), and the compensation network. mount a 1 f bypass capacitor directly across the vreg pin (pin 7 ) and the pgnd pin (pin 13 ). in addition, a 0.1 f should be tied across the vreg pin (pin 7 ) and the gnd pin (pin 5 ). power section as shown in figure 91 , an appropriate configuration to localize large current transfer from the high voltage input (v in ) to the output (v out ) and then back to the power ground is to put the v in plane on the left, the output p lane on the right, and the main power ground plane in between the two. current transfers from the input capacitors to the output capacitors, through q1/q2, during the on state (see figure 95 ). the direction of this current (yellow arrow) is maintained as q1/q2 turns off and q3/q4 turns on. when q3/q4 turns on, the current direction continues to be maintained ( yellow arrow) as it circles from the bulk capacitor power ground terminal to the output capacitors, through q3/q4. arranging the power planes in this manner minimizes the area in which changes in flux occur if the current through q1/q2 stops abruptly. sudden changes in flux, usually at the source terminals of q1/q2 and the drain terminal of q3/q4, cause large d v /dt at the sw node. the sw node is near the top of the evaluation board. the sw node should use the least amount of area possible and be away from any sensitive analog circuitry and components . this is because the sw node is where most sudden changes in f lux density occur. when possible, replicate this pad onto layer 2 and layer 3 for thermal relief and eliminate any other voltage and current pathways directly beneath the sw node plane. populate the sw node plane with vias, mainly around the exposed pad of the inductor terminal and around the perimeter of the source of q1/q2 and the drain of q3/q4. the output voltage power plane (v out ) is at the right most end of the evaluation board. this plane should be replicated, descending down to multiple layers with vias surrounding the inductor terminal and the positive terminals of the output bulk capacitors. ensure that the negative terminals of the output capacitors are placed close to the main power ground (pgnd), as previously mentioned. all of these points form a tight circle (component geometry permitting) that minimizes the area of flux change as the event switches between d and 1 ? d. 09347-086 figure 95 . primary current pathways during the on state of the upper side mosfet (left arrow) and the on state of the lower side mosfet (right arrow)
data sheet ADP1874/adp1875 rev. a | page 39 of 44 differential sensing because the ADP1874 / adp1875 operate in valley current - mode control, a differential voltag e reading is taken across the drain and source of the lower side mosfet. the drain of the lower side mosfet should be connected as close as possible to the sw pin (pin 15 ) of the ic. likewise, the source should be connected as close as possible to the pgnd pin (pin 13 ) of the ic. when possible, both of these track lines should be narrow and away from any other active device or voltage/current path. 09347-087 layer 1: sense line for sw (drain of lower mosfet) layer 1: sense line for pgnd (source of lower mosfet) pgnd sw figure 96 . drain/source tracking tapping of the lower side mosfet for cs amp diffe rential sensing (yellow sense line on layer 2) . differential sensing should also be employed between the outermost output capacitor and the feedback resistor divider (see figure 93 and figure 94 ). connect the positive terminal of the output capacitor to the top resistor (r t ). connect the negative terminal of the output capacitor to the negative terminal of the bottom resistor, which connects to the analog ground plane as wel l. both of these track lines, as previously mentioned, should be narrow and away from any other active device or voltage/ current path.
ADP1874/adp1875 data sheet rev. a | page 40 of 44 typical application circuits 1 2 a, 300 k h z high current applica tion circuit 10k? v reg murata: (high voltage input capacitors) 22f, 25v, x7r, 1210 grm32er71e226ke15l panasonic: (output capacitors) 270f, sp-series, 4v, 7m? eefue0g271lr infineon mosfets: bsc042n03ms g (lower side) bsc080n03ms g (upper side) wrth inductors: 1.2h, 2.00m?, 20a 744325120 q3 q4 q1 q2 high voltage input v in = 12v c bst 100nf v out = 1.8v, 12a c3 22f c4 22f c5 22f c6 22f c7 22f c8 n/a c9 n/a c23 270f + c22 270f + c21 270f + c20 270f + c27 n/a c14 to c19 n/a + c26 n/a + c25 n/a + c24 n/a + 1.2h r snb 2? c snb 1.5nf r top 2k? r7 10k? r bot 1k? v out 1 vin 16 bst 2 comp 15 sw 3 en 14 drvh 5 gnd 12 drvl ADP1874/ adp1875 c c 560pf c par 56pf r c 49.3k? c1 1f c vin 22f c2 0.1f jp3 r res 100k? 4 fb 13 pgnd 6 res 11 pgood 7 vreg 10 ss 8 vreg_in 9 track 5k? v reg c ss 34nf v reg 09347-088 figure 97 . ap plication circuit for 12 v input, 1.8 v output, 12 a, 300 khz (q2/q4 no connect) 5.5 v input, 600 k h z application circuit 10k? v reg murata: (high voltage input capacitors) 22f, 25v, x7r, 1210 grm32er71e226ke15l panasonic: (output capacitors) 180f, sp-series, 4v, 10m? eefue0g181xr infineon mosfets: bsc042n03ms g (lower side) bsc080n03ms g (upper side) wrth inductors: 0.47h, 0.8m?, 30a 744355147 q3 q4 q1 q2 high voltage input v in = 5.5v c bst 100nf v out = 2.5v, 12a c3 22f c4 22f c5 22f c6 22f c7 22f c8 n/a c9 n/a c23 n/a + c22 180f + c21 180f + c20 180f + c27 n/a c14 to c19 n/a + c26 n/a + c25 n/a + c24 n/a + 1.2h r snb 2? c snb 1.5nf r top 3.2k? r7 10k? r bot 1k? v out 1 vin 16 bst 2 comp 15 sw 3 en 14 drvh 5 gnd 12 drvl ADP1874/ adp1875 c c 220pf c f 22pf r c 56.9k? c1 1f c vin 22f c2 0.1f jp3 r res 100k? 4 fb 13 pgnd 6 res 11 pgood 7 vreg 10 ss 8 vreg_in 9 track 5k? v reg c ss 34nf v reg 09347-089 figure 98 . application circuit for 5.5 v input, 2.5 v output, 12 a, 600 khz (q2/q4 no connect)
data sheet ADP1874/adp1875 rev. a | page 41 of 44 300 k h z high current applica tion circuit 10k? v reg murata: (high voltage input capacitors) 22f, 25v, x7r, 1210 grm32er71e226ke15l panasonic: (output capacitors) 270f, sp-series, 4v, 7m? eefue0g271lr infineon mosfets: bsc042n03ms g (lower side) bsc080n03ms g (upper side) wrth inductors: 1.2h, 2.00m?, 20a 744325120 q3 q4 q1 q2 high voltage input v in = 13v c bst 100nf v out = 1.8v, 12a c3 22f c4 22f c5 22f c6 22f c7 22f c8 n/a c9 n/a c23 270f + c22 270f + c21 270f + c20 270f + c27 n/a c14 to c19 n/a + c26 n/a + c25 n/a + c24 n/a + 1.2h r snb 2? c snb 1.5nf r top 2k? r7 10k? r bot 1k? v out 1 vin 16 bst 2 comp 15 sw 3 en 14 drvh 5 gnd 12 drvl ADP1874/ adp1875 c c 560pf c par 56pf r c 49.3k? c1 1f c vin 22f c2 0.1f jp3 r res 100k? 4 fb 13 pgnd 6 res 11 pgood 7 vreg 10 ss 8 vreg_in 9 track 5k? v reg c ss 34nf v reg 09347-090 figure 99 . application circuit for 13 v input, 1.8 v output, 12 a, 300 khz (q2/q4 no connect)
ADP1874/adp1875 data sheet rev. a | page 42 of 44 outline dimensions compliant t o jedec st andards mo-137-ab controllin g dimension s are in inches; millimeter dimension s (in p arenthese s) are rounded-o ff inch equiv alents for reference onl y and are not appropria te for use in design. 16 9 8 1 s e a t i n g p l a n e 0 . 0 1 0 ( 0 . 2 5 ) 0 . 0 0 4 ( 0 . 1 0 ) 0 . 0 1 2 ( 0 . 3 0 ) 0 . 0 0 8 ( 0 . 2 0 ) 0 . 0 2 5 ( 0 . 6 4 ) b s c 0 . 0 4 1 ( 1 . 0 4 ) r e f 0 . 0 1 0 ( 0 . 2 5 ) 0 . 0 0 6 ( 0 . 1 5 ) 0 . 0 5 0 ( 1 . 2 7 ) 0 . 0 1 6 ( 0 . 4 1 ) 0 . 0 2 0 ( 0 . 5 1 ) 0 . 0 1 0 ( 0 . 2 5 ) 8 0 copla narit y 0.004 (0.10) 0 . 0 6 5 ( 1 . 6 5 ) 0 . 0 4 9 ( 1 . 2 5 ) 0 . 0 6 9 ( 1 . 7 5 ) 0 . 0 5 3 ( 1 . 3 5 ) 0 . 1 9 7 ( 5 . 0 0 ) 0 . 1 9 3 ( 4 . 9 0 ) 0 . 1 8 9 ( 4 . 8 0 ) 0 . 1 5 8 ( 4 . 0 1 ) 0 . 1 5 4 ( 3 . 9 1 ) 0 . 1 5 0 ( 3 . 8 1 ) 0 . 2 4 4 ( 6 . 2 0 ) 0 . 2 3 6 ( 5 . 9 9 ) 0 . 2 2 8 ( 5 . 7 9 ) 01-28- 2008-a figure 100 . 16 - lea d shrink small outline package [qso p] (rq - 16) dimensions shown in inches and ( millimeters ) ordering guide model 1 temperature range package description package option branding ( first line/ second line) ADP1874 ar q z - 0.3 -r7 ?40c to +125c 1 6 - lead shrink small outline package [q sop ] rq -16 187 4/0.3 ADP1874 ar q z - 0.6 -r7 ?40c to +125c 16- lead shrink small outline package [qsop] rq -16 1874/0.6 ADP1874 ar q z - 1.0 -r7 ?40c to +125c 16- lead shrink small outline package [qsop] rq -16 1874/1.0 adp187 4 - 0.3 - evalz evaluation board ADP1874 - 0.6- evalz e valuation board ADP1874 - 1.0- evalz evaluation board adp1875arqz - 0.3 -r7 ?40c to +125c 16- lead shrink small outline package [qsop] rq -16 1875/0.3 adp1875arqz - 0.6 -r7 ?40c to +125c 16- lead shrink small outline package [qsop] rq -16 1875/0.6 adp1875a rqz - 1.0 -r7 ?40c to +125c 16- lead shrink small outline package [qsop] rq -16 1875/1.0 adp1875 - 0.3- evalz evaluation board adp1875 - 0.6- evalz evaluation board adp1875 - 1.0- evalz evaluation board 1 z = rohs compliant part.
data sheet ADP1874/adp1875 rev. a | page 43 of 44 notes
ADP1874/adp1875 data sheet rev. a | page 44 of 44 notes ? 2011 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09347 - 0 - 7/12(a)

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