combined with inexpensive serial memory, the neuron 5000 processor provides a lower-cost, higher-performance lonworks solution than those based on previous-generation neuron 3120? and neuron 3150? chips. the neuron 5000 processor incorporates communication and control func - tions on a single chip, in both hardware and frmware, to facilitate the design of a l on w orks device. its fexible 5-pin communications port can be confg - ured to interface with a wide variety of media transceivers including twisted- pair, rf, ir, fber-optics, and coaxial at a wide range of data rates. features ? 3.3v operation. ? higher-performance neuron ? core internal system clock scales up to 80 mhz. ? enables lower-cost device designs. ? serial memory interface for inexpensive external eeprom and fash non-volatile memories. ? supports up to 254 network variables (nvs) and 127 aliases. ? user programmable interrupts provide faster response time to external events. ? includes hardware uart with 16-byte receive and transmit fifos. ? 7mm x 7mm 48-pin qfn package. ? 5-pin network communications port with 3.3v drive and 5v-tolerant pins. ? 12 i/o pins with 35 programmable standard i/o models. ? supports up to 42kb of application code space. ? 64kb ram (44kb user accessible) and 16kb rom on-chip memories. ? unique 48-bit neuron id in every device for network installation and management. ? -40c to +85c operating temperature range. neuron ? 5000 processor the next-generation neuron chip for l on w orks ? control networks www.echelon.com ?
? www.echelon.com description the neuron 5000 processor includes 3 independent 8-bit logical processors to manage the physical mac layer, the network, and the user application. these are called the media-access control (mac) processor, the network (net) processor, and the application (app) processor, respectively (see figure 1). at higher system clock rates, there is also a fourth processor to handle interrupts. i / o comm port external tr ansformer jt ag 5 xin xout rst~ svc~ clock, reset, and service irq cpu app cpu net cpu mac cpu serial memory interface nvm (spi or i 2 c) rom (16k x 8) ram (64k x 8) / / 12 2-6 5 / figure 1: neuron 5000 processor backward compatibility the pins for the neuron 5000 processors communications port drive a 3.3v signal and are 5v input-tolerant. thus, the neuron 5000 processor is compatible with 3.3v transceivers and with 5v transceivers that have ttl-compatible input. the neuron 5000 processor is compatible with tp/xf-1250 and eia-485 channels, and can be used with the lonworks lpt-11 link power transceiver. it also supports a variety of other channels used with previous-generation neuron chips, such as rf, ir, fber-optic, and coaxial. it does not, however, support a tp/xf-78 channel. to support a tp/ft-10 channel, use an echelon free topology smart transceiver (ft 5000 smart transceiver); to support a pl-20 power line channel, use an echelon power line smart transceiver (pl 3120/3150/3170 smart transceiver). echelons smart transceivers integrate the transceiver for the channel type and the neuron core into a single chip, which enables smaller designs and provides cost savings. the neuron core in the neuron 5000 processor uses the same instruction set and architecture as the previous-generation neuron core, with 2 new additional instructions for hardware multiplication and division. the series 5000 neuron core is source code compatible with applications written for the series 3100 neuron core. applications written for the series 3100 neuron core must be recompiled with the nodebuilder ? fx development tool or the mini fx evaluation kit before they can be used with the neuron 5000 processor. the neuron 5000 processor uses neuron frmware version 19. firmware versions prior to version 19 are not compatible with the neuron 5000 processor. the neuron frmware is pre-programmed into the on- chip rom. the neuron 5000 processor can also be confgured to read newer frmware from external memories, allowing the frmware to be upgraded over time. enhanced performance faster system clock. the internal system clock for the neuron 5000 processor can be user-confgured to run from 5mhz to 80mhz. the required external crystal provides a 10mhz clock frequency, and an internal pll boosts the frequency to a maximum of 80mhz as the internal system clock speed. the previous-generation neuron 3120/3150 core divided the external oscillator frequency by two to create the internal system clock. hence, a neuron 3120/3150 core running with a 10mhz external crystal had a 5mhz internal system clock. a neuron 5000 processor running with an 80mhz internal clock is thus 16 times faster than a 10mhz neuron 3120/3150 core running with a 5mhz internal system clock. the 5mhz system clock mode in the neuron 5000 processor provides backward compatibility to support time-critical applications designed for the 10mhz neuron 3150 or neuron 3120 processor. the neuron core inside the neuron 5000 processor includes a built-in hardware multiplier and divider to increase the performance of arithmetic operations. support for more network variables. because it uses neuron system frmware version 19, the neuron 5000 processor supports applications with up to 254 network variables and 127 aliases for neuron hosted devices (devices without a host microprocessor). a series 3100 neuron chip or smart transceiver with neuron frmware version 15 or earlier supports up to 62 network variables and 62 aliases for neuron hosted devices. series 3100 chips with neuron frmware version 16 or later support up to 254 network variables. you must use the nodebuilder fx development tool to take advantage of 254 network variables. interrupts. the neuron 5000 processor lets developers defne application interrupts to handle asynchronous events triggered by selected state changes on any of the 12 i/o pins, by on-chip hardware timer-counter units, or by an on-chip high- performance hardware system timer. an application uses the neuron c interrupt() clause to defne the interrupt condition and the interrupt task that handles the condition. the neuron c program runs the interrupt task whenever the interrupt condition is met. see the neuron c programmers guide for more information about writing interrupt tasks and handling interrupts. jtag . the neuron 5000 processor provides an interface for the institute of electrical and electronics engineers (ieee) standard test access port and boundary- scan architecture (ieee 1149.1-1990) of the joint test action group (jtag) to allow a series 5000 chip to be included in the boundary-scan chain for device production tests. a boundary scan description language (bsdl) fle for the neuron 5000 processor can be downloaded from echelons web site. communications port the neuron 5000 processor includes a versatile 5-pin communications port that can be confgured in two ways: 3.3 v single-ended mode and 3.3 v special- purpose mode. in single-ended mode, pin cp0 is used for receiving serial data, pin cp1 for transmitting serial data, and pin cp2 for enabling an external transmitter. data is communicated using diferential manchester encoding. in special-purpose mode, pin cp0 is used for receiving serial data, pin cp1 for transmitting serial data, pin cp2 transmits a bit clock, and pin cp4 transmits a frame clock for use by an external intelligent transceiver. in this mode, the external transceiver is responsible for encoding and decoding the data stream. unlike the neuron 3120/3150 chips, the neuron 5000 processor does not support the diferential mode confguration for the communications port. thus, devices that require diferential mode transceiver types must be redesigned for a neuron 5000 processor to use single-ended mode with external circuitry to provide single-ended to diferential mode conversions. see the series 5000 chip data book and the connecting a neuron 5000 processor to an external transceiver engineering bulletin for more information . any 3.3v transceiver or a 5v transceiver with ttl-compatible inputs can be used with the neuron 5000 processor because the communications port has pins that are 5v tolerant and drive a 3.3v signal. common transceiver types that can be used with a neuron 5000 processor include twisted-pair, rf, ir, fber-optic, and coaxial.
www.echelon.com ? i/o pins and counters the neuron 5000 processor provides 12 bidirectional i/o pins that are 5v tolerant and can be confgured to operate in one or more of 35 predefned standard input/ output models. the chip also has two 16-bit timer/counters that reduce the need for external logic and software development. memory architecture the neuron 5000 processor uses inexpensive external serial eeprom and fash memories for non-volatile application and data storage, and optionally for future neuron frmware upgrades. it has 16kb of rom and 64kb (44 kb user-accessible) of ram on the chip. it has no on-chip non-volatile memory (eeprom or fash) for application use. each chip, however, contains its unique neuron identifer (neuron id) in an on-chip, non-volatile, read-only memory. the application code and confguration data are stored in the external non-volatile memory (nvm) and copied into the internal ram during device reset; the instructions then execute from internal ram. writes to nvm are shadowed in the internal ram and pushed out to external nvm by the neuron frmware (see figure 1). the application does manage nvm directly. external memories supported . the neuron 5000 processor supports two serial interfaces for accessing of-chip non-volatile memories: serial inter-integrated circuit (i 2 c) and serial peripheral interface (spi). eeprom and fash memory devices can use either the i 2 c interface or the spi interface; fash memory devices must use the spi interface . external serial eeproms and fash devices, which are inexpensive and come in very small form factors, are available from many vendors. the neuron 5000 processor requires at least 2kb of of-chip memory available in an eeprom device to store the con- fguration data. the application code can be stored either in the eeprom (by using a larger-capacity eeprom device) or in a fash memory device used in addition to the 2kb (minimum) eeprom. thus, the external memory for a neuron 5000 processor has one of the confgurations listed in table 1: confgu - ration eeprom flash comments i 2 c spi spi 1 ? a single i 2 c eeprom memory device, from 2kb to 64kb in size. confgu - ration eeprom flash comments i 2 c spi spi 2 ? ? one i 2 c eeprom (at least 2kb in size, up to 64kb in size, but the system uses only the frst 2kb of the eeprom memory). one spi fash memory device. 3 ? a single spi eeprom memory device, from 2kb to 64kb in size. 4 ? ? one spi eeprom (at least 2kb in size, up to 64kb in size, but the system uses only the frst 2kb of the eeprom memory). one spi fash memory device. table 1: allowed external memory device confgurations as table 1 shows, the neuron 5000 processor supports using a single eeprom memory device, or a single eeprom memory device plus a single fash memory device. if the neuron 5000 processor detects an external fash memory device, the fash memory represents the entire user non- volatile memory for the device. that is, any additional eeprom memory beyond the mandatory 2kb is not used. using the i 2 c interface. when using the i 2 c interface for external eeprom, the neuron 5000 processor is always the master i 2 c device (see figure 2). the clock speed supported for the i 2 c serial memory interface is 400khz (fast i 2 c mode). the i 2 c memory device must specify i 2 c address 0. both 1-byte and 2-byte address modes are supported, but 3-byte addressing mode is not. sd a 3.3 v _c s1 ~ miso sc l i 2 c sl av e ( eepr om ) series 5000 chip figure 2: using the i 2 c interface for external nvm eeprom memory using the spi interface . the neuron 5000 processor is always the master spi device; any external nvm devices are always slave devices. the neuron 5000 processor can support up to two spi slave devices from the serial memory interface: one eeprom device at cs0~ and one fash device at cs1~ (see figure 3). the neuron 5000 processor supports 2-byte addressing mode for spi eeprom devices, but does not support 3-byte addressing. the neuron 5000 processor runs the spi protocol from the serial memory interface at 2.5mhz and supports spi mode 0. in mode 0, the base value of the clock is zero; the data is read on the clocks rising edge and changed on the clocks falling edge. most external nvms support spi modes 0 and 3. sp i sl av e (e epro m) sc k mo si mi so sp i sl av e (f la sh ) cs 0~ sd a_ cs 1~ series 5000 chip figure 3: using the spi interface for external nvm memories using both i 2 c and spi interfaces. figure 4 shows a neuron 5000 processor that includes both an i 2 c memory device (a 2kb eeprom device) and a spi memory device (a fash memory device). although both eeprom and fash memory share the sda_cs1~ pin, there is no confict because only one of them can be active at a time. sda is an active high signal and cs1~ is an active low signal. while small applications could use eeprom both for application code and confguration data, larger applications might fnd it economical to use a small eeprom for confguration data and a fash device for application code. the choice between eeprom and fash can be afected by multiple factors, including: ? use of a single external memory versus two memories. ? cost comparison between a large eeprom device and a combination of a small eeprom and large fash devices. ? use of non-volatile variables by the application, which can require a large number of writes to the device.
www.echelon.com ? sc k mo si mi so cs 0~ sd a_ cs 1~ sc l i 2 c sl av e (e epro m) spi sl av e (f la sh ) series 5000 chip 3.3 v figure 4: using both i 2 c and spi interfaces for external nvm memories memory devices supported. the neuron 5000 processor supports any eeprom device that uses the spi or i 2 c protocol, and meets the clock speed and addressing requirements described above. while all eeprom devices have a uniform write procedure, fash devices from various manufacturers difer slightly in their write procedure. thus, a small library routine is stored in the external eeprom device that helps the system write successfully to the external fash device. echelon has qualifed the following spi fash memory devices for use with the neuron 5000 processor: ? atmel ? at25f512b 512-kilobit 2.7-volt minimum spi serial flash memory. ? numonyx? m25p05-a 512-kbit, serial fash memory, 50mhz spi bus interface. ? silicon storage technology sst25vf512a 512 kbit spi serial flash. ? additional devices may be qualifed in the future. memory map. a neuron 5000 processor has a memory map of 64kb. a neuron c application program uses this memory map to organize its memory and data access. the memory map is a logical view of device memory, rather than a physical view, because the chips processors only directly access ram. the memory map divides the neuron 5000 processors physical 64kb ram into the following types of logical memory, as shown in figure 5: ? system frmware image (stored in on-chip rom or external nvm). ? on-chip ram or nvm. memory ranges for each are confgurable within the device hardware template. the non-volatile memory represents the area shadowed from external nvm into the ram. ? on-chip ram for stack segments and ramnear data. ? mandatory external eeprom that holds confguration data and non- volatile application variables. ? reserved space for system use. if a 64kb external serial eeprom or fash device is used, the maximum allowed size of application code is 42kb as defned by extended nvm area in the memory map. an additional 16kb of the remaining space can hold an external system frmware image, in case a future frmware upgrade is required. re se rv ed ma n dat or y eepr om on -c hi p ra m ex t ended me mo ry (c onf i gur abl e as : ex t ended ra m or no n- vo la t ile me mo ry ) on -c hi p ro m 0x 0000 to 0x 3 fff 0x 4000 to 0x e7 ff 0x e 800 to 0x e fff 0x f0 00 to 0x f7 ff 0x f8 00 to 0x ffff 2 kb 2 kb 2 kb 42 kb 16 kb figure 5: ft 5000 smart transceiver memory map programming memory devices. because the neuron 5000 processor does not have any on-chip user-accessible nvm, only the external serial eeprom or fash devices need to be programmed with the application and confguration data. the memory devices can be programmed in any of the following ways: in-circuit programming on the board. over the network. pre-programming before soldering on the board. migration considerations most device designs that use the previous- generation neuron 3120 or neuron 3150 chip can transition to using the neuron 5000 processor. however, because the supply voltage and memory architecture of neuron 3120/3150 chips and neuron 5000 processors are diferent, the transition requires a hardware redesign of the boards. the recommended migration path for devices based on a neuron chip depends on the transceiver type used with the neuron chip, as shown in table 2. current transceiver type used equivalent series 5000 design comments ftt-10a transceiver ft 5000 smart transceiver plus ft-x3 communications transformer use an ft 5000 smart transceiver for tp/ft-10 channels. eia-485 transceiver neuron 5000 processor plus eia-485 transceiver or (if possible) ft 5000 smart transceiver plus ft-x3 communications transformer if your design is fexible enough to allow either an eia-485 channel or a tp/ft-10 channel, use the ft 5000 smart transceiver with the tp/ft-10 channel. tpt twisted pair transceiver module (for a tp/xf-1250 channel type) neuron 5000 processor plus tpt/xf-1250 twisted pair transceiver module (for a tp/xf-1250 channel type) the neuron 5000 processor must be confgured to operate in 3.3v single-ended mode with the tpt twisted pair transceiver module and external circuitry must be added for single-ended to differential mode conversion. lonworks lpt-11 link power transceiver neuron 5000 processor plus lpt-11 link power transceiver the neuron 5000 processor must be confgured to operate in 3.3v single-ended mode with the lpt-11 link power transceiver. other transceiver type neuron 5000 processor plus other transceiver type the neuron 5000 processor can connect to other transceiver types for the supported channel types, but more hardware design work may be required. table 2: migration for devices with neuron chips see the series 5000 chip data book and the connecting a neuron 5000 processor to an external transceiver engineering bulletin for more information about migrating device designs for neuron 3120/3150 chips to neuron 5000 processors.
pin name pin number type description cp0 32 communi - cations single-ended mode: receive serial data special purpose mode: receive serial data agnd 33 ground ground cp1 34 communi - cations single-ended mode: transmit serial data special purpose mode: transmit serial data nc 35 n/a do not connect gnd 36 ground ground cp2 37 communi - cations single-ended mode: external transceiver enable special purpose mode: bit clock cp3 38 communi - cations do not connect cp4 39 communi - cations single-ended mode: collision detect special purpose mode: frame clock cs0~ 40 digital i/o spi slave select 0 (cs0~, active low) (for external memory connection only) vdd3v3 41 power 3.3 v power vdd3v3 42 power 3.3 v power sda _cs1~ 43 digital i/o i 2 c: serial data (sda) spi: slave select 1 (cs1~, active low) (for external memory connection only) vdd1v8 44 power 1.8 v power input (from internal voltage regulator) scl 45 digital i/o i 2 c: serial clock (scl) (for external memory connection only) miso 46 digital i/o spi master input, slave output (miso) (for external memory connection only) sck 47 digital i/o spi serial clock (sck) (for external memory connection only) www.echelon.com ? end-to-end solutions a typical neuron 5000 processor-based device requires a power source, crystal, external memory, and an i/o interface to the device being controlled (see figure 6 for a typical neuron 5000 processor-based device). echelon provides all of the building blocks required to successfully design and feld cost-efective, robust products based on the neuron 5000 processor. our end-to- end solutions include a comprehensive set of development tools, network interfaces, routers, and network tools. pre-production design review services, training, and worldwide technical supportincluding on-site supportare available through echelons support technical assistance program. cr ysta l (1 0 mh z) po we r so ur ce se ri al eepro m (2 kb or la r ger ) i/o l on w orks or other network channe l neuron 5000 processo r external tr ansceiver sense or contro l devices: motors, va lves, lights, relays , switches, controllers serial spi flash (optional ) figure 6: typical lonworks based device neuron 5000 processor pin confguration figure 7: neuron 5000 processor pinout neuron 5000 processor pin descriptions a ll digital inputs are low-voltage transistor- transistor logic (lvttl) compatible, low leakage, 5v-tolerant. all digital outputs are slew-rate limited to reduce electromagnetic interference (emi) concerns. pin name pin number type description svc~ 1 digital i/o service (active low) io0 2 digital i/o io0 for i/o objects io1 3 digital i/o io1 for i/o objects io2 4 digital i/o io2 for i/o objects io3 5 digital i/o io3 for i/o objects vdd1v8 6 power 1.8 v power input (from internal voltage regulator) io4 7 digital i/o io4 for i/o objects vdd3v3 8 power 3.3 v power io5 9 digital i/o io5 for i/o objects io6 10 digital i/o io6 for i/o objects io7 11 digital i/o io7 for i/o objects io8 12 digital i/o io8 for i/o objects io9 13 digital i/o io9 for i/o objects io10 14 digital i/o io10 for i/o objects io11 15 digital i/o io11 for i/o objects vdd1v8 16 power 1.8 v power input (from internal voltage regulator) trst~ 17 digital input jtag test reset (active low) vdd3v3 18 power 3.3 v power tck 19 digital input jtag test clock tms 20 digital input jtag test mode select tdi 21 digital input jtag test data in tdo 22 digital output jtag test data out xin 23 oscillator in crystal oscillator input xout 24 oscillator out crystal oscillator output vddpll 25 power 1.8 v power input (from internal voltage regulator) gndpll 26 power ground vout1v8 27 power 1.8 v power output (of internal voltage regulator) rst~ 28 digital i/o reset (active low) vin3v3 29 power 3.3 v input to internal voltage regulator vdd3v3 30 power 3.3 v power avdd3v3 31 power 3.3 v power neuron 5000 processor 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 gnd nc cp1 agnd gp0 av dd3v3 vdd3v3 vin3v3 rst~ vout1v8 gndpll vddpll gnd pa d dashed line represents pad (pin 49) pad must be connected to gnd svc~ io0 io1 io2 io3 vdd1v8 io4 vdd3v3 io5 io6 io7 io8 13 14 15 16 17 18 19 20 21 22 23 24 io9 io10 io1 1 vdd1v8 trst~ vdd3v3 tck tms tdi tdo xin xout 48 47 46 45 44 43 42 41 40 39 38 37 mosi sck miso scl vdd1v 8 sda_cs1~ vdd3v 3 vdd3v 3 cs0~ cp4 cp3 cp2
www.echelon.com ? pin name pin number type description mosi 48 digital i/o spi master output, slave input (mosi) (for external memory connection only) pad 49 ground pad ground table 3: neuron 5000 processor pin description electrical characteristics neuron 5000 processor operating conditions param - eter 1 description minimum typical maximum v dd3 supply voltage 3.00 v 3.3 v 3.60 v v lvi low-voltage indicator trip point 2.70 v 2.96 v t a ambient temperature -40 c +85 c f xin xin clock frequency 2 - 10,0000 mhz - i dd3 current consumption 3 5mhz 10mhz 20mhz 40mhz 80mhz 9 ma 9 ma 15 ma 23 ma 38 ma 15 ma 15 ma 23 ma 33 ma 52 ma table 4: neuron 5000 processor operating conditions not es 1. all parameters assume nominal supply voltage (v dd3 = 3.3 v 0.3 v) and operating temperature (t a between -40oc and +85oc), unless otherwise noted. 2. see clock requirements in the series 5000 chip data book for more detailed information about the xin clock frequency. 3. assumes no load on digital i/o pins, and that the i /o lines are not switching. digital pin characteristics the digital i/o pins (io0Cio11) have lvttl- level inputs. pins io0Cio7 also have low- level-detect latches. the rst~ and svc~ pins have internal pull-ups, and the rst~ pin has hysteresis. table 5 below lists the characteristics of the digital i/o pins, which include io0Cio11, cp0- cp4 and the other digital pins listed in table 3. param - eter 1 description mini - mum typical maxi - mum v oh output drive high at i oh = 8 ma 2.4 v v dd3 v ol output drive low at i ol = 8 ma gnd 0.4 v v ih input high level 2.0 v 5.5 v v il input low level gnd 0.8 v v hys input hysteresis for rst ~ pin 300 mv i in input leakage current - 10 a r pu pullup resistance 2 13 k ? 23 k ? i pu pullup current when pin at 0 v 2 130 a 275 a table 5: neuron 5000 processor digital pin characteristics notes 1. all parameter s assume nominal supply voltage (v dd3 = 3.3 v 0.3 v) and operating temperature (t a between -40oc and +85oc), unless otherwise noted. 2. applies to rst~ and svc~ pins only. recommended neuron 5000 processor pad layout figure 8: neuron 5000 processor pad layout neuron 5000 processor ic mechanical specifcation figure 9: neuron 5000 processor ic mechanical specifcations notes 1. all dimensions are in millimeters. 2. dimensions and tolerances conform to asme y14.5m.-1994. 3. package warpage max. 0.08 mm. 4. package corners unless otherwise specifed are r0.1750.025 mm.
www.echelon.com ? neuron 5000 tape and reel devices are uniformly loaded in the carrier tape such that the device pin one is oriented in quadrant 1 toward the side of the tape having round sprocket holes. figure 10 illustrates the pin-one location. user direction of feed figure 10: neuron 5000 pin one orientation figure 11 shows the outline dimensions of the carrier tape. figure 11: carrier tape outline drawing ao = bo = 7.25 ko = 1.10 no tes 1. all dimensions are in millimeters. 2. tolerances unless noted: 1pl + 0.2. 2pl + 0.1 3. 10 sprocket hole pitch cumulative tolerance +0.2 4. camber in compliance with eia 481. 5. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. for more information, refer to eia-481-b, taping of surface mount components for automatic placement. figure 12 shows the neuron 5000 series 13 reel drawing and specifcation. figure 12: neuron 5000 10 reel and hub drawing
www.echelon.com ? figure 13 shows the 5000 series 7 reel drawing and specifcation. figure 13: neuron 5000 7 reel and hub drawing ? 2014 echelon, lonworks, and the echelon logo are trademarks of echelon corporation registered in the united states and other countries.izot is a trademark of echelon corporation. content subject to change without notice. specifcations rohs-compliant the neuron 5000 processor is compliant with the european directive 2002/95/ec on the restriction of the use of certain hazardous substances (rohs) in electrical and electronic equipment. emc specifcations depend on the network transceiver used with the neuron 5000 processor. transmission speed depends on network transceiver: 78 kbit/s for tp/ft-10 channel; 1250 kbit/s for tp/xf-1250 channel. (see eia-485 channel specifcation for transmission speed characteristics.) operating temperature -40 to 85c refow soldering temperature profle refer to joint industry standard document ipc/jedec j-std-020d.1 (march 2008). peak refow soldering temperature ordering information neuron 5000 processor 14305r-2000 14305r-500
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