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- 1 - K4T51043QJ rev. 1.0, mar. 2011 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2011 samsung electronics co., ltd. all rights reserved. datasheet k4t51083qj k4t51163qj 512mb j-die ddr2 sdram 60 & 84fbga with lead-free & halogen-free (rohs compliant) free datasheet http:///
- 2 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ revision history revision no. history draft date remark editor 0.5 - preliminary spec. release jun. 2010 - s.h.kim 1.0 - first release. mar. 2011 - j.y.lee free datasheet http:///
- 3 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ table of contents 512mb j-die ddr2 sdram 1. ordering information ........................................................................................................ ............................................. 4 2. key features................................................................................................................ ................................................. 4 3. package pinout/mechanical dimension & addressing........ .............. .............. .............. .............. ............ ...................... 5 3.1 x4 package pinout (top view) : 60ball fbga package .............. .............. ........... ........... ........... ............ ................. 5 3.2 x8 package pinout (top view) : 60ball fbga package .............. .............. ........... ........... ........... ............ ................. 6 3.3 x16 package pinout (top view) : 84ball fbga package . .............. .............. ........... ........... ........... .......... ................ 7 3.4 fbga package dimension (x4/x8)............................................................................................. ............................. 8 3.5 fbga package dimension (x16)............................................................................................... .............................. 9 4. input/output functional descrip tion............. .............. .............. .............. ............ ........... ........... ..................................... 10 5. ddr2 sdram addressing . .............. .............. .............. .............. .............. ........... ............ ......... .................................... 11 6. absolute maximum rati ngs .................................................................................................... ...................................... 12 7. ac & dc operating conditions................................................................................................ ..................................... 12 7.1 recommended dc operating conditions (sstl_1.8)........ ..................................................................... ................ 12 7.2 operating temperature condition ............................................................................................ ............................... 13 7.3 input dc logic level ....................................................................................................... ........................................ 13 7.4 input ac logic level ....................................................................................................... ........................................ 13 7.5 ac input test conditions................................................................................................... ...................................... 13 7.6 differential input ac logic level.......................................................................................... ..................................... 14 7.7 differential ac output parameters .......................................................................................... ................................. 14 8. odt dc electrical characteristics ................... ........................................................................ ...................................... 14 9. ocd default characteristics ................................................................................................. ......................................... 15 10. idd specification parameters and test conditions ........................................................................... ......................... 16 11. ddr2 sdram idd spec table ...... .............. .............. .............. .............. .............. ........... ........... ................................ 18 12. input/output capacitance ................................................................................................... ......................................... 20 13. electrical characteristics & ac timing for ddr2- 1066/800/667 ............ .............. .............. ........... ............ ................. 20 13.1 refresh parameters by device density...................................................................................... ........................... 20 13.2 speed bins and cl, trcd, trp, trc and tras for corre sponding bin ....... .............. .............. ............ ........... ...... 20 13.3 timing parameters by speed grade ..................... ..................................................................... ........................... 21 14. general notes, which may apply for all ac paramete rs ....................................................................... ....................... 23 15. specific notes for dedicated ac parameters ................................................................................. ............................. 25 free datasheet http:///
- 4 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 1. ordering information note : 1. speed bin is in order of cl-trcd-trp 2. 12digit, "b" stands for flip chip fbga pkg. 2. key features org. ddr2-1066 7-7-7 ddr2-800 5-5-5 ddr2-800 6-6-6 ddr2-667 5-5-5 package 128mx4 - K4T51043QJ-bce7 K4T51043QJ-bcf7 K4T51043QJ-bce6 60 fbga 64mx8 - k4t51083qj-bce7 k4t51083qj-bcf7 k4t51083qj-bce6 60 fbga 32mx16 k4t51163qj-bcf8 k4t51163qj-bce7 k4t51163qj-bcf7 k4t51163qj-bce6 84 fbga speed ddr2-1066 7-7-7 ddr2-800 5-5-5 ddr2-800 6-6-6 ddr2-667 5-5-5 units cas latency 7 5 6 5 tck trcd(min) 13.125 12.5 15 15 ns trp(min) 13.125 12.5 15 15 ns trc(min) 58.125 57.5 60 60 ns ? jedec standard v dd = 1.8v 0.1v power supply ?v ddq = 1.8v 0.1v ? 333mhz f ck for 667mb/sec/pin, 400mhz f ck for 800mb/sec/pin and 533mhz f ck for 1066mb/sec/pin ? 4 banks ?posted cas ? programmable cas latency: 3, 4, 5, 6 ? programmable additive latency: 0, 1 , 2 , 3, 4 , 5 ? write latency(wl) = read latency(rl) -1 ? burst length: 4 , 8(interleave/nibble sequential) ? programmable sequential / interleave burst mode ? bi-directional differential data-s trobe (single-ended data-strobe is an optional feature) ? off-chip driver(ocd) impedance adjustment ? on die termination ? special function support -50ohm odt -high temperature self-refresh rate enable ? average refresh period for commecial temp.: 7.8us at lower than t case 85 free datasheet http:///
- 5 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 3. package pinout/mechanical dimension & addressing 3.1 x4 package pinout (top view) : 60ball fbga package note : 1. pin b3 has identical capacitance as pin b7. 2. v ddl and v ssdl are power and ground for the dll. a b c d e f g h j k l v dd nc v ss nc v ssq dm v ddq v ddq v ddq v ssq v ssq dqs dqs nc dq0 v ddq dq2 v ssq nc v ssdl v dd ck ras ck cas cs a2 a6 a4 a11 a8 nc a13 nc a12 a9 a7 a5 a0 v dd a10/ap v ss v ddq v ssq dq1 dq3 nc v ddl a1 a3 ba1 v ref v ss cke we ba0 v dd v ss odt nc 12 3 789 ball locations (x4) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 123456789 a b c d e f g h j k l : populated ball + : depopulated ball top view (see the als through the package) free datasheet http:///
- 6 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 3.2 x8 package pinout (top vi ew) : 60ball fbga package note : 1. pins b3 and a2 have identic al capacitance as pins b7 and a8. 2. for a read, when enabled, strobe pair rdqs & rdqs are identical in function and timing to strobe pair dqs & dqs and input masking function is disabled. 3. the function of dm or rdqs/rdqs are enabled by emrs command. 4. v ddl and v ssdl are power and ground for the dll. a b c d e f g h j k l v dd nu/ v ss dq6 v ssq v ddq v ddq v ddq v ssq v ssq dqs dqs dq7 dq0 v ddq dq2 v ssq dq5 v ssdl v dd ck ras ck cas cs a2 a6 a4 a11 a8 nc a13 nc a12 a9 a7 a5 a0 v dd a10/ap v ss v ddq v ssq dq1 dq3 dq4 v ddl a1 a3 ba1 v ref v ss cke we ba0 v dd v ss dm/ rdqs rdqs nc odt 123 789 ball locations (x8) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 123456789 a b c d e f g h j k l : populated ball + : depopulated ball top view (see the als through the package) free datasheet http:///
- 7 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 3.3 x16 package pinout (top view) : 84ball fbga package note : 1. vddl and vssdl are power and ground for the dll. 2. in case of only 8 dqs out of 16 dq s are used, ldqs, ldqsb and dq0~7 must be used. 3. a12 ball is only for mrs and emrs mode setting. a b c d e f g h j k l v dd nc v ss dq6 v ssq ldm v ddq v ddq v ddq v ssq v ssq ldqs ldqs dq7 dq0 v ddq dq2 v ssq dq5 v ssdl v dd ck ras ck cas cs a2 a6 a4 a11 a8 nc nc nc a12 a9 a7 a5 a0 v dd a10/ap v ss v ddq v ssq dq1 dq3 dq4 v ddl a1 a3 ba1 v ref v ss cke we ba0 v dd v ss v dd nc v ss dq14 v ssq udm v ddq v ddq v ssq dq9 dq11 dq12 v ddq v ddq v ssq v ssq udqs udqs dq15 dq8 v ddq dq10 v ssq dq13 nc odt m n p r 12 3 7 8 9 + + + + + + + + + + + + 123456789 a b c d e f g h j k l + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + m n p r : populated ball + : depopulated ball top view ball locations (x16) (see the balls through the package) + + + + + free datasheet http:///
- 8 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 3.4 fbga package dimension (x4/x8) 9.50 0.10 7.50 0.10 #a1 0.370.05 1.100.10 (0.30) # a1 index mark (0.60) 9.50 0.10 0.80 x 10 = 8.00 0.80 7.50 0.10 1.60 0.80 x 8 = 6. 40 4.00 0.80 a b a b c d e f h j k l g 0.10max 3.20 0.80 987654321 60- ? free datasheet http:///
- 9 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 3.5 fbga package dimension (x16) 12.50 0.10 7.50 0.10 #a1 0.370.05 1.100.10 (0.30) # a1 index mark (0.60) 12.50 0.10 0.80 x 14 = 11.20 0.80 7.50 0.10 1.60 0.80 x 8 = 6. 40 5.60 0.80 a b a b c d e f h j k l g 0.10max 3.20 0.80 987654321 84- ? free datasheet http:///
- 10 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 4. input/output functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and contro l input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivates, in ternal clock signals and dev ice input buffers and out- put drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. after v ref has become stable during the power on and initialization swquence, it must be maintained for proper operation of the cke receiver. for proper self-refresh entry and exit, v ref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power-down. i nput buffers, excluding cke, are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external rank selection on sys- tems with multiple ranks. cs is considered part of the command code. odt input on die termination: odt (registered high) enables termination resi stance internal to the ddr2 sdram. when enabled, odt is only appli ed to each dq, dqs, dqs , rdqs, rdqs , and dm signal for x4/x8 configurations. for x16 configuration, odt is appl ied to each dq, udqs/udqs , ldqs/ldqs , udm, and ldm signal. the odt pin will be ignored if the extended mode register set(emrs) is programmed to disable odt. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm (udm), (ldm) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coinci- dent with that input data during a write access. dm is sa mpled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. fo r x8 device, the function of dm or rdqs/rdqs is enabled by emrs command. ba0 - ba1 input bank address inputs: ba0, ba1 and ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determi nes if the mode register or extended m ode register is to be accessed during a mrs or emrs cycle. a0 - a13 input address inputs: provided the row address for active commands and the column address and auto precharge bit for read/write commands to select one location out of the memo ry array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1 and ba2. the address inputs also provide the op- code during mode register set commands. dq input/output data input/ output: bi-directional data bus. dqs, (dqs ) (ldqs), (ldqs ) (udqs), (udqs ) (rdqs), (rdqs ) input/output data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. for the x16, ldqs corresponds to the data on dq0-dq7; udqs corresponds to the data on dq8-dq15. for the x8, an rdqs option using dm pin can be enabled via t he emrs(1) to simplify read timing. the data strobes dqs, ldqs, udqs, and rdqs may be used in single ended mode or pa ired with optional complementary signals dqs , ldqs , udqs , and rdqs to provide differential pair signaling to the system during both reads and writes. a c ontrol bit at emrs(1)[a10] enables or disables all complementary data strobe signals. in this data sheet, "differential dqs signals" refers to any of the following with a10 = 0 of emrs(1) x4 dqs/dqs x8 dqs/dqs if emrs(1)[a11] = 0 x8 dqs/dqs , rdqs/rdqs , if emrs(1)[a11] = 1 x16 ldqs/ldqs and udqs/udqs "single-ended dqs signals" refers to any of the following with a10 = 1 of emrs(1) x4 dqs x8 dqs if emrs(1) [a11] = 0 x8 dqs, rdqs, if emrs(1) [a11] = 1 x16 ldqs and udqs nc no connect : no internal electrical connection is present. v dd /v ddq supply power supply : 1.8v +/- 0.1v, dq power supply : 1.8v +/- 0.1v v ss /v ssq supply ground , dq ground v ddl supply dll power supply : 1.8v +/- 0.1v v ssdl supply dll ground v ref supply reference voltage free datasheet http:///
- 11 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 5. ddr2 sdram addressing 512mb * reference information: the following tables are address mapping information for other densities. 256mb 1gb 2gb 4gb configuration 128mb x4 64mb x 8 32mb x16 # of bank 4 4 4 bank address ba0,ba1 ba0,ba1 ba0,ba1 auto precharge a10/ap a10/ap a10/ap row address a0 ~ a13 a0 ~ a13 a0 ~ a12 column address a0 ~ a9,a11 a0 ~ a9 a0 ~ a9 configuration 64mb x4 32mb x 8 16mb x16 # of bank 4 4 4 bank address ba0,ba1 ba0,ba1 ba0,ba1 auto precharge a10/ap a10/ap a10/ap row address a0 ~ a12 a0 ~ a12 a0 ~ a12 column address a0 ~ a9,a11 a0 ~ a9 a0 ~ a8 configuration 256mb x4 128mb x 8 64mb x16 # of bank 8 8 8 bank address ba0 ~ ba2 ba0 ~ ba2 ba0 ~ ba2 auto precharge a10/ap a10/ap a10/ap row address a0 ~ a13 a0 ~ a13 a0 ~ a12 column address a0 ~ a9,a11 a0 ~ a9 a0 ~ a9 configuration 512mb x4 256mb x 8 128mb x16 # of bank 8 8 8 bank address ba0 ~ ba2 ba0 ~ ba2 ba0 ~ ba2 auto precharge a10/ap a10/ap a10/ap row address a0 ~ a14 a0 ~ a14 a0 ~ a13 column address a0 ~ a9,a11 a0 ~ a9 a0 ~ a9 configuration 1 gb x4 512mb x 8 256mb x16 # of bank 8 8 8 bank address ba0 ~ ba2 ba0 ~ ba2 ba0 ~ ba2 auto precharge a10/ap a10/ap a10/ap row address a0 - a15 a0 - a15 a0 - a14 column address a0 - a9,a11 a0 - a9 a0 - a9 free datasheet http:///
- 12 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 6. absolute maximum ratings note : 1. stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions a bove those indicated in the operational sectio ns of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the ce nter/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. 3. v dd and v ddq must be within 300mv of each other at all times; and v ref must be not greater than 0.6 x v ddq . when v dd and v ddq and v ddl are less than 500mv, v ref may be equal to or less than 300mv. 4. voltage on any input or i/o may not exceed voltage on v ddq . 7. ac & dc operating conditions 7.1 recommended dc operating conditions (sstl_1.8) note : there is no specific device v dd supply voltage requirement for sstl-1.8 compliance. however under all conditions v ddq must be less than or equal to v dd . 1. the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 2. peak to peak ac noise on v ref may not exceed +/-2% v ref (dc). 3. v tt of transmitting device must track v ref of receiving device. 4. ac parameters are measured with v dd , v ddq and v ddl tied together. symbol parameter rating units note v dd voltage on v dd pin relative to v ss - 1.0 v ~ 2.3 v v 1 v ddq voltage on v ddq pin relative to v ss - 0.5 v ~ 2.3 v v 1 v ddl voltage on v ddl pin relative to v ss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to v ss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 free datasheet http:///
- 13 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 7.2 operating temperature condition note : 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, pl ease refer to jesd51.2 standard. 2. at 85 - 95 q c operation temperature range, doubling refresh commands in frequency to a 32ms period ( trefi=3.9 us ) is required, and to ent er to self refresh mode at this temperature range, an emrs command is required to change internal refresh rate. 7.3 input dc logic level symbol parameter min. max. units note v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v 7.4 input ac logic level symbol parameter ddr2-667, ddr2-800 ddr2-1066 units min. max. min. max. v ih (ac) ac input logic high v ref + 0.200 v ddq + v peak v ref + 0.200 - v v il (ac) ac input logic low v ssq - v peak v ref - 0.200 - v ref - 0.200 v figure 1. ac input test signal waveform note : 1. f or information related to v peak value, refer to overshoot/undershoot specification in device operation and timing datasheet; maximum peak ampli- tude allowed for overshoot and undershoot. 7.5 ac input test conditions note : 1. input waveform timing is referenced to the input signal crossing through the v ih/il (ac) level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) min for rising edges and the range from v ref to v il (ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. symbol parameter rating units note t oper operating temperature 0 to 95 q c 1, 2 symbol condition value units note v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr free datasheet http:///
figure 2. differential signal levels - 14 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 7.6 differential input ac logic level symbol parameter min. max. units note v id (ac) ac differential input voltage 0.5 v ddq v 1 v ix (ac) ac differential cross point voltage 0.5 * v ddq - 0.175 0.5 * v ddq + 0.175 v 2 note : 1. v id (ac) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input signal (such as ck, dqs, ldqs or udqs) and v cp is the com- plementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih (ac) - v il (ac). 2. the typical value of v ix (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ix (ac) is expected to track variations in v ddq . v ix (ac) indicates the voltage at which differential input signals must cross. 3. for information related to v peak value, refer to overshoot/undershoot spec ification in device operation and timing datasheet; maximum peak amplitude allowed fo r over- shoot and undershoot. 7.7 differential ac output parameters symbol parameter min. max. units note v ox (ac) ac differential cross point voltage 0.5 * v ddq - 0.125 0.5 * v ddq + 0.125 v 1 note : 1. the typical value of v ox (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ox (ac) is expected to track variations in v ddq . v ox (ac) indicates the volt- age at which differential output signals must cross. 8. odt dc electrical characteristics note : test condition for rtt measurements measurement definition for rtt(eff): apply v ih (ac) and v il (ac) to test pin separately, then measure current i(v ih (ac)) and i( v il (ac)) respectively. v ih (ac), v il (ac)(dc), and v ddq values defined in sstl_18 rtt(eff) = v ih (ac) - v il (ac) i( v ih (ac) ) - i( v il (ac) ) delta vm = 2 x vm v ddq x 100% - 1 measurement definition for v m : measure voltage (v m ) at test pin (midpoint) with no load. parameter/condition symbol min nom max units note rtt effective impedance value for emrs(a6,a2)=0,1; 75 ohm rtt1(eff) 60 75 90 ohm 1 rtt effective impedance value for emrs(a6,a2)=1,0; 150 ohm rtt2(eff) 120 150 180 ohm 1 rtt effective impedance value for emrs(a6,a2)=1,1; 50 ohm rtt3(eff) 40 50 60 ohm 1 deviation of vm with respect to v ddq /2 delta vm - 6 + 6 % 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox free datasheet http:///
- 15 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 9. ocd default characteristics note : 1. absolute specifications (0c free datasheet http:///
- 16 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 10. idd specification parameters and test conditions (idd values are for full operating range of voltage and temperature, notes 1 - 5) symbol proposed conditions units note idd0 operating one bank active-precharge current ; tck = tck(idd), trc = trc(idd), tras = trasmin(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), trc = trc (idd), tras = trasmin(idd), trcd = trcd(idd); cke is high, cs is high between valid commands; address businputs are switching; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle; tck = tck(idd); cke is low; other cont rol and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ; all banks idle; tck = t ck(idd); cke is high, cs is high; other control and address bus inputsare stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; tck = tck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; tck = tck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; tck = tck(idd), tras = tras max(idd), trp = trp(idd); cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl (idd), al = 0; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), tras = tras- max(idd), trp = trp(idd); cke is high, cs is high between valid commands; address bus inputs are switch- ing; data pattern is same as idd4w ma idd5b burst auto refresh current ; tck = tck(idd); refresh command at every trfc(idd) interval; cke is high, cs is high between valid com- mands; other control and address bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke free datasheet http:///
- 17 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ note : 1. idd specifications are tested after the device is properly initialized 2. input slew rate is specified by ac parametric test condition 3. idd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs , udqs, and udqs . idd values must be met with all combinations of emrs bits 10 and 11. 5. definitions for idd low is defined as v in free datasheet http:///
- 18 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 11. ddr2 sdram idd spec table symbol 128mx4 (K4T51043QJ) unit note 800@cl=5 800@cl=6 667@cl=5 ce7 cf7 ce6 idd0 54 53 50 ma idd1 61 61 60 ma idd2p888ma idd2q202020ma idd2n252525ma idd3p-f202020ma idd3p-s121212ma idd3n353534ma idd4w858575ma idd4r909286ma idd5 75 75 75 ma idd6 8 8 8 ma idd7 140 135 130 ma symbol 64mx8 (k4t51083qj) unit note 800@cl=5 800@cl=6 667@cl=5 ce7 cf7 ce6 idd0 54 53 50 ma idd1 62 62 60 ma idd2p888ma idd2q202020ma idd2n252525ma idd3p-f202020ma idd3p-s121212ma idd3n353535ma idd4w959585ma idd4r 110 110 96 ma idd5 81 75 75 ma idd6 8 8 8 ma idd7 155 150 140 ma free datasheet http:///
- 19 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ symbol 32mx16 (k4t51163qj) unit note 1066@cl=7 800@cl=5 800@cl=6 667@cl=5 cf8 ce7 cf7 ce6 idd0 70 62 60 58 ma idd1 80 75 75 70 ma idd2p8888ma idd2q22202020ma idd2n28252525ma idd3p-f22202020ma idd3p-s12121212ma idd3n40353535ma idd4w 120 100 100 90 ma idd4r 160 130 130 115 ma idd5 80 75 75 75 ma idd68888ma idd7 200 185 180 170 ma free datasheet http:///
- 20 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 12. input/output capacitance 13. electrical characteristics & ac timing for ddr2-1066/800/667 ( 0 < free datasheet http:///
- 21 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 13.3 timing parameters by speed grade (for information related to the entries in this table, refer to both the general notes and the specific notes following this ta ble.) parameter symbol ddr2-1066 ddr2-800 ddr2-667 units note min max min max min max dq output access time from ck/ck tac - 350 350 -400 400 -450 450 ps 40 dqs output access time from ck/ck tdqsck - 300 300 -350 350 -400 400 ps 40 average clock high pulse width tch(avg) 0.48 0.52 0.48 0.52 0.48 0.52 tck(avg) 35,36 average clock low pulse width tcl(avg) 0.48 0.52 0.48 0.52 0.48 0.52 tck(avg) 35,36 ck half pulse period thp min(tcl,tc h) x min(tcl(ab s), tch(abs)) x min(tcl(ab s), tch(abs)) x ps 37 average clock period tck(avg) 1875 7500 2500 8000 3000 8000 ps 35,36 dq and dm input hold time tdh(base) 75 x 125 x 175 x ps 6,7,8,21 ,28,31 dq and dm input setup time tds(base) 0 x 50 x 100 x ps 6,7,8,20 ,28,31 control & address input pulse width for each input tipw 0.6 x 0.6 x 0.6 x tck(avg) dq and dm input pulse width for each input tdipw 0.35 x 0.35 x 0.35 x tck(avg) data-out high-impedance time from ck/ck thz x tac max x tac(max) x tac(max) ps 18,40 dqs/dqs low-impedance time from ck/ck tlz(dqs) tac min tac max tac(min) tac(max) tac(min) tac(max) ps 18,40 dq low-impedance time from ck/ck tlz(dq) 2* tac min tac max 2* tac(min) tac(max) 2* tac(min) tac(max) ps 18,40 dqs-dq skew for dqs and associated dq signals tdqsq x 175 x 200 x 240 ps 13 dq hold skew factor tqhs x 250 x 300 x 340 ps 38 dq/dqs output hold time from dqs tqh thp - tqhs x thp - tqhs x thp - tqhs x ps 39 dqs latching rising transitions to associated clock edges tdqss - 0.25 0.25 - 0.25 0.25 -0.25 0.25 tck(avg) 30 dqs input high pulse width tdqsh 0.35 x 0.35 x 0.35 x tck(avg) dqs input low pulse width tdqsl 0.35 x 0.35 x 0.35 x tck(avg) dqs falling edge to ck setup time tdss 0.2 x 0.2 x 0.2 x tck(avg) 30 dqs falling edge hold time from ck tdsh 0.2 x 0.2 x 0.2 x tck(avg) 30 mode register set command cycle time tmrd 2x 2 x 2 x nck mrs command to odt update delay tmod 0 12 0 12 0 12 ns 32 write postamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck(avg) 10 write preamble twpre 0.35 x 0.35 x 0.35 x tck(avg) address and control input hold time tih(base) 200 x 250 x 275 x ps 5,7,9,23 ,29 address and control input setup time tis(base) 125 x 175 x 200 x ps 5,7,9,22 ,29 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck(avg) 19,41 read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck(avg) 19,42 activate to activate command period for 1kb page size products trrd 7.5 x 7.5 x 7.5 x ns 4,32 activate to activate command period for 2kb page size products trrd 10 x 10 x 10 x ns 4,32 free datasheet http:///
- 22 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ parameter symbol ddr2-1066 ddr2-800 ddr2-667 units note min max min max min max four activate window for 1kb page size products tfaw 35 x35 x 37.5 x ns 32 four activate window for 2kb page size products tfaw 45 x45 x 50 x ns 32 cas to cas command delay tccd 2 x 2 x 2 x nck write recovery time twr 15 x 15 x 15 x ns 32 auto precharge write recovery + precharge time tdal wr+trp x wr + tnrp x wr + tnrp x nck 33 internal write to read command delay twtr 7.5 x 7.5 x7.5 x ns 24,32 internal read to precharge command delay trtp 7.5 x 7.5 x 7.5 x ns 3,32 exit self refresh to a non-read command txsnr trfc + 10 x trfc + 10 x trfc + 10 x ns 32 exit self refresh to a read command txsrd 200 x 200 x 200 x nck exit precharge power down to any command txp 3 x 2 x 2 x nck exit active power down to read command txard 3 x 2 x 2 x nck 1 exit active power down to read command (slow exit, lower power) txards 10 - al x 8 - al x 7 - al x nck 1,2 cke minimum pulse width (high and low pulse width) tcke 3 x 3 x 3 x nck 27 odt turn-on delay taond 2 2 2 2 2 2 nck 16 odt turn-on taon tac(min) tac(max) + 2.575 tac(min) tac(max)+ 0.7 tac(min) tac(max)+ 0.7 ns 6,16,40 odt turn-on (power-down mode) taonpd tac(min)+2 3*tck + tac(max)+ 1 tac(min)+2 2*tck(avg) +tac(max) +1 tac(min)+2 2*tck(avg) +tac(max) +1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 2.5 2.5 nck 17,45 odt turn-off taof tac(min) tac(max)+ 0.6 tac(min) tac(max)+ 0.6 tac(min) tac(max)+ 0.6 ns 17,43,4 5 odt turn-off (power-down mode) taofpd tac(min)+2 2.5*tck + tac(max)+ 1 tac(min)+2 2.5*tck(av g)+tac(ma x)+1 tac(min)+2 2.5*tck(av g)+tac(ma x)+1 ns odt to power down entry latency tanpd 4 x 3 x3 x nck odt power down exit latency taxpd 11 x 8 x8 x nck ocd drive mode output delay toit 0 12 0 12 0 12 ns 32 minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck +tih x tis+tck(av g) +tih x tis+tck(av g) +tih xns15 free datasheet http:///
figure 4. slew rate test load figure 3. ac timing reference load - 23 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 14. general notes, which may apply for all ac parameters 1. ddr2 sdram ac timing reference load figure 3 represents the timing reference load used in defining the relevant timing parameters of the part. it is not intended t o be either a precise repre sentation of the typical system environm ent or a depiction of the actual load pres ented by a production tester. system designer s will use ibis or other sim- ulation tools to correlate the timing refe rence load to a system environment. manufact urers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). the output timing reference voltage level for si ngle ended signals is the crosspoint with v tt . the output timing reference voltage level for differential sig- nals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs ) signal. 2. slew rate measurement levels a) output slew rate for fallin g and rising edges is measured between v tt - 250 mv and v tt + 250 mv for single ended signal s. for differential signals (e.g. dqs - dqs ) output slew rate is measured between dqs - dqs = - 500 mv and dqs - dqs = + 500 mv. output slew rate is guaranteed by design, but is not nec essarily tested on each device. b) input slew rate for single ended signals is measured from v ref (dc) to v ih (ac),min for rising edges and from v ref (dc) to v il (ac),max for falling edges. for differential signals (e.g. ck - ck ) slew rate for rising edges is measured from ck - ck = - 250 mv to ck - ck = + 500 mv (+ 250 mv to - 500 mv for falling edges). c) v id is the magnitude of the difference between the input voltage on ck and the input voltage on ck , or between dqs and dqs for differential strobe. 3. ddr2 sdram output slew rate test load output slew rate is characterized under the test conditions as shown in figure 4. v ddq dut dq dqs dqs output v tt = v ddq /2 25 : timing reference point rdqs rdqs v ddq dut dq dqs, dqs rdqs, rdqs output v tt = v ddq /2 25 : test point free datasheet http:///
figure 6. data output (read) timing figure 5. data input (write) timing - 24 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 4. differential data strobe ddr2 sdram pin timings are spec ified for either single ended mode or different ial mode depending on the setting of the emrs "en able dqs" mode bit; timing advantages of differential mode are realized in system design. the method by which the ddr2 sdram pin timings are measur ed is mode depen- dent. in single ended mode, timing relationshi ps are measured relative to the rising or falling edges of dqs crossing at v ref . in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing methods is guaranteed by design and characterization. note that when differential data strobe m ode is disabled via the emrs, the complementary pin, dqs , must be tied externally to v ss through a 20 : to 10 k : resistor to insure proper operation. 5. ac timings are for linear signal tr ansitions. see specific notes on der ating for other signal transitions. 6. all voltages are referenced to v ss . 7. these parameters guarantee device behavior, but they are not necessarily tested on each device. they may be guaranteed by de vice design or tester correlation. 8. tests for ac timing, idd, and electrical (ac and dc) characteri stics, may be conducted at nominal reference/supply voltage lev els, but the related specifications and device operation ar e guaranteed for the full voltage range specified. tds tdh twpre twpst tdqsh tdqsl dqs dqs d dmin dqs dq dm tdh dmin dmin dmin d d d dqs v il (ac) v ih (ac) v il (ac) v ih (ac) v il (dc) v ih (dc) v il (dc) v ih (dc) tds tch tcl ck ck ck/ck dqs/dqs dq dqs dqs trpst q trpre tdqsq(max) tqh tqh tdqsq(max) q qq free datasheet http:///
- 25 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 15. specific notes for dedicated ac parameters 1. user can choose which active power down ex it timing to use via mrs (bit 12). txard is expected to be used for fast active powe r down exit timing. txards is expected to be used fo r slow active power down exit timing. 2. al = additive latency. 3. this is a minimum requirement. minimum read to precharge timing is al + bl / 2 provided that the trtp and tras(min) have been s atisfied. 4. a minimum of two clocks (2 x tc k or 2 x nck) is required irre spective of operating frequency. 5. timings are specified with command/addre ss input slew rate of 1.0 v/ns. 6. timings are specified with dqs, dm, and dqs?s (dqs/rdqs in single ended mode) input slew rate of 1.0v/ns. 7. timings are specified with ck/ck differential slew rate of 2.0 v/ns. ti mings are guaranteed for dqs signals with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1.0 v/ns in single ended mode. 8. data setup and hold time derating. [ table 1 ] ddr2-400/533 tds/tdh derating with differential data strobe [ table 2 ] ddr2-667/800/1066 tds/tdh derating with differential data strobe free datasheet http:///
- 26 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ [ table 3 ] ddr2-400/533 tds1/tdh1 derating with single-ended data strobe for all input signals the total tds (setup time) and tdh (hold time ) required is calculated by adding the data sheet tds(base) and tdh(base) value to the free datasheet http:///
figure 7. iiiustration of nominal slew rate for tds (differential dqs, dqs ) - 27 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ v ss tds tdh setup slew rate setup slew rate rising signal falling signal ' tf ' tr v ref (dc) - v il (ac)max ' tf = v ih (ac)min - v ref (dc) ' tr = v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max nominal slew rate nominal slew rate v ref to ac region v ref to ac region tds tdh tvac dqs dqs free datasheet http:///
figure 8. iiiustration of nominal slew rate for tds (single-ended dqs) - 28 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ v ss tds tdh setup slew rate setup slew rate rising signal falling signal ' tf ' tr v ref (dc) - v il (ac)max ' tf = v ih (ac)min - v ref (dc) ' tr = v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max nominal slew rate nominal slew rate v ref to ac region v ref to ac region dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max v ss tdh tds note1 note : dqs signal must be monotonic between v il (ac)max and v ih (ac)min. free datasheet http:///
figure 9. iiiustration of tangent line for tds (differential dqs, dqs ) - 29 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ v ss setup slew rate setup slew rate rising signal falling signal ' tf ' tr tangent line[v ref (dc) - v il (ac)max] ' tf = tangent line[v ih (ac)min - v ref (dc)] ' tr = v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tds tdh tds tdh dqs dqs free datasheet http:///
figure 10. iiiustration of tangent line for tds (single-ended dqs) - 30 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ v ss setup slew rate setup slew rate rising signal falling signal ' tf ' tr tangent line[v ref (dc) - v il (ac)max] ' tf = tangent line[v ih (ac)min - v ref (dc)] ' tr = v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tds tdh dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max v ss tdh tds note1 note : dqs signal must be monotonic between v il (dc)max and v ih (dc)min. free datasheet http:///
figure 11. iiiustration of nominal sl ew rate for tdh (differential dqs, dqs ) - 31 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ v ss hold slew rate hold slew rate falling signal rising signal ' tr ' tf v ref (dc) - v il (dc)max ' tr = v ih (dc)min - v ref (dc) ' tf = v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max nominal slew rate nominal slew rate dc to v ref region dc to v ref region tds tdh tds tdh dqs dqs free datasheet http:///
figure 12. iiiustration of nominal slew rate for tdh (single-ended dqs) - 32 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ v ss hold slew rate hold slew rate falling signal rising signal ' tr ' tf v ref (dc) - v il (dc)max ' tr = v ih (dc)min - v ref (dc) ' tf = v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max nominal slew rate nominal slew rate dc to v ref region dc to v ref region tds tdh dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max v ss tdh tds note1 note : dqs signal must be monotonic between v il (dc)max and v ih (dc)min. free datasheet http:///
figure 13. iiiustration of tangent line for tdh (differential dqs, dqs ) - 33 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ hold slew rate ' tf ' tr tangent line [ v ih (dc)min - v ref (dc) ] ' tf = tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref (dc) - v il (dc)max ] ' tr = rising signal tds tdh tds tdh dqs dqs v ss v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max free datasheet http:///
figure 14. iiiustration of tangent line for tdh (single-ended dqs) - 34 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ hold slew rate ' tf ' tr tangent line [ v ih (dc)min - v ref (dc) ] ' tf = tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref (dc) - v il (dc)max ] ' tr = rising signal note : dqs signal must be monotonic between v il (dc)max and v ih (dc)min. tds tdh dqs v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max v ss tdh tds note1 v ss v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max free datasheet http:///
- 35 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 9. tis and tih (input setup and hold) derating [ table 4 ] derating values for ddr2-400, ddr2-533 free datasheet http:///
- 36 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ [ table 5 ] derating values for ddr2-667, ddr2-800, ddr2-1066 for all input signals the total tis (setup time) and tih (hold time) required is calc ulated by adding the data sheet tis(base) and tih(base) value to the free datasheet http:///
figure 15. iiiustration of nominal slew rate for tis - 37 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ v ss setup slew rate setup slew rate rising signal falling signal ' tf ' tr v ref (dc) - v il (ac)max ' tf = v ih (ac)min - v ref (dc) ' tr = v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max nominal slew rate nominal slew rate v ref to ac region v ref to ac region ck ck tis tih tis tih free datasheet http:///
figure 16. iiiustration of tangent line for tis - 38 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ v ss setup slew rate setup slew rate rising signal falling signal ' tf ' tr tangent line[v ref (dc) - v il (ac)max] ' tf = tangent line[v ih (ac)min - v ref (dc)] ' tr = tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line ck ck tis tih tis tih v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max free datasheet http:///
figure 17. iiiustration of nominal slew rate for tih - 39 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ hold slew rate hold slew rate falling signal rising signal ' tr ' tf v ref (dc) - v il (dc)max ' tr = v ih (dc)min - v ref (dc) ' tf = nominal slew rate nominal slew rate dc to v ref region dc to v ref region ck ck tis tih tis tih v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max v ss free datasheet http:///
figure 18. iiiustration of tangent line for tih - 40 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ hold slew rate ' tf ' tr tangent line [ v ih (dc)min - v ref (dc) ] free datasheet http:///
figure 19. method for calculating transitions and endpoints - 41 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 10. the maximum limit for this parameter is not a device limit. the device will operate with a greate r value for this parameter, b ut system performance (bus turnaround) will degrade accordingly. 11. min ( tcl, tch) refers to the smaller of the actual clock lo w time and the actual clock high time as provided to the device (i .e. this value can be greater than the minimum specification limits for tcl and tch). for example, tcl and tch are = 50% of the period, less the half period jitter ( tjit(hp)) of the clock source, and less the half period jitter due to crosstalk ( tjit(crosstalk)) into the clock traces. 12. tqh = thp - tqhs, where : thp = minimum half clock perio d for any given cycle and is defined by clock high or clock low (tch, tcl). tqhs accounts for: 1) the pulse duration dist ortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition foll owed by the worst case pull-in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 13. tdqsq: consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between dqs/ dqs and associated dq in any given cycle. 14. tdal = wr + ru{ trp[ns] / tck[ns] }, where ru stands for round up. wr refers to the twr parameter stored in the mrs. fo r trp, if the result of the divi sion is not already an integer, roun d up to the next highest integer. tck refers to the application clock period. example: for ddr533 at tck = 3.75ns with wr programmed to 4 clocks. tdal = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 15. the clock frequency is allowed to change during se lf refresh mode or precharge power-down mode. 16. odt turn on time min is when the device l eaves high impedance and odt resistance begins to turn on. odt turn on time max is whe n the odt resis- tance is fully on. both are measured from taond, which is inte rpreted differently per speed bin. for ddr2-400/533, taond is 10 ns (= 2 x 5 ns) after the clock edge that registered a first odt high if tck = 5 ns. for ddr2-667/800, taond is 2 cloc k cycles after the clock edge t hat registered a first odt high counting the actual input clock edges. 17. odt turn off time min is when the device starts to turn off od t resistance. odt turn off time max is when the bus is in high i mpedance. both are mea- sured from taofd, which is interpreted differently per speed bi n. for ddr2-400/533, taofd is 12.5 ns (= 2.5 x 5 ns) after the clock edge that regis- tered a first odt low if tck = 5 ns. for ddr2-667/800, if tck(avg) = 3 ns is assumed, taofd is 1. 5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first odt low and by counting the actual input clock edges. 18. thz and tlz transitions occur in the same ac cess time as valid data tr ansitions. these parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (thz), or begins driving (tlz) . figure 19 shows a method to calculate th e point when device is no longer driving (thz), or beginsdriving (tlz ) by measuring the signal at two differ ent voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. tlz(dq) refers to tlz of the dqs and tlz( dqs) refers to tlz of the (u/l/r)dqs and (u/l/r )dqs each treated as single-ended signal. 19. trpst end point and trpre begin point are not referenced to a spec ific voltage level but specify when the device output is no l onger driving (trpst), or begins driving (trpre). figure 19 shows a method to calculate these points when the device is no longer driving (trpst), or begins driving (trpre) by measuring the signal at two different voltages. the ac tual voltage measurement points ar e not critical as long as th e calculation is consis- tent. thz trpst end point t1 t2 v oh + x mv v oh + 2x mv v ol + 2x mv v ol + x mv tlz t2 t1 v tt + 2x mv v tt + x mv v tt - x mv v tt - 2x mv tlz,trpre begin point = 2*t1-t2 thz,trpst end point = 2*t1-t2 free datasheet http:///
figure 21. differential input waveform timing - tis and tih figure 20. differential input waveform timing - tds and tdh - 42 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 20. input waveform timing tds with differential data strobe enabled mr[bit10]=0, is referenced from the input signal crossing at t he v ih (ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the v il (ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test. dqs, dqs signals must be monotonic between v il (dc)max and v ih (dc)min. see figure 20. 21. input waveform timing tdh with differential data strobe enabled mr[bit10]=0, is referenced from the differential data strobe cr osspoint to the input sig- nal crossing at the v ih (dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il (dc) level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between v il (dc)max and v ih (dc)min. see figure 20. 22. input waveform timing is referenced from the input signal crossing at the v ih (ac) level for a rising signal and v il (ac) for a falling signal applied to the device under test. see figure 21. 23. input waveform timing is referenced from the input signal crossing at the v il (dc) level for a rising signal and v ih (dc) for a falling signal applied to the device under test. see figure 21. tds v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max v ss dqs dqs tdh tds tdh tis ck ck tih tis tih v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max v ss free datasheet http:///
- 43 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 24. twtr is at lease two clocks (2 x tck or 2 x nck) independent of operation frequency. 25. input waveform timing with single-ended data strobe enabled mr[bit 10] = 1, is referenced from the input signal crossing at the v ih (ac) level to the sin- gle-ended data strobe crossing v ih/l (dc) at the start of its transition for a rising si gnal, and from the input signal crossing at the v il (ac) level to the single-ended data strobe crossing v ih/l (dc) at the start of its transition for a falling sign al applied to the device under test. the dqs signal must be monotonic between v il (dc)max and v ih (dc)min. 26. input waveform timing with single-ended data strobe enabled mr[bit 10] = 1, is referenced from the input signal crossing at the v ih (dc) level to the single-ended data strobe crossing v ih/l (ac) at the end of its transition for a rising sign al, and from the input signal crossing at the v il (dc) level to the single-ended data strobe crossing v ih/l (ac) at the end of its transition for a falling signal app lied to the device under test. the dqs signal must be monotonic between v il (dc)max and v ih (dc)min. 27. tckemin of 3 clocks means cke must be r egistered on three consecutive positive cloc k edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke transiti on, cke may not transition from its valid le vel during the time period of tis + 2 x tck + tih. 28. if tds or tdh is violated, data corruption may occur and the dat a must be re-written with valid data before a valid read can b e executed. 29. these parameters are measured from a command/address signal (cke, cs , ras , cas , we , odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck ) crossing. the spec values are not affect ed by the amount of clock jitte r applied (i.e. tjit(per), tjit(cc), etc.), as the set up and hold are relative to the clock signal crossing that latches t he command/address. that is, these parameters should be met whethe r clock jitter is pres- ent or not. 30. these parameters are measured from a data strobe signal ((l/u/r)dqs/dqs ) crossing to its respec tive clock signal (ck/ck ) crossing. the spec val- ues are not affected by the amount of clock jitter applied (i.e. tj it(per), tjit(cc), etc.), as these are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. 31. these parameters are measured from a data signal ((l/u)dm, (l/u)d q0, (l/u)dq1, etc.) transition edge to its respective data str obe signal ((l/u/ r)dqs/dqs ) crossing. 32. for these parameters, the ddr2 sdram device is characterized and verified to support tnparam = ru{tparam / tck(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. for example, the device will support tnrp = ru{trp / tc k(avg)}, which is in clock cycle s, if all input clock jitter spec ifications are met. this means: for ddr2-667 5-5-5, of which trp = 15ns, the devic e will support tnrp = ru{trp / tck(avg)} = 5, i.e. as long as the input clock jit ter specifications are met, precharge command at tm and active comm and at tm+5 is valid even if (tm+5 - tm) is less than 15ns due to input clock jitte r. 33. tdal [nck] = wr [nck] + tnrp [nck] = wr + ru {trp [ps] / tck(av g) [ps] }, where wr is the value programmed in the mode registe r set. 34. new units, ?tck(avg)? and ?nck?, are introduced in ddr2-667 and ddr2-8 00. unit ?tck(avg)? represents the actual tck(avg) of the input clock under operation. unit ?nck? represents one clock cycle of the input clock, counti ng the actual clock edges. note that in ddr2-400 and ddr2-533, ?tck? is used for both concepts. ex) txp = 2 [nck] means; if power down exit is regi stered at tm, an active command may be registered at tm+2, even if (t m+2 - tm) is 2 x tck(avg) + terr(2per),min. 35. input clock jitter spec parameter. these parameters and the on es in the table below are referr ed to as 'input clock jitter spe c parameters' and these parameters apply to ddr2-667 and ddr2-800 only. the jitter spec ified is a random jitter meeting a gaussian distribution. parameter symbol ddr2-667 ddr2-800 ddr2-1066 units note min max min max min max clock period jitter tjit(per) -125 125 -100 100 -90 90 ps 35 clock period jitter during dll locking per iod tjit(per,lck) -100 100 -80 80 -80 80 ps 35 cycle to cycle clock period jitter tjit(cc) -250 250 -200 200 -180 180 ps 35 cycle to cycle clock per iod jitter during dll locking period t jit(cc,lck) -200 200 -160 160 -160 160 ps 35 cumulative error across 2 cycles terr(2per) -175 175 -150 150 -132 132 ps 35 cumulative error across 3 cycles terr(3per) -225 225 -175 175 -157 157 ps 35 cumulative error across 4 cycles terr(4per) -250 250 -200 200 -175 175 ps 35 cumulative error across 5 cycles terr(5per) -250 250 -200 200 -188 188 ps 35 cumulative error across n cycles, n = 6 ... 10 , inclusive terr(6-10per) -350 350 -300 300 -250 250 ps 35 cumulative error across n cycles, n = 11 ... 50, inclusive terr(11-50per) -450 450 -450 450 -425 425 ps 35 duty cycle jitter tjit(duty) -125 125 -100 100 -75 75 ps 35 free datasheet http:///
- 44 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ definitions : - tck(avg) tck(avg) is calculated as the average cloc k period across any c onsecutive 200 cycle window. - tch(avg) and tcl(avg) tch(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. tcl(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses. - tjit(duty) tjit(duty) is defined as the cumulative set of tch jitter and tcl jitter. tch jitter is the largest deviation of any single t ch from tch(avg). tcl jitter is the largest deviation of any single tcl from tcl(avg). tjit(duty) = min/max of {tjit(ch), tjit(cl)} where, tjit(ch) = {tchi- tch(avg) where i=1 to 200} tjit(cl) = {tcli- tcl(avg) where i=1 to 200} - tjit(per), tjit(per,lck) tjit(per) is defined as the largest dev iation of any single tck from tck(avg). tjit(per) = min/max of {tcki- tck(avg) where i=1 to 200} tjit(per) defines the single period jitter when the dll is already locked. tjit(per,lck) uses the same definition for si ngle period jitter, during the dll locking period only. tjit(per) and tjit(per,lck) are not guaranteed through final production testing. - tjit(cc), tjit(cc,lck) tjit(cc) is defined as the differenc e in clock period between two consecutive clock cycles : tjit (cc) = max of |tck i+1 - tcki| tjit(cc) defines the cycle to cycle jitter when the dll is already locked. tjit(cc,lck) uses the same def inition for cycle to c ycle jitter, during the dll locking period only. tjit(cc) and tjit(cc,lck) are not guaranteed through final production testing. - terr(2per), terr (3per), terr (4per), terr (5per), terr (6-10per) and terr (11-50per) terr is defined as the cumulative error acro ss multiple consecutive cycles from tck(avg). tck(avg) = where n = 200 n tck j j = 1 /n n = 200 n tch j j = 1 /(n x tck(avg)) n = 200 n tcl j j = 1 /(n x tck(avg)) n = 2 i + n - 1 tck j j = 1 - n x tck(avg) for terr(2per) n = 3 for terr(3per) n = 4 for terr(4per) n = 5 for terr(5per) 6 for terr(6-10per) 11 for terr(11-50per) free datasheet http:///
- 45 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 36. these parameters are specified per their average values, however it is understood that the following relationship between the a verage timing and the absolute instantaneous timing holds at all times. (min and max of spec values are to be used for calculations in the table belo w.) example: for ddr2-667, tch(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps 37. thp is the minimum of the absolute half peri od of the actual input clock. thp is an input parameter but not an input specificat ion parameter. it is used in conjunction with tqhs to derive the dr am output timing tqh. the value to be used for tqh calculation is determined by the fo llowing equation; thp = min ( tch(abs), tcl(abs) ), where, tch(abs) is the minimum of t he actual instantaneous clock high time; tcl(abs) is the minimum of the actual instantaneo us clock low time; 38. tqhs accounts for: 1) the pulse duration distortion of on-chip clock circuits, which represents how well the actual thp at the input is trans ferred to the output; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers 39. tqh = thp - tqhs, where: thp is the minimum of the absolute half period of the ac tual input clock; and tqhs is t he specification value under the m ax column. {the less half-pulse width distortion present, the larger the tqh value is; and the larger the valid data eye will be.} examples: 1) if the system provides thp of 1315 ps into a ddr2-667 sdram, the dram provides tqh of 975 ps minimum. 2) if the system provides thp of 1420 ps into a ddr2-667 sdram, the dram provides tqh of 1080 ps minimum. 40. when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(6-10per) of the inpu t clock. (output derat- ings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2- 667 sdram has terr(6-10per)min = - 272 ps and terr(6-10per)max = + 293 p s, then tdqsck- min(derated) = tdqsckmin - terr(6-10per)max = - 400 ps - 293 ps = - 693 ps and tdqsckmax(derated) = tdqsckmax - terr(6-10per)mi n = 400 ps + 272 ps = + 672 ps. similarly, tlz(dq) for ddr2-667 derates to tlz(dq)min(derated) = - 900 ps - 293 ps = - 1193 ps and tlz( dq)max(derated) = 450 ps + 272 ps = + 722 ps. 41. when the device is operated with input cloc k jitter, this parameter needs to be derated by the actual tjit(per) of the input c lock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-667 sdram has tjit(per)min = - 72 ps and tjit(per)max = + 93 ps, then tr premin(derated) = trpremin + tjit(per)min = 0.9 x tck(avg) - 72 ps = + 2178 ps and trpremax(derated) = trpremax + tjit(per)max = 1.1 x tck(avg) + 93 ps = + 2843 ps. 42. when the device is operated with input clock jitter, this parame ter needs to be derated by the actual tjit(duty) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-667 sd ram has tjit(duty),min = - 72 ps and tjit(duty)max = + 93 ps, then trpstmin(derated) = trpstmin + tjit(duty)min = 0.4 x tck(avg) - 72 ps = + 928 ps and trpstmax(derated) = trpstmax + tj it(duty)max = 0.6 x tck(avg) + 93 ps = + 1592 ps. 43. when the device is operated with input clock jitter, this parameter needs to be derated by { - tjit(duty)max - terr(6-10per)ma x } and { - tjit(duty)min - terr(6-10per)min } of the actual input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-667 sdram has terr(6-10per)min = - 272 ps, terr(6- 10per)max = + 293 ps, tjit(duty)min = - 106 ps and tjit(duty)max = + 94 ps, then taofmin(derated) = taofmin + { - tjit(duty)max - terr(6-10per)max } = - 450 ps + { - 94 ps - 293 ps} = - 837 ps and taofmax(derated) = taofmax + { - tjit(duty)min - terr(6-10per)min } = 1050 ps + { 106 ps + 272 ps } = + 1428 ps. parameter symbol min max units absolute clock period tck(abs) tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max ps absolute clock high pulse width tch(abs) tch(avg)min x tck(avg)min + tjit(duty)min tch(avg)max x tck(avg)max + tjit(duty)max ps absolute clock low pulse width tcl(abs) tcl(avg)min x tck(avg)min + tjit(duty)min tcl(avg)max x tck(avg)max + tjit(duty)max ps free datasheet http:///
- 46 - k4t51163qj datasheet ddr2 sdram rev. 1.0 k4t51083qj K4T51043QJ 44. for taofd of ddr2-400/533, the 1/2 clock of tck in the 2.5 x tck assumes a tch, input clock high pulse width of 0.5 relative t o tck. taof,min and taof,max should each be derated by the same amount as the actual amount of tch offset present at the dram input with respect to 0.5. for example, if an input clock has a worst case tch of 0.45, the taofmin should be derated by subtracting 0.05 x tck from it, whereas if an input clock has a worst case tch of 0.55, the taofmax should be der ated by adding 0.05 x tck to it. therefore, we have; taofmin(derated) = tac,min - [0.5 - min(0.5, tchmin)] x tck taofmax(derated) = tac,max + 0.6 + [max(0.5, tchmax) - 0.5] x tck or taofmin(derated) = min(tacmin, tacmin - [0.5 - tchmin] x tck) taofmax(derated) = 0.6 + ma x(tacmax, tacmax + [tchmax - 0.5] x tck) where tchmin and tchmax are the minimum and maximum of tch actually meas ured at the dram input balls. 45. for taofd of ddr2-667/800, the 1/2 clock of nck in the 2.5 x nc k assumes a tch(avg), average input clock high pulse width of 0 .5 relative to tck(avg). taofmin and taofmax should each be derated by the same am ount as the actual amount of tch(avg) offset present at the dram input with respect to 0.5. for example, if an input clock has a worst case tch(av g) of 0.48, the taofmin should be derated by subtracting 0.02 x tck (avg) from it, whereas if an input clock has a worst case tch(avg) of 0.52, the taofmax shoul d be derated by adding 0.02 x tck(avg) to it. therefore, we hav e; taofmin(derated) = tacmin - [0.5 - min(0.5, tch(avg)min)] x tck(avg) taofmax(derated) = tacmax + 0. 6 + [max(0.5, tch(avg)max) - 0.5] x tck(avg) taofmin(derated) = min(tacmin, tacmin - [0.5 - tch(avg)min] x tck(avg)) taofmax(derated) = 0.6 + max(tacm ax, tacmax + [tch(avg)max - 0.5] x tck(avg)) where tch(avg),min and tch(avg),max are the minimum and maximum of tch(avg) actually measured at the dram input balls. note : tthat these deratings are in addition to the taof derating per input clock jitter, i.e. tjit(duty) and terr(6-10per). howeve r tac values used in the equations shown above are from the timing parameter table and are not dera ted. thus the final derated values for taof are; taofmin(derated_final) = taofmin(derated) + { - tjit(duty)max - terr(6-10per)max } taofmax(derated_final) = taofmax(derated) + { - tjit(duty)min - terr(6-10per)min } free datasheet http:///

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