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sc28l202 dual universal asynchronous receiver/transmitter (duart) objective specification ic19 data handbook 1998 oct 05 integrated circuits
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) designed for aglueless operation in 68xxx and x86 environmentso 2 1998 oct 05 description the 28l202 is a high performance functional upgrade for the philips dual channel uarts. the scc2692 and sc26c92 operating at 3.3 or 5 volts supply with added features and deeper partitioned fifos. its configuration on power up is similar that of the sc26c92. its differences from the sc26c92 are: 256 character receiver, 256 character transmit fifos, crc error detection, 3 and 5 volt compatibility, 8 i/o ports for each uart. irda compatibility, arbitrating interrupt system and overall faster buss and data speeds. it is fabricated in an advanced cmos process that allows stand by current of less that one microampere. pin programming will allow the device to operate with either the motorola or intel bus interface by changing the function of some pins. (reset is inverted, dackn enabled for example). the philips semiconductors 28l202 dual universal asynchronous receiver/transmitter (duart) is a single-chip cmoslsi communications device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. it interfaces directly with microprocessors and may be used in a polled or interrupt driven system. the operating mode and data format of each channel can be programmed independently. additionally, each receiver and transmitter can select its operating speed as one of twenty-three fixed baud rates; a 16x clock derived from a programmable counter/timer, or an external 1x or 16x clock. the baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. the ability to independently program the operating speed of the receiver and transmitter make the duart particularly attractive for dual-speed channel applications such as clustered terminal systems. each receiver and transmitter is buffered by eight character fifos to minimize the potential of receiver overrun, transmitter underrun and to reduce interrupt overhead in interrupt driven systems. in addition, a flow control capability is provided to disable a remote transmitter when the receiver buffer is full. also provided on the 28l202 are a multipurpose 7-bit input port and a multipurpose 8-bit output port. these can be used as general-purpose i/o ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control. the 28l202 are available in two package versions: a 44-pin plcc and 44-pin plastic quad flat pack (pqfp). features ? 3.3 or 5.0 volt operation ? dual full-duplex independent asynchronous receiver/transmitters ? 256 or larger character fifos for each receiver and transmitter ? power up as 8 bit data no parity one stop bit 9600 baud ? pin programming (pqfp package) to 68k or 80xxx bus interface ? programmable data format 5 to 8 data bits plus parity odd, even, no parity or force parity 1, 1.5 or 2 stop bits programmable in 1/16-bit increments ? 16-bit programmable counter/timer ? programmable baud rate for each receiver and transmitter selectable from: 23 fixed rates: 50 to 230.4k baud other baud rates to mhz at 16x programmable user-defined rates derived from a programmable counter/timer external 1x or 16x clock ? parity, framing, and overrun error detection ? false start bit detection ? line break detection and generation ? programmable channel mode normal (full-duplex) automatic echo local loop back remote loop back multi-drop mode (also called `wake-up' or `9-bit') ? multi-function 7-bit input port can serve as clock or control inputs change of state detection on eight inputs inputs have typically >100k pull-up resistors ? multi-function 8-bit output port individual bit set/reset capability outputs can be programmed to be status/interrupt signals ? versatile interrupt system single interrupt output with eight maskable interrupting conditions output port can be configured to provide a total of up to six separate interrupt outputs that may be wire ored. each fifo can be programmed for four different interrupt levels. watch dog timer for each receiver ? maximum data transfer rates: 1x 1mb/sec, 16x 1mb/sec ? automatic wake-up mode for multi-drop applications ? start-end break interrupt/status ? detects break which originates in the middle of a character ? on-chip crystal oscillator ? power down mode ? receiver time-out mode ? single +3.3v or +5v power supply ? powers up to emulate scc2692 and sc26c92
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 3 ordering information description industrial v cc = +3.3 +5v 10%, t a = 40 to +85 c drawing number 44-pin plastic leaded chip carrier (plcc) 28L202A1A sot1872 44-pin plastic quad flat pack (pqfp) 28l202a1b sot3072
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 4 pin configuration diagram pin function pin function 1nc 27d2 2a0 28d0 3 i/ob3 29 i/oa6 4 a1 30 i/oa4 5 i/ob1 31 i/oa2 6 a2 32 i/oa0 7 a3 33 txda 8 i/ob0 34 nc 9 wrn 35 rxda 10 rdn 36 x1/clk 11 rxdb 37 x2 12 i/m 38 reset 13 txdb 39 cen 14 i/oa1 40 i/ob2 15 i/oa3 41 i/ob6 16 i/oa5 42 i/ob5 17 i/oa7 43 i/ob4 18 d1 44 v cc 19 d3 45 a4 20 d5 46 a5 21 d7 47 i/ob7 22 v ss 48 pre 23 nc 49 v cc 24 intrn 50 v ss 25 d6 51 nc 26 d4 52 nc 1 46 20 33 47 34 21 8 plcc 7 top view index corner sd00680
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 5 pin configuration diagram pin function pin function 1nc 27d2 2a0 28d0 3 i/ob3 29 i/oa6 4 a1 30 i/oa4 5 i/ob1 31 i/oa2 6 a2 32 i/oa0 7 a3 33 txda 8 i/ob0 34 nc 9 r/wn 35 rxda 10 dackn 36 x1/clk 11 rxdb 37 x2 12 i/m 38 resetn 13 txdb 39 cen 14 i/oa1 40 i/ob2 15 i/oa3 41 iackn 16 i/oa5 42 i/ob5 17 i/oa7 43 i/ob4 18 d1 44 v cc 19 d3 45 a4 20 d5 46 a5 21 d7 47 i/ob7 22 v ss 48 pre 23 nc 49 v cc 24 intrn 50 v ss 25 d6 51 nc 26 d4 52 nc 1 46 20 33 47 34 21 8 plcc 7 top view index corner sd00681
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 6 absolute maximum ratings 1 symbol parameter rating unit t a operating ambient temperature range 2 see note 3 c tstg storage temperature range 65 to +150 c v cc voltage from v cc to gnd 4 0.5 to +7.0 v v ss voltage from any pin to gnd 0.5 to v cc + 0.5 v pd5 power dissipation at v cc = 5.6 volts 1 w pd3 power dissipation at v cc = 3.3 volts 0.5 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the. operation section of this specification is not implied. 2. for operating at elevated temperatures, the device must be derated based on +150 c maximum junction temperature. 3. parameters are valid over specified temperature range. see ordering information table for applicable temperature range and op erating supply range. 4. this product includes circuitry specifically designed for the protection of its internal devices from damaging effects of exc essive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rate d maxim.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 7 8 d0d7 rdn wrn cen a0a5 reset intrn x1/clk x2 4 bus buffer operation control address decode r/w control interrupt control imr isr timing baud rate generator clock selectors counter/ timer xtal osc csra csrb acr ctlr channel a transmit holding reg transmit shift register receive holding reg (3) receive shift register mra1, 2 cra sra i/o port a change of state detectors (4) i/o port b function select logic opcr txda rxda i/o7:0a i/o7:0b v cc gnd control timing internal databus channel b (as above) ipcr acr opr ctlr u rxdb txdb 8 8 sd00679 fifo ram fifo databus fifo control i/m figure 1. block diagram
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 8 pin configuration for 80xxx bus interface (intel) symbol pin type name and function i/m i bus configuration : when high or not connected configures the bus interface to the conditions shown in this table. d0d7 i/o data bus : bi-directional 3-state data bus used to transfer commands, data and status between the duart and the cpu. d0 is the least significant bit. cen i chip enable : active-low input signal. when low, data transfers between the cpu and the duart are enabled on d0d7 as controlled by the wrn, rdn and a0a3 inputs. when high, places the d0d7 lines in the 3-state condi- tion. wrn i write strobe : when low and cen is also low, the contents of the data bus is loaded into the addressed register. the transfer occurs on the rising edge of the signal. rdn i read strobe : when low and cen is also low, causes the contents of the addressed register to be presented on the data bus. the read cycle begins on the falling edge of rdn. a0a3 i address inputs : select the duart internal registers and ports for read/write operations. reset i reset : a high level clears internal registers (sra, srb, imr, isr, opr, opcr), puts op0 op7 in the high state, stops the counter/timer, and puts channels a and b in the inactive state, with the txda and txdb outputs in the mark (high) state. sets mr pointer to mr1. intrn o interrupt request : active-low, open-drain, output which signals the cpu that one or more of the eight maskable inter- rupting conditions are true. x1/clk i crystal 1 : crystal or external clock input. a crystal or clock of the specified limits must be supplied at all times. when a crystal is used, a capacitor must be connected from this pin to ground (see figure 7). x2 o crystal 2 : connection for other side of the crystal. when a crystal is used, a capacitor must be connected from this pin to ground (see figure 7). if x1/clk is driven from an external source, this pin must be left open. rxda i channel a receiver serial data input : the least significant bit is received first. amarko is high; aspaceo is low. rxdb i channel b receiver serial data input : the least significant bit is received first. amarko is high; aspaceo is low. txda o channel a transmitter serial data output : the least significant bit is transmitted first. this output is held in the amarko condition when the transmitter is disabled, idle or when operating in local loop back mode. amarko is high; aspaceo is low. txdb o channel b transmitter serial data output : the least significant bit is transmitted first. this output is held in the `mark' condition when the transmitter is disabled, idle, or when operating in local loop back mode. `mark' is high; `space' is low. i/o[7:0]a o general-purpose input and output ports channel a : the character of these pins is controlled by i/opcr. they may be inputs or outputs and will present many internal clocks and interrupt signals: rts, cts, dtr, dsr etc. all have change of state detectors and the input is always active. i/o[7:0}b o general-purpose input and output ports channel b : the character of these pins is controlled by i/opcr. they may be inputs or outputs and will present many internal clocks and interrupt signals: rts, cts, dtr, dsr etc. all have change of state detectors and the input is always active. v cc pwr power supply : +3.3 or +5v supply input 10% gnd pwr ground
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 9 pin configuration for 68xxx bus interface (intel) symbol pin type name and function i/m i bus configuration : when low configures the bus interface to the conditions shown in this table. d0d7 i/o data bus : bi-directional 3-state data bus used to transfer commands, data and status between the duart and the cpu. d0 is the least significant bit. csn i chip enable : active-low input signal. when low, data transfers between the cpu and the duart are enabled on d0d7 as controlled by the r/wn and a0a3 inputs. when high, places the d0d7 lines in the 3-state condition. r/wn i read/write : input signal. when csn is low r/wn high input a read cycle, when low a write cycle. iackn i interrupt acknowledge : active low input indicates an interrupt acknowledge cycle. usually asserted by the cpu in response to an interrupt request. when asserted places the interrupt vector on the bus and asserts dackn. dackn o data transfer acknowledge : a3state active low output asserted in a write, read, or interrupt acknowledge cycle to indicate proper transfer of data between the cpu and the duart. a0a3 i address inputs : select the duart internal registers and ports for read/write operations. resetn i reset : a low level clears internal registers (sra, srb, imr, isr, opr, opcr), puts op0op7 in the high state, stops the counter/timer, and puts channels a and b in the inactive state, with the txda and txdb outputs in the mark (high) state. sets mr pointer to mr1. intrn o interrupt request : activelow, open-drain, output which signals the cpu that one or more of the eight maskable interrupting conditions are true. x1/clk i crystal 1 : crystal or external clock input. a crystal or clock of the specified limits must be supplied at all times. when a crystal is used, a capacitor must be connected from this pin to ground (see figure 7). x2 o crystal 2 : connection for other side of the crystal. when a crystal is used, a capacitor must be connected from this pin to ground (see figure 7). if x1/clk is driven from an external source, this pin must be left open. rxda i channel a receiver serial data input : the least significant bit is received first. amarko is high; aspaceo is low. rxdb i channel b receiver serial data input : the least significant bit is received first. amarko is high; aspaceo is low. txda o channel a transmitter serial data output : the least significant bit is transmitted first. this output is held in the amarko condition when the transmitter is disabled, idle or when operating in local loop back mode. amarko is high; aspaceo is low. txdb o channel b transmitter serial data output : the least significant bit is transmitted first. this output is held in the `mark' condition when the transmitter is disabled, idle, or when operating in local loop back mode. `mark' is high; `space' is low. i/o[7:0]a i/o general-purpose input and output ports channel a : the character of these pins is controlled by i/opcr. they may be inputs or outputs and will present many internal clocks and interrupt signals: rts, cts, dtr, dsr etc. all have change of state detectors and the input is always active. i/o[7:0]b i/o general-purpose input and output ports channel b : the character of these pins is controlled by i/opcr. they may be inputs or outputs and will present many internal clocks and interrupt signals: rts, cts, dtr, dsr etc. all have change of state detectors and the input is always active. v cc power power supply : +3.3 or +5v supply input 10% v ss power ground
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 10 ac characteristics 1, 2, 3 symbol parameter limits 4 symbol parameter min typ max unit reset timing (see figure 2) t res reset pulse width 200 ns bus timing 5 (see figure 3) t* as a0a3 setup time to rdn, wrn low 10 ns t* ah a0a3 hold time from rdn, wrn low 45 ns t* cs cen setup time to rdn, wrn low 0 ns t* ch cen hold time from rdn wrn low 0 ns t* rw wrn, rdn pulse width (low time) 110 ns t* dd data valid after rdn low 90 ns t* da rdn low to data bus active 6 0 ns t* df data bus floating after rdn or cen high 30 ns t* di rdn or cen high to data bus invalid 3 0 ns t* ds data bus setup time before wrn or cen high (write cycle) 75 ns t* dh data hold time after wrn high 8 ns t* rwd high time between read and/or write cycles 1, 7 55 ns port timing 1 (see figure 5) t* ps port in setup time before rdn low (read ip ports cycle) 0 ns t* ph port in hold time after rdn high 0 ns t* pd op port valid after wrn or cen high (opr write cycle) 110 ns interrupt timing (see figure 6) intrn (or op3op7 when used as interrupts) negated from: read rxfifo (rxrdy/ffull interrupt) 100 ns write txfifo (txrdy interrupt) 100 ns t* ir reset command (delta break change interrupt) 100 ns stop c/t command (counter/timer interrupt) 100 ns read ipcr (delta input port change interrupt) 100 ns write imr (clear of change interrupt mask bit(s)) 100 ns clock timing (see figure 7) t* clk x1/clk high or low time 80 ns f* clk x1/clk frequency 8 0.1 3.686 4 mhz f* ctc c/t clk (ip2) high or low time (c/t external clock input) 55 ns f* ctc c/t clk (ip2) frequency 4 0 8 mhz t* rx rxc high or low time (16x) 30 ns f* rx rxc frequency (16x) 0 16 mhz rxc frequency (1x) 4, 9 0 1 mhz t* tx txc high or low time (16x) 30 ns f* tx txc frequency (16x) 16 mhz txc frequency (1x) 4, 5 0 1 mhz transmitter timing (see figure 8) t* txd txd output delay from txc low (txc input pin) 120 ns t* tcs output delay from txc output pin low to txd data output 30 30 ns receiver timing (see figure 9) t* rxs rxd data setup time to rxc high 100 ns t* rxh rxd data hold time from rxc high 100 ns notes: 1. parameters are valid over specified temperature range. 2. all voltage measurements are referenced to ground (gnd). for testing, all inputs swing between 0.4 v and 3.0 v with a transit ion time of 5 ns maximum. for x1/clk this swing is between 0.4 v and 4.4 v. all time measurements are referenced at input voltage of 0.8 v and 2.0 v and output voltages of 0.8 v and 2.0 v, as appropriate. 3. test conditions for outputs; c l = 150 pf, except interrupt outputs. test conditions for interrupt outputs; c l = 50 pf, rl = 2.7 kohm to v cc . 4. typical values are at +25 c, typical supply voltages, and typical processing parameters. 5. timing is illustrated and referenced to the wrn and rdn inputs. also, cen may be the astrobingo input. cen and rdn (also cen and wrn) are ored internally. the signal asserted last initiates the cycle and the signal negated first terminates the cycle. 6. guaranteed by characterization of sample units. 7. if cen is used as the astrobingo input, the parameter defines the minimum high times between one cen and the next. the rdn si gnal must be negated for t rwd to guarantee that any status register changes are valid. 8. minimum frequencies are not tested but are guaranteed by design. 9. clocks for 1x mode should be symmetrical.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 11 over all description the sc28l202 is composed of several functional blocks. they are listed in the approximate order of hierarchy as seen from the pins of the device. ? timing circuits ? bus interface. 68k or x86 format ? i/o ports ? uarts ? arbitrating interrupt structure ? character & address recognition ? variable fifo partition structure ? test modes and boundary scan brief description of functional blocks timing circuits crystal oscillator the crystal oscillator is the main timing element for the 28l202. it is nominally set at 14.7456 mhz and may be used to 29.4912 mhz. the use of an external clock allows all frequencies to 40 mhz. brg the brg is the baud rate generator, is driven by the crystal input and generated all of the 24 afixedo internal baud rates. counter-timer. the counter-timer provides miscellaneous baud rated, timing periods and acts as an extra watchdog timer for the for the receivers. it has 8 clock sources. bus interface the bus interface operates in a68ko or ax86o format as selected by the i/m pin. the signals used by this section are the address, data bus, chip select, read/write, data acknowledge and interrupt acknowledge and interrupt request. assertion of dackn requires two edges of the x1clk after the assertion of cen. i/o ports each uart is provided with 8 i/o ports. each port is equipped with a change of state detector. the input circuit of these pins is always active. under program control the ports my display internal signals or static logic levels. the functions represented by the i/o ports include hardware flow control. modem signals, signals for interrupt conditions or various internal clocks and timing intervals. noisy inputs to the i/o ports are filtered (de-bounced) by a 38.4 khz clock. uarts the uarts are fully independent, full duplex and provide all normal asynchronous functions: 5 to 8 data bits, parity odd or even, programmable stop bit length, false start bit detection. also provided are 256 byte fifos xon/xoff software flow control and irda pulse modulation. the brg, counter-timer, or external clocks provide the baud rates. the receivers and transmitters may operate in either the a1xo or a16xo modes. interrupt arbitration the interrupt system uses a highly programmable arbitrating technique to establish when an interrupt should be presented to the processor. the advantageous feature of this system is the presentation of the context of the interrupt. it is presented in both a current interrupt register and in the interrupt vector. the context of the interrupt shows the interrupting channel, identifies which of the 8 possible sources in requesting interrupt service and in the case of a receiver or transmitter gives the current fill level of the fifo. the content of the current interrupt register also drives the global registers of the interrupt system. these registers are indirect addresses (pointers) to the fields describing the internal source requesting interrupt service. programming of bid control registers allows the interrupt level of any source to be varied at any time over a range of 256 levels. character and address recognition the character recognition system is designed as a general system. there is one for each uart. each recognition block stores up to three characters. the recognition is done on a byte boundary and sets status and interrupt when an recognition event occurs. each has four modes of operation. a subset of the recognition system is xon/xoff character recognition and multi-drop address recognition. if xon/xoff or multi-dorp function is enabled the recognition system passes the information about the recognition event to the appropriate receiver or transmitter state machine for execution. in any case the information about a recognition event is available to the interrupt system and to the control processor. fifo partitioning and control the fifo memory is implemented in ram. nominally 1000 bytes of ram are divided between the four fifos of the duart. the default partition is 256 (0xff) bytes for each fifo. under program control size of the partition for any a particular fifo may be varied from 1 to 1024. the interrupt level for each fifo is also under program control and is continuously variable through out the range of the partition. a small processor controls all of the fifo reading, writing, interrupting, flow control signaling, and status reporting. test modes three test modes are provided to verify uart function and processor interface integrity. these are auto echo, local loop back, and remote loop back. through local loop back the software developer may verify all of the interrupt, flow control; the hardware designer verifies all of the timing and pin connections. this information is obtained without any recourse to external test equipment or terminals. boundary scan provides verification of manufacturing process and to a lesser extent identifies damage that may occur to pins due to electrical over stress or electrostatic discharge. detailed descriptions note : for the convenience of the reader some paragraphs in the following section will be repeated in descriptions of closely linked functions. timing circuits crystal oscillator the crystal oscillator operates directly from a crystal, tuned between 14.7456 mhz and 29 4912 mhz connected across the x1/cclk and x2 inputs with a minimum of external components. brg values listed for the clock select registers correspond to a 14.7456 mhz
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 12 crystal frequency. use of different frequencies will change the astandardo baud rates by precisely the ratio of 14.7456 to the different crystal. an external clock up to 40 mhz frequency range may be connected to x1/cclk. if an external clock is used instead of a crystal, x1/cclk must be driven and x2 left floating. the x1 clock serves as the basic timing reference for the baud rate generator (brg) and is available to the brg timers, counter-timers, and control logic. baud rate generator brg the baud rate generator operates from the oscillator or external x1/cclk clock input and generates 24 commonly used data communications baud rates (including middi) ranging from 50 to 230.4k baud. these common rates may be doubled (up to 460.8 and 1500k baud) when faster clocks are used on the x1/x2 clock inputs. (see receiver and transmitter clock select register descriptions.) all of these are available simultaneously for use by any receiver or transmitter. the clock outputs from the brg are at 16x the actual baud rate. counter-timer the two counter/timers are programmable 16 bit dividers that are used for generating miscellaneous clocks or generating timeout periods. these clocks may be used by any or all of the receivers and transmitters in the duart or may be directed to an i/o pin for external use. counter/timer programming the counter timer is a 16-bit programmable divider that operates in one of five modes: character count, pulse mode, counter, timer, and time out. character count counts characters. the pulse mode generates a periodic pulse of one clock period in width. the timer mode it generates a square wave. in the counter mode it generates a time delay. in the time out mode it monitors the time between received characters. the c/t uses the numbers loaded into the counter/timer lower register (ctlr) and the counter/timer upper register (ctur) as its divisor. the counter timer is controlled with six commands: start/stop c/t, read/write counter/timer lower register and read/write counter/timer upper register. these commands have slight differences depending on the mode of operation. please see the detail of the commands under the ctlr/ctur register descriptions. when ever the these timers are selected via the receiver or transmitter clock select register their output will be configured as a 16x clock for the respective receiver or transmitter. therefore one needs to program the timers to generate a clock 16 times faster than the data rate. the formula for calculating 'n', the number loaded to the ctur and ctlt registers. for the timer mode the formula is as follows: n brg timer input frequency 2 16 baud rate desired 1 for the pulse mode the formula is as follows: n brg timer input frequency 16 baud rate desired 1 note : `n' may assume values of 0 and 1. in previous philips data communications controllers these values were not allowed. the counter/timer control register (ctcr) controls the brg timer input frequency. the frequency generated from the above formula will be at a rate 16 times faster than the desired baud rate. the transmitter and receiver state machines include divide by 16 circuits, which provide the final frequency and provide various timing edges used in the qualifying the serial data bit stream. often this division will result in a non-integer value: 26.3 for example. one may only program integer numbers to a digital divider. there for 26 would be chosen. if 26.7 were the result of the division then 27 would be chosen. this gives a baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage error of 1.14% or 1.12% respectively, well within the ability of the asynchronous mode of operation. higher input frequency to the counter reduces the error effect of the fractional division. one should be cautious about the assumed benign effects of small errors since the other receiver or transmitter with which one is communicating may also have a small error in the precise baud rate. in a acleano communications environment using one start bit, eight data bits and one stop bit the total difference allowed between the transmitter and receiver frequency is approximately 4.6%. less than eight data bits will increase this percentage. bus interface the bus interface operates in two modes selected by the i/m pin. if this pin is high or left open the signals dackn signal is not generated or used and data flow to and from the chip is controlled by the state the cen, rdn, wrn pin combination. if the i/m pin is tied low the data is written to the device when the dackn pin is asserted low by the duart. read data is presented by a delay from cen active. the host interface is comprised of the signal pins cen, wrn rdn, (or r/wn) iackn, dackn, irqn, 6 address pins and 8 three-state data bus pins. addressing of the various functions of the duart is through the address bus a (5:0). data is presented on the 8-bit data bus. dackn cycle when operating in the a68ko mode bus cycle completion is indicated by the dackn pin (an open drain signal) going low. this occurs two x1 clock edges after the cycle begins. usually in this mode the address and data are set up with respect to the leading edges of the bus cycle. when operating in the ax86o mode dackn is not generated. data is written on the termination of cen or wrn which ever one occurs first. read data is presented from the leading edge of the read condition; cen and rdn both low. iackn cycle, update cir when the host cpu responds to the interrupt, it will usually assert the iackn signal low. this will cause the duart to generate an iackn cycle in which the condition of the interrupting device is determined. when iackn asserts, the last valid interrupt number is captured in the cir. the value captured presents all of the important details of the highest priority interrupt at the moment the iackn (or the aupdate ciro command) was asserted. due to system interrupt latency, the interrupt condition captured by the cir may not be the condition that caused the initial assertion of the interrupt. the dual uart will respond to the iackn cycle with an interrupt vector. the interrupt vector may be a fixed value, the content of the interrupt vector register, or when ainterrupt vector modificationo is enabled via icr, it may contain codes for the interrupt type and/or
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 13 interrupting channel. this allows the interrupt vector to steer the interrupt service directly to the proper service routine. the interrupt value captured in the cir remains until another iackn cycle occurs or until an aupdate ciro command is given to the duart. the interrupting channel and interrupt type fields of the cir set the current ainterrupt contexto of the duart. the channel component of the interrupt context allows the use of global interrupt information registers that appear at fixed positions in the register address map. for example, a read of the global rxfifo will read the channel b rxfifo if the cir interrupt context is channel b receiver. at another time read of the grxfifo may read the channel a rxfifo (cir holds a channel a receiver interrupt) and so on. global registers exist to facilitate qualifying the interrupt parameters and for writing to and reading from fifos without explicitly addressing them. the cir will load with 0x'00 if iackn or update cir is asserted when the arbitration circuit is not asserting an interrupt. in this condition there is no arbitration value that exceeds the threshold value. when interrupt vector modification is active in this situation the interrupt vector bits associated with the cir will all be zero. i/o ports eight i/o ports are provided for each channel. they may be programmed to be inputs or outputs. the input circuits are always active whether programmed as and input or an output. a 2 bit code controls what function these pins will present. most i/o ports default to high impedance input state on power up. those pins used for modem control (rts, dtr) will set to output high unless the pre pin is tied low. input characteristics eight i/o pins are provided for each channel. these pins are configured individually to be inputs or outputs. as inputs they may be used to bring external data to the bus, as clocks for internal functions or external control signals. each i/o pin has a achange of stateo detector. the change detectors are used to signal a change in the signal level at the pin (either 0 to 1 or 1 to 0 transitions). the level change on these pins must be stable for 25 to 50 us (two edges of the 38.4 khz baud rate clock) before the detectors will signal a valid change. these are typically used for interface signals from modems to the duart and from there to the host. output port the opr, opcr, mr, and cr registers may control the i/o pins when configured as outputs. via appropriate programming the pins of the output port may be configures as another parallel port to external circuits, or they may represent internal conditions of the uart. when this 8-bit port is used as a general-purpose output port, the output port pins drive a state that is the complement of the output port register (opr). the opr register is set and reset by writing to the sopr and ropr addresses. (see the description of the sopr and ropr registers). the output pins will drive the inverse data polarity of the opr registers. the opcr register conditions these output pins to be controlled by the opr or by other signals in the chip. output ports are driven high on hardware reset. uart operation receiver and transmitter the dual uart has two full duplex asynchronous receiver/transmitters. the operating frequency for the receiver and transmitter can be selected independently from the baud rate generator, the counter, or from an external input. registers that are central to basic full-duplex operation are the mode registers (mr0, mr1 and mr2), the clock select registers (rxcsr and txcsr), the command register (cr), the status register (sr), the transmit holding register (txfifo), the receive holding register (rxfifo) interrupt status register (isr) and interrupt mask register (imr). transmitter status bits the sr (status register, one per uart) contains two bits that show the condition of the transmitter fifo. these bits are txrdy and txemt. txrdy means the txfifo has space available for one or more bytes; txemt means the txfifo is completely empty and the last stop bit has been completed. txemt can not be active without txrdy also being active. these two bits will go active upon initial enabling of the transmitter. they will extinguish on the disable or reset of the transmitter. transmission resumes and the txemt bit is cleared when the cpu loads at least one new character into the txfifo. the txrdy will not extinguish until the txfifo is completely full. the txrdy bit will always be active when the transmitter is enabled and there is at lease one open position in the txfifo. the transmitter is disabled by a hardware reset, a transmitter reset in the command register or by the transmitter disable bit also in the command register (cr). the transmitter must be explicitly enabled via the cr before transmission can begin. note that characters cannot be loaded into the txfifo while the transmitter is disabled, hence it is necessary to enable the transmitter and then load the txfifo. it is not possible to load the txfifo and then enable the transmission. note the difference between transmitter disable and transmitter reset. either hardware or software may cause the reset action. when reset the transmitter stops transmission immediately. the transmit data output will be driven high, transmitter status bits set to zero and any data remaining in the txfifo will be discarded. the transmitter disable is controlled by the tx enable bit in the command register. setting this bit to zero will not stop the transmitter immediately but will allow it to complete any tasks presently underway. it is only when the last character in the txfifo and its stop bit(s) have been transmitted that the transmitter will go to its disabled state. while the transmitter enable/disable bit in the command register is at zero the txfifo will not accept any more characters. transmission of abreako transmission of a break character is often needed as a synchronizing condition in a data stream. the abreako is defined as a start bit followed by all zero data bits by a zero parity bit (if parity is enabled) and a zero in the stop bit position. the forgoing is the minimum time to define a break. the transmitter can be forced to send a break (continuous low condition) by issuing a start break command via the cr. this command does not have any timing associated with it. once issued the txd output will be driven low (the spacing condition) and remain there until the host issues a command to astop breako via the cr or the transmitter is issued a software or hardware reset. in normal operation the break is usually much longer than one character time. 1x and 16x modes, transmitter the transmitter clocking has two modes: 16x and 1x. data is always sent at the 1x rate. however the logic of the transmitter may be operated with a clock that is 16 times faster than the data rate or at the same rate as the data i.e. 1x. all clocks selected internally for the transmitter (and the receiver) will be 16x clocks. only when an
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 14 external clock is selected may the transmitter logic and state machine operate in the 1x mode. the 1x or 16x clocking makes little difference in transmitter operation. (this is not true in the receiver) in the 16x-clock mode the transmitter will recognize a byte in the txfifo within 1/16 to 2/16-bit time and thus begin transmission of the start bit. in the 1x mode this delay may be up to 2 bit times. transmitter fifo the fifo configuration of the as 28l202 is not fixed in size. the dimension of each fifo is under program control and may set from a value of 1 byte to 1021. it is designed to facilitate large data blocks and to provide very flexible interrupt for each fifo. interrupt levels may be set to any level within the fifo size and may be set differently for each fifo. logic associated with the fifo encodes the number of filled positions for presentation to the interrupt arbitration system. the encoding is always 1 less than the number of filled positions. thus, a full rxfifo will bid with the value or 255; when empty it will not bit at all; one position occupied bids with the value 0. an empty fifo will not bid since no character is available. normally rxfifo will present a bid to the arbitration system whenever it has one or more filled positions. the mr2 [3:2 bits allow the user to modify this characteristic so that bidding will not start until one of four levels (one or more filled, 1/2 filled, 3/4 filled, full) have been reached. as will be shown later this feature may be used to make slight improvements in the interrupt service efficiency. a similar system exists in the transmitter. the fifo is controlled by three parameters: size, interrupt level and page size. the hardware reset establishes the fifo size for each receiver and transmitter at 256 bytes, the interrupt level at 128 bytes, and the page size 0. the internal fifo control unit manages the fifo loading, addressing, empty-full status and current fill level. it also notifies the rts/cts xon/xoff circuits when the fifo levels have reached the appropriate fill levels to trigger their corresponding actions. transmitter the 28l202 is conditioned to transmit data when the transmitter is enabled through the command register. the transmitter of the 28l202 indicates to the cpu that it is ready to accept a character by setting the txrdy bit in the status register. this condition can be programmed to generate an interrupt request at i/o6 or i/o7 and intrn. when the transmitter is initially enabled the txrdy and txempt bits will be set in the status register. when a character is loaded to the transmit fifo the txempt bit will be reset. the txempt bit will not set until the transmit fifo is empty and the transmit shift register has finished transmitting the stop bit of the last character written to the transmit fifo, or the transmitter is disabled and then re-enabled. the txrdy bit is set whenever the transmitter is enabled and the txfifo is not full. data is transferred from the holding register to transmit shift register when it is idle or has completed transmission of the previous character. characters cannot be loaded into the txfifo while the transmitter is disabled. the transmitter converts the parallel data from the cpu to a serial bit stream on the txd output pin. it automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. the least significant bit is sent first. following the transmission of the stop bits, if a new character is not available in the txfifo, the txd output remains high and the txemt bit in the status register (sr) will be set to 1. transmission resumes and the txemt bit is cleared when the cpu loads a new character into the txfifo. if the transmitter is disabled, it continues operating until the character currently being transmitted is completely sent out. the transmitter can be forced to send a continuous low condition by issuing a send break command. the transmitter can be reset through a software command. if it is reset, operation ceases immediately and the transmitter must be enabled through the command register before resuming operation. if cts option is enabled (mr2 [4] = 1), the cts input at i/o0 or i/o1 must be low in order for the character to be transmitted. the transmitter will check the state of the cts input at the beginning of each character transmitted. if it is found to be high, the transmitter will delay the transmission of any following characters until the cts has returned to the low state. cts going high during the serialization of a character will not affect that character. the transmitter can also control the rtsn outputs, i/o0 or i/o1 via mr2 [5]. when this mode of operation is set the meaning of the i/o0 or i/o1 signals is aall bytes loaded to the transmitter's fifo have been transmitted including the last stop bit(s). receiver operation receiver the receiver accepts serial data on the rxd pin, converts the serial input to parallel format, checks for start bit, stop bit, parity bit (if any), framing error or break condition, and presents the assembled character and its status condition to the cpu via the rxfifo. three status bits are fifoed with each character received. the rxfifo is really 11 bits wide: eight data and 3 status. unused fifo bits for character lengths less than 8 bits are set to zero. it is important to note that receiver logic considers the entire message to be contained within the start bit to the stop bit. it is not aware that a message may contain many characters. the receiver returns to its idle mode at the end of each stop bit! as described below it immediately begins to search for another start bit, which is normally, of course, immediately forth coming. 1x and 16x mode, receiver the receiver operates in one of two modes: 1x and 16x. of the two, the 16x is more robust and the preferred mode. although the 1x mode may allow a faster data rate is does not provide for the alignment of the receiver 1x data clock to that of the transmitter. this strongly implies that the 1x clock of the remote transmitter is available to the receiver; the two devices are physically close to each other. the 16x mode operates the receiver logic at a rate 16 times faster than the 1x data rate. this allows for validation of the start bit, validation of level changes at the receiver serial data input (rxd), and a stop bit length as short as 9/16 bit time. of most importance in the 16x mode is the ability of the receiver logic to align the phase of the receiver 1x data clock to that of the transmitter with an accuracy of less than 1/16 bit time. receiver the receiver of the 28l202 is conditioned to receive data when enabled through the command register. the receiver looks for a high-to-low (mark-to-space) transition of the start bit on the rxd input pin. if a transition is detected, the state of the rxd pin is sampled each 16x clock for 7-1/2 clocks (16x clock mode) or at the next rising edge of the bit time clock (1x clock mode). if rxd is sampled high, the start bit is invalid and the search for a valid start bit begins again. if rxd is still low, a valid start bit is assumed. the receiver then continues to sample the input at one-bit time intervals at the theoretical center of the bit. when the proper number of data
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 15 bits and parity bit (if used) have been assembled, and one half-stop bit has been detected the receiver loads the byte to the fifo. the least significant bit is received first. the data is then transferred to the receive fifo and the rxrdy bit in the sr is set to a 1. this condition can be programmed to generate an interrupt at op4 or op5 and intrn. if the character length is less than 8 bits, the most significant unused bits in the rxfifo are set to zero. after the stop bit is detected, the receiver will immediately look for the next start bit. however, if a non-zero character was received with the stop bit at a zero level (framing error) and rxd remains low for at least another one half bit time after the stop bit was sampled, then the receiver operates as if a new start bit had been detected. it then continues assembling the next character. the error conditions of parity error, framing error, and overrun error (if any) are strobed into the sr at the received character boundary. this is just before the rxrdy status bit is set. if a break condition is detected (rxd is low for the entire character including the stop bit), a character consisting of all zeros will be loaded into the rxfifo and the received break bit in the sr is set to 1. the rxd input must return to high for two (2) clock edges of the x1 crystal clock for the receiver to recognize the end of the break condition and begin the search for a start bit. this will usually require a high time of one x1 clock period or 3 x1 edges since the clock of the controller is not synchronous to the x1 clock. receiver status bits there are five (5) status bits that are evaluated with each byte (or character) received: received break, framing error, parity error, overrun error, and change of break. the first three are appended to each byte and stored in the rxfifo. the last two are not necessarily related to the byte being received or a byte that is in the rxfifo. they are however developed by the receiver state machine. the areceived breako will always be associated with a zero byte in the rxfifo. it means that zero character was a break character and not a zero data byte. the reception of a break condition will always set the achange of breako (see below) status bit in the interrupt status register (isr). a framing error occurs when a non-zero character was seen and that character has a zero in the stop bit position. the parity error indicates that the receiver-generated parity was not the same as that sent by the transmitter. the overrun error occurs when the rxfifo is full, the receiver shift register is full and another start bit is detected. at this moment the receiver has 257 valid characters and the start bit of the 258th has been seen. at this point the host has approximately 7/16 bit time to read a byte from the rxfifo or the overrun condition will be set and the 258th character will overrun the 257th and the 258th the 259th and so on until an open position in the rxfifo is seen. the fundamental meaning of the overrun is that data has been lost. data in the rxfifo remains valid. the receiver will begin placing characters in the rxfifo as soon as a position becomes vacant. note: precaution must be taken when reading an overrun fifo. there will be 256th valid characters. data will begin loading as soon as the first character is read. the 257th character will have been received as valid but it will not be known how many characters were lost between the two characters of the 256th and 257th reads of the rxfifo the achange of breako means that either a break has been detected or that the break condition has been cleared. this bit is available in the isr. the break change bit being set in the isr and the received break bit being set in the sr will signal the beginning of a break. at the termination of the break condition only the change of break in the isr will be set. after the break condition is detected the termination of the break will only be recognized when the rxd input has returned to the high state for two successive edges of the 1x clock; 1/2 to 1 bit time. the receiver is disabled by reset or via cr commands. a disabled receiver will not interrupt the host cpu under any circumstance in the normal mode of operation. if the receiver is in the multi-drop or special mode, it will be partially enabled and thus may cause an interrupt. refer to section on wake-up and the register description for mr1 for more information. receiver fifo the receiver buffer memory is a 256 byte fifo with three status bits appended to each data byte. (the fifo is then 256 11-bit awordso). the receiver state machine gathers the bits from the receiver shift register and the status bits from the receiver logic and writes the assembled byte and status bits to the rxfifo. logic associated with the fifo encodes the number of filled positions for presentation to the interrupt arbitration system. the encoding is always 1 less than the number of filled positions. thus, a full rxfifo will bid with the value or 255; when empty it will not bit at all; one position occupied bids with the value 0. an empty fifo will not bid since no character is available. normally rxfifo will present a bid to the arbitration system whenever it has one or more filled positions. the mr2 [3:2 bits allow the user to modify this characteristic so that bidding will not start until one of four levels (one or more filled, 1/2 filled, 3/4 filled, full) have been reached. as will be shown later this feature may be used to make slight improvements in the interrupt service efficiency. a similar system exists in the transmitter. rxfifo status bits. status reporting modes the description below applies to the upper three bits in the astatus registero these three bits are not ain the status registero; they are part of the rxfifo. the three status bits at the top of the rxfifo are presented as the upper three bits of the status register included in each uart. the error status of a character, as reported by a read of the sr (status register upper three bits) can be provided in two ways, as programmed by the error mode control bit in the mode register: acharacter mode o or the ablock modeo. the block mode may be further modified (via a cr command) to set the status bits as the characters enter the fifo or as they are read from the fifo. in the 'character' mode, status is provided on a character by character basis as the characters are read from the rxfifo: the astatuso applies only to the character at the top of the rxfifo the next character to be read. in the 'block' mode, the status provided in the sr for these three bits is the logical or of the status for all characters coming to the top of the rxfifo, since the last reset error command was issued. in this mode each of the status bits stored in the rxfifo are passed through a latch as they are sequentially written to the receiver fifo. if any of the characters has an error bit set that latch will set and remain set until it is reset with a areceiver reseto is issued from the command register or a chip reset is issued. the purpose of this mode is indicating an error in the data block as opposed to an error in a character.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 16 the latch used in the block mode to indicate aproblem datao is usually set as the characters are read out of the rxfifo. via a command in the cr the latch may be configured to set the latch as the characters are pushed (loaded to) the rxfifo. this gives the advantage of indicating aproblem datao up to 256 (or the fifo size) characters earlier. in either mode, reading the sr does not affect the rxfifo. the rxfifo is 'popped' only when the rxfifo is read. therefore, the sr should be read prior to reading the corresponding data character. if the rxfifo is full when a new character is received, the character is held in the receiver shift register until a position is available in the rxfifo. at this time there are 257 valid characters in the rxfifo. if an additional character is received while this state exists, the contents of the rxfifo are not affected: the character previously in the shift register is lost and the overrun error status bit, sr [4], will be set upon receipt of the start bit of the new (overrunning) character. wake up mode the sc28l202 provides two modes of this common asynchronous aparty lineo protocol: the new automatic mode with 3 sub modes and the default host operated mode. the automatic mode has several sub modes (see below). in the full automatic the internal state machine devoted to this function will handle all operations associated with address recognition, data handling, receiver enables and disables. in both modes the meaning of the parity bit is changed. it is often referred to as the a/d bit or the address/data bit. it is used to indicate whether the byte presently in the receiver shift register is an aaddresso byte or a adatao byte. a1o usually means address; a0o data. its purpose is to allow several receivers connected to the same data source to be individually addressed. of course addressing could be by group also. normally the amastero would send an address byte to all receivers alisteningo. the receiver will then recognize its address and then enable itself to receive the following data stream. upon receipt of an address not its own it would then disable itself. as descried below appropriate status bits are available to describe the operation. enabling the wake up mode this mode is selected by programming bits mr1 [4:3] to '11'. the sub modes are controlled by bits 6, 1, 0 in the mr0 register. bit 6 controls the loading of the address byte to the rxfifo and mr0 [1:0] determines the sub mode as shown in the following list. ? mr0 [1:0] = 00 normal wake up mode (default). host controls operation via interrupts and commands written to the command register (cr). ? mr0 [1:0] = 01 auto wake. enable receiver on address recognition for this station. upon recognition of its assigned address the local receiver will be enabled and normal receiver communications with the host will be established. ? mr0 [1:0] = 10 auto doze. disable receiver on address recognition, not for this station. upon recognition of an address character that is not its own, in the auto doze mode, the receiver will be disabled and the address just received either discarded or pushed to the rxfifo depending on the programming of mr0 [6]. ? mr0 [1:0] = 11 auto wake and doze. both modes described above. the programming of mr0 [1:0] to 11 will enable both the auto wake and auto doze features. the enabling of the wake-up mode executes a partial enabling of the receiver state machine. even though the receiver has been reset the wake up mode will over ride the disable and reset condition. normal wake up (the default configuration) in the default (mode a00o above and the least efficient) configuration for this mode of operation, a 'master' station transmits an address character followed by data characters for the addressed 'slave' station. the slave stations, whose receivers are normally disabled (not reset), examine the received data stream. upon recognition of its address bit interrupts the cpu (by setting rxrdy). the cpu (host) compares the received address to its station address and enables the receiver if it wishes to receive the subsequent data characters. upon receipt of another address character, the cpu may disable the receiver to initiate the process again. a transmitted character consists of a start bit, the programmed number of data bits, an address/data (a/d) bit, and the programmed number of stop bits. the cpu selects the polarity of the transmitted a/d bit by programming bit mr1 [2]. mr1 [2] = 0 transmits a zero in the a/d bit position which identifies the corresponding data bits as data . mr1 [2] = 1 transmits a one in the a/d bit position which identifies the corresponding data bits as an address . the cpu should program the mode register prior to loading the corresponding data bytes into the txfifo. while in this mode, the receiver continuously looks at the received data stream, whether it is enabled or disabled. if disabled, it sets the rxrdy status bit and loads the character into the rxfifo if the received a/d bit is a one, but discards the received character if the received a/d bit is a zero. if the receiver is enabled, all received characters are transferred to the cpu via the rxfifo. in either case, the data bits are loaded into the data fifo while the a/d bit is loaded into the status fifo position normally used for parity error (sr [5]). framing error, overrun error, and break detect operate normally whether or not the receiver is enabled. receiver reset and disable receiver disable stops the receiver immediately data being assembled in the receiver shift register is lost. data and status in the fifo is preserved and may be read. a re-enable of the receiver after a disable will cause the receiver to begin assembling characters at the next start bit detected. a receiver reset will discard the present shift register date, reset the receiver ready bit (rxrdy), clear the status of the byte at the top of the fifo and re-align the fifo read/write pointers. this effectively aclearso the receiver fifo although the fifo data is not altered. a `watchdog timer' is associated with each receiver. its interrupt is enabled by mr0 [7]. the purpose of this timer is to alert the control processor that characters are in the rxfifo which have not been read and/or the data stream has stopped. this situation may occur at the end of a transmission when the last few characters received are not sufficient to cause an interrupt. this counter times out after 64 bit times. it is reset each time a character is transferred from the receiver shift register to the rxfifo or a read of the rxfifo is executed. receiver time-out mode in addition to the watch dog timer described in the receiver section, the counter/timer may be used for a similar function. its programmability, of course, allows much greater precision of timeout intervals.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 17 the time-out mode uses the received data stream to control the counter. each time a received character is transferred from the shift register to the rxfifo, the counter is restarted. if a new character is not received before the counter reaches zero count, the counter ready bit is set, and an interrupt can be generated. this mode can be used to indicate when data has been left in the rxfifo for more than the programmed time limit. otherwise, if the receiver has been programmed to interrupt the cpu when the receive fifo is full, and the message ends before the fifo is full, the cpu may not know there is data left in the fifo. the ctu and ctl value would be programmed for just over one character time, so that the cpu would be interrupted as soon as it has stopped receiving continuous data. this mode can also be used to indicate when the serial line has been marking for longer than the programmed time limit. in this case, the cpu has read all of the characters from the fifo, but the last character received has started the count. if there is no new data during the programmed time interval, the counter ready bit will get set, and an interrupt can be generated. writing the appropriate command to the command register enables the time-out mode. writing an `ax' to cra or crb will invoke the time-out mode for that channel. writing a `cx' to cra or crb will disable the time-out mode. the time-out mode should only be used by one channel at once, since it uses the c/t. if, however, the time-out mode is enabled from both receivers, the time-out will occur only when both receivers have stopped receiving data for the time-out period. ctu and ctl must be loaded with a value greater than the normal receive character period. the time-out mode disables the regular start/stop counter commands and puts the ca/t into counter mode under the control of the received data stream. each time a received character is transferred from the shift register to the rxfifo, the c/t is stopped after 1 c/t clock, reloaded with the value in ctu and ctl and then restarted on the next c/t clock. if the c/t is allowed to end the count before a new character has been received, the counter ready bit, isr [3], will be set. if imr [3] is set, this will generate an interrupt. receiving a character after the c/t has timed out will clear the counter ready bit, isr [3], and the interrupt. invoking the `set time-out mode on' command, crx = `ax', will also clear the counter ready bit and stop the counter until the next character is received. time out mode caution when operating in the special time out mode, it is possible to generate what appears to be a afalse interrupto, i.e. an interrupt without a cause. this may result when a time-out interrupt occurs and then, before the interrupt is serviced, another character is received, i.e. the data stream has started again. (the interrupt latency is longer than the pause in the data stream.) in this case, when a new character has been receiver, the receiver, thereby withdrawing its interrupt will restart the counter/timer. if, at this time, the interrupt service begins for the previously seen interrupt, a read of the isr will show the acounter readyo bit not set. if nothing else is interrupting, this read of the isr will return a x'00 character. crc modes and control the crc (cyclic redundancy check) control. the crc generator may be programmed to one of four modes as listed below. ? crc16: divisor x 16 + x 15 + x 2 + 1, dividend preset to zeros. the tx sends the calculated crc non-inverted. the rx indicates an error if the computed crc is not equal to 0. ? crc16: divisor = x 16 + x 15 + x 2 + 1, dividend preset to ones. the tx sends the calculated crc non-inverted. the rx indicates an error if the computed crc is not equal to 0. ? crcccitt: divisor = x 16 + x 12 + x 5 + 1, dividend preset to zeros the tx sends the calculated crc non-inverted. the rx indicates an error if the computed crc is not equal to 0. ? crcccitt: divisor = x 16 + x 12 + x 5 + 1, dividend preset to ones the tx sends the calculated crc inverted. the rx indicates an error if the computed crc is not equal to 0xf0b8'. data sent to the crc generator will exclude the stop, parity and stop bits. the crc remainder may be read from the crc registers if desired. interrupt arbitration interrupt control the interrupt system determines when an interrupt should be asserted thorough an arbitration (or bidding) system. this arbitration is exercised over the several systems within the duart that may generate an interrupt. these will be referred to as ainterrupt sourceso. there are 18 in all. in general the arbitration is based on the fill level of the receiver fifo or the empty level of the transmitter fifo. the fifo levels are encoded into an 8-bit number, which is concatenated to the channel number and source identification code. all of this is compared (via the bidding or arbitration process) to a user defined athresholdo. whenever a source exceeds the numerical value of the threshold the interrupt will be generated. at the time of interrupt acknowledge (iackn) the source which has the highest bid (not necessarily the source that caused the interrupt to be generated) will be captured in a acurrent interrupt registero (cir). this register will contain the complete definition of the interrupting source: channel, type of interrupt (receiver, transmitter, change of state, etc.), and fifo fill level. the value of the bits in the cir are used to drive the interrupt vector and global registers such that controlling processor may be steered directly to the proper service routine. a single read operation to the cir provides all the information needed to qualify and quantify the most common interrupt sources. the interrupt sources for each channel are listed below. ? transmit fifo empty level for each channel ? receive fifo fill level for each channel ? change in break received status for each channel ? receiver with error for each channel ? change of state on channel input pins ? receiver watch-dog time out event ? xon/xoff character recognition ? address character recognition ? counter/timer associated with the interrupt system are the interrupt mask register (imr) and the interrupt status register (isr) resident in each uart. programming of the imr selects which of the above sources may enter the arbitration process. only the bidders in the isr whose associated bit in the imr is set to one (1) will be permitted to enter the arbitration process. the isr can be read by the host cpu to determine all currently active interrupting conditions. for
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 18 convenience the bits of the isr may be masked by the bits of the imr. the setting of bit 6 in mr1 controls whether the isr is read unmasked or masked. enabling and activating interrupt sources an interrupt source becomes enabled when writing a one to the proper interrupt mask register bit (imr) activates its interrupt capability. an interrupt source can never generate an irqn or have its abido or interrupt number appear in the cir unless the source has been enabled by the appropriate bit in an imr. an interrupt source is active if it is presenting its bid to the interrupt arbiter for evaluation. most sources have simple activation requirements. the watch-dog timer, break received, xon/xoff or address recognition and change of state interrupts become active when the associated events occur and the arbitration value generated thereby exceeds the threshold value programmed in the icr (interrupt control register). the transmitter and receiver functions have additional controls to modify the condition upon which the initiation of interrupt abiddingo begins: the txint and rxint fields of the mr0 and mr2 registers. these fields can be used to start bidding or arbitration when the rxfifo is not empty, 50% full, 75% full or 100% full. for the transmitter it is not full, 50% empty, 75% empty and empty. example: to increase the probability of transferring the contents of a nearly full rxfifo, do not allow it to start bidding until 50% or 75% full. this will prevent its relatively high priority from winning the arbitration process at low fill levels. a high threshold level could accomplish the same thing, but may also mask out low priority interrupt sources that must be serviced. note that for fast channels and/or long interrupt latency times using this feature should be used with caution since it reduces the time the host cpu has to respond to the interrupt request before receiver overrun occurs. setting interrupt priorities the bid or interrupt number presented to the interrupt arbiter is composed of character counts, channel codes, fixed and programmable bit fields. the interrupt values are generated for various interrupt sources as shown in the table below: the value represented by the bits 11 to 4 in the table below are compared against the value represented by the athreshold. the athresholdo, bits 6 to 0 of the icr (interrupt control register), is aligned such that bit 6 of the threshold is compared to bit 9 of the interrupt value generated by any of the sources. whenever the value of the interrupt source is greater than the threshold the interrupt will be generated. the channel number arbitrates only against other channels. the threshold is not used for the channel arbitration. this results in channel b having the highest arbitration number. the decreasing order is b to a. if all other parts of an arbitration cycle are equal then the channel number will determine which channel will dominate in the arbitration process. type b11b7 b6 b5 b4 b3 bits 2:0 receiver w/o error rxfifo byte count 1 0 0 1 channel no receiver w/ error rxfifo byte count 1 1 0 1 channel no transmitter 0 txfifo byte count 1 0 0 channel no change of break programmed field 0 0 1 0 channel no change of state programmed field 0 1 1 0 channel no xon/xoff programmed field 0 1 1 1 channel no address recognition programmed field 0 0 1 1 channel no receiver watch-dog rxfifo byte count 1 as rxfifo above channel no threshold bits 6:0 of interrupt control register 000
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 19 note several characteristics of the above table in bits 6:3. these bits contain the identification of the bidding source as indicated below: 0000 no interrupt source active 0x001 receiver without error x101 receiver with error (errors are: parity, framing and overrun. break is not considered an error) xx00 transmitter 0010 change of break 0110 change of state on i/o ports 0111 xon/xoff event 00111 address recognition 0011 counter/timer the codes form bits 4:0 drive part of the interrupt vector modification and the global interrupt type register. the codes are unique to each source type and identify them completely. the channel numbering progresses from aao to abo as the binary numbers 0 to 1 and identify the interrupting channel uniquely. as the channels arbitrate abo will have the highest bidding value and aao the lowest note that the transmitter byte count is offset from that of the receiver by one bit. this is to give the receiver more authority in the arbitration since and over-run receiver corrupts the message but an under-run transmitter is not harmful. this puts some constraints on how the threshold value is selected. if a threshold is chosen that has its msb set to one then a transmitter can never generate an interrupt! of course the counter point to this is the desire to set the interrupt threshold high so interrupts occur only when a maximum or near maximum number of characters may be transferred. to give some control over this dilemma control bits have been provided in the mr0 and mr2 registers of each channel to individually control when a receiver or transmitter may interrupt. the use of these bits will prevent a receiver or a transmitter from entering the arbitration process even though its fifo fill level is above that indicated by the threshold value set. the bits in the mr0 and mr2 register are named txint (mr0 [5:4]) and rxint (mr2 [3:2]) interrupt arbitration and irqn generation interrupt arbitration is the process used to determine that an interrupt request should be presented to the host. the arbitration is carried out between the ainterrupt thresholdo and the asourceso whose interrupt bidding is enabled by the imr. the interrupt threshold is part of the icr (interrupt control register) and is a value programmed by the user. the asourceso present a value to the interrupt arbiter. that value is derived from four fields: the channel number, type of interrupt source, fifo fill level, and a programmable value. only when one or more of these values exceeds the threshold value in the interrupt control register will the interrupt request (irqn) be asserted. following assertion of the irqn the host will either assert iackn (interrupt acknowledge) or will use the command to aupdate the ciro. at the time either action is taken the cir will capture the value of the source that is prevailing in the arbitration process. (call this value the winning bid). the x1clk drives the arbitration process. it scans the 12 bits of the arbitration bus at the x1clk rate developing a value for the cir every 26 x1 cycles. new arbitration values presented to the arbitration block during an arbitration cycle will be evaluated in the next arbitration cycle. for sources other than receiver and transmitters the user may set the high order bits of an interrupt source's bid value, thus tailoring the relative priority of the interrupt sources. the fill level of their respective fifos controls the priority of the receivers and transmitters. the more filled spaces in the rxfifo the higher the bid value; the more empty spaces in the txfifo the higher its priority. channels whose programmable high order bits are set will be given interrupt priority higher than those with zeros in their high order bits, thus allowing increased flexibility. the transmitter and receiver bid values contain the character counts of the associated fifos as high order bits in the bid value. thus, as a receiver's rxfifo fills, it bids with a progressively higher priority for interrupt service. similarly, as empty space in a transmitter's txfifo increases, its interrupt arbitration priority increases. iackn cycle, update cir when the host cpu responds to the interrupt, it will usually assert the iackn signal low. this will cause the duart to generate an iackn cycle in which the condition of the interrupting device is determined. when iackn asserts, the last valid interrupt number is captured in the cir. the value captured presents most of the important details of the highest priority interrupt at the moment the iackn (or the aupdate ciro command) was asserted. the dual uart will respond to the iackn cycle with an interrupt vector. the interrupt vector may be a fixed value, the content of the interrupt vector register, or when ainterrupt vector modificationo is enabled via icr, it may contain codes for the interrupt type and/or interrupting channel. this allows the interrupt vector to steer the interrupt service directly to the proper service routine. the interrupt value captured in the cir remains until another iackn cycle occurs or until an aupdate ciro command is given to the duart. the interrupting channel and interrupt type fields of the cir set the current ainterrupt contexto of the duart. the channel component of the interrupt context allows the use of global interrupt information registers that appear at fixed positions in the register address map. for example, a read of the global rxfifo will read the channel b rxfifo if the cir interrupt context is channel b receiver. at another time read of the grxfifo may read the channel d rxfifo (cir holds a channel d receiver interrupt) and so on. global registers exist to facilitate qualifying the interrupt parameters and for writing to and reading from fifos without explicitly addressing them. the cir will load with x'00 if iackn or update cir is asserted when the arbitration circuit is not asserting an interrupt. in this condition there is no arbitration value that exceeds the threshold value. when interrupt vector modification is active in this situation the interrupt vector bits associated with the cir will all be zero. global registers the aglobal registerso, 19 in all, are driven by the interrupt system. these are not real hardware devices. they are defined by the content of the cir (current interrupt register) as a result of an interrupt arbitration. in other words they are indirect registers pointed to by the content of the cir. the list of global register follows: ? gibcr the byte count of the interrupting fifo ? gicr channel number of the interrupting channel ? gitr type identification of interrupting channel
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 20 ? grxfifo pointer to the interrupting receiver fifo ? gtxfifo pointer to the interrupting transmitter fifo a read of the grxfifo will give the content of the rxfifo that presently has the highest bid value. the purpose of this system is to enhance the efficiency of the interrupt system. the global registers and the cir update procedure are further described in the interrupt arbitration system polling many users prefer polled to interrupt driven service where there are not a large number of fast data channels and/or the host cpu's other interrupt overhead is low. the dual uart is functional in this environment. the most efficient method of polling is the use of the aupdate ciro command (with the interrupt threshold set to zero) followed by a read of the cir. this dummy write cycle will perform the same cir capture function that an iackn falling edge would accomplish in an interrupt driven system. a subsequent read of the cir, at the same address, will give information about an interrupt, if any. if the cir contains 0s, no interrupt is awaiting service. if the value is non-zero, the fields of the cir may be decoded for type; channel and character count information. optionally, the global interrupt registers may be read for particular information about the interrupt status or use of the global rxd and txd registers for data transfer as appropriate. the interrupt context will remain in the cir until another update cir command or an iackn cycle is initiated by the host cpu occurs. the cir loads with x'00 if update cir is asserted when the arbitration circuit has not detected an arbitration value that exceeds the threshold value of the icr. the global registers and cir may be used as avectorso to the service type required. traditional methods of polling status registers may also be used. they of course are less efficient but give the most variable and quickest method of changing the order in which interrupt sources are evaluated and interrogated. character recognition character recognition character recognition is specific to each of the two uarts. three programmable characters are provided for the character recognition for each channel. the three are general purpose in nature and may be set to only cause an interrupt or to initiate some rather complex operations specific to amulti-dropo address recognition or in-band xon/xoff flow control. character recognition is accomplished via cam memory. the content addressable memory continually examines the incoming data stream. upon the recognition of a control character appropriate bits are set in the xon/xoff interrupt status register (xisr) and interrupt status register (isr). the setting of these bit(s) will initiate any of the automatic sequences or and/or an interrupt that may have enabled via the mr0 register. the characters of the recognition system are fully programmable. the xon/xoff characters may be set to the standard characters if the hardware preconditioning is set by the pre pin. they do not have a pre-defined areset valueo they may, however, be loaded by a agang writeo or agang loado command as described in the axon xoff characterso paragraph. the character recognition circuits are basically designed to provide general-purpose character recognition. additional control logic has been added to allow for xon/xoff flow control and for recognition of the address character in the multi-drop or awake-upo mode. this logic also allows for the generation of interrupts in either the general-purpose recognition mode or the specific conditions mentioned above. xon xoff characters the programming of these characters is usually done individually. however a method has been provided to write to all of registers in one operation by way of the agang loado and agang writeo commands provided in the channel a command register. when these commands are executed all registers are programmed with the same characters. the awriteo command loads a used defined character; the aloado command loads the standard xon/xoff characters. xon is 0x11, xoff 0x13. any enabling of the xon/xoff functions will use the contents of the xon and xoff character registers as the basis on which recognition is predicated. multi-drop or wake up or 9 bit mode this mode is used to address a particular uart among a group connected to the same serial data source. normally it is accomplished by redefining the meaning of the parity bit such that it indicates a character as address or data. while this method is fully supported in the sc28l202 it also supports recognition of the character itself. upon recognition of its address the receiver will be enabled and data pushed onto the rxfifo. further the address recognition has the ability, if so programmed, to disable (not reset) the receiver when an address is seen that is not recognized as its own. the particular features of aauto wake and auto dozeo are described in the detail descriptions below. note: care should be taken in the programming of the character recognition registers. programming x'00, for example, may result in a break condition being recognized as a control character. this will be further complicated when binary data is being processed. character stripping the mr0 register provides for stripping the characters used for character recognition. recall that the character recognition may be conditioned to control several aspects of the communication. however this system is first a character recognition system. the status of the various states of this system is reported in the xisr and isr registers. the character stripping of this system allows for the removal of the specified control characters from the data stream: two for the xon /xoff and one for the wake up. via control in the mr0 register these characters may be discarded (stripped) from the data stream when the recognition system aseeso them or they may be sent on the rxfifo. whether they are stripped or not the recognition system will process them according to the action requested; flow control, wake up, interrupt generation, etc. care should be exercised in programming the stripping option if noisy environments are encountered. if a normal character were corrupted to an xoff character the transmitter would be stopped. if that character were now stripped from the fifo stack, then that stripping action would make it difficult to determine the cause of transmitter stopping. receiver mode since the receiving fifo resources in the dual uart are limited, some means of controlling a remote transmitter is desirable in order to lessen the probability of receiver overrun. the dual uart provides two methods of controlling the data flow. there is a hardware-assisted means of accomplishing control, the so-called out-of-band flow control, and an in-band flow control method.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 21 the out-of-band flow control is implemented through the ctsnrtsn signaling via the i/o ports. the operation of these hardware handshake signals is described in the receiver and transmitter discussions. in-band flow control is a protocol for controlling a remote transmitter by embedding special characters within the message stream, itself. two characters, xon and xoff, which do not represent normal printable character take on flow control definitions when the xon/xoff capability is enabled. flow control characters received may be used to gate the channel transmitter on and off. this activity is referred to as auto-transmitter mode. to protect the channel receiver from overrun, fixed fill levels (hardware set at 12 characters) of the rxfifo may be employed to automatically insert xon/xoff characters in the transmitter's data stream. this mode of operation is referred to as auto-receiver mode. commands issued by the host cpu via the cr can simulate all these conditions. auto-transmitter mode when a channel receiver pushes an xoff character into the rxfifo, the channel transmitter will finish transmission of the current character and then stop transmitting. a transmitter so idled can be restarted by the receipt of an xon character by the receiver or by a hardware or software reset. the last option results in the loss of the un-transmitted contents of the txfifo. when operating in this mode the command register commands for the transmitter are not effective. while idle data may be written to the txfifo and it continue to present its fill level to the interrupt arbiter and maintains the integrity of its status registers. use of '00' as an xon/xoff character is complicated by the receiver break operation which pushes a '00' character on the rxfifo. the xon/xoff character detectors do not discriminate this case from an xon/xoff character received through the rxd pin. note : to be recognized as an xon or xoff character, the receiver must have room in the rxfifo to accommodate the character. an xon/xoff character that is received resulting in a receiver overrun does not effect the transmitter nor is it pushed into the rxfifo, regardless of the state of the xon/xoff transparency bit, mr0 (7). xon /xoff characters the xon/xoff character with errors will be accepted as valid. the user has the option sending or not sending these characters to the fifo. error bits associated with xon/xoff will be stored normally to the receiver fifo. the channel's transmitter may be programmed to automatically transmit an xoff character without host cpu intervention when the rxfifo fill level exceeds a fixed limit (12). in this mode it will transmit an xon character when the rxfifo level drops below a second fixed limit (8). a character from the txfifo that has been loaded into the txd shift register will continue to transmit. character(s) in the txfifo that have not been loaded to the transmitter shift register are unaffected by the xon or xoff transmission. they will be transmitted after the xon/xoff activity concludes. if the fill level condition that initiates xon activity negates before the flow control character can begin transmission, the transmission of the flow control character will not occur, i.e. either of the following sequences may be transmitted depending on the timing of the fifo level changes with respect to the normal character times: character xoff xon character character character hardware keeps track of xoff characters sent that are not rescinded by an xon. this logic is reset by writing mr0 (3) to '0'. if the user drops out of auto-receiver mode while the xisr shows xoff as the last character sent the xon/xoff logic would not automatically send the negating xon. host mode when neither the auto-receiver or auto-transmitter modes are set, the xon/xoff logic is operating in the host mode. in host mode, all activity of the xon/xoff logic is initiated by commands to the crx. the xoff command forces the transmitter to disable exactly as though an xoff character had been received by the rxfifo. the transmitter will remain disabled until the chip is reset or the cr (7:3) = 10110 (xoff resume) command is given. in particular, reception of an xon or disabling or re-enabling the transmitter will not cause resumption of transmission. redundant crtxecommands, i.e. crtxon crtxon, are harmless, although they waste time. a crtxon may be used to cancel a crtxoff (and vice versa) but both may be transmitted depending on the command timing with respect to that of the transmitter state machine. the kill crtx command can be used to cleanly terminate any crtx commands pending with the minimum impact on the transmitter. note : in no case will an xon/xoff character transmission be aborted. once the character is loaded into the tx shift register, transmission continues until completion or a chip reset is encountered. the kill crtx command has no effect in either of the auto modes. mode control xon/xoff mode control is accomplished via the mr0. bits 3 and 2 reset to zero resulting in all xon/xoff processing being disabled. if mr0 [2] is set, xon/xoff characters received may gate the transmitter. if mr0 [3] is set, the transmitter will transmit xon and xoff when triggered by attainment of fixed fill levels in the channel rxfifo. the mr0 [7] bit also has an xon/xoff function control. if this bit is set, a received xon or xoff character is not pushed into the rxfifo. if cleared, the power-on and reset default, the received xon or xoff character is pushed onto the rxfifo for examination by the host cpu. the mr0 (7) function operates regardless of the value in mr0 (3:2). xon/xoff interrupts the xon/xoff logic generates interrupts only in response to recognizing either of the characters in the xoncr or xoffcr (xon or xoff character registers). the transmitter activity initiated by the xon/xoff logic or any cr command does not generate an interrupt. the character comparators operate regardless of the value in mr0 (3:2). hence the comparators may be used as general-purpose character detectors by setting mr0 (3:2)='00' and enabling the xon/xoff interrupt in the imr. the dual uart can present the xon/xoff recognition event to the interrupt arbiter for irqn generation. the irqn generation may be masked by setting bit 4 of the interrupt mask register, imr. the bid level of an xon/xoff recognition event is controlled by the bidding control register x, bcrx, of the channel. the interrupt status can be examined in isr [4]. if cleared, no xon/xoff recognition event is
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 22 interrupting. if set, an xon or xoff recognition event has been detected. the x interrupt status register, xisr, can be read for details of the interrupt and to examine other, non-interrupting, status of the xon/xoff logic. refer to the xisr in the register descriptions. the character recognition function and the associated interrupt generation is disabled on hardware or software reset. fifo partitioning and control fifo control for variable partitions of ram. the fifo for this duart is based on static ram memory. a base block of 1024 11-bit bytes of memory is used. on reset this memory is partitioned into 256 bytes for each receiver and transmitter with an interrupt level set at 128 bytes or half full. however the size of each partition is under program control and may be varied from 0 to 1021 bytes fifo interrupt is also variable and may be set at any level within the partition. xon and xoff levels are set to 8 bytes below the full level of the partition size used. memory control uses 10 bit registers to control the afifoo partition size and interrupt level for each receiver and transmitter. these control registers use a basic 8 bit register and another 8-bit register that contains two bits for each partition that is set to a size above 255 bytes. fifo control registers. each fifo has three principal registers: size, interrupt level and two bits in the fifo page register. the fifo size and the fifo's two bits in the page register comprise a total of ten (10) bits that will be used by the fifo control engine to set up the address. the reset value of these registers will configure the fifos to a size of 256 (0xff) bytes and an interrupt level of 128 (0x80). the bits of the page register are set a 0 (0x00). the meaning of the fifo interrupt level is defined to mean the remaining bytes that are available in the fifo before it is filled. for example it the interrupt level is set a 50 and the fifo size is set at 220 then the interrupt will occur then the receiver fills to 170 bytes. for the transmitter the interrupt would extinguish when the transmitter fifo was load with 170 bytes. recall that a full transmitter fifo will not generate an interrupt and that an empty receiver fifo will not generate an interrupt the transmitter buffer memory is a one byte register driven by the transmitter fifo. the fifo control writes characters to this buffer. this buffer accepts data only when the transmitter is enabled. the transmitter state machine reads them out in the order they were received and presents them to the transmitter shift register for serialization. the transmitter adds the required start, parity and stop bits as required by the mr2 register programming. the start bit (always one bit time in length) is sent first followed by the least significant bit (lsb) to the most significant bit (msb) of the character, the parity bit (if used) and the required stop bit(s). logic associated with the fifo encodes the number of empty positions available in an eight-bit value. this value is concatenated with the channel number and type interrupt type identifier and presented to the interrupt arbitration system. the encoding of the apositions emptyo value is always 1 less than the number of available positions. thus, an empty txfifo will bid with the value of the partition size; when full it will not bid at all. one position empty bids with the value 0. a full fifo will not bid since a character written to it will be lost normally a txfifo will present a bid to the arbitration system whenever it has one or more empty positions. the mr0 [5:4] allow the user to modify this characteristic so that bidding will not start until one of four levels (empty, 3/4 empty, 1/2 empty, not full) have been reached. as will be shown later this feature may be used to make slight improvements in the interrupt service efficiency. a similar system exists in the receiver. programming writing control words into the appropriate registers programs the operation of the duart. operational feedback is provided via status registers that can be read by the cpu. the addressing of the registers is described in table no tag. the contents of certain control registers are initialized to zero on reset. care should be exercised if the contents of a register are changed during operation, since certain changes may cause operational problems. for example, changing the number of bits per character while the transmitter is active may cause the transmission of an incorrect character. in general, the contents of the mr, the csr, and the opcr should only be changed while the receiver(s) and transmitter(s) are not enabled, and certain changes to the acr should only be made while the c/t is stopped. each channel has 3 mode registers (mr0, 1, 2) which control the basic configuration of the channel. independent mr address pointers control access to these registers. these pointers are set to 0 or 1 by mr control commands in the command register amiscellaneous commandso. each time the mr registers are accessed the mr pointer increments, stopping at mr2. it remains pointing to mr2 until set to 0 or 1 via the miscellaneous commands of the command register. the pointer is set to 1 on reset for compatibility with previous philips semiconductors uart software. mode, command, clock select, and status registers are duplicated for each channel to provide total independent operation and control. refer to table 1 for register bit descriptions. the reserved registers at addresses h`02' and 0x0a' should never be read during normal operation since they are reserved for internal diagnostics. register maps the registers of the sc28l202 are loosely partitioned into two groups: those used in controlling data channels and those used in handling the actual data flow and status. tables 1 and 2 show the general configuration of all the register addresses. note : some registers contain control bits that configure the entire chip. these are denoted by a a o symbol
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 23 table 1. summary register map, control address (hex) c = channel register name acronym read/write 0c 0000 (0x00) mode register 0 mr0a mr0 r/w 0c 0001 (0x01) mode register 1 mr1a mr1 r/w 0c 0010 (0x02) 0c 0011 (0x03) bid control, break change bcrbrk r/w 0c 0100 (0x04) bid control, change of state bcrcos r/w 0c 0101 (0x05) reset output port register ropr w 0c 0110 (0x06) bid control, xon/xoff bcrx r/w 0c 0111 (0x07) bid control, address recognition bcra r/w 0c 1000 (0x08) xon character register xoncr r/w 0c 1001 (0x09) xoff character register xoffcr r/w 0c 1010 (0x0a) address recognition character arcr r/w 0c 1100 (0x0c) receiver clock select register rxcsr r/w 00 1101 (0x0d) test register reserved, set to 0 0c 1110 (0x0e) transmitter clock select register txcsr r/w 10 1110 (0x2c) set output port register sopr w 01 1111 (0x1f) fifo partition page count fppc r/w 01 1011 (0x1b) interrupt control register icr r/w 01 1101 (0x1d) watch-dog timer run control wdtrcr r/w 01 1111 (0x1f) interrupt vector register ivr r/w
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 24 table 2. summary register map, data address (hex) c = channel register name read cycle acronym register name write cycle acronym 1c 0000 (0xc0) mode register 2 mr2 mode register 2 mr2 1c 0001 (0xc1) status register sr command register cr 1c 0010 (0xc2) interrupt status register isr interrupt mask register imr 1c 0011 (0xc3) receiver fifo rxfifo transmitter fifo txfifo 1c 0100 (0xc4) input port register ipr 1c 0101 (0xc5) x character status register xisr 1c 0110 (0xc6) counter/timer lower c/tl counter timer lower preset c/tlp 1c 0111 (0xc7) counter/timer upper c/tu counter timer upper preset c/tup 1c 1000 (0xc8) fifo partition register rx fp_rx 1c 1001 (0xc9) fifo partition register tx fp_tx 1c 1010 (0xca) fifo interrupt level rx fil_rx 1c 1011 (0xcb) fifo interrupt level tx fil_tx 1c 1100 (0xcc) i/o port configuration 30 iopcr30 10 1011 (0x2d) global interrupt channel register gicr i/o port configuration 74 iopcr74 10 1110 (0x2e) global interrupt byte count gibcr 10 1111 (0x2f) global interrupt type register gitr 11 1011 (0x3d) current interrupt register cir update current interrupt register ucir 11 1110 (0x3e) global rx fifo grxfifo grxfifo global txfifo gtxfifo gtxfifo 11 1111 (0x3f)
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 25 the three mr registers are accessed via the mr pointer and commands 0x1n and 0xbn (where n = represents receiver and transmitter enable bits) table 3. register bit formats these are support functions for both channels input port change register ipcr r auxiliary control register acr r/w interrupt status register isr r interrupt mask register imr r/w counter timer upper value ctu r counter timer lower value ctl r counter timer preset upper ctpu r/w counter timer preset lower ctpl r/w input port register ipr r output configuration register opcr r/w set output port bits r/w reset output port bits r/w the following named registers are the same for channels a and b mode register mrna mrnb r/w status register sra srb r only clock select csra csrb r/w command register cra crb r/w receiver fifo rxfifoa rxfifob r only transmitter fifo txfifoa txfifob r/w table 4. bit rate generator characteristics (crystal or clock = 14.7456 mhz) normal rate (baud) actual 16x clock (khz) error (%) 50 0.8 0 75 1.2 0 110 1.759 0.069 134.5 2.153 0.059 150 2.4 0 200 3.2 0 300 4.8 0 600 9.6 0 1050 16.756 0.260 1200 19.2 0 1800 28.8 0 2000 32.056 0.175 2400 38.4 0 4800 76.8 0 7200 115.2 0 9600 153.6 0 19.2k 307.2 0 38.4k 614.4 0 note: duty cycle of 16x clock is 50% 1%.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 26 register descriptions mode registers mr0a mr0 mode register 0 mr0 is accessed by setting the mr pointer to 0 via command b of the command register. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mr0a mr0b mr0b[3:0] are reserved rx watch dog 0 = disable 1 = enable rxint bit 2 see tables in mr0 description txint (1:0) see table 7 don't care set to 0 baud rate extended ii 0 = normal 1 = extend ii test 2 set to 0 baud rate extended 1 0 = normal 1 = extend mr0 [7] ethis bit controls the receiver watchdog timer. 0 = disable, 1 = enable. when enabled, the watch dog timer will generate a receiver interrupt if the receiver fifo has not been accessed within 64 bit times of the receiver 1x clock. this is used to alert the control processor that data is in the rxfifo that has not been read. this situation may occur when the byte count of the last part of a message is not large enough to generate an interrupt. mr0 [6] ebit 2 of receiver fifo interrupt level. this bit along with bit 6 of mr1 sets the fill level of the 8 byte fifo that generates the receiver interrupt. mr0 [6] mr1 [6] note that this control is split between mr0 and mr1. this is for backward compatibility to the scc2692 and scn2681. table 5. receiver fifo interrupt fill level (mr0 (3)=0 mr0[6] mr1[6] interrupt condition 00 1 or more bytes in fifo (rx rdy) 01 3 or more bytes in fifo 10 6 or more bytes in fifo 11 8 bytes in fifo (rx full) table 6. receiver fifo interrupt fill level (mr0 (3) = 1 mr0[6] mr1[6] interrupt condition 00 1 or more bytes in fifo (rx rdy) 01 6 or more bytes in fifo 10 12 or more bytes in fifo 11 16 bytes in fifo (rx full) for the receiver these bits control the number of fifo positions empty when the receiver will attempt to interrupt. after the reset the receiver fifo is empty. the default setting of these bits cause the receiver to attempt to interrupt when it has one or more bytes in it. mr0 [5:4] etx interrupt fill level. table 7. transmitter fifo interrupt fill level mr0 (3) = 0 mr0[5:4] interrupt condition 00 8 bytes empty (tx empty) 01 4 or more bytes empty 10 6 or more bytes empty 11 1 or more bytes empty (tx rdy) table 8. transmitter fifo interrupt fill level mr0 (3) = 1 mr0[5:4] interrupt condition 00 16 bytes empty (tx empty) 10 8 or more bytes empty 10 12 or more bytes empty 01 1 or more bytes empty (tx rdy) for the transmitter these bits control the number of fifo positions empty when the receiver will attempt to interrupt. after reset the transmit fifo has 256 bytes empty. it will then attempt to interrupt as soon as the transmitter is enabled. the default setting of the mr0 bits (00) condition the transmitter to attempt to interrupt only when it is completely empty. as soon as one byte is loaded, it is no longer empty and hence will withdraw its interrupt request. mr0 [3]e selects the fifo depth at 8 or 16 bytes. see tables 5 and 7. mr0 [2:0] ethese bits are used to select one of the six baud rate groups. see table 9 for the group organization. 000 normal mode 001 extended mode i 100 extended mode ii other combinations of mr2 [2:0] should not be used. note : mr0 [3:0] are not used in channel b and should be set to 0.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 27 mr1a mr1 mode register 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mr1a mr1b rx controls rts rxint bit 1 error mode parity mode parity type bits per character 0 = no 1 = yes 0 = rxrdy 1 = ffull 0 = char 1 = block 1 00 = with parity 01 = force parity 10 = no parity 11 = multi-drop mode 0 = even 1 = odd 00 = 5 01 = 6 10 = 7 11 = 8 note: 1. in block error mode, using the error-reset command (command 0x4n) will clear block error conditions or a receiver reset. mr1a is accessed when the channel a mr pointer points to mr1. the pointer is set to mr1 by reset or by a `set pointer' command applied via cr command 1. after reading or writing mr1a, the pointer will point to mr2a. mr1a [7]echannel a receiver request-to-send control (flow control) this bit controls the deactivation of the rtsan output (op0) by the receiver. this output is normally asserted by setting opr [0] and negated by resetting opr [0]. mr1a [7] = 1 causes rtsan to be negated (op0 is driven to a `1' [v cc ]) upon receipt of a valid start bit if the channel a fifo is full. this is the beginning of the reception of the ninth byte. if the fifo is not read before the start of the tenth byte, an overrun condition will occur and the tenth byte will be lost. however, the bit in opr [0] is not reset and rtsan will be asserted again when an empty fifo position is available. this feature can be used for flow control to prevent overrun in the receiver. use of the receiver's rtsn output signal to control the ctsn input of the transmitting stops the transmitter when the receiver fifo is full. mr1 [6] ebit 1 of the receiver interrupt control. see description under mr0 [6]. mr1a [5]echannel a error mode select this bit selects the operating mode of the three fifoed status bits (fe, pe, and received break) for channel a. in the `character' mode, status is provided on a character-by-character basis; the status applies only to the character at the top of the fifo. in the `block' mode, the status provided in the sr for these bits is the accumulation (logical-or) of the status for all characters coming to the top of the fifo since the last `reset error' command for channel a was issued. mr1a [4:3|echannel a parity mode select if `with parity' or `force parity' is selected a parity bit is added to the transmitted character and the receiver performs a parity check on incoming data mr1a [4:3] = 11 selects channel a to operate in the special multi-drop mode described in the operation section. mr1a [2]echannel a parity type select this bit selects the parity type (odd or even) if the `with parity' mode is programmed by mr1a [4:3], and the polarity of the forced parity bit if the `force parity' mode is programmed. it has no effect if the `no parity' mode is programmed. in the special multi-drop mode it selects the polarity of the a/d bit. mr1a [1:0]echannel a bits per character select this field selects the number of data bits per character to be transmitted and received. the character length does not include the start, parity, and stop bits.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 28 mr2aechannel a mode register 2 mr2a is accessed when the channel a mr pointer points to mr2, which occurs after any access to mr1a. accesses to mr2a do not c hange the pointer. mr2 mode register 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mr2a mr2b channel mode tx controls rts cts enable tx stop bit length note : add 0.5 to binary codes 07 for 5 bit character lengths. 00 = normal 01 = auto-echo 10 = local loop 11 = remote loop 0 = no 1 = yes 0 = no 1 = yes 0 = 0.563 4 = 0.813 8 = 1.563 c = 1.813 1 = 0.625 5 = 0.875 9 = 1.625 d = 1.875 2 = 0.688 6 = 0.938 a = 1.688 e = 1.938 3 = 0.750 7 = 1.000 b = 1.750 f = 2.000 note: 1. add 0.5 to values shown for 07 if channel is programmed for 5 bits/char. mr2a [7:6]echannel a mode select each channel of the duart can operate in one of four modes. mr2a [7:6] = 00 is the normal mode, with the transmitter and receiver operating independently. mr2a [7:6] = 01 places the channel in the automatic echo mode, which automatically retransmits the received data. the following conditions are true while in automatic echo mode: 1. received data is reclocked and retransmitted on the txda output. 2. the receiver clock is used for the transmitter. 3. the receiver must be enabled, but the transmitter need not be enabled. 4. the channel a txrdy and txemt status bits are inactive. 5. the received parity is checked, but is not regenerated for transmission; i.e. transmitted parity bit is as received. 6. character framing is checked, but the stop bits are retransmitted as received. 7. a received break is echoed as received until the next valid start bit is detected. 8. cpu to receiver communication continues normally, but the cpu to transmitter link is disabled. two diagnostic modes can also be configured. mr2a [7:6] = 10 selects local loop back mode. in this mode: 1. the transmitter output is internally connected to the receiver input. 2. the transmitter clock is used for the receiver. 3. the txda output is held high. 4. the rxda input is ignored. 5. the transmitter must be enabled, but the receiver need not be enabled. 6. cpu to transmitter and receiver communications continues normally. the second diagnostic mode is the remote loop back mode, selected by mr2a [7:6] = 11. in this mode: 1. received data is reclocked and retransmitted on the txda output. 2. the receiver clock is used for the transmitter. 3. received data is not sent to the local cpu, and the error status conditions are inactive. 4. the received parity is not checked and is not regenerated for transmission, i.e., transmitted parity is as received. 5. the receiver must be enabled. 6. character framing is not checked, and the stop bits are retransmitted as received. 7. a received break is echoed as received until the next valid start bit is detected. the user must exercise care when switching into and out of the various modes. the selected mode will be activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted character. likewise, if a mode is deselected the device will switch out of the mode immediately. an exception to this is switching out of auto echo or remote loop back modes. if the de-selection occurs just after the receiver has sampled the stop bit (indicated in auto echo by assertion of rxrdy), and the transmitter is enabled, the transmitter will remain in auto echo mode until the entire stop has been re-transmitted. mr2a [5] echannel a transmitter request-to-send control this bit controls the deactivation of the rtsan output (op0) by the transmitter. this output is normally asserted by setting opr [0] and negated by resetting opr [0]. mr2a [5] = 1 caused opr [0] to be reset automatically one bit time after the characters in the channel a transmit shift register and in the txfifo, if any, are completely transmitted including the programmed number of stop bits, if the transmitter is not enabled. this feature can be used to automatically terminate the transmission of a message as follows: 1. program auto-reset mode: mr2a [5] = 1. 2. enable transmitter. 3. asset rtsan: opr [0] = 1. 4. send message. 5. disable transmitter after the last character is loaded into the channel a txfifo. 6. the last character will be transmitted and opr [0] will be reset one bit time after the last stop bit, causing rtsan to be negated.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 29 mr2a [4] echannel a clear-to-send control if this bit is 0, ctsan has no effect on the transmitter. if this bit is a 1, the transmitter checks the state of ctsan (ipo) each time it is ready to send a character. if ipo is asserted (low), the character is transmitted. if it is negated (high), the txda output remains in the marking state and the transmission is delayed until ctsan goes low. changes in ctsan while a character is being transmitted do not affect the transmission of that character. mr2a [3:0] echannel a stop bit length select this field programs the length of the stop bit appended to the transmitted character. stop bit lengths of 9/16 to 1 and 1-9/16 to 2 bits, in increments of 1/16 bit, can be programmed for character lengths of 6, 7, and 8 bits. for a character length of 5 bits, 1-1/16 to 2 stop bits can be programmed in increments of 1/16 bit. in all cases, the receiver only checks for a `mark' condition at the center of the stop bit position (one bit time after the last data bit, or after the parity bit if enabled is sampled). if an external 1x clock is used for the transmitter, mr2a [3] = 0 selects one stop bit and mr2a [3] = 1 selects two stop bits to be transmitted.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 30 fp rxa fifo partition (typical for all fifos) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the 8 bits describing the page size or top page when page size differs from 256 bytes are used defines the abottomo page size when page is note 256 bytes. for a 300 byte fifo this would be set to decimal 44 (0x2c) and the corresponding fppc would be set to 2 pages or binary 01. fppc fifo partition page count bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 txa txb rxa rxb 00 = 1 pages 01 = 2 pages 10 = 3 pages 11 = 4 pages 00 = 1 pages 01 = 2 pages 10 = 3 pages 11 = 4 pages 00 = 1 pages 01 = 2 pages 10 = 3 pages 11 = 4 pages 00 = 1 pages 01 = 2 pages 10 = 3 pages 11 = 4 pages this register is set to 0x00 at reset. this register will be non zero when one or more fifos are greater that 256 bytes fil fifo interrupt level (typical for all fifos) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 the 8 bits describing the level of the bottom page where interrupt arbitration occurs. normally set to zero this register is used to control when the fifo fill level will enter the interrupt arbitration. this is used to improve interr upt efficiency when channels have a large difference in baud rates and to bias the transmitter to be less important that the receiver. csraechannel a clock select register csra [7:4] channel a receiver clock select this field selects the baud rate clock for the channel a receiver. the field definition is shown in table 9. csr clock select register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 csra csrb receiver clock select transmitter clock select see text and table 9 see text and table 9
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 31 table 9. baud rate (base on a 14.7456mhz crystal clock) mr0[0] = 0 (normal mode) mr0[0] = 1 (extended mode i) mr0[2] = 1 (extended mode ii) csra[7:4] acr[7] = 0 acr[7] = 1 acr[7] = 0 acr[7] = 1 acr[7] = 0 acr[7] = 1 0000 50 75 300 450 4,800 7,200 0001 110 110 110 110 880 880 0010 134.5 134.5 134.5 134.5 1,076 1,076 0011 200 150 1200 900 19.2k 14.4k 0100 300 300 1800 1800 28.8k 28.8k 0101 600 600 3600 3600 57.6k 57.6k 0110 1,200 1,200 7200 7,200 115.2k 115.2k 0111 1,050 2,000 1,050 2,000 1,050 2,000 1000 2,400 2,400 14.4k 14.4k 57.6k 57.6k 1001 4,800 4,800 28.8k 28.8k 4,800 4,800 1010 7,200 1,800 7,200 1,800 57.6k 14.4k 1011 9,600 9,600 57.6k 57.6k 9,600 9,600 1100 38.4k 19.2k 230.4k 115.2k 38.4k 19.2k 1101 timer timer timer timer timer timer 1110 *** i/o? ip416x ip416x ip416x ip416x ip416x ip416x 1111 ip41x ip41x ip41x ip41x ip41x ip41x note: the receiver clock is always a 16x clock except for csra [7:4] = 1111. csra [3:0]echannel a transmitter clock select this field selects the baud rate clock for the channel a transmitter. the field definition is as shown in table 9, except as follows: csra[3:0] acr[7] = 0 acr[7] = 1 1110 1111 ip316x ip31x ip316x ip31x the transmitter clock is always a 16x clock except for csr [3:0] = 1111. csrbechannel b clock select register csrb [7:4]echannel b receiver clock select this field selects the baud rate clock for the channel b receiver. the field definition is as shown in table 9, except as follows: csrb [7:4] acr[7] = 0 acr[7] = 1 1110 1111 ip616x ip61x ip616x ip61x the receiver clock is always a 16x clock except for csrb [7:4] = 1111. csrb [3:0]echannel b transmitter clock select this field selects the baud rate clock for the channel b transmitter. the field definition is as shown in table 9, except as follows: csrb [3:0] acr[7] = 0 acr[7] = 1 1110 1111 ip516x ip51x ip516x ip51x the transmitter clock is always a 16x clock except for csrb [3:0] = 1111.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 32 table 10. cr - command register cr is used to write commands to the quad uart. bits 7:3 bit 2 bit 1 bit 0 channel command codes see acommand register tableo 1 = hold present condition of tx & rx enables 0 = change tx & rx enable conditions 1 = enable tx 0 = disable tx 1 = enable rx 0 = disable rx cr[2] - lock txd and rxfifo enables if set, the transmitter and receiver enable bits, cr[1:0] are not significant. the enabled/disabled state of a receiver or transmitter can be changed only if this bit is at zero during the time of the write to the command register. writes to the upper bits of the cr would usually have cr[2] at 1 to maintain the condition of the receiver and transmitter. the bit provides a mechanism for writing commands to a channel, via cr[7:3], without the necessity of keeping track of or reading the current enable status of the receiver and transmitter. cr[1] - enable transmitter a one written to this bit enables operation of the transmitter. the txrdy status bit will be asserted. when disabled by writing a zero to this bit, the command terminates transmitter operation and resets the txrdy and txemt status bits. however, if a character is being transmitted or if characters are loaded in the txfifo when the transmitter is disabled, the transmission of the all character(s) is completed before assuming the inactive state. cr[0] - enable receiver a one written to this bit enables operation of the receiver. if not in the special wake-up mode, this also forces the receiver into the search for start bit state. if a zero is written, this command terminates operation of the receiver immediately - a character being received will be lost. the command has no effect on the receiver status bits or any other control registers. if the special wake-up mode is programmed, the receiver operates even if it is disabled (see wake-up mode). cr[7:3] - miscellaneous commands (see table below) the encoded value of this field can be used to specify a single command as follows: 00000 no command. 00001 reserved. 00010 reset receiver. resets the receiver as if a hardware reset had been applied. the receiver is disabled and the fifo pointer is reset to the first location effectively discarding all unread characters in the fifo. 00011 reset transmitter. resets the transmitter as if a hardware reset had been applied. 00100 reset error status. clears the received break, parity error, framing error, and overrun error bits in the status register (sr[7:4]). used in character mode to clear overrun error status (although rb, pe and fe bits will also be cleared), and in block mode to clear all error status after a block of data has been received. 00101 reset break change interrupt. causes the break detect change bit in the interrupt status register (isr[2]) to be cleared to zero. 00110 start break. forces the txd output low (spacing). if the transmitter is empty, the start of the break condition will be delayed up to two bit times. if the transmitter is active, the break begins when transmission of the current character is completed. if there are characters in the txfifo, the start of break is delayed until those characters, or any others loaded after it have been transmitted (txemt must be true before break begins). the transmitter must be enabled to start a break. 00111 stop break. the txd line will go high (marking) within two bit times. txd will remain high for one bit time before the next character, if any, is transmitted. 01000 assert rtsn. causes the rtsn output to be asserted (low). 01001 negate rtsn. causes the rtsn output to be negated (high). note: the two commands above actually reset and set, respectively, the i/o2 or i/o1 pin associated with the i/opior register. 01010 reserved. 01011 reserved. 01100 reserved. 01101 block error status mode. upon reset of the device or an individual receiver, the block mode of receiver error status accumulates as each character moves to the bottom of the rxfifo, the position from which it will be read. in this mode of operation, the rxfifo may contain a character with non-zero error status for some time. the status will not reflect the error character's presence until it is ready to be popped from the rxfifo. command 01101 allows the error status to be updated as each character is pushed into the rxfifo. this allows the earliest detection of a problem character, but complicates the determination of exactly which character is causing the error. this mode of block error accumulation may be exited only by resetting the chip or the individual receiver. 01111 reserved. 10000 transmit an xon character 10001 transmit an xoff character 10010 reserved for channels b-d, for channel a: enables a gang write of xon character registers. after this command is issued, a write to the channel a xon character register will result in a write to all channel's xon character registers. this command provides a mechanism to initialize all the xon character registers with one write. a write to channel a xon character register returns the quad uart to the individual xon write mode. 10011 reserved for channels b-d, for channel a: enables gang write of xoff character registers. after this command is issued, a write to the channel a xoff character register will result in a write to all channel's xoff character registers. this command provides a mechanism to initialize all the xoff character registers with one write. a write to channel a xoff character register returns the quad uart to the individual xoff write mode. note: gang writing of xon/xoff character commands: issuing command causes the next write to xon/xoff character register a to effect a simultaneous write into the other 3 xon/xoff character registers. after the xon/xoff character register a is written, the 28l194 returns to individual write mode for the xon/xoff character registers. other intervening reads and writes are ignored. the device resets to individual write mode. 10100 reserved for channels b-d, for channel a: executes a gang load of xon character registers. executing this command causes a write of the value x'11 to all channel's xon character registers. this command provides a mechanism to initialize all the xon character registers to
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 33 a default value with one write. execution of this command is immediate and does not effect the timing of subsequent host i/o operations. 10101 reserved for channels b-d, for channel a: executes a gang load of xoff character registers. executing this command causes a write of the value x'13 to all channel's xoff character registers. this command provides a mechanism to initialize all the xoff character registers to a default value with one write. execution of this command is immediate and does not effect the timing of subsequent host i/o operations. 10110 xoff resume command (crxoffre; not active in aauto-transmit modeo). a command to cancel a previous host xoff command. upon receipt, the channel's transmitter will transfer a character, if any, from the txfifo and begin transmission. 10111 host xoff command (crxoff). this command allows tight host cpu control of the flow control of the channel transmitter. when interrupted for receipt of an xoff character by the receiver, the host may stop transmission of further characters by the channel transmitter by issuing the host xoff command. any character that has been transferred to the txd shift register will complete its transmission, including the stop bit. 11000 cancel host transmit flow control command. issuing this command will cancel a previous transmit command if the flow control character is not yet loaded into the txd shift register. if there is no character waiting for transmission or if its transmission has already begun, then this command has no effect. 11001-11011 reserved. 11011 reset address recognition status. this command clears the interrupt status that was set when an address character was recognized by a disabled receiver operating in the special mode. 11100-11101 reserved. 11110 resets all uart channel registers. this command provides a means to zero all the uart channels that are not reset to x'00 by a reset command or a hardware reset. 11111 reserved for channels b-d, for channel a: executes a chip wide reset. executing this command in channel a is equivalent to a hardware reset with the resetn pin. executing command register reset in channel b-d, has no effect. table 11. command register code commands x'12, x13, x'14, x'15, x'1f (marked with*) are global and exist only in channel a's register space. channel command code channel command channel command code channel command cr[7:3] description cr[7:3] description 00000 nop 10000 transmit xon 00001 reserved 10001 transmit xoff 00010 reset receiver 10010 gang write xon character registers * 00011 reset transmitter 10011 gang write xoff character registers * 00100 reset error status 10100 gang load xon character registers dc1 * 00101 reset break change interrupt 10101 gang load xoff character registers dc3 * 00110 begin transmit break 10110 xoff resume command 00111 end transmit break 10111 host xoff command 01000 assert rtsn (i/o2 or i/o1) 11000 cancel transmit x char command 01001 negate rtsn (i/o2 or i/o1) 11001 reserved 01010 set time-out mode on 11010 reserved 01011 reserved 11011 reset address recognition status 01100 set time-out mode off 11100 reserved 01101 block error status configure 11101 reserved 01110 reserved 11110 reset all uart channel registers 01111 reserved 11111 reset device *
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 34 sraechannel a status register sr status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sra srb received break 1 framing error 1 parity error 1 overrun error txemt txrdy ffull rxrdy 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes 0 = no 1 = yes note: 1. these status bits are appended to the corresponding data character in the receive fifo. a read of the status provides these bits (7:5) from the top of the fifo together with bits (4:0). these bits are cleared by a areset error statuso command. in character mod e they are discarded when the corresponding data character is read from the fifo. in block error mode, the error-reset command (command 4 x or receiver reset )must used to clear block error conditions sra [7]echannel a received break this bit indicates that an all zero character of the programmed length has been received without a stop bit. only a single fifo position is occupied when a break is received: further entries to the fifo are inhibited until the rxda line returns to the marking state for at least one-half a bit time two successive edges of the internal or external 1x clock. this will usually require a high time of one x1 clock period or 3 x1 edges since the clock of the controller is not synchronous to the x1 clock. when this bit is set, the channel a `change in break' bit in the isr (isr [2]) is set. isr [2] is also set when the end of the break condition, as defined above, is detected. the break detect circuitry can detect breaks that originate in the middle of a received character. however, if a break begins in the middle of a character, it must persist until at least the end of the next character time in order for it to be detected. this bit is reset by command 4 (0100) written to the command register or by receiver reset. sra [6]echannel a framing error this bit, when set, indicates that a stop bit was not detected when the corresponding data character in the fifo was received. the stop bit check is made in the middle of the first stop bit position. sra [5]echannel a parity error this bit is set when the `with parity' or `force parity' mode is programmed and the corresponding character in the fifo was received with incorrect parity. in the special multi-drop mode the parity error bit stores the receive a/d (address/data) bit. sra [4]echannel a overrun error this bit, when set, indicates that one or more characters in the received data stream have been lost. it is set upon receipt of a new character when the fifo is full and a character is already in the receive shift register waiting for an empty fifo position. when this occurs, the character in the receive shift register (and its break detect, parity error and framing error status, if any) is lost. this bit is cleared by a `reset error status' command. sra [3]echannel a transmitter empty (txemta) this bit will be set when the transmitter under runs, i.e., both the txemt and txrdy bits are set. this bit and txrdy are set when the transmitter is first enabled and at any time it is re-enabled after either (a) reset, or (b) the transmitter has assumed the disabled state. it is always set after transmission of the last stop bit of a character if no character is in the thr awaiting transmission. it is reset when the thr is loaded by the cpu, a pending transmitter disable is executed, the transmitter is reset, or the transmitter is disabled while in the under run condition. sra [2]echannel a transmitter ready (txrdya) this bit, when set, indicates that the transmit fifo is not full and ready to be loaded with another character. this bit is cleared when the transmit fifo is loaded by the cpu and there are (after this load) no more empty locations in the fifo. it is set when a character is transferred to the transmit shift register. txrdya is reset when the transmitter is disabled and is set when the transmitter is first enabled. characters loaded to the txfifo while this bit is 0 will be lost. this bit has different meaning from isr [0]. sra [1]echannel a fifo full (ffulla) this bit is set when a character is transferred from the receive shift register to the receive fifo and the transfer causes the fifo to become full, i.e., all eight fifo positions are occupied. it is reset when the cpu reads the receive fifo. if a character is waiting in the receive shift register because the fifo is full, ffulla will not be reset when the cpu reads the receive fifo. this bit has different meaning from isr(1) when mr1 6 is programmed to a `1'. sra [0]echannel a receiver ready (rxrdya) this bit indicates that a character has been received and is waiting in the fifo to be read by the cpu. it is set when the character is transferred from the receive shift register to the fifo and reset when the cpu reads the receive fifo, only if (after this read) there are no more characters in the fifo. srbechannel b status register the bit definitions for this register are identical to the bit definitions for sra, except that all status applies to the channel b receiver and transmitter and the corresponding inputs and outputs.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 35 opcreoutput port configuration register opcr output port configuration register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 op7 op6 op5 op4 op3 op2 op1 op0 0 = opr[7] 1 = txrdy b 0 = opr[6] 1 = txrdy a 0 = opr[5] 1 = rxrdy/ffull b 0 = opr[4] 1 = rxrdy/ffull a 00 = opr[3] 01 = c/t output 10 = txcb(1x) 11 = rxcb(1x) 00 = opr[2] 01 = txca(16x) 10 = txca(1x) 11 = rxca(1x) opcr [7]eop7 output select this bit programs the op7 output to provide one of the following: 0 the complement of opr [7]. 1 the channel b transmitter interrupt output which is the complement of isr [4]. when in this mode op7 acts as an open-drain output. note that this output is not masked by the contents of the imr. opcr [6]eop6 output select this bit programs the op6 output to provide one of the following: 0 the complement of opr [6]. 1 the channel a transmitter interrupt output which is the complement of isr [0]. when in this mode op6 acts as an open-drain output. note that this output is not masked by the contents of the imr. opcr [5]eop5 output select this bit programs the op5 output to provide one of the following: 0 the complement of opr [5]. 1 the channel b receiver interrupt output which is the complement of isr [5]. when in this mode op5 acts as an open-drain output. note that this output is not masked by the contents of the imr. opcr [4]eop4 output select this field programs the op4 output to provide one of the following: 0 the complement of opr [4]. 1 the channel a receiver interrupt output which is the complement of isr [1]. when in this mode op4 acts as an open-drain output. note that this output is not masked by the contents of the imr. opcr [3:2]eop3 output select this bit programs the op3 output to provide one of the following: 00 the complement of opr [3]. 01 the counter/timer output, in which case op3 acts as an open-drain output. in the timer mode, this output is a square wave at the programmed frequency. in the counter mode, the output remains high until terminal count is reached; at which time it goes low. the output returns to the high state when the counter is stopped by a stop counter command. note that this output is not masked by the contents of the imr. 10 the 1x clock for the channel b transmitter, which is the clock that shifts the transmitted data. if data is not being transmitted, a free running 1x clock is output. 11 the 1x clock for the channel b receiver, which is the clock that samples the received data. if data is not being received, a free running 1x clock is output. opcr [1:0]eop2 output select this field programs the op2 output to provide one of the following: 00 the complement of opr [2]. 01 the 16x clock for the channel a transmitter. this is the clock selected by csra [3:0], and will be a 1x clock if csra [3:0] = 1111. 10 the 1x clock for the channel a transmitter, which is the clock that shifts the transmitted data. if data is not being transmitted, a free running 1x clock is output. 11 the 1x clock for the channel a receiver, which is the clock that samples the received data. if data is not being received, a free running 1x clock is output.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 36 sopreset the output port bits (opr) sopr [7:0]eones in the byte written to this register will cause the corresponding bit positions in the opr to set to 1. zeros have no effect. this allows software to set individual bits with our keeping a copy of the opr bit configuration. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set opr bits op 7 op 6 op 5 op 4 op 3 op 2 op 1 op 0 1 = set bit 0 = no change 1 = set bit 0 = no change 1 = set bit 0 = no change 1 = set bit 0 = no change 1 = set bit 0 = no change 1 = set bit 0 = no change 1 = set bit 0 = no change 1 = set bit 0 = no change roprereset output port bits (opr) ropr [7:0]eones in the byte written to the ropr will cause the corresponding bit positions in the opr to set to 0. zeros have no effect. this allows software to reset individual bits with our keeping a copy of the opr bit configuration. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset opr bits op 7 op 6 op 5 op 4 op 3 op 2 op 1 op 0 1 = reset bit 0 = no change 1 = reset bit 0 = no change 1 = reset bit 0 = no change 1 = reset bit 0 = no change 1 = reset bit 0 = no change 1 = reset bit 0 = no change 1 = reset bit 0 = no change 1 = reset bit 0 = no change opr output port register the output pins (op pins) drive the compliment of the data written to this register. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 opr op 7 op 6 op 5 op 4 op 3 op 2 op 1 op 0 0 = pin high 1 = pin low 0 = pin high 1 = pin low 0 = pin high 1 = pin low 0 = pin high 1 = pin low 0 = pin high 1 = pin low 0 = pin high 1 = pin low 0 = pin high 1 = pin low 0 = pin high 1 = pin low acr auxiliary control register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 acr brg set select counter timer mode mode and clock sour select delta ip3 int enable delta ip3 int enable delta ip3 int enable delta ip3 int enable 0 = set 1 1 = set 2 see table 12 0 = off 1 = enabled 0 = off 1 = enabled 0 = off 1 = enabled 0 = off 1 = enabled acreauxiliary control register acr [7]ebaud rate generator set select this bit selects one of two sets of baud rates to be generated by the brg (see table 9). the selected set of rates is available for use by the channel a and b receivers and transmitters as described in csra and csrb. baud rate generator characteristics are given in table 9?. acr [6:4]ecounter/timer mode and clock source select this field selects the operating mode of the counter/timer and its clock source as shown in table 12. acr [3:0]eip3, ip2, ip1, ip0 change-of-state interrupt enable this field selects which bits of the input port change register (ipcr) cause the input change bit in the interrupt status register (isr [7]) to be set. if a bit is in the `on' state the setting of the corresponding bit in the ipcr will also result in the setting of isr [7], which results in the generation of an interrupt output if imr [7] = 1. if a bit is in the `off' state, the setting of that bit in the ipcr has no effect on isr [7]. table 12. acr 6:4 field definition acr 6:4 mode clock source 000 counter external (ip2) 001 counter txca 1x clock of channel a transmitter 010 counter txcb 1x clock of channel b transmitter 011 counter crystal or external clock (x1/clk) divided by 16 100 timer external (ip2) 101 timer external (ip2) divided by 16 110 timer crystal or external clock (x1/clk) 111 timer crystal or external clock (x1/clk) divided by 16 note: the timer mode generates a square wave.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 37 table 13. i/opcr30 (ports 30) bits 7:6 bits 5:4 bits 3:2 bits 1:0 i/o3 control i/o2 control i/o1 control i/o0 control 00 - general purpose input 01 - opr[3] output 10 - tx interrupt 11 - reserved 00 - general purpose input 01 - opr[2] output 10 - rx interrupt 11 - reserved 00 - general purpose input 01 - opr[1] output 10 - cts 11 - reserved 00 - general purpose input 01 - opr[0] output 10 - rts 11 - reserved table 14. i/opcr74 (ports 74) bits 7:6 bits 5:4 bits 3:2 bits 1:0 i/o3 control i/o2 control i/o1 control i/o0 control 00 - general purpose input 01 - opr[7] output 10 - dma tx 11 - reserved 00 - general purpose input 01 - opr[6] output 10 - dma rx 11 - reserved 00 - general purpose input 01 - opr[5] output 10 - dsr 11 - reserved 00 - general purpose input 01 - opr[5] output 10 - dtr 11 - reserved
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 38 table 15. isr - interrupt status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i/o port change of state receiver watch-dog time-out address recognition event xon/off event always 0 change of break state rxrdy receiver has entered arbitration process txrdy transmitter has entered arbitration process this register provides the status of all potential interrupt sources for a uart channel. when generating an interrupt arbitration value, the contents of this register are masked by the interrupt mask register (imr). if a bit in the isr is a '1' and the corresponding bit in the imr is also a '1', interrupt arbitration for this source will begin. if the corresponding bit in the imr is a zero, the state of the bit in the isr can have no affect on the irqn output. note that the imr may or may not mask the reading of the isr as determined by mr1[6]. if mr1[6] is cleared, the reset and power on default, the isr is read without modification. if mr1[6] is set, the a read of the isr gives a value of the isr anded with the imr. isr[7] - input change of state this bit is set when a change of state occurs at the i/o1 or i/o0 input pins. it is reset when the cpu reads the input port register, ipr. isr[6] watch-dog time-out this bit is set when the receiver's watch-dog timer has counted more than 64 bit times since the last rxfifo event. rxfifo events are a read of the rxfifo or grxfifo, or the push of a received character into the fifo. the interrupt will be cleared automatically upon the push of the next character received or when the rxfifo or grxfifo is read. the receiver watch-dog timer is included to allow detection of the very last characters of a received message that may be waiting in the rxfifo, but are too few in number to successfully initiate an interrupt. refer to the watch-dog timer description for details of how the interrupt system works after a watch-dog time-out. isr[5] - address recognition status change this bit is set when a change in receiver state has occurred due to an address character being received from an external source and comparing to the reference address in arcr. the bit and interrupt is negated by a write to the cr with command x11011, reset address recognition status. isr[4] - xon/xoff status change this bit is set when an xon/xoff character being received from an external source. the bit is negated by a read of the channel xon interrupt status register, xisr. isr[3] - reserved always reads a 0 isr[2] - change in channel break status this bit, when set, indicates that the receiver has detected the beginning or the end of a received break. it is reset when the cpu issues a reset break change interrupt command via the cr. isr[1] - receiver ready the general function of this bit is to indicate that the rxfifo has data available. the particular meaning of this bit is programmed by mr2[3:2]. if programmed as receiver ready(mr2[3:2] = 00), it indicates that at least one character has been received and is waiting in the rxfifo to be read by the host cpu. it is set when the character is transferred from the receive shift register to the rxfifo and reset when the cpu reads the last character from the rxfifo. if mr2[3:2] is programmed as fifo full, isr[1] is set when a character is transferred from the receive holding register to the rxfifo and the transfer causes the rxfifo to become full, i.e. all fifo positions are occupied. it is reset when ever rxfifo is not full. if there is a character waiting in the receive shift register because the fifo is full, the bit is set again when the waiting character is transferred into the fifo. the other two conditions of these bits, 3/4 and half full operate in a similar manner. the isr[1] bit is set when the rxfifo fill level meets or exceeds the value; it is reset when the fill level is less. see the description of the mr2 register. note: this bit must be at a one (1) for the receiver to enter the arbitration process. it is the fact that this bit is zero (0) when the rxfifo is empty that stops an empty fifo from entering the interrupt arbitration. also note that the meaning if this bit is not quite the same as the similar bit in the status register (sr). isr[0] - transmitter ready the general function of this bit is to indicate that the txfifo has an at least one empty space for data. the particular meaning of the bit is controlled by mr0[5:4] indicates the txfifo may be loaded with one or more characters. if mr0[5:4] = 00 (the default condition) this bit will not set until the txfifo is empty - all fifo bytes available. if the fill level of the txfifo is below the trigger level programmed by the txint field of the mode register 0, this bit will be set. a one in this position indicates that at least one character can be sent to the txfifo. it is turned off as the txfifo is filled above the level programmed by mr0[5:4. this bit turns on as the fifo empties; the rxfifo bit turns on as the fifo fills. this often a point of confusion in programming interrupt functions for the receiver and transmitter fifos. note: this bit must be at a one (1) for the transmitter to enter the arbitration process. it is the fact that this bit is zero (0) when the rxfifo is full that stops a full fifo from entering the interrupt arbitration. also note that the meaning if this bit is not quite the same as the similar bit in the status register (sr).
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 39 table 16. imr - interrupt mask register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 i/o port change of state receiver watch-dog time-out address recognition event xon/off event set to 0 change of break state rxrdy interrupt txrdy interrupt the programming of this register selects which bits in the isr cause an interrupt output. if a bit in the isr is a '1' and the corresponding bit in the imr is a '1', the interrupt source is presented to the internal interrupt arbitration circuits, eventually resulting in the irqn output being asserted (low). if the corresponding bit in the imr is a zero, the state of the bit in the isr has no affect on the irqn output. imr[7] - controls if a change of state in the inputs equipped with input change detectors will cause an interrupt. imr[6] - controls the generation of an interrupt by the watch-dog timer event. if set, a count of 64 idle bit times in the receiver will begin interrupt arbitration. imr[5] - enables the generation of an interrupt in response to changes in the address recognition circuitry of the special mode (multi-drop or wake-up mode). imr[4] - enables the generation of an interrupt in response to recognition of an in-band flow control character. imr[3] - reserved imr[2] - enables the generation of an interrupt when a break condition has been detected by the channel receiver. imr[1] - enables the generation of an interrupt when servicing for the rxfifo is desired. imr[0] - enables the generation of an interrupt when servicing for the txfifo is desired.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 40 table 17. xisr - xon-xoff interrupt status register see mr0 for a description of enabling these functions bits 7:6 bits 5:4 bits 3:2 bits 1:0 received x character status automatic x character transmission status txd flow status txd character status 00 - none 01 - xoff received 10 - xon received 11 - both received 00 - none 01 - xon transmitted 10 - xoff transmitted 11 - illegal, does not occur 00 - normal 01 - txd halt pending 10 - re-enabled 11 - flow disabled 00 - normal txd data 01 - wait on normal data 10 - xoff in pending 11 - xon in pending note: bits of this register may be cleared by a read of the register. xisr[7:6] - received x character status. this field can be read to determine if the receiver has encountered an xon or xoff character in the incoming data stream. these bits are maintained until a read of the xisr. the field is updated by x character reception regardless of the state of mr0(7, 3:2) or imr(4). the field can therefore be used as a character detector for the bit patterns stored in the xon and xoff character registers. xisr[5:4] - automatic transmission status. this field indicates the last flow control character sent in the auto receiver flow control mode. if auto receiver mode has not been enabled, this field will always read b'00. it will likewise reset to b'00 if mr0(3) is reset. if the auto receiver mode is exited while this field reads b'10, it is the user's responsibility to transmit an xon, when appropriate. xisr[3:2] - txd flow status. this field tracks the transmitter's flow status as follows: 00 - normal. the flow control is under host control. 01 - txd halt pending. after the current character finishes the transmitter will stop. the status will then change to b'00. 10 - re-enabled. the transmitter had been halted and restarted. it is sending data characters. after a read of the xisr, it will return to anormalo status. 11 - disabled. the transmitter is flow controlled. xisr[1:0] - txd character status. this field allows determination of the type of character being transmitted. if xisr(1:0) is b'01, the channel is waiting for a data character to transfer from the txfifo. this condition will only occur for a bit time after an xon or xoff character transmission unless the txfifo is empty.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 41 ctpu and ctplecounter/timer registers ctpu counter timer preset upper bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ctpu the lower eight (8) bits for the 16 bit counter timer preset register ctpl counter -timer preset low bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ctpl the upper eight (8) bits for the 16 bit counter timer preset register the ctpu and ctpl hold the eight msbs and eight lsbs, respectively, of the value to be used by the counter/timer in either the counter or timer modes of operation. the minimum value that may be loaded into the ctpu/ctpl registers is h`0002'. note that these registers are write-only and cannot be read by the cpu. in the timer mode, the c/t generates a square wave whose period is twice the value (in c/t clock periods) of the ctpu and ctpl. the waveform so generated is often used for a data clock. the formula for calculating the divisor n to load to the ctpu and ctpl for a particular 1x data clock is shown below. n = (c/t clock frequency) divided by (2 x 16 x baud rate desired) n = (c/t clock frequency)/ (2 x 16 x baud rate desired) often this division will result in a non-integer number, 26.3 for example. one can only program integer numbers in a digital divider. therefore, 26 would be chosen. this gives a baud rate error of 0.3/26.3, which is 1.14% and well within the ability asynchronous mode of operation. if the value in ctpu and ctpl is changed, the current half-period will not be affected, but subsequent half periods will be. the c/t will not be running until it receives an initial `start counter' command (read at address a3a0 = 1110). after this, while in timer mode, the c/t will run continuously. receipt of a start counter command (read with a3a0 = 1110) causes the counter to terminate the current timing cycle and to begin a new cycle using the values in ctpu and ctpl. the counter ready status bit (isr [3]) is set once each cycle of the square wave. the bit is reset by a stop counter command (read with a3a0 = 0xf). the command however, does not stop the c/t. the generated square wave is output on op3 if it is programmed to be the c/t output. in the counter mode, the value c/t loaded into ctpu and ctpl by the cpu is counted down to 0. counting begins upon receipt of a start counter command. upon reaching terminal count h`0000', the counter ready interrupt bit (isr [3]) is set. the counter continues counting past the terminal count until stopped by the cpu. if op3 is programmed to be the output of the c/t, the output remains high until terminal count is reached; at which time it goes low. the output returns to the high state and isr [3] is cleared when the counter is stopped by a stop counter command. the cpu may change the values of ctpu and ctpl at any time, but the new count becomes effective only on the next start counter commands. if new values have not been loaded, the previous count values are preserved and used for the next count cycle in the counter mode, the current value of the upper and lower 8 bits of the counter (ctu, ctl) may be read by the cpu. it is recommended that the counter be stopped when reading to prevent potential problems that may occur if a carry from the lower 8 bits to the upper 8 bits occurs between the times that both halves of the counter are read. however, note that a subsequent start counter command will cause the counter to begin a new count cycle using the values in ctpu and ctpl. when the c/t clock divided by 16 is selected, the maximum divisor becomes 1,048,575. the cts, rts, cts enable tx signals cts (clear to send) is usually meant to be a signal to the transmitter meaning that it may transmit data to the receiver. the cts input is on pin ip0 for txa and on ip1 for txb. the cts signal is active low; thus; it is called ctsan for txa and ctsbn for txb. rts is usually meant to be a signal from the receiver indicating that the receiver is ready to receive data. it is also active low and is, thus, called rtsan for rxa and rtsbn for rxb. rtsan is on pin op0 and rtsbn is on op1. a receiver's rts output will usually be connected to the cts input of the associated transmitter. therefore, one could say that rts and cts are different ends of the same wire! mr2 (4) is the bit that allows the transmitter to be controlled by the cts pin (ip0 or ip1). when this bit is set to one and the cts input is driven high, the transmitter will stop sending data at the end of the present character being serialized. it is usually the rts output of the receiver that will be connected to the transmitter's cts input. the receiver will set rts high when the receiver fifo is full and the start bit of the ninth character is sensed. transmission then stops with nine valid characters in the receiver. when mr2 (4) is set to one, ctsn must be at zero for the transmitter to operate. if mr2 (4) is set to zero, the ip pin will have no effect on the operation of the transmitter. mr1 (7) is the bit that allows the receiver to control op0. when the receiver controls op0 (or op1), the meaning of that pin will be. resetn t res sd00133 figure 2.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 42 a0a3 cen t as t cs t ch rdn t rw t rwd d0d7 (read) t dd t df float float valid not valid wdn t rwd valid d0d7 (write) t ds t dh t ah sd00087 figure 3. (b) output pins rdn ip0ip6 wrn op0op7 t ps t ph t pd old data new data (a) input pins sd00135 figure 4.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 43 notes: 1. intrn or op3-op7 when used as interrupt outputs. 2. the test for open-drain outputs is intended to guarantee switching of the output transistor. measurement of this response is referenced from the midpoint of the switching signal, v m , to a point 0.5v above v ol . this point represents noise margin that assures true switching has occurred. beyond this level, the effects of external cir cuitry and test environment are pronounced and can greatly affect the resultant measurement. v m v ol +0.5v v ol wrn interrupt 1 output t ir v m v ol +0.5v v ol rdn interrupt 1 output t ir sd00136 figure 5. c1 = c2 ~ 24pf for c l = 20pf t clk t ctc t rx t tx x1/clk ctclk rxc txc t clk t ctc t rx t tx +5v 470 w x1 x2* clk *note: x2 must be left open. x2 3.6864mhz x1 c1 c2 sc26c92 note: resistor required for ttl input. to uart circuit 50k w to 100k w 3pf 3pf c1 and c2 should be chosen according to the crystal manufacturer's specification. c1 and c2 values will include any parasitic capacitance of the wiring and x1 x2 pins. gain at 3.6864mhz: 9 to 13 db phase at 3.6864mhz: 272 to 276 degrees. 2pf 4pf package capacitance approximately 4pf. sd00154 figure 6.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 44 t txd t tcs 1 bit time (1 or 16 clocks) txd txc (input) txc (1x output) sd00138 figure 7. t rxs t rxh rxc (1x input) rxd sd00139 figure 8. transmitter enabled txd d1 d2 d3 d4 d6 break txrdy (sr2) wrn d1 d8 d9 d10 d12 start break stop break d11 will not be written to the txfifo ctsn 1 (ip0) rtsn 2 (op0) opr(0) = 1 opr(0) = 1 notes: 1. timing shown for mr2(4) = 1. 2. timing shown for mr2(5) = 1. sd00155 figure 9.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 45 d1 d2 d8 d9 d10 d11 d12 d13 rxd d12, d13 will be lost due to receiver disable. receiver enabled rxrdy (sr0) ffull (sr1) rxrdy/ ffull (op5) 2 rdn status data d1 status data d2 status data d3 status data d10 d11 will be lost due to overrun overrun (sr4) reset by command rts 1 (op0) opr(0) = 1 notes: 1. timing shown for mr1(7) = 1. 2. shown for opcr(4) = 1 and mr(6) = 0. sd00156 figure 10. transmitter enabled txd add#1 txrdy (sr2) wrn mr1(43) = 11 mr1(2) = 1 1 bit 9 d0 0 bit 9 add#2 1 bit 9 master station add#1 mr1(2) = 0 d0 mr1(2) = 1 add#2 rxd add#1 1 bit 9 d0 0 bit 9 add#2 1 bit 9 peripheral station 0 bit 9 0 bit 9 receiver enabled rxrdy (sr0) rdn/wrn mr1(43) = 11 add#1 status data d0 status data add#2 sd00096 figure 11.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 46 intrn d0d7 txda/b op0op7 50pf +5v 2.7k 150pf +5v i = 2.4ma v ol i = 400 m a v oh sd00157 figure 12.
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 47 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 48 qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2
philips semiconductors objective specification sc28l202 dual universal asynchronous receiver/transmitter (duart) 1998 oct 05 49 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. date of release: 10-98 document order number: 9397 750 04467
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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