**********
c-mos sddi packing (gate array)
- top view - CXD8988AR (1/4)
il11 156
155
150
145
140
135
130
125
120
115
110
105 157
160
165
170
175
180
185
190
195
200
205
208 1
5
10
15
20
25
30
35
40
45
50
52 104
100
95
90
85
80
75
70
65
60
55
53 nc gnd gnd gnd gnd v dd (+3.3 v) gnd nc nc gnd gnd gnd v dd (+3.3 v) v dd (+3.3 v) v dd (+3.3 v) v dd (+3.3 v) v dd (+3.3 v) gnd gnd gnd gnd gnd v dd (+3.3 v) v dd (+3.3 v) gnd gnd gnd gnd gnd v dd (+3.3 v) v dd (+3.3 v) v dd (+3.3 v) v dd (+3.3 v)
CXD8988AR (2/4) 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42 ovdwe7
ovdwe6
gnd
ovdwe5
ovdwe4
ovdwe3
ovdwe2
ovdwe1
ovdwe0
v dd
ovdrw
owremk
owrsync
owrvdpr
gnd
oatrwn
oatwen
bsybus7
bsybus6
bsybus5
bsybus4
bsybus3
bsybus2
bsybus1
bsybus0
gnd
v dd
idirrdh
ipkcsn
istrbn
istat1
istat0
bmon7
bmon6
bmon5
bmon4
bmon3
gnd
bmon2
bmon1
bmon0
osxrfrm o
o
? o
o
o
o
o
o
? o
o
o
o
? o
o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
i/o
? ? i
i
i
i
i
i/o
i/o
i/o
i/o
i/o
? i/o
i/o
i/o
o (v dd = +3.3 v) pin
no. i/o signal 43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84 v dd
isxigopt
isxifrm
isxih
ig2rstn
ireffrm
irefh
gnd
isxsync
isxdt7
isxdt6
isxdt5
isxdt4
isxdt3
isxdt2
isxdt1
isxdt0
gnd
v dd
isxprty
ivwck
nc
nc
ivgopst
iareff
ovpfw2gt
oapwgt
opfr2gt
opfragt
gnd
xtre
xtwe
xmm
ordperr
ocoref
ocoreh
v dd
xsm
xtst
ivaself
ivaselh
ivrck ? i
i
i
i
i
i
? i
i
i
i
i
i
i
i
i
? ? i
i
? ? i
i
o
o
o
o
? i
i
i
o
o
o
? i
i
i
i
i pin
no. i/o signal 85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126 gnd
ocrprty
ocrsync
ocrdt7
ocrdt6
ocrdt5
ocrdt4
ocrdt3
ocrdt2
ocrdt1
ocrdt0
gnd
v dd
oatend
ovend
oaend
iatint
ivint
iaint
iaten
iven
iaen
gnd
odlfs2
odlfs1
opki12
opki34
opki56
opki78
v dd
ipko12
ipko34
ipko56
ipko78
gnd
ibyp12
ibyp34
ibyp56
ibyp78
ibrr12
ibrr34
ibrr56 ? o
o
o
o
o
o
o
o
o
o
? ? o
o
o
i
i
i
i
i
i
? o
o
o
o
o
o
? i
i
i
i
? i
i
i
i
i
i
i pin
no. i/o signal 127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168 ibrr78
ifs128
ifs1
gnd
v dd
oapfwrp
oapfwd8
oapfwd7
oapfwd6
oapfwd5
oapfwd4
oapfwd3
oapfwd2
oapfwd1
oapfwd0
gnd
oadrw
oadwe0
oadwe1
oaweall
v dd
oaact
oaspin
osplat
ogt5f
iaudsiml
ia5fsq2
gnd
ia5fsq1
ia5fsq0
ovancln
ovidxln
oaatoen
ipko12b
ipko34b
ivagck
nc
gnd
v dd
oatrstrn
oatren
ovre7 i
i
i
? ? o
o
o
o
o
o
o
o
o
o
? o
o
o
o
? o
o
o
o
i
i
? i
i
o
o
o
i
i
i
? ? ? o
o
o pin
no. i/o signal 169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208 ovre6
ovre5
ovre4
ovre3
ovre2
ovre1
ovre0
gnd
ovrstr
ovoen74
ovoen30
oarstr
oare1
oare0
v dd
xack
bck
xtck
irdemk
irdprty
gnd
irddt7
irddt6
irddt5
irddt4
irddt3
irddt2
irddt1
irddt0
irdsync
owrdt7
gnd
v dd
owrdt6
owrdt5
owrdt4
owrdt3
owrdt2
owrdt1
owrdt0 o
o
o
o
o
o
o
? o
o
o
o
o
o
? i
i/o
i
i
i
? i
i
i
i
i
i
i
i
i
o
? ? o
o
o
o
o
o
o pin
no. i/o signal
CXD8988AR (3/4) input
ia5fsq0 - ia5fsq2
iaen
iaint
iareff
iaten
iatint
iaudsiml
ibrr12
ibrr34
ibrr56
ibrr78
ibyp12
ibyp34
ibyp56
ibyp78
idirrdh
ifs1
ifs128
ig2rstn
ipkcsn
ipko12
ipko34
ipko56
ipko78
ipko12b
ipko34b
irddt0 - irddt7
irdemk
irdprty
irdsync
ireffrm
irefh
istat0, istat1
istrbn
isxdt0 - isxdt7
isxifrm
isxigopt
isxih
isxprty
isxsync
ivagck
ivaself
ivaselh
iven
ivgopst
ivint
ivrck
ivwck
xack, xmm, xsm
xtck, xtre
xtst, xtwe
; audio 5f sequence 0 - 2
; audio enable pulse
; audio interrupt pulse
; audio reference frame
; attribute enable pulse
; attribute interrupt pulse
; audio simulation mode
; audio brr data in 1/2-ch
; audio brr data in 3/4-ch
; audio brr data in 5/6-ch
; audio brr data in 7/8-ch
; audio non-brr data in 1/2-ch
; audio non-brr data in 3/4-ch
; audio non-brr data in 5/6-ch
; audio non-brr data in 7/8-ch
; system interface direction
; audio fs1
; audio fs128
; 2 gop reset
; system interface chip select
; audio packed data in 1/2-ch
; audio packed data in 3/4-ch
; audio packed data in 5/6-ch
; audio packed data in 7/8-ch
; audio packed data - b 1/2-ch
; audio packed data - b 3/4-ch
; fifo read data 0 - 7
; fifo read end mark
; fifo read parity
; fifo read sync
; frame pulse (ref. lock)
; h pulse (ref. lock)
; system interface address 0, 1
; system interface strobe
; enc output data 0 - 7
; frame pulse (input lock)
; gop start pulse
; h pulse (input lock)
; enc output parity
; enc output sync
; vanc gen. 27 mhz clock
; vanc selected frame
; vanc selected h
; video enable pulse
; video gop start
; video interrupt pulse
; read 27 mhz clock
; video write 27 mhz clock
; ic test
CXD8988AR (4/4) output
oaact
oaatoen
oadrw
oadwe0, oadwe1
oaend
oapfwd0 - oapfwd8
oapfwpr
oapwgt
oare0, oare1
oarstr
oaspin
oatend
oatren
oatrstrn
oatrwn
oatwen
oaweall
ocoref
ocoreh
ocrdt0 - ocrdt7
ocrprty
ocrsync
odlfs1, odlfs2
ogt5f
opfr2gt
opfragt
opki12
opki34
opki56
opki78
ordperr
osplat
osxrfrm
ovancln
ovdrw
ovdwe0 - ovdwe7
ovend
ovidxln
ovoen30
ovoen74
ovpfw2gt
ovre0 - ovre7
ovrstr
owrdt0 - owrdt7
owremk
owrsync
owrvdpr
input/output
bck
bmon0 - bmon7
bsybus0 - bsybus7
; audio active pulse
; audio/attribute fifo output enable
; audio fifo reset write
; audio fifo write enable 0, 1
; audio end pulse
; audio fifo write data 0 - 8
; audio fifo write parity
; audio write gop
; audio fifo read enable 0, 1
; audio fifo reset read
; audio s/p input data
; attribute end pulse
; attribute fifo read enable
; attribute fifo reset read
; attribute fifo reset write
; attribute fifo write enable
; audio fifo write enable all
; sddi core frame
; sddi core h
; packed data 0 - 7
; packed data parity
; packed data sync
; delayed fs1, 2
; audio 5f pulse
; read 2 gop
; advance read gop
; audio pack data out 1/2-ch
; audio pack data out 3/4-ch
; audio pack data out 5/6-ch
; audio pack data out 7/8-ch
; read parity error
; audio s/p latch pulse
; enc read start
; vanc line pulse
; video fifo reset write
; video fifo write enable 0 - 7
; video end pulse
; video index line pulse
; video fifo output enable 3 - 0
; video fifo output enable 7 - 4
; video write 2 gop
; video fifo read enable 0 - 7
; video fifo reset read
; video fifo write data 0 - 7
; video fifo write end pulse
; video fifo write sync
; video fifo write parity
; ic test
; monitor output 0 - 7
; system interface bus 0 - 7
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