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?1 cxp83408/83412/83416 CXP83409/83413/83417 e93z15d15-ps cmos 8-bit single chip microcomputer description the cxp83408/83412/83416 and CXP83409/83413/ 83417 are a cmos 8-bit microcomputer which consists of a/d converter, serial interface, timer/counter, time base timer, 32khz timer/counter, lcd controller/ driver, remote control receiving circuit and pwm output, as well as basic configurations like 8-bit cpu, rom, ram and i/o port. they are integrated into a single chip. also cxp83408/83412/83416 and CXP83409/83413/ 83417 sleep/ stop function which enables to lower power consumption. features a wide instruction set (213 instructions) which covers various types of data 16-bit arithmetic/multiplication and division/ boolean bit operation instructions minimum instruction cycle 400ns at 10mhz operation (4.5 to 5.5v) 122s at 32khz operation (2.7 to 5.5v) incorporated rom capacity 8k bytes (cxp83408, 83409) 12k bytes (cxp83412, 83413) 16k bytes (cxp83416, 83417) incorporated ram capacity 448 bytes (lcd display data area included) peripheral functions ?a/d converter 8 bits, 8 channels, successive approximation system (conversion time: 32s/10mhz) ?serial interface incorporated 8-bit and 8-stage fifo (1 to 8 bytes auto transfer), 1 circuit 2 channels ?timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32khz timer/counter ?lcd controller/driver maximum 128 segments display possible (during 1/4 duty) 4 common outputs, 32 segment outputs display method: static, 1/2, 1/3 and 1/4 duty bias method: 1/2 and 1/3 bias ?remote control receiving circuit 8-bit pulse measurement counter, 6-stage fifo ?pwm output 14 bits 1 channel, 8 bits 1 channel interruption 12 factors, 12 vectors, multi-interruption possible standby mode sleep/stop package 80-pin plastic qfp/lqfp piggyback/evaluator cxp83400 (cxp83408, 83412, 83416) cxp83401 (CXP83409, 83413, 83417) structure silicon gate cmos ic sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxp83408/83412/83416 80 pin qfp (plastic) 80 pin lqfp (plastic) CXP83409/83413/83417 80 pin qfp (plastic)
?2 cxp83408/83412/83416, CXP83409/83413/83417 xtal a/d converter 14bit pwm generator remocon serial interface unit 0 8bit timer/counter 0 8bit timer 1 fifo fifo interrupt controller spc700 cpu core rom 8k/12k/16k bytes prescaler/ time base timer 32khz timer/counter ram 448 bytes 8 an0 to an7 pwm0 rmc si0 so0 si1 so1 ec cs0 sck0 sck1 int0 int1 int2 nmi/int3 tex tx extal v dd vss port c 8 pc0 to pc7 port h 1 ph0 port b 8 pb0 to pb7 port e 5 2 pe0 to pe4 pe5 to pe6 2 lcd controller/ driver 32 seg0 to seg31 4 com0 to com3 v l v lc1 v lc2 port a 8 pa0 to pa7 port d 8 pd0 to pd7 port f 8 pf0 to pf7 v lc3 adj pwm1 8bit pwm generator cs1 to clock generator/ system control rst 2 2 block diagram
3 cxp83408/83412/83416, CXP83409/83413/83417 pe3/int3/nmi pe4/rmc pe5/pwm0 pe6/to/adj pb0/cs1 pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ph0/pwm1 pa0/an0 pa1/an1 pa2/an2 pd6/seg22 pd5/seg21 pd4/seg20 pd3/seg19 pd2/seg18 pd1/seg17 pd0/seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com3 pa3/an3 pa4/an4 pa5/an5 pa6/an6 pa7/an7 rst extal xtal v ss v l v lc3 v lc2 v lc1 com0 com1 com2 pe2/int2 pe1/int1 pe0/int0/ec pf7/seg31 pf6/seg30 nc tex tx v dd pf5/seg29 pf4/seg28 pf3/seg27 pf2/seg26 pf1/seg25 pf0/seg24 pd7/seg23 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 70 69 68 67 65 66 71 72 73 74 75 76 77 78 79 80 1 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 pin assignment (top view) cxp83408/83412/83416 (qfp package) note) nc (pin 75) is always connected to v dd .
4 cxp83408/83412/83416, CXP83409/83413/83417 pe5/pwm0 pe6/to/adj pb0/cs1 pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ph0/pwm1 pa0/an0 pd4/seg20 pd3/seg19 pd2/seg18 pd1/seg17 pd0/seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 pa1/an1 pa2/an2 pa3/an3 pa4/an4 pa5/an5 pa6/an6 pa7/an7 rst extal xtal v ss v l v lc3 v lc2 v lc1 com0 com1 com2 com3 seg0 pe4/rmc pe3/int3/nmi pe2/int2 pe1/int1 pe0/int0/ec pf7/seg31 pf6/seg30 nc tex tx v dd pf5/seg29 pf4/seg28 pf3/seg27 pf2/seg26 pf1/seg25 pf0/seg24 pd7/seg23 pd6/seg22 pd5/seg21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 70 69 68 67 65 66 71 72 73 74 75 76 77 78 79 80 1 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 pin assignment (top view) cxp83408/83412/83416 (lqfp package) note) nc (pin 73) is always connected to v dd .
5 cxp83408/83412/83416, CXP83409/83413/83417 pe5/pwm0 pe6/to/adj pb0/cs1 pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ph0/pwm1 pa0/an0 pd4/seg20 pd3/seg19 pd2/seg18 pd1/seg17 pd0/seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 pa1/an1 pa2/an2 pa3/an3 pa4/an4 pa5/an5 pa6/an6 pa7/an7 rst extal xtal v ss v l v lc3 v lc2 v lc1 com0 com1 com2 com3 seg0 pe4/rmc pe3/int3/nmi pe2/int2 pe1/int1 pe0/int0/ec pf7/seg31 pf6/seg30 nc tex tx v dd pf5/seg29 pf4/seg28 pf3/seg27 pf2/seg26 pf1/seg25 pf0/seg24 pd7/seg23 pd6/seg22 pd5/seg21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 70 69 68 67 65 66 71 72 73 74 75 76 77 78 79 80 1 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 pin assignment (top view) CXP83409/83413/83417 (qfp package) note) nc (pin 73) is always connected to v dd .
6 cxp83408/83412/83416, CXP83409/83413/83417 pin description symbol i/o functions i/o/analog input pa0/an0 to pa7/an7 (port a) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) analog inputs to a/d converter. (8 pins) i/o pc0 to pc7 (port c) 8-bit i/o port. i/o can be set in a unit of single bits. capable of driving 12ma sync current. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) i/o/output ph0/pwm1 (port h) 1-bit i/o port. incorporation of pull-up resistor can be set through the software. (1 pin) 8-bit pwm output. input/input/input input/input input/input input/input/input input/input output/output output/output/ output pe0/int0/ec pe1/int1 pe2/int2 pe3/int3/nmi pe4/rmc pe5/pwm0 pe6/to/adj (port e) 7-bit port. lower 5 bits are for inputs; upper 2 bits are for outputs. (7 pins) external interruption request input. (4 pins) remote control receiving circuit input. 14-bit pwm output. rectangular wave output for 8-bit timer/ counter and 32khz oscillation frequency divider output. i/o/input i/o/input i/o/i/o i/o/input i/o/output i/o/i/o i/o/input i/o/output pb0/cs1 pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 (port b) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) chip select input for serial interface (ch1). chip select input for serial interface (ch0). serial clock i/o (ch0). serial data input (ch0). serial data output (ch0). serial clock i/o (ch1). serial data input (ch1). serial data output (ch1). external event inputs for timer/counter. non-maskable intrruption request input.
7 cxp83408/83412/83416, CXP83409/83413/83417 symbol i/o functions output/output pd0/seg16 to pd7/seg23 (port d) 8-bit output port. (8 pins) lcd segment signal output. (16 pins) output/output pf0/seg24 to pf7/seg31 (port f) 8-bit output port. (8 pins) output output output seg0 to seg15 com0 to com3 v lc1 to v lc3 v l input crystal connectors for system clock oscillation. when the clock is supplied externally, input to extal; opposite phase clock should be input to xtal. extal output xtal input crystal connectors for 32khz timer/counter clock generation circuit. for usage as event counter, connect clock oscillation source to tex, and leave tx open. tex output tx input low-level active, system reset. rst nc. under normal operating conditions, connect to v dd . nc positive power supply. v dd gnd. vss lcd segment signal output. lcd common signal output. lcd bias power supply. control pin to cutt off the current flowing to external lcd bias resistor during standby.
8 cxp83408/83412/83416, CXP83409/83413/83417 ip pull-up resistor port b data port b direction 0 when reset rd (port b) data bus ? pull-up transistors approx. 100k ? ? 0 when reset schmitt input cs1 cs0 si0 si1 port b 8 pins hi-z hi-z when reset pa0/an0 to pa7/an7 pb0/cs1 pb1/cs0 pb3/si0 pb6/si1 port b 4 pins 2 pins hi-z pb2/sck0 pb5/sck1 ip pull-up resistor port a data port a direction 0 when reset port a input selection 0 when reset rd (port a) data bus a/d converter ? pull-up resistors approx. 100k ? ? input multiplexer 0 when reset input protection circuit i/o circuit format for pins port a pin circuit format ? pull-up transistors approx. 100k ? pull-up resistor port b data port b direction 0 when reset rd (port b) data bus ip ? 0 when reset schmitt input sck in output enable port b output selection 0 when reset sck out
9 cxp83408/83412/83416, CXP83409/83413/83417 2 pins hi-z hi-z pin when reset circuit format pb4/so0 pb7/so1 pc0 to pc7 8 pins 5 pins hi-z pe0/int0/ec pe1/int1 pe2/int2 pe3/int3/nmi pe4/rmc ip schmitt input int0/ec int1 int2 int3/nmi rmc data bus rd (port e) ip pull-up resistor port c data port c direction 0 when reset rd (port c) data bus ? 1 large current 12ma ? 2 pull-up transistors approx. 100k ? ? 2 0 when reset ? 1 ? pull-up transistors approx. 100k ? pull-up resistor port b data port b direction 0 when reset rd (port b) data bus ip ? 0 when reset output enable port b output selection 0 when reset so port e port c port b
10 cxp83408/83412/83416, CXP83409/83413/83417 1 pin high level with pull-up transistor on resistor when reset high level pin when reset circuit format pe6/to/adj pe5/pwm0 ? 1 ? 2 port e data 1 when reset port e output selection (upper) mpx port e output selection (lower) adj2k adj16k to internal reset signal ? 1 pull-up transistors approx. 150k ?. adj signals are frequency divider outputs for 32khz oscillation frequency adjustment. adj2k provides usage as buzzer output. ? 2 to output enable port e 1 pin hi-z ph0/pwm1 data bus rd (port h) a a ip aa aa aaaa aaaa port h data ? aaaa aaaa port h direction 0 when reset ? pull-up transistors approx. 100k ? aaaa aaaa pull-up resistor aaaa aaaa port h output selection pwm1 0 when reset 0 when reset port h 1 pin port e port e output selection rd (port e) data bus 0 when reset port e data 1 when reset pwm0 ()
11 cxp83408/83412/83416, CXP83409/83413/83417 16 pins v dd level pin when reset circuit format seg0 to seg15 v ch v cl segment output (v dd level) pd0 to pd7 pf0 to pf7 segment data segment driver port/segment output selection 0 when reset port data pd7 to pd4 pd3 to pd0 pf7 to pf0 by a bit unit by 4-bit unit port d port f 4 pins v dd level com0 to com3 v lc1 v lc2 v lc3 v dd common 24 pins segment 1 pin hi-z v l lcd control (dsp bit) 0 when reset
12 cxp83408/83412/83416, CXP83409/83413/83417 2 pins oscillation pin when reset circuit format extal xtal extal xtal ip ip 2 pins oscillation tex tx tex tx ip ip 1 pin low level rst ip schmitt input mask option pull-up resistor aa aa op diagram shows circuit composition during oscillation. feedback resistor is removed during stop, and xtal becomes high level. diagram shows circuit composition during oscillation. when the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed and tex and tx become low level and high level respectively.
13 cxp83408/83412/83416, CXP83409/83413/83417 ? 1 v in and v out must not exceed v dd + 0.3v. ? 2 the large current drive transistor is the n-ch transistor of port c (pc). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. supply voltage lcd bias voltage input voltage output voltage high level output current high level total output current low level total output current operating temperature storage temperature allowable power dissipation v dd v lc1 , v lc2 , v lc3 v in v out i oh i oh i ol i olc i ol topr tstg p d low level output current 0.3 to +7.0 0.3 to +7.0 ? 1 0.3 to +7.0 ? 1 0.3 to +7.0 ? 1 5 50 15 20 100 20 to +75 55 to +150 600 380 380 v v v v ma ma ma ma ma c c mw mw mw output (value per pin) total for all output pins all pins excluding large current output (value per pin) large current outputs (value per pin ? 2 ) total for all output pins qfp-80p-l01 lqfp-80p-l01 qfp-80p-l03 item symbol rating unit remarks absolute maximum ratings (vss = 0v reference)
14 cxp83408/83412/83416, CXP83409/83413/83417 ? 1 value for each pin of normal input ports (pa, pb4, pb7, pc and ph0). ? 2 value of the following pins: rst, cs0, cs1, si0, si1, sck0, sck1, ec/int0, int1, int2, nmi/int3, and rmc. ? 3 specifies only during external clock input. ? 4 optimal values are determined by lcd used. high level input voltage low level input voltage operating temperature supply voltage lcd bias voltage 5.5 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v c v item symbol min. max. unit remarks 4.5 3.5 2.7 2.5 vss 0.7v dd 0.8v dd v dd 0.4 0 0 0.3 20 v lc1 v lc2 v lc3 v ih v ihs v ihex v il v ils v ilex topr during 1/2 and 1/4 frequency division operating modes guaranteed operation range during 1/16 frequency division operating mode or sleep mode quaranteed operation range guaranteed operation range with tex clock guaranteed data hold range during stop lcd power supply range ? 4 ? 1 hysteresis input ? 2 extal ? 3 ? 1 hysteresis input ? 2 extal ? 3 v dd recommended operating conditions (vss = 0v reference)
15 cxp83408/83412/83416, CXP83409/83413/83417 v dd = 4.5v, i oh = 0.5ma v dd = 4.5v, i oh = 1.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v high level output current 4.0 3.5 0.5 0.5 0.1 0.1 1.5 2.78 v v v v v v a a a ma a a a k ? k ? pc pa, pb, pc, pd ? 1 , pe5, pe6, pf, ph0, v l (vo l only) extal tex rst ? 2 item symbol pins conditions min. v dd i dd1 i il i ih i iz i dd2 i dds1 i dds2 i dds3 v oh v ol i ihe i ile i iht i ilt i ilr low level output current input current 3 5 typ. 0.4 0.6 1.5 40 40 10 10 400 45 10 5 15 max. unit dc characteristics electrical characteristics (ta = 20 to +75 c, vss = 0v reference) v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) v dd = 5.5v termin ation of 10mhz and 32khz crystal oscillation supply current ? 4 v dd = 5.5v, v il = 0.4v v dd = 4.5v, v ih = 4.0v v dd = 5.5v, v i = 0, 5.5v v dd = 5v, v lc1 = 3.75v v lc2 = 2.5v v lc3 = 1.25v high-speed mode operation (1/2 frequency divider clock) sleep mode stop mode i/o leakage current r com common output impedance r seg segment output impedance pa to pc ? 3 , ph ? 3 , pe0 to pe4, rst ? 2 com0 to com3 seg0 to seg15 , seg16 to seg31 ? 1 40 100 8 10 30 18 35 1.1 9 ma a ma a a
16 cxp83408/83412/83416, CXP83409/83413/83417 item symbol pins conditions min. pa to pc, pe1 to pe4, extal, tex, rst clock 1mhz 0v for all pins excluding measured pins c in typ. max. unit ? 1 common pins of pd0/seg16 to pd7/seg23, pf0/seg24, pf7/seg31, pd and pf are the case when the common pin is selected as port; seg16 to seg31 is when the common pin is selected as segment output. ? 2 rst specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. ? 3 pa to pc, and ph0 specify the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. (pe0 to pe4 specify the leakage current.) ? 4 when all output pins are left open. input capacity pf 20 10
17 cxp83408/83412/83416, CXP83409/83413/83417 ? 1 t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control registor (clc: 00fe h ). t sys (ns) = 2000/fc (upper two bits = 00 ), 4000/fc (upper two bits = 01 ), 16000/fc (upper two bits = 11 ) extal t xh t xl t cf t cr 0.4v v dd 0.4v 1/fc aaaaa a aaa a aaaaa aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal external clock extal xtal 74hc04 c 1 c 2 aaaa a aa a aaaa 32khz clock applied condition crystal oscillation tex tx c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise and fall time event count input clock pulse width event count input clock rise and fall time system clock frequency event count input clock input pulse width event count input clock rise and fall time f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal extal extal ec ec tex tx tex tex mhz ns ns ns ms khz s ms item symbol pin conditions min. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied condition) fig. 3 fig. 3 1 37.5 t sys + 50 ? 1 10 typ. 32.768 max. 10 200 20 20 (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 2. clock applied conditions fig. 1. clock timing tex ec t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr fig. 3. event count clock timing
18 cxp83408/83412/83416, CXP83409/83413/83417 (2) serial transfer (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item cs0 sck0 (cs1 sck1) delay time cs0 sck0 (cs1 sck1) floating delay time cs0 so0 (cs1 so1) delay time cs0 so0 (cs1 so1) floating delay time cs0 (cs1) high level width sck0 (sck1) cycle time sck0 (sck1) high and low level widths si0 (si1) input setup time (for sck0 (sck1 ) ) si0 (si1) input hold time (for sck0 (sck1 ) ) sck0 so0 (sck1 so1) delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 (sck1) sck0 (sck1) so0 (so1) so0 (so1) cs0 (cs1) sck0 (sck1) sck0 (sck1) si0 (si1) si0 (si1) so0 (so1) input mode output mode input mode output mode sck0 (sck1) input mode sck0 (sck1) output mode sck0 (sck1) input mode sck0 (sck1) output mode sck0 (sck1) input mode sck0 (sck1) output mode ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc 50 100 200 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns t sys + 200 100 max. unit chip select transfer mode (sck0 (sck1) = output mode) chip select transfer mode (sck0 (sck1) = output mode) chip select transfer mode chip select transfer mode chip select transfer mode conditions note 1) t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (clc: 00fe h ). t sys (ns) = 2000/fc (upper two bits = 00 ), 4000/fc (upper two bits = 01 ), 16000/fc (upper two bits = 11 ) note 2) the load condition for the sck0 (sck1) output mode, so0 (so1) output delay time is 50pf + 1ttl.
19 cxp83408/83412/83416, CXP83409/83413/83417 fig. 4. serial transfer ch0 timing cs0 (cs1) sck0 (sck1) 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 (si1) t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0 (so1)
20 cxp83408/83412/83416, CXP83409/83413/83417 conversion time sampling time analog input voltage t conv t samp v ian v zt ? 1 v ft ? 2 an0 to an7 ta = 25 c v dd = 5.0v v ss = 0v linearity error zero transition voltage full-scale transition voltage resolution s s v v dd + 0.3 160/f adc ? 3 12/f adc ? 3 0 item symbol pin conditions min. typ. max. unit bits (3) a/d converter characteristics (ta = 20 to +75 c, v dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = 0v reference) 8 3 lsb 70 mv 5030 10 4970 10 4910 mv fig. 5. definition of a/d converter terms analog input linearity error v ft v zt 00 h 01 h fe h ff h digital conversion value 00 ( = f ex /2) 01 ( = f ex /4) 11 ( = f ex /16) f adc = fc/2 f adc = fc/4 f adc = fc/16 f adc = fc f adc = fc/2 f adc = fc/8 cks pck1, pck0 0 ( /2 selection) 0 ( selection) ? 1 v zt : value atwhich the digital conversion value changes from 00 h to 01 h and vice versa. ? 2 v ft : value at which the digital conversion value changes from fe h to ff h and vice versa. ? 3 f adc indicates the below values due to the contents of bit 6 (ck3) of the a/d control registor (adc: 00f9 h ) and bit 7 (pck1) and bit 6 (pck0) of the clock control resistor (clc: 00fe h ).
21 cxp83408/83412/83416, CXP83409/83413/83417 external interruption high and low level widths reset input low level width int0 int1 int2 nmi/int3 rst 1 32/fc s s item symbol pin conditions min. max. unit t ih t il t rsl (4) interruption, reset input (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) 0.2v dd 0.8v dd t ih t il t il t ih int0 int1 int2 nmi/int3 (nmi is specified only for the falling edge) fig 6. interruption input timing t rsl 0.2v dd rst fig. 7. rst input timing
22 cxp83408/83412/83416, CXP83409/83413/83417 appendix fig. 8. spc700 series recommended oscillation circuit c 1 aaaa a aa a aaaa extal xtal c 2 rd aaaa a aa a aaaa extal xtal rd (i) main clock aaaa a aa a aaaa extal xtal c 1 c 2 rd xtal (ii) main clock aaaa a aa a aaaa extal xtal c 1 c 2 rd aaaa a aa a aaaa tex tx (iii) sub clock manufacturer murata mfg co., ltd. river eletec co., ltd. kinseki ltd. model csa4.19mg csa8.00mg cst4.19mgw ? 1 cst8.00mtw ? 1 hc-49/u03 hc-49/u (-s) fc (mhz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 18 18 30 15 22 30 15 22 0 2.2k 470 560 0 c 1 (pf) c 2 (pf) rd ( ? ) circuit example (i) csa10.0mt (ii) cst10.00mtw ? 1 (i) models with an asterisk ( ? 1 ) have the built-in ground capacitance (c 1 , c 2 ). item content reset pin pull-up resistor non-existent existent mask option table product name package cxp83408/83412/83416 CXP83409/83413/83417 80-pin plastic qfp/lqfp 80-pin plastic qfp (0.65mm pitch) package table
23 cxp83408/83412/83416, CXP83409/83413/83417 (100a) 3 45 6 0.1 5.0 1.0 v dd supply voltage [v] i dd supply current [ma] i dd vs. v dd (fc = 10mhz, ta = 25 c, typical) 7 2 0.05 (50a) 0.01 (10a) 0.5 10.0 20.0 sleep mode 32khz mode (instruction) 32khz sleep mode sleep mode 0 15 10 5 fc system clock [mhz] i dd supply current [ma] i dd vs. fc 5 10 16 20 1/2 dividing mode 1/2 dividing mode (v dd = 5v, ta = 25 c, typical) characteristic curves
24 cxp83408/83412/83416, CXP83409/83413/83417 package outline unit : mm package structure sony code eiaj code jedec code qfp-80p-l01 qfp080-p-1420 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 1.6g 23.9 0.4 20.0 ?0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 ?0.1 + 0.15 14.0 ?0.1 + 0.4 17.9 0.4 16.3 0.1 ?0.05 + 0.2 2.75 ?0.15 + 0.35 0.8 0.2 0.15 ?0.05 + 0.1 80pin qfp (plastic) m 0.2 0.15 0? to 10? detail a a cxp83408/83412/83416 package structure sony code eiaj code jedec code qfp-80p-l01 qfp080-p-1420 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 1.6g 23.9 0.4 20.0 0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 0.1 + 0.15 14.0 0.1 + 0.4 17.9 0.4 16.3 0.1 0.05 + 0.2 2.75 0.15 + 0.35 0.8 0.2 0.15 0.05 + 0.1 80pin qfp (plastic) m 0.2 0.15 0 ? to 10 ? detail a a cxp83408/83412/83416 lead specifications item lead material alloy 42 lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec.
25 cxp83408/83412/83416, CXP83409/83413/83417 package outline unit : mm sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin 42 / copper alloy qfp-80p-l03 p-qfp80-14x14-0.65 0.6g 80pin qfp (plastic) 16.0 0.4 14.0 0.1 + 0.4 b 0 ? to 10 ? 0.5 0.2 0.1 0.1 + 0.15 (15.0) 1.5 0.15 + 0.35 40 21 20 1 41 60 61 80 m 0.24 0.1 0.65 b = 0.3 0.1 ( 0.3 ) (0.127) + 0.15 0.127 0.05 + 0.1 detail a : solder a solder plating CXP83409/83413/83417 lead specifications item lead material alloy 42 lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec. sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin 42 / copper alloy qfp-80p-l03 p-qfp80-14x14-0.65 0.6g 80pin qfp (plastic) 16.0 0.4 14.0 0.1 + 0.4 b 0 ? to 10 ? 0.5 0.2 0.1 0.1 + 0.15 (15.0) 1.5 0.15 + 0.35 40 21 20 1 41 60 61 80 m 0.24 0.1 0.65 b = 0.3 0.1 ( 0.3 ) (0.127) + 0.15 0.127 0.05 + 0.1 detail a : solder a solder plating CXP83409/83413/83417
26 cxp83408/83412/83416, CXP83409/83413/83417 20 21 40 41 60 61 80 1 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy package structure 14.0 0.2 ? 12.0 0.1 (0.22) b a 1.5 0.1 + 0.2 0.5 0.2 (13.0) 80pin lqfp (plastic) 0.5g lqfp-80p-l01 p-lqfp80-12x12-0.5 0.1 note: dimension " ? " does not include mold protrusion. 0.13 m 0.5 b = 0.18 0.03 ( 0.18 ) (0.127) + 0.08 0.127 0.02 + 0.05 detail b : solder detail a 0 ? to 10 ? 0.1 0.1 0.5 0.2 b package outline unit : mm sony corporation cxp83408/83412/83416 20 21 40 41 60 61 80 1 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy package structure 14.0 0.2 ? 12.0 0.1 (0.22) b a 1.5 0.1 + 0.2 0.5 0.2 (13.0) 80pin lqfp (plastic) 0.5g lqfp-80p-l01 p-lqfp80-12x12-0.5 0.1 note: dimension " ? " does not include mold protrusion. 0.13 m 0.5 b = 0.18 0.03 ( 0.18 ) (0.127) + 0.08 0.127 0.02 + 0.05 detail b : solder detail a 0 ? to 10 ? 0.1 0.1 0.5 0.2 b lead specifications item lead material alloy 42 lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec. cxp83408/83412/83416

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