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psoc ? 5lp: cy8c52lp family datasheet programmable system-on-chip (psoc?) cypress semiconductor corporation ? 198 champion court ? san jose, ca 95134-1709 ? 408-943-2600 document number: 001-84933 rev. *e revised may 22, 2014 general description psoc ? 5lp is a true programmable embedded system-on-chip, integrat ing configurable analog and digital peripherals, memory, and a microcontroller on a single chip. the psoc 5lp architecture boosts performance through: ? 32-bit arm cortex-m3 core plus dma controller at up to 80 mhz ? ultra low power with industry's widest voltage range ? programmable digital and analog peripherals enable custom functions ? flexible routing of any analog or digital peripheral function to any pin psoc devices employ a highly configurable system-on-chip architecture for embedded control design. they integrate configurable analog and digital circuits, controlled by an on-chip microcontroller. a single psoc device can integrate as many as 100 digita l and analog peripheral functions, r educing design time, board space, po wer consumption, and system co st while improving system quali ty. features ? operating characteristics ? voltage range: 1.71 to 5.5 v, up to 6 power domains ? temperature range (ambient) ?40 to 85 c [1] ? dc to 80-mhz operation ? power modes ? active mode 3.1 ma at 6 mhz, and 15.4 ma at 48 mhz ? 2-a sleep mode ? 300-na hibernate mode with ram retention ? boost regulator from 0.5-v input up to 5-v output ? performance ? 32-bit arm cortex-m3 cpu, 32 interrupt inputs ? 24-channel direct memory access (dma) controller ? memories ? up to 256 kb program flash, with cache and security features ? up to 32 kb additional flash for error correcting code (ecc) ? up to 64 kb ram ? 2 kb eeprom ? digital peripherals ? four 16-bit timer, counter, and pwm (tcpwm) blocks ? i 2 c, 1 mbps bus speed ? usb 2.0 certified full-speed (fs) 12 mbps ? 20 to 24 universal digital blocks (udb), programmable to create any number of functions: ? 8-, 16-, 24-, and 32-bit timers, counters, and pwms ?i 2 c, uart, spi, i2s, lin 2.0 interfaces ? cyclic redundancy check (crc) ? pseudo random sequence (prs) generators ? quadrature decoders ? gate-level logic functions ? programmable clocking ? 3- to 74-mhz internal oscillator, 2% accuracy at 3 mhz ? 4- to 25-mhz external crystal oscillator ? internal pll clock generation up to 80 mhz ? low-power internal oscillator at 1, 33, and 100 khz ? 32.768-khz external watch crystal oscillator ? 12 clock dividers routable to any peripheral or i/o ? analog peripherals ? 12-bit sar adc ? 8-bit dac ? two comparators ? capsense ? support, up to 62 sensors ? 1.024 v 1% internal voltage reference ? versatile i/o system ? 46 to 72 i/o pins ? up to 62 general-purpose i/os (gpios) ? up to eight performance i/o (sio) pins ? 25 ma current sink ? programmable input threshold and output high voltages ? can act as a general-purpose comparator ? hot swap capability and overvoltage tolerance ? two usbio pins that can be used as gpios ? route any digital or analog peripheral to any gpio ? lcd direct drive from any gpio, up to 46 16 segments ? capsense support from any gpio ? 1.2-v to 5.5-v interface voltag es, up to four power domains ? programming, debug, and trace ? jtag (4-wire), serial wire debug (swd) (2-wire), single wire viewer (swv), and traceport (5-wire) interfaces ? arm debug and trace modules embedded in the cpu core ? bootloader programming through i 2 c, spi, uart, usb, and other interfaces ? package options: 68-pin qfn and 100-pin tqfp ? development support with free psoc creator? tool ? schematic and firmware design support ? over 100 psoc components? integrate multiple ics and system interfaces into on e psoc. components are free embedded ics represented by icons. drag and drop component icons to design systems in psoc creator. ? includes free gcc compiler, supports keil/arm mdk compiler ? supports device programming and debugging note 1. the maximum storage temperature is 150 c in compliance with jedec standard jesd22-a103, high temperature storage life.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 2 of 109 more information cypress provides a wealth of data at www.cypress.com to help you to select the right psoc device for your design, and to help you to quickly and effectively integrate the device into your design. for a comprehensive list of resources, see the knowledge base article kba86521, how to design with psoc 3, psoc 4, and psoc 5lp . following is an abbreviated list for psoc 5lp: ? overview: psoc portfolio , psoc roadmap ? product selectors: psoc 1 , psoc 3 , psoc 4 , psoc 5lp in addition, psoc creator includes a device selection tool. ? application notes: cypress offers a large number of psoc application notes covering a bro ad range of topics, from basic to advanced level. recommended application notes for getting started with psoc 5lp are: ? an77759 : getting started with psoc 5lp ? an77835 : psoc 3 to psoc 5lp migration guide ? an61290: hardware design considerations ? an57821: mixed signal circuit board layout ? an58304 : pin selection for analog designs ? an81623: digital design best practices ? an73854: introduction to bootloaders ? development kits: ? cy8ckit-001 provides a common development platform for any one of the psoc 1, psoc 3, psoc 4, or psoc 5lp families of devices. ? cy8ckit-050 is designed for analog performance. it enables you to evaluate, develop and prototype high precision analog, low-power and low-voltage applications powered by psoc 5lp. both kits support the psoc expansion board kit ecosystem. expansion kits are available for a number of applications including capsense, precision temperature measurement, and power supervision. the miniprog3 device provides an interface for flash programming and debug. psoc creator psoc creator is a free windows-based integrated design environment (i de). it enables concurrent hardware and firmware design of psoc 3, psoc 4, and psoc 5lp based systems. create designs usin g classic, familiar schematic capture supported by over 100 pre-verified, production-ready psoc components; see the list of component datasheets . with psoc creator, you can: 1. drag and drop component icons to build your hardware system design in the main design workspace 2. codesign your application firm ware with the psoc hardware, using the psoc creator ide c compiler 3. configure components using the configuration tools 4. explore the library of 100+ components 5. review component datasheets figure 1. multiple-sensor example project in psoc creator
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 3 of 109 contents 1. architectural overview ..................................................4 2. pinouts ............................................................................6 3. pin descriptions ...........................................................10 4. cpu ................................................................................11 4.1 arm cortex-m3 cpu ...........................................11 4.2 cache controller ..................................................12 4.3 dma and phub ...................................................12 4.4 interrupt controller ...............................................15 5. memory ..........................................................................17 5.1 static ram ...........................................................17 5.2 flash program memory ........................................17 5.3 flash security .......................................................17 5.4 eeprom ...... ............... ........... ........... ........... ........17 5.5 nonvolatile latches (nvls) ..................................18 5.6 external memory interface ...................................19 5.7 memory map ........................................................20 6. system integration .......................................................21 6.1 clocking system ...................................................21 6.2 power system ......................................................24 6.3 reset ....................................................................27 6.4 i/o system and routing .......................................28 7. digital subsystem ........................................................35 7.1 example peripherals ............................................35 7.2 universal digital block ..........................................37 7.3 udb array description ..... ....................................40 7.4 dsi routing interface descr iption ........................40 7.5 usb ......................................................................42 7.6 timers, counters, and pwms ..............................42 7.7 i 2 c ........................................................................43 8. analog subsystem .......................................................44 8.1 analog routing .....................................................45 8.2 successive approximation adc ...........................47 8.3 comparators .........................................................47 8.4 lcd direct drive ..................................................48 8.5 capsense .............................................................49 8.6 temp sensor ........................................................49 8.7 dac ......................................................................49 9. programming, debug interfaces, resources .............50 9.1 jtag interface .....................................................51 9.2 swd interface ......................................................52 9.3 debug features ....................................................53 9.4 trace features .....................................................53 9.5 swv and traceport interfaces ......................53 9.6 programming features .........................................53 9.7 device security ............ ........................................53 10. development support ................................................54 10.1 documentation .............. .....................................54 10.2 online .................................................................54 10.3 tools ...................................................................54 11. electrical specifications ............................................55 11.1 absolute maximum rating s ................................55 11.2 device level specificatio ns ................................56 11.3 power regulators ...............................................59 11.4 inputs and outputs .............................................62 11.5 analog peripherals ........ .....................................69 11.6 digital peripherals ..............................................83 11.7 memory ..............................................................87 11.8 psoc system resources ...................................91 11.9 clocking ......................... .....................................94 12. ordering information ..................................................98 12.1 part numbering conventions .............................99 13. packaging .... .............. .............. ............... .............. .....100 14. acronyms ..................................................................102 15. reference documents .......... ....................................103 16. document conventions ...........................................104 16.1 units of measure ..............................................104 appendix: csp package summary............................... 105 17. revision history .......................................................108 18. sales, solutions, and legal information ................109
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 4 of 109 1. architectural overview introducing the cy8c52lp family of ultra low power, flash programm able system-on-chip (psoc) devices, part of a scalable 8-bit psoc 3 and 32-bit psoc 5lp platform. the cy8c52lp family provides configurable blocks of analog, digital, a nd interconnect circu itry around a cpu subsystem. the comb ination of a cpu with a flexible analog subsystem, digital sub system, routing, and i/o enables a high level of integration in a wide variety of consumer, industrial, and medical applications. figure 1-1. simplified block diagram figure 1-1 illustrates the major components of the cy8c52lp family. they are: ? arm cortex-m3 cpu subsystem ? nonvolatile subsystem ? programming, debug, and test subsystem ? inputs and outputs ? clocking ? power ? digital subsystem ? analog subsystem psoc?s digital subsystem pr ovides half of its unique configurability. it connects a digital signal from any peripheral to any pin through the digital system interconnect (dsi). it also provides functional flexibility through an array of small, fast, low power udbs. psoc creator provides a library of pre-built and tested standard digital peripher als (uart, spi, lin, prs, crc, timer, counter, pwm, and, or, and so on) that are mapped to the udb array. you can also easily create a digital circuit using boolean primitives by means of graphical design entry. each udb contains programmable array logic (pal)/programmable logic device (pld) functionality, together with a small state machine engine to support a wide variety of peripherals. analog system lcd direct drive capsense temperature sensor adc 2 x cmp + - system wide resources program debug & trace boundary scan program & debug cortex m3 cpu interrupt controller phub dma cache controller sram flash eeprom emif cpu system memory system system bus digital interconnect analog interconnect 1.71 to 5.5 v 0. 5 to 5.5 v ( optional ) 425mhz ( optional ) xtal osc 32.768 khz ( optional ) rtc timer imo clock tree wdt and wake ilo clocking system 1.8 v ldo smp por and lvd sleep power power management system usb phy gpios gpios gpios gpios gpios gpios sio gpios sios sar adc i2c master/ slave universal digital block array (24 x udb) 4 x timer counter pwm fs usb 2.0 digital system udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb uart logic 12- bit pwm i2c slave 8- bit spi 12- bit spi logic 8- bit timer 16- bit prs udb 8- bit timer quadrature decoder 16- bit pwm sequencer usage example for udb udb udb udb udb udb udb udb udb dac 22 to
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 5 of 109 in addition to the flexibility of the udb array, psoc also provides configurable digital blocks targeted at specific functions. for the cy8c52lp family these blocks can include four 16-bit timers, counters, and pwm blocks; i 2 c slave, master, and multimaster; full-speed usb. for more details on the peripherals see the ?example peripherals? section on page 35 of this datasheet. for information on udbs, dsi, and other digital blocks, see the ?digital subsystem? section on page 35 of this datasheet. psoc?s analog subsystem is the second half of its unique configurability. all analog performance is based on a highly accurate absolute voltage reference with less than 1% error over temperature and voltage. the configurable a nalog subsystem includes: ? analog muxes ? comparators ? voltage references ? adc ? dac all gpio pins can route analog signals into and out of the device using the internal analog bus. this allows the device to interface up to 62 discrete analog signals. the cy8c52lp family offers a sar adc. featuring 12-bit conversions at up to 1 m samples per second, it also offers low nonlinearity and offset errors and snr better than 70 db. it is well suited for a variety of higher speed analog applications. a high-speed voltage or current dac supports 8-bit output signals at an update rate of 8 msps in idac and 1 msps in vdac. it can be routed out of any gpio pin. you can create higher resolution voltage pwm dac outputs using the udb array. this can be used to create a pulse width modulated (pwm) dac of up to 10 bits, at up to 48 khz. the digital dacs in each udb support pwm, prs, or delta-sigma algorithms with programmable widths. in addition to the adc and dac, the analog subsystem provides multiple comparators. see the ?analog subsystem? section on page 44 of this datasheet for more details. psoc?s cpu subsystem is built around a 32-bit three-stage pipelined arm cortex-m3 processor running at up to 80 mhz. the cortex-m3 includes a tight ly integrated nested vectored interrupt controller (nvic) and various debug and trace modules. the overall cpu subsystem incl udes a dma controller, flash cache, and ram. the nvic provides low latency, nested interrupts, and tail-chaining of interrupts and other features to increase the efficiency of interrupt handling. the dma controller enables peripherals to exchange data without cpu involvement. this allows the cpu to run slower (saving power) or use those cpu cycles to improve the performance of firmware algorithms. the flash cache also reduces system power consumption by allowing less frequent flash access. psoc?s nonvolatile subsystem consists of flash, byte-writeable eeprom, and nonvolatile configuration options. it provides up to 256 kb of on-chip flash. the cpu can reprogram individual blocks of flash, enabling boot loaders. you can enable an ecc for high-reliability applications. a powerful and flexible protection model secures your sensitive information, allowing selective memory block locking for read and write protection. two kb of byte-writable eeprom is availabl e on-chip to store application data. additionally, selected configuration options such as boot speed and pin drive mode are stored in nonvolatile memory. this allows settings to activate immediately after power-on reset (por). the three types of psoc i/o are ex tremely flexible. all i/os have many drive modes that are set at por. psoc also provides up to four i/o voltage domains thro ugh the vddio pins. every gpio has analog i/o, lcd drive, capsense, flexible interrupt generation, slew rate control, and digital i/o capability. the sios on psoc allow v oh to be set independently of vddio when used as outputs. when sios are in input mode they are high impedance. this is true even w hen the device is not powered or when the pin voltage goes above the supply voltage. this makes the sio ideally suited for use on an i 2 c bus where the psoc may not be powered when other devices on the bus are. the sio pins also have high current sink capability for applications such as led drives. the programmable input threshold feature of the sio can be used to make the sio function as a general purpose analog comparator. for devices with full-speed usb, the usb physical interface is also provided (usbio). when not using usb these pins may also be used for limited digital functionality and device programming. all the features of the psoc i/os are covered in detail in the ?i/o system and routing? section on page 28 of this datasheet. the psoc device incorporates flexible internal clock generators, designed for high stability and factory trimmed for high accuracy. the internal main oscillator (imo ) is the master clock base for the system and has 2% accuracy at 3 mhz. the imo can be configured to run from 3 mhz up to 74 mhz. multiple clock derivatives can be generated from the main clock frequency to meet application needs. the device provides a pll to generate system clock frequencies up to 80 mhz from the imo, external crystal, or external reference cloc k. it also contains a separate, very low-power internal low-speed oscillator (ilo) for the sleep and watchdog timers. a 32.768-khz external watch crystal is also supported for use in rtc a pplications. the clocks, together with programmable clock dividers, provide the flexibility to integrate most timing requirements. the cy8c52lp family supports a wide supply operating range from 1.71 to 5.5 v. this allows operation from regulated supplies such as 1.8 5%, 2.5 v 10%, 3.3 v 10%, or 5.0 v 10%, or directly from a wide range of battery types. in addition, it provides an integrated high-efficiency synchronous boost converter that can power the device from supply voltages as low as 0.5 v. this enables the device to be powered directly from a single battery. in addition, you can use the bo ost converter to generate other voltages required by the device, such as a 3.3 v supply for lcd glass drive. the boost?s output is available on the v boost pin, allowing other devices in the application to be powered from the psoc. psoc supports a wide range of low-power modes. these include a 300 na hibernate mode with ram retention and a 2-a sleep mode with rtc. in the second mode the optional 32.768-khz watch crystal runs continuously and maintains an accurate rtc. power to all major f unctional blocks, incl uding the programmable digital and analog peripherals, can be controlled independently by firmware. this allows low-power background processing when some peripherals are not in use. this, in turn, provides a total device current of only 3.1 ma when the cpu is running at 6mhz.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 6 of 109 the details of the psoc power modes are covered in the ?power system? section on page 24 of this datasheet. psoc uses jtag (4-wire) or swd (2-wire) interfaces for programming, debug, and test. using these standard interfaces you can debug or program the pso c with a variety of hardware solutions from cypress or third party vendors. the cortex-m3 debug and trace modules include fpb, dwt, etm, and itm. these modules have many features to help solve difficult debug and trace problems. details of the programming, test, and debugging interfaces are discussed in the ?programming, debug interfaces, resources? section on page 50 of this datasheet. 2. pinouts each vddio pin powers a specific set of i/o pins. (the usbios are powered from vddd.) using the vddio pins, a single psoc can support multiple voltage levels, reducing the need for off-chip level shifters. the black lines drawn on the pinout diagrams in figure 2-3 and figure 2-4 show the pins that are powered by each vddio. each vddio may source up to 100 ma total to its associated i/o pins, as shown in figure 2-1 . figure 2-1. vddio current limit conversely, for the 100-pin and 68-pin devices, the set of i/o pins associated with any vddio ma y sink up to 100 ma total, as shown in figure 2-2 . figure 2-2. i/o pins current limit psoc v ddio x i ddio x = 100 ma i/o pins psoc v ddio x ipins = 100 ma i/o pins v ssd
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 7 of 109 figure 2-3. 68-pin qfn part pinout [3] (tracedata2] , gpio) p2[6] (tracedata3] , gpio) p2[7] (i2c0 : scl, sio) p12[4] (i2c0 : sda, sio) p12[5] vssb ind vboost vbat vssd xres ( tms, swdio, gpio) p1[0] ( tck, swdck, gpio) p1[1] (configurable xres, gpio) p1[2] ( tdo, swv, gpio) p1[3] (tdi, gpio) p1[4] ( ntrst, gpio) p1[5] vddio1 (gpio) p1[6] vccd (gpio) p3[3] (gpio) p1[7] (sio) p12[6] (sio) p12[7] (usbio, d+, swdio) p15[6] (usbio, d-, swdck) p15[7] vddd vssd (mhz xtal: xo, gpio) p15[0] (mhz xtal: xi, gpio) p15[1] (gpio) p3[0] (gpio) p3[1] (extref 1 , g p i o ) p 3 [ 2 ] (gpio) p3[4] (gpio) p3[5] p0[3 ] (gpio, extref 0) p0[2] ( gpio) p0[1] ( gpio) p0[0] ( gpio) p12[3] (sio) p12[2] (sio) vssd vdda vssa vcca p15[3] ( gpio, khz xtal : xi) p15[2] ( gpio, khz xtal : xo) p12[1] (sio, i2c1 : sda) p12[0] (sio, 12c1 : scl) p3[7] ( gpio) p3[6] ( gpio) vddio3 p2[5] (gpio, tracedata[1]) vddio2 p2[4] (gpio, tracedata[0]) p2[3] (gpio, traceclk) p2[2] (gpio) p2[1] (gpio) p2[0] (gpio) p15[5] (gpoi) p15[4] (gpio) vddd vssd vccd p0[7] (gpio) p0[6] (gpio, idac0) p0[5] (gpio) p0[4] (gpio) vddio0 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 qfn (top view ) lines show vddio to i/o supply association [4] [4] notes 2. pins are do not use (dnu) on devices without usb. the pin must be left floating. 3. the center pad on the qfn package should be connected to digi tal ground (vssd) for best mechanical, thermal, and electrical p erformance. if not connected to ground, it should be electrically float ed and not connected to any other signal. 4. pins are do not use (dnu) on devices without usb. the pin must be left floating.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 8 of 109 figure 2-4. 100-pin tqfp part pinout figure 2-5 and figure 2-6 show an example schematic and an example pcb lay out, for the 100-pin tqfp part, for optimal analog performance on a 2-layer board. ? the two pins labeled vddd must be connected together. ? the two pins labeled vccd must be connected together, with capacitance added, as shown in figure 2-5 and power system on page 24. the trace between the two vccd pins should be as short as possible. ? the two pins labeled vssd must be connected together. for information on circuit board layout issues for mixed signals, refer to the application note an57821 - mixed signal circuit board layout considerations for psoc? 3 and psoc 5. tqfp (tracedata[1], gpio) p2[5] (tracedata[2], gpio) p2[6] (tracedata[3], gpio) p2[7] (i2c0: scl, sio) p12[4] (i2c0: sda, sio) p12[5] (gpio) p6[4] (gpio) p6[5] (gpio) p6[6] (gpio) p6[7] vssb ind vboost vbat vssd xres (gpio) p5[0] (gpio) p5[1] (gpio) p5[2] (gpio) p5[3] (tms, swdio, gpio) p1[0] (tck, swdck, gpio) p1[1] (configurable xres, gpio) p1[2] (tdo, swv, gpio) p1[3] (tdi, gpio) p1[4] (ntrst, gpio) p1[5] vddio1 (gpio) p5[7] nc (opamp3-/extref1, gpio) p3[2] (gpio) p1[6] (gpio) p1[7] (sio) p12[6] (sio) p12[7] (gpio) p5[4] (gpio) p5[5] (gpio) p5[6] (usbio, d+, swdio) p15[6] (usbio, d-, swdck) p15[7] vddd vssd vccd nc (mhz xtal: xo, gpio) p15[0] (mhz xtal: xi, gpio) p15[1] (idac1, gpio) p3[0] (idac3, gpio) p3[1] (opamp3+, gpio) p3[3] (opamp1-, gpio) p3[4] (opamp1+, gpio) p3[5] vddio3 vddio0 p0[3] (gpio, opamp0-/extref0) p0[2] (gpio, opamp0+/sar1 extref) p0[1] (gpio, opamp0out) p0[0] (gpio, opamp2out) p4[1] (gpio) p4[0] (gpio) p12[3] (sio) p12[2] (sio) vssd vdda vssa vcca nc nc nc nc nc nc p15[3] (gpio, khz xtal: xi) p15[2] (gpio, khz xtal: xo) p12[1] (sio, i2c1: sda) p12[0] (sio, i2c1: scl) p3[7] (gpio, opamp3out) p3[6] (gpio, opamp1out) vddio2 p2[4] (gpio, tracedata[0]) p2[3] (gpio, traceclk) p2[2] (gpio) p2[1] (gpio) p2[0] (gpio) p15[5] (gpio) p15[4] (gpio) p6[3] (gpio) p6[2] (gpio) p6[1] (gpio) p6[0] (gpio) vddd vssd vccd p4[7] (gpio) p4[6] (gpio) p4[5] (gpio) p4[4] (gpio) p4[3] (gpio) p4[2] (gpio) p0[7] (gpio, idac2) p0[6] (gpio, idac0) p0[5] (gpio, opamp2-) p0[4] (gpio, opamp2+/sar0 extref) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 49 lines show vddio to i/o supply association [5] [5] note 5. pins are do not use (dnu) on devices without usb. the pin must be left floating.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 9 of 109 figure 2-5. example schematic for 100-pin tqfp part with power connections note the two vccd pins must be connected together with as short a trace as possible. a trace under the device is recommended, as shown in figure 2-6 . figure 2-6. example pcb layout for 100-pin tqfp part for optimal analog performance vssb 10 ind 11 vboost 12 vbat 13 vssd 14 xres 15 vddd 37 vssd 38 vccd 39 vcca 63 vssa 64 vdda 65 vssd 66 vccd 86 vssd 87 vddd 88 sio, p12[2] 67 sio, p12[3] 68 p4[0] 69 p4[1] 70 oa2out, p0[0] 71 oa0out, p0[1] 72 oa0+, sar1ref, p0[2] 73 oa0-, ref0, p0[3] 74 vddio0 75 oa2+, sar0ref, p0[4] 76 oa2-, p0[5] 77 idac0, p0[6] 78 idac2, p0[7] 79 p4[2] 80 p4[3] 81 p4[4] 82 p4[5] 83 p4[6] 84 p4[7] 85 p5[0] 16 p5[1] 17 p5[2] 18 p5[3] 19 p1[0], swdio, tms 20 p1[1], swdck, tck 21 p1[2] 22 p1[3], swv, tdo 23 p1[4], tdi 24 p1[5], ntrst 25 vddio1 26 p1[6] 27 p1[7] 28 p12[6], sio 29 p12[7], sio 30 p5[4] 31 p5[5] 32 p5[6] 33 p5[7] 34 usb d+, p15[6] 35 usb d-, p15[7] 36 p6[7] 9 p6[0] 89 p6[1] 90 p6[2] 91 p6[3] 92 p15[4] 93 p15[5] 94 p2[0] 95 p2[1] 96 p2[2] 97 p2[3] 98 p2[4] 99 vddio2 100 p2[5] 1 p2[6] 2 p2[7] 3 p12[4], sio 4 p12[5], sio 5 p6[4] 6 p6[5] 7 p6[6] 8 nc 40 nc 41 p15[0], mhzxout 42 p15[1], mhzxin 43 p3[0], idac1 44 p3[1], idac3 45 p3[2], oa3-, ref1 46 p3[3], oa3+ 47 p3[4], oa1- 48 p3[5], oa1+ 49 vddio3 50 oa1out, p3[6] 51 oa3out, p3[7] 52 sio, p12[0] 53 sio, p12[1] 54 khzxout, p15[2] 55 khzxin, p15[3] 56 nc 57 nc 58 nc 59 nc 60 nc 61 nc 62 vssd vdda vcca vccd vssd vddd vssd vddd vddd vssd vssa vssa vssd vssd vssd vssd 0.1 uf c8 vssd vddd vddd vddd vddd vddd vssd 1 uf c9 0.1 uf c10 0.1 uf c11 0.1 uf c16 0.1 uf c12 0.1 uf c6 0.1 uf c2 1 uf c15 1 uf c1 vssd vddd vssd vdda vssd vccd 1 uf c17 vssa vdda vddd vssd vdda vssa vssd plane vssa plane
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 10 of 109 3. pin descriptions idac0. low resistance output pin for high idac. extref0, extref1. external reference input to the analog system. sar0 extref, sar1 extref. external references for sar adcs gpio. general purpose i/o pin provides interfaces to the cpu, digital peripherals, analog peripherals, interrupts, lcd segment drive, and capsense [6] . i2c0: scl, i2c1: scl. i 2 c scl line providing wake from sleep on an address match. any i/o pin can be used for i 2 c scl if wake from sleep is not required. i2c0: sda, i2c1: sda. i 2 c sda line providing wake from sleep on an address match. any i/o pin can be used for i 2 c sda if wake from sleep is not required. ind. inductor connection to boost pump. khz xtal: xo, khz xtal: xi. 32.768-khz crystal oscillator pin. mhz xtal: xo, mhz xtal: xi. 4 to 25-mhz crystal oscillator pin. ntrst. optional jtag test reset programming and debug port connection to reset the jtag connection. sio. special i/o provides interfaces to the cpu, digital peripherals and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. swdck. serial wire debug clock programming and debug port connection. swdio. serial wire debug input and output programming and debug port connection. tck. jtag test clock programming and debug port connection. tdi. jtag test data in programming and debug port connection. tdo. jtag test data out programming and debug port connection. tms. jtag test mode select programming and debug port connection. traceclk. cortex-m3 traceport connection, clocks tracedata pins. tracedata[3:0]. cortex-m3 traceport connections, output data. swv. single wire viewer output. usbio, d+. provides d+ connection directly to a usb 2.0 bus. may be used as a digital i/o pin; it is powered from vddd instead of from a v ddio . pins are do not use (dnu) on devices without usb. usbio, d-. provides d- connection directly to a usb 2.0 bus. may be used as a digital i/o pin; it is powered from v ddd instead of from a v ddio . pins are do not use (dnu) on devices without usb. vboost. power sense connection to boost pump. vbat. battery supply to boost pump. vcca. output of the analog core regulator or the input to the analog core. requires a 1uf ca pacitor to vssa. the regulator output is not designed to drive external circuits. note that if you use the device with an external core regulator (externally regulated mode), the voltage applied to this pin must not exceed the allowabl e range of 1.71 v to 1.89 v. when using the internal core regulator, (internally regulated mode, the default), do not tie any power to this pin. for details see ?power system? section on page 24. vccd. output of the digital core regulator or th e input to the digital core. the two vccd pins must be shorted together, with the trace between them as short as possible, and a 1uf capacitor to vssd. the regulator output is not designed to drive external circuits. note that if you use the device with an external core regulator (externally regulated mode), the voltage applied to this pin must not exceed the allowable range of 1.71 v to 1.89 v. when using the internal core regulator (internally regulated mode, the default), do not tie any power to this pin. for details see ?power system? section on page 24. vdda. supply for all analog peripherals and analog core regulator. vdda must be the highest voltage present on the device. all other supply pins must be less than or equal to vdda. vddd. supply for all digital peripherals and digital core regulator. vddd must be less than or equal to vdda. vssa. ground for all analog peripherals. vssb. ground connection for boost pump. vssd. ground for all digital logic and i/o pins. vddio0, vddio1, vddio2, vddio3. supply for i/o pins. each vddio must be tied to a valid operating voltage (1.71 v to 5.5 v), and must be less than or equal to vdda. xres (and configurable xres ). external reset pin. active low with internal pull-up. pin p1[2] may be configured to be a xres pin; see ?nonvolatile latches (nvls)? on page 18. notes 6. gpios with opamp outputs are not recommended for use with capsense.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 11 of 109 4. cpu 4.1 arm cortex-m3 cpu the cy8c52lp family of devices has an arm cortex-m3 cpu core . the cortex-m3 is a low power 32-bit three-stage pipelined harvard architecture cpu that delivers 1.25 dmips/mhz. it is intended for deeply embedded applications that require fast interr upt handling features. figure 4-1. arm cortex-m3 block diagram the cortex-m3 cpu subsystem includes these features: ? arm cortex-m3 cpu ? programmable nested vectored interrupt controller (nvic), tightly integrated with the cpu core ? full-featured debug and trace mo dules, tightly integrated with the cpu core ? up to 256 kb of flash memory, 2 kb of eeprom, and 64 kb of sram ? cache controller ? peripheral hub (phub) ? dma controller ? external memory interface (emif) 4.1.1 cortex-m3 features the cortex-m3 cpu features include: ? 4-gb address space. predefined address regions for code, data, and peripherals. multiple buses for efficient and simultaneous accesses of instructions, data, and peripherals. ? the thumb ? -2 instruction set, which offers arm-level performance at thumb-level code d ensity. this includes 16-bit and 32-bit instructions. advanced instructions include: ? bit-field control ? hardware multiply and divide ? saturation ? if-then ? wait for events and interrupts ? exclusive access and barrier ? special register access the cortex-m3 does not su pport arm instructions. nested vectored interrupt controller (nvic) debug block (serial and jtag) embedded trace module (etm) trace port interface unit (tpiu) interrupt inputs jtag/swd trace pins: 5 for traceport or 1 for swv mode cortex m3 cpu core i- bus s- bus d- bus 256 kb ecc flash 1 kb cache 32 kb sram dma ahb bridge & bus matrix phub gpio & emif prog. digital prog. analog special functions peripherals ahb spokes ahb ahb ahb bus matrix cortex m3 wrapper c- bus data watchpoint and trace (dwt) instrumentation trace module (itm) flash patch and breakpoint (fpb) bus matrix 32 kb sram bus matrix
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 12 of 109 ? bit-band support for the sram region. atomic bit-level write and read operations for sram addresses. ? unaligned data storage and access. contiguous storage of data of different byte lengths. ? operation at two privilege levels (privileged and user) and in two modes (thread and handler). some instructions can only be executed at the privileged level. there are also two stack pointers: main (msp) and pr ocess (psp). these features support a multitasking operating system running one or more user-level processes. ? extensive interrupt and system exception support. 4.1.2 cortex-m3 operating modes the cortex-m3 operates at either the privileged level or the user level, and in either the thread mode or the handler mode. because the handler mode is only enabled at the privileged level, there are actually only three states, as shown in table 4-1 . at the user level, access to certai n instructions, special registers, configuration registers, and debugging components is blocked. attempts to access them cause a fault exception. at the privileged level, access to all instructions and registers is allowed. the processor runs in the handler mode (always at the privileged level) when handling an exception, and in the thread mode when not. 4.1.3 cpu registers the cortex-m3 cpu registers are listed in ta b l e 4 - 2 . registers r0-r15 are all 32 bits wide. 4.2 cache controller the cy8c52lp family has a 1 kb, 4-way set-associative cache between the cpu and the flash memory. this improves instruction execution rate and reduces system power consumption by requiring less frequent flash access. 4.3 dma and phub the phub and the dma controller are responsible for data transfer between the cpu and peripherals, and also data transfers between peripherals. the phub and dma also control device configuration during boot. the phub consists of: ? a central hub that includes the dma controller, arbiter, and router table 4-1. operational level condition privileged user running an exception handler mode not used running main program thread mode thread mode table 4-2. cortex m3 cpu registers register description r0-r12 general purpose registers r0-r12 have no special architecturally defined uses. most instructions that spec ify a general purpose register spec ify r0-r12. ? low registers: registers r0-r7 are accessible by all instructions that specify a general purpose register. ? high registers: registers r8-r12 are accessible by all 32-bit instructions that specify a general purpose register; they are not accessible by all 16-bit instructions. r13 r13 is the stack pointer register. it is a banked register that switches between two 32-bit stack pointers: the main stack pointer (msp) and the process stack pointer (psp). the psp is used only when the cpu operates at the user level in thread mode. the msp is used in all other privilege levels and modes. bits[0:1] of the sp are ignored and considered to be 0, so the sp is always aligned to a word (4 byte) boundary. r14 r14 is the link register (lr). the lr stores the return address when a subroutine is called. r15 r15 is the program counter (pc). bit 0 of the pc is ignored and considered to be 0, so instructions are always aligned to a half word (2 byte) boundary. xpsr the program status registers are divided into three status registers, which are accessed either together or separately: ? application program st atus register (apsr) holds program execution status bits such as zero, carry, negative, in bits[27:31]. ? interrupt program status register (ipsr) holds the current exception number in bits[0:8]. ? execution program stat us register (epsr) holds control bits for interrupt continuable and if-then instructions in bits[10:15] and [25:26]. bit 24 is alwa ys set to 1 to indicate thumb mode. trying to clear it causes a fault exception. primask a 1-bit interrupt ma sk register. when set, it allows only the nonmaskable interrupt (nmi) and hard fault exception. all other exceptions and interrupts are masked. faultmask a 1-bit interrupt mask register. when set, it allows only the nmi. all other exceptions and interrupts are masked. basepri a register of up to nine bits th at define the masking priority level. when set, it disables all interrupts of the same or higher priority value. if set to 0 then the masking function is disabled. control a 2-bit register for controlling the operating mode. bit 0: 0 = privileged level in thread mode, 1 = user level in thread mode. bit 1: 0 = default stack (msp) is used, 1 = alternate stack is used. if in thread mode or user level then the alternate stack is the psp. there is no alternate stack for handler mode; the bit must be 0 while in handler mode. table 4-2. cortex m3 cpu registers (continued) register description
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 13 of 109 ? multiple spokes that radiate outward from the hub to most peripherals there are two phub masters: the cpu and the dma controller. both masters may initiate transactions on the bus. the dma channels can handle peripheral communication without cpu intervention. the arbiter in t he central hub determines which dma channel is the highest priority if there are multiple requests. 4.3.1 phub features ? cpu and dma controller are both bus masters to the phub ? eight multi-layer ahb bus parallel access paths (spokes) for peripheral access ? simultaneous cpu and dma access to peripherals located on different spokes ? simultaneous dma source and destination burst transactions on different spokes ? supports 8-, 16-, 24-, and 32-bit addressing and data 4.3.2 dma features ? 24 dma channels ? each channel has one or more transaction descriptors (tds) to configure channel behavior. up to 128 total tds can be defined ? tds can be dynamically updated ? eight levels of priority per channel ? any digitally routable signal, the cpu, or another dma channel, can trigger a transaction ? each channel can generate up to two interrupts per transfer ? transactions can be stalled or canceled ? supports transaction size of infinite or 1 to 64 k bytes ? large transactions may be broken into smaller bursts of 1 to 127 bytes ? tds may be nested and/or chained for complex transactions 4.3.3 priority levels the cpu always has higher priority than the dma controller when their accesses require the same bus resources. due to the system architecture, the cpu ca n never starve the dma. dma channels of higher priority (lower priority number) may interrupt current dma transfers. in the case of an interrupt, the current transfer is allowed to complete its current transaction. to ensure latency limits when multiple dma accesses are requested simultaneously, a fairness algor ithm guarantees an interleaved minimum percentage of bus bandwidth for priority levels 2 through 7. priority levels 0 and 1 do not take part in the fairness algorithm and may use 100% of the bus bandwidth. if a tie occurs on two dma requests of the same priority level, a simple round robin method is used to evenly share the allocated bandwidth. the round robin allocation can be disabled for each dma channel, allowing it to always be at the head of the line. priority levels 2 to 7 are guaranteed the minimum bus bandwidth shown in table 4-4 after the cpu and dma priority levels 0 and 1 have satisfied their requirements. when the fairness algorithm is disabled, dma access is granted based solely on the priority level; no bus bandwidth guarantees are made. 4.3.4 transaction modes supported the flexible configuration of each dma channel and the ability to chain multiple channels allow the creation of both simple and complex use cases. general use cases include, but are not limited to: 4.3.4.1 simple dma in a simple dma case, a single td transfers data between a source and sink (peripherals or memory location). the basic timing diagrams of dma read and write cycles are shown in figure 4-2 . for more description on ot her transfer modes, refer to the technical reference manual. table 4-3. phub spokes and peripherals phub spokes peripherals 0 sram 1 ios , picu , emif 2 phub local configuration, power manager , clocks , ic , swv , eeprom , flash programming interface 3 analog interface and trim , decimator 4 usb , i 2 c , timers, counters, and pwms 5 reserved 6 udbs group 1 7 udbs group 2 table 4-4. priority levels priority level % bus bandwidth 0100.0 1 100.0 2 50.0 3 25.0 4 12.5 56.2 63.1 71.5
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 14 of 109 figure 4-2. dma timing diagram. 4.3.4.2 auto repeat dma auto repeat dma is typically used when a static pattern is repetitively read from system memo ry and written to a peripheral. this is done with a single td that chains to itself. 4.3.4.3 ping pong dma a ping pong dma case uses double buffering to allow one buffer to be filled by one client while an other client is consuming the data previously received in the other buffer. in its simplest form, this is done by chaining two tds together so that each td calls the opposite td when complete. 4.3.4.4 circular dma circular dma is similar to ping pong dma except it contains more than two buffers. in this case there are multiple tds; after the last td is complete it chai ns back to the first td. 4.3.4.5 indexed dma in an indexed dma case, an external master requires access to locations on the system bus as if those locations were shared memory. as an example, a peripheral may be configured as an spi or i 2 c slave where an address is received by the external master. that address becomes an index or offset into the internal system bus memory space. this is accomplished with an initial ?address fetch? td that reads t he target address location from the peripheral and writes that va lue into a subsequent td in the chain. this modifies the td chain on the fly. when the ?address fetch? td completes it moves on to the next td, which has the new address information embedded in it. this td then carries out the data transfer with the address location required by the external master. 4.3.4.6 scatter gather dma in the case of scatter gather dma, there are multiple noncontiguous sources or destin ations that are required to effectively carry out an overall dma transaction. for example, a packet may need to be transmitted off of the device and the packet elements, including the header, payload, and trailer, exist in various noncontiguous locations in memory. scatter gather dma allows the segments to be concatenated together by using multiple tds in a chain. the chain gathers the data from the multiple locations. a similar concept applies for the reception of data onto the device. certain parts of the received data may need to be scattered to various loca tions in memory for software processing convenience. each td in the chain specifies the location for each discrete element in the chain. 4.3.4.7 packet queuing dma packet queuing dma is similar to scatter gather dma but specifically refers to packet pr otocols. with these protocols, there may be separate configuration, data, and status phases associated with sending or receiving a packet. for instance, to transmit a packet, a memory mapped configuration register can be written inside a peripheral, specifying the overall length of the ensuing data phase. the cpu can set up this conf iguration informati on anywhere in system memory and copy it with a simple td to the peripheral. after the configuration phase, a data phase td (or a series of data phase tds) can begin (potentially using scatter gather). when the data phase td(s) finish, a status phas e td can be invoked that reads some memory mapped status information from the peripheral and copies it to a location in system memory specified by the cpu for later inspection. multiple sets of configuration, data, and status phase ?subchains? can be st rung together to create larger chains that transmit multiple packets in this way. a similar concept exists in the opposite direction to receive the packets. 4.3.4.8 nested dma one td may modify another td, as the td configuration space is memory mapped similar to any other peripheral. for example, a first td loads a second td?s configuration and then calls the second td. the second td moves data as required by the application. when complete, the second td calls the first td, which again updates the second td?s configuration. this process repeats as often as necessary. clk addr 16/32 write data ready basic dma read transfer without wait states ab data (a) address phase data phase ab address phase data phase clk write data ready data (a) basic dma write transfer without wait states addr 16/32
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 15 of 109 4.4 interrupt controller the cortex-m3 nvic supports 16 system exceptions and 32 interrupts from peripherals, as shown in table 4-5 . bit 0 of each exception vector i ndicates whether the exception is executed using arm or thumb instructions. because the cortex-m3 only supports thumb instructions, this bit must always be 1. the cortex-m3 non maskable interrupt (nmi) input can be routed to any pin, via the dsi, or disconnected from all pins. see ?dsi routing interface description? section on page 40. the nested vectored interrupt controller (nvic) handles interrupts from the peripherals, and passes the interrupt vectors to the cpu. it is closely integrated with the cpu for low latency interrupt handling. features include: ? 32 interrupts. multiple so urces for each interrupt. ? configurable number of priority levels: from 3 to 8. ? dynamic reprioritization of interrupts. ? priority grouping. this allows selection of preempting and non preempting interrupt levels. ? support for tail-chaining, and late arrival, of interrupts. this enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. ? processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead. if the same priority level is assi gned to two or more interrupts, the interrupt with the lower vector number is executed first. each interrupt vector may choose from three interrupt sources: fixed function, dma, and udb. the fixed function interrupts are direct connections to the most common interrupt sources and provide the lowest resource cost connection. the dma interrupt sources provide direct connections to the two dma interrupt sources provided per dma channel. the third interrupt source for vectors is from the udb digital routing array. this allows any digital signal available to the udb array to be used as an interrupt source. all interrupt sources may be routed to any interrupt vector using the udb interrupt source connections. table 4-5. cortex-m3 exceptions and interrupts exception number exception type priority exception table address offset function 0x00 starting value of r13 / msp 1 reset ?3 (highest) 0x04 reset 2 nmi ?2 0x08 non maskable interrupt 3 hard fault ?1 0x0c all classes of fault, when the corresponding fault handler cannot be activated because it is currently disabled or masked 4 memmanage programmable 0x10 memory management fault, for example, instruction fetch from a nonexecutable region 5 bus fault programmable 0x14 error respons e received from the bus system; caused by an instruction prefetch abort or data access error 6 usage fault programmable 0x18 typically caused by invalid instructions or trying to switch to arm mode 7 ? 10 ? ? 0x1c ? 0x28 reserved 11 svc programmable 0x2c system serv ice call via svc instruction 12 debug monitor programmable 0x30 debug monitor 13 ? ? 0x34 reserved 14 pendsv programmable 0x38 deferred request for system service 15 systick programmable 0x3c system tick timer 16 ? 47 irq programmable 0x40 ? 0x3fc peripheral interrupt request #0 ? #31
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 16 of 109 table 4-6. interrupt vector table interrupt # cortex-m3 exception # fixed function dma udb 0 16 low voltage detect (lvd ) phub_termout0[0] udb_intr[0] 1 17 cache/ecc phub_te rmout0[1] udb_intr[1] 218 reserved phub_termout0[2] udb_intr[2] 3 19 sleep (pwr mgr) phub_termout0[3] udb_intr[3] 4 20 picu[0] phub_termout0[4] udb_intr[4] 5 21 picu[1] phub_termout0[5] udb_intr[5] 6 22 picu[2] phub_termout0[6] udb_intr[6] 7 23 picu[3] phub_termout0[7] udb_intr[7] 8 24 picu[4] phub_termout0[8] udb_intr[8] 9 25 picu[5] phub_termout0[9] udb_intr[9] 10 26 picu[6] phub_termout0[10] udb_intr[10] 11 27 picu[12] phub_termout0[11] udb_intr[11] 12 28 picu[15] phub_termout0[12] udb_intr[12] 13 29 comparators combined phub_termout0[13] udb_intr[13] 14 30 reserved phub_termout0[14] udb_intr[14] 15 31 i 2 c phub_termout0[15] udb_intr[15] 16 32 reserved phub_termout1[0] udb_intr[16] 17 33 timer/counter0 phub_t ermout1[1] udb_intr[17] 18 34 timer/counter1 phub_t ermout1[2] udb_intr[18] 19 35 timer/counter2 phub_t ermout1[3] udb_intr[19] 20 36 timer/counter3 phub_t ermout1[4] udb_intr[20] 21 37 usb sof int phub_t ermout1[5] udb_intr[21] 22 38 usb arb int phub_termout1[6] udb_intr[22] 23 39 usb bus int phub_termout1[7] udb_intr[23] 24 40 usb endpoint[0] phub_termout1[8] udb_intr[24] 25 41 usb endpoint data phub_termout1[9] udb_intr[25] 26 42 reserved phub_termout1[10] udb_intr[26] 27 43 lcd phub_termout1[11] udb_intr[27] 28 44 reserved phub_termout1[12] udb_intr[28] 29 45 decimator int phub_termout1[13] udb_intr[29] 30 46 phub_err_int phub_termout1[14] udb_intr[30] 31 47 eeprom_fault_int phub _termout1[15] udb_intr[31]
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 17 of 109 5. memory 5.1 static ram cy8c52lp static ram (sram) is used for temporary data storage. code can be executed at full speed from the portion of sram that is located in the code space. this process is slower from sram above 0x20000000. the device provides up to 64 kb of sram. the cpu or the dma controller can access all of sram. the sram can be accessed simultaneously by the cortex-m3 cpu and the dma controller if accessing different 32-kb blocks. 5.2 flash program memory flash memory in psoc devices provides nonvolatile storage for user firmware, user configuration data, bulk data storage, and optional ecc data. the main flash memory area contains up to 256 kb of user program space. up to an additional 32 kb of flash space is available for error correcting codes (ecc). if ecc is not used this space can store device configuration data and bulk user data. user code may not be run out of the ecc flash me mory section. ecc can correct one bit error and detect two bit errors per 8 bytes of firmware memory; an interrupt can be generated when an error is detected. the flash output is 9 bytes wide with 8 bytes of data and 1 byte of ecc data. the cpu or dma controller read both user code and bulk data located in flash through the ca che controller. this provides higher cpu performance. if ecc is enabled, the cache controller also performs error checking and correction. flash programming is performed through a special interface and preempts code execution out of flash. code execution may be done out of sram during flash programming. the flash programming interfac e performs flash erasing, programming and setting code prot ection levels. flash in-system serial programming (issp), typically used for production programming, is possible through both the swd and jtag interfaces. in-system programming, typically used for bootloaders, is also possible using serial interfaces such as i 2 c, usb, uart, and spi, or any communications protocol. 5.3 flash security all psoc devices include a flexible flash protection model that prevents access and visibility to on-chip flash memory. this prevents duplication or reverse en gineering of proprietary code. flash memory is organized in blo cks, where each block contains 256 bytes of program or data and 32 bytes of ecc or configuration data. the device offers the ability to assign one of four protection levels to each row of flash. table 5-1 lists the protection modes available. flash protection levels can only be changed by performing a complete flash erase. the full protection and field upgrade settings disable external access (through a debugging tool such as psoc creator, for example). if your application requires code update through a boot loader, then use the field upgrade setting. use the unprotected setting only when no security is needed in your application. the psoc device also offers an advanced security feature called device security which permanently disables all test, programming, and debug ports, protecting your application from external access (see the ?device security? section on page 53). fo r more information on how to take full advantage of the security features in psoc, see the psoc 5 trm. disclaimer note the following details of the fl ash code protection features on cypress devices. cypress products meet the specifications contained in their particular cypress datasheets. cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. there may be methods, unknown to cypress, that can breach the code protection features. an y of these methods, to our knowledge, would be dishonest and possibly illegal. neither cypress nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? cypress is willing to work with the customer who is concerned about the integrity of their code. code protection is constantly evolving. we at cypress are committed to continuously improving the code protecti on features of our products. 5.4 eeprom psoc eeprom memory is a byte addressable nonvolatile memory. the cy8c52lp has 2 kb of eeprom memory to store user data. reads from eeprom are random access at the byte level. reads are done directly; wr ites are done by sending write commands to an eeprom progra mming interfac e. cpu code execution can continue from flash during eeprom writes. eeprom is erasable and writeab le at the row level. the eeprom is divided into 128 rows of 16 bytes each. the cpu can not execute out of eeprom. there is no ecc hardware associated with eeprom. if ecc is required it must be handled in firmware. it can take as much as 20 milliseconds to write to eeprom or flash. during this time the device should not be reset, or unexpected changes may be made to portions of eeprom or flash. reset sources (see section 6.3.1 ) include xres pin, software reset, and watchdog; ca re should be taken to make sure that these are not inadvertent ly activated. in addition, the low voltage detect circuits should be configured to generate an interrupt instead of a reset. table 5-1. flash protection protection setting allowed not allowed unprotected external read and write + internal read and write ? factory upgrade external write + internal read and write external read field upgrade internal read and write external read and write full protection internal read external read and write + internal write
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 18 of 109 5.5 nonvolatile latches (nvls) psoc has a 4-byte array of nonvolatile latches (nvls) that are used to configure the device at reset. the nvl register map is s hown in ta b l e 5 - 3 . the details for individual fields and their factory default settings are shown in table 5-3 :. although psoc creator provides support for modifying the device configuration nvls, the number of nvl erase/write cycles is lim ited ? see ?nonvolatile latches (nvl)? on page 88 . table 5-2. device configuration nvl register map register address 7 6 5 4 3 2 1 0 0x00 prt3rdm[1:0] prt2rdm[1:0] prt1rdm[1:0] prt0rdm[1:0] 0x01 prt12rdm[1:0] prt6rdm[1:0] prt5rdm[1:0] prt4rdm[1:0] 0x02 xresmen dbgen prt15rdm[1:0] 0x03 dig_phs_dly[3:0] eccen dps[1:0] cfgspeed table 5-3. fields and factory default settings field description settings prtxrdm[1:0] controls reset drive mode of the corresponding io port. see ?reset configuration? on page 34. all pins of the port are set to the same mode. 00b (default) - high impedance analog 01b - high impedance digital 10b - resistive pull up 11b - resistive pull down xresmen controls whether pin p1[2 ] is used as a gpio or as an external reset. see ?pin descriptions? on page 10, xres description. 0 (default) - gpio 1 - external reset dbgen debug enable allows access to the debug system, for third-party programmers. 0 - access disabled 1 (default) - access enabled cfgspeed controls the speed of the imo-based clock during the device boot process, for fa ster boot or low-power operation. 0 (default) - 12-mhz imo 1 - 48-mhz imo dps{1:0] controls the usage of various p1 pins as a debug port. see ?programming, debug interfaces, resources? on page 50. 00b - 5-wire jtag 01b (default) - 4-wire jtag 10b - swd 11b - debug ports disabled eccen controls whether ecc flash is used for ecc or for general configuration and data storage. see ?flash program memory? on page 17. 0 (default) - ecc disabled 1 - ecc enabled dig_phs_dly[3:0] selects the digital clock phase delay. see the trm for details.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 19 of 109 5.6 external memory interface cy8c52lp provides an external memory interface (emif) for connecting to external memory devices. the connection allows read and write accesses to external memories. the emif operates in conjunction with udbs, i/o ports, and other hardware to generate external memory address and control signals. at 33 mhz, each memo ry access cycle takes four bus clock cycles. figure 5-1 is the emif block diagram. the emif supports synchronous and asynchronous memories. the cy8c52lp only supports one type of external memory device at a time. external memory is located in the cortex-m3 external ram space; it can use up to 24 address bits. see table 5-4 on page 20 and memory map on page 20. the memory can be 8 or 16 bits wide. cortex-m3 instructio ns can be fetched/executed from external memory, although at a slower rate than from flash. there is no provision for code security in external memory. if code must be kept secure, then it should be placed in internal flash. see flash security on page 17 and device security on page 53. figure 5-1. emif block diagram phub io if udb emif i/o ports i/o ports i/o ports data, address , and control signals data, address, and control signals address signals data signals control signals data, address, and control signals em control signals other control signals dsi dynamic output control dsi to port control external_ mem_ data[15:0] external_ mem_ addr [23:0]
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 20 of 109 5.7 memory map the cortex-m3 has a fixed address map, which allows peripherals to be accessed by simple memory access instructions. 5.7.1 address map the 4-gb address space is divided into the ranges shown in ta b l e 5 - 4 : the bit-band feature allows individual bits in sram to be read or written as atomic operations. this is done by reading or writing bit 0 of corresponding words in the bit-band alias region. for example, to set bit 3 in the word at address 0x20000000, write a 1 to address 0x2200000c. to test the value of that bit, read address 0x2200000c and the result is either 0 or 1 depending on the value of the bit. most memory accesses done by t he cortex-m3 are aligned, that is, done on word (4-byte) boundary addresses. unaligned accesses of words and 16-bit half-words on nonword boundary addresses can also be done, although they are less efficient. 5.7.2 address map and cortex-m3 buses the icode and dcode buses are used only for accesses within the code address range, 0 - 0x1fffffff. the system bus is used for data accesses and debug accesses within the ranges 0x20000000 - 0xdfffffff and 0xe0100000 - 0xffffffff. instruction fetches can also be done within the range 0x20000000 - 0x3fffffff, although these can be slower than instruction fetches via the icode bus. the private peripheral bus (ppb) is used within the cortex-m3 to access system control registers and debug and trace module registers. table 5-4. address map address range size use 0x00000000 ? 0x1fffffff 0.5 gb program code. this includes the exception vector table at power up, which starts at address 0. 0x20000000 ? 0x3fffffff 0.5 gb static ram. this includes a 1 mbyte bit-band region starting at 0x20000000 and a 32 mbyte bit-band alias region starting at 0x22000000. 0x40000000 ? 0x5fffffff 0.5 gb peripherals. 0x60000000 ? 0x9fffffff 1 gb external ram. 0xa0000000 ? 0xdfffffff 1 gb external peripherals. 0xe0000000 ? 0xffffffff 0.5 gb internal peripherals, including the nvic and debug and trace modules. table 5-5. peripheral data address map address range purpose 0x00000000 ? 0x0003ffff 256 k flash 0x1fff8000 ? 0x1fffffff 32 k sram in code region 0x20000000 ? 0x20007fff 32 k sram in sram region 0x40004000 ? 0x400042ff clocking, plls, and oscillators 0x40004300 ? 0x400043ff power management 0x40004500 ? 0x400045ff ports interrupt control 0x40004700 ? 0x400047ff flash programming interface 0x40004800 ? 0x400048ff cache controller 0x40004900 ? 0x400049ff i 2 c controller 0x40004e00 ? 0x40004eff decimator 0x40004f00 ? 0x40004fff fixed timer/counter/pwms 0x40005000 ? 0x400051ff i/o ports control 0x40005400 ? 0x400054ff external memory interface (emif) control registers 0x40005800 ? 0x40005fff analog subsystem interface 0x40006000 ? 0x400060ff usb controller 0x40006400 ? 0x40006fff udb working registers 0x40007000 ? 0x40007fff phub configuration 0x40008000 ? 0x400087ff eeprom 0x4000a000 ? 0x4000a400 reserved 0x40010000 ? 0x4001ffff digital interconnect configuration 0x48000000 ? 0x48007fff flash ecc bytes 0x60000000 ? 0x60ffffff external memory interface (emif) 0xe0000000 ? 0xe00fffff co rtex-m3 ppb registers, including nvic, debug, and trace table 5-5. peripheral data address map (continued) address range purpose
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 21 of 109 6. system integration 6.1 clocking system the clocking system generates, di vides, and distributes clocks throughout the psoc system. for the majority of systems, no external crystal is required. the imo and pll together can generate up to a 80-mhz clock, accurate to 2% over voltage and temperature. additional internal and external clock sources allow each design to optimize accuracy, power, and cost. all of the system clock sources can be used to generate other clock frequencies in the 16-bit clock dividers and udbs for anything you want, for example a uart baud rate generator. clock generation and distribution is automatically configured through the psoc creator ide graphical interface. this is based on the complete system?s requ irements. it greatly speeds the design process. psoc creator allows designers to build clocking systems with minimal input. yo u can specify desired clock frequencies and accuracies, and the software locates or builds a clock that meets the required specifications. this is possible because of the programmability inherent in psoc. key features of the clocking system include: ? seven general purpose clock sources ? 3- to 74-mhz imo, 2% at 3 mhz ? 4- to 25-mhz external crystal oscillator (mhzeco) ? clock doubler provides a doubled clock frequency output for the usb block, see usb clock domain on page 24. ? dsi signal from an external i/o pin or other logic ? 24- to 80-mhz fractional phase-locked loop (pll) sourced from imo, mhzeco, or dsi ? 1-khz, 33-khz, 100-khz ilo for watchdog timer (wdt) and sleep timer ? 32.768-khz external crystal oscillator (eco) for rtc ? imo has a usb mode that auto-locks to the usb bus clock requiring no external crystal for usb. (usb equipped parts only) ? independently sourced clock in all clock dividers ? eight 16-bit clock divider s for the digital system ? four 16-bit clock dividers for the analog system ? dedicated 16-bit divider for the cpu bus and cpu clock ? automatic clock configuration in psoc creator table 6-1. oscillator summary source fmin tolerance at fmin fmax tolerance at fmax startup time imo 3 mhz 2% over voltage and temperature 74 mhz 7% 13 s max mhzeco 4 mhz crystal dependent 25 mhz crystal dependent 5 ms typ, max is crystal dependent dsi 0 mhz input dependent 67 mhz input dependent input dependent pll 24 mhz input dependent 80 mhz input dependent 250 s max doubler 48 mhz input dependent 48 mhz input dependent 1 s max ilo 1 khz ?50%, +100% 100 khz ?55%, +100% 15 ms max in lowest power mode khzeco 32 khz crystal dependent 32 khz crystal dependent 500 ms typ, max is crystal dependent
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 22 of 109 figure 6-1. clocking subsystem 6.1.1 internal oscillators 6.1.1.1 internal main oscillator in most designs the imo is the only clock source required, due to its 2% accuracy. the imo operates with no external components and outputs a stable clock. a factory trim for each frequency range is stored in the device. with the factory trim, tolerance varies from 2% at 3 mhz, up to 7% at 74 mhz. the imo, in conjunction with the pl l, allows generation of cpu and system clocks up to the devi ce's maximum frequency (see usb clock domain ). the imo provides clock outputs at 3, 6, 12, 24, 48 and 74 mhz. 6.1.1.2 clock doubler the clock doubler outputs a clock at twice the frequency of the input clock. the doubler works at input frequency of 24 mhz, providing 48 mhz for the usb. it can be configured to use a clock from the imo, mhzeco, or the dsi (external pin). 6.1.1.3 phase-locked loop the pll allows low frequency, high accuracy clocks to be multiplied to higher frequencies. this is a tradeoff between higher clock frequency and accuracy and, higher power consumption and increased startup time. the pll block provides a mechanism for generating clock frequencies based upon a variety of input sources. the pll outputs clock frequencies in the range of 24 to 80 mhz. its input and feedback dividers supply 4032 discrete ratios to create almost any desired system clock frequency. the accuracy of the pll output depends on the accuracy of the pll input source. the most common pll use is to multiply the imo clock at 3 mhz, where it is most accurate, to generate the cpu and system clocks up to the device?s maximum frequency. the pll achieves phase lock within 250 s (verified by bit setting). it can be configured to use a clock from the imo, mhzeco, or dsi (external pin). the pll clock source can be used until lock is complete and signaled with a lock bit. the lock signal can be routed through the dsi to generate an interrupt. disable the pll before entering low power modes. 6.1.1.4 internal low speed oscillator the ilo provides clock frequencies for low power consumption, including the watchdog timer, and sleep timer. the ilo generates up to three different clocks: 1 khz, 33 khz, and 100 khz. the 1-khz clock (clk1k) is typically used for a background ?heartbeat? timer. this clock inherently lends itself to low power supervisory operations such as the watchdog timer and long sleep intervals using the central timewheel (ctw). the central timewheel is a 1-khz, free-running, 13-bit counter clocked by the ilo. the central timewheel is always enabled except in hibernate mode and when the cpu is stopped during debug on chip mode. it can be used to generate periodic interrupts for timing purposes or to wake the system from a low power mode. firmware can reset the central timewheel. 4-25 mhz eco 3-74 mhz imo 32 khz eco 1,33,100 khz ilo s k e w 7 7 digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit digital clock divider 16 bit analog clock divider 16 bit bus clock divider 16 bit 48 mhz doubler for usb 24-80 mhz pll system clock mux external io or dsi 0-67 mhz s k e w analog clock divider 16 bit s k e w analog clock divider 16 bit s k e w analog clock divider 16 bit bus clock cpu clock
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 23 of 109 the central timewheel can be pr ogrammed to wake the system periodically and optionally issue an interrupt. this enables flexible, periodic wakeups from low power modes or coarse timing applications. systems that require accurate timing should use the rtc capability instead of the central timewheel. the 100-khz clock (clk100k) can be used as a low power system clock to run the cpu. it c an also generate time intervals using the fast timewheel. the fast timewheel is a 5-bit counter, clocked by the 100-khz clock. it features programmabl e settings and automatically resets when the terminal count is reached. an optional interrupt can be generated each time the terminal count is reached. this enables flexible, periodic interrupts of the cpu at a higher rate than is allowed using the central timewheel. the 33-khz clock (clk33k) comes from a divide-by-3 operation on clk100k. this output can be used as a reduced accuracy version of the 32.768-khz eco clock with no need for a crystal. 6.1.2 external oscillators 6.1.2.1 mhz external crystal oscillator the mhzeco provides high frequency, high precision clocking using an external crystal (see figure 6-2 ). it supports a wide variety of crystal types, in the range of 4 to 25 mhz. when used in conjunction with the pll, it can ge nerate cpu and system clocks up to the device's maximum frequency (see internal low speed oscillator ). the gpio pins connecting to the external crystal and capacitors are fixe d. mhzeco accuracy depends on the crystal chosen. figure 6-2. mhzeco block diagram 6.1.2.2 32.768 khz eco the 32.768-khz external crystal o scillator (32khzeco) provides precision timing with minimal power consumption using an external 32.768-khz watch crystal (see figure 6-3 ). the 32khzeco also connects directly to the sleep timer and provides the source for the rtc. the rtc uses a 1-second interrupt to implement the rtc functionality in firmware. the oscillator works in two distinct power modes. this allows you to trade off power consumption with noise immunity from neighboring circuits. the gpio pins connected to the external crystal and capacitors are fixed. figure 6-3. 32khzeco block diagram it is recommended that the external 32.768-khz watch crystal have a load capacitance (cl) of 6 pf or 12.5 pf. check the crystal manufacturer's datasheet. the two external capacitors, cl1 and cl2, are typically of the same value, and their total capacitance, cl1cl2 / (cl1 + cl2), including pin and trace capacitance, should equal the crystal cl value. for more infor- mation, refer to application note an54439: psoc 3 and psoc 5 external oscillators . see also pin capacitance specifications in the ?gpio? section on page 62. 6.1.2.3 digital system interconnect the dsi provides routing for clocks taken from external clock oscillators connected to i/o. the oscillators can also be generated within the device in the digi tal system and udbs. while the primary dsi clock input provides access to all clocking resources, up to eight other dsi clocks (internally or externally generated) may be routed directly to the eight digital clock dividers. this is only possible if there are multiple precision clock sources. 6.1.3 clock distribution all seven clock sources are inputs to the central clock distribution system. the distributi on system is designed to create multiple high precision clocks. these clocks are customized for the design?s requirements and el iminate the common problems found with limited resolution prescalers attached to peripherals. the clock distribution system gener ates several types of clock trees. ? the system clock is used to sele ct and supply the fastest clock in the system for general system clock requirements and clock synchronization of the psoc device. ? bus clock 16-bit divider uses the system clock to generate the system?s bus clock used for data transfers and the cpu. the cpu clock is directly de rived from the bus clock. ? eight fully programmable 16-bit clock dividers generate digital system clocks for general use in the digital system, as configured by the design?s requi rements. digital system clocks can generate custom clocks de rived from any of the seven xo (pin p15[0]) 4 - 25 mhz crystal osc xclk_mhz 4 ? 25 mhz crystal capacitors external components xi (pin p15[1]) xo (pin p15[2]) 32 khz crystal osc xclk32k 32 khz crystal capacitors external components xi (pin p15[3])
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 24 of 109 clock sources for any purpose. examples include baud rate generators, accurate pwm periods, and timer clocks, and many others. if more than eight digital clock dividers are required, the universal digital bl ocks (udbs) and fixed function timer/counter/pwms can also genera te clocks. ? four 16-bit clock dividers genera te clocks for the analog system components that require clocking, such as the adc. the analog clock dividers include skew control to ensure that critical analog events do not occur simultaneously with digital switching events. this is done to reduce analog system noise. each clock divider consists of an 8-input multiplexer, a 16-bit clock divider (divide by 2 and hi gher) that generates ~50% duty cycle clocks, system clock resynchro nization logic, and deglitch logic. the outputs from each digita l clock tree can be routed into the digital system interconnect and then brought back into the clock system as an input, allowing clock ch aining of up to 32 bits. 6.1.4 usb clock domain the usb clock domain is unique in that it operates largely asynchronously from the main clock network. the usb logic contains a synchronous bus interface to the chip, while running on an asynchronous clock to process usb data. the usb logic requires a 48 mhz frequency. this frequency is generated from the doubled value of 24 mhz from internal oscillator, dsi signal, or crystal oscillator. 6.2 power system the power system consists of separate analog, digital, and i/o supply pins, labeled vdda, vddd, and vddiox, respectively. it also includes two internal 1.8 v regulators that provide the digital (vccd) and analog (vcca) supplies for the internal core logic. the output pins of the regulators (vccd and vcca) and the vddio pins must have capacitors connected as shown in figure 6-4 . the two vccd pins must be shorted together, with as short a trace as possible, and connected to a 1 f 10% x5r capacitor. the power system also contains a sleep regulator, an i 2 c regulator, and a hibernate regulator. figure 6-4. psoc power system note the two v ccd pins must be connected together wit h as short a trace as possible. a tr ace under the device is recommended, as shown in figure 2-6 . you can power the device in internally regulated mode, where the voltage applied to the v ddx pins is as high as 5.5 v, and the internal regulators provide the core voltages. in this mode, do not apply power to the v ccx pins, and do not tie the v ddx pins to the v ccx pins. you can also power the device in externally regul ated mode, that is, by directly powering the v ccd and v cca pins. in this configuration, the v ddd pins should be shorted to the v ccd pins and the v dda pin should be shorted to the v cca pin. the allowed supply range in this configuration is 1.71 v to 1.89 v. after power up in this configuration, the internal re gulators are on by default, and sh ould be disabled to reduce power consumption. vssb vssd vddio1 vddio 2 vddio0 vddio 3 vccd vddd vssd vccd vddd vssa vcca vdda digital regulators analog regulator analog domain digital domain i2c regulator sleep regulator hibernate regulator i/o supply i/o supply i/o supply i/o supply . vddio2 vddio0 vddio3 vddio1 0.1 f 0.1 f 0.1 f 0.1 f vddd vddd 1 f 1 f vdda 0.1 f 0.1 f 0.1 f
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 25 of 109 6.2.1 power modes psoc 5lp devices have four different power modes, as shown in ta b l e 6 - 2 and ta b l e 6 - 3 . the power modes allow a design to easily provide required functional ity and processing power while simultaneously minimizing power consumption and maximizing battery life in low power and portable devices. psoc 5lp power modes, in order of decreasing power consumption are: ? active ? alternate active ? sleep ? hibernate active is the main processing mode. its functionality is configurable. each power contro llable subsystem is enabled or disabled by using separate power configuration template registers. in alte rnate active mode, fewer subsystems are enabled, reducing power. in sleep mode most resources are disabled regardless of the template settings. sleep mode is optimized to provide timed sleep intervals and real time clock functionality. the lowest power mode is hibernate, which retains register and sram state, but no clocks, and allows wakeup only from i/o pins. figure 6-5 illustrates the allowable transitions between power modes. sleep and hibernate modes should not be entered until all vddio supplies are at valid voltage levels. table 6-2. power modes power modes description entry condition wakeup source active clocks regulator active primary mode of operation, all peripherals available (program- mable) wakeup, reset, manual register entry any interrupt any (program- mable) all regulators available. digital and analog regulators can be disabled if external regulation used. alternate active similar to active mode, and is typically configured to have fewer peripherals active to reduce power. one possible configuration is to use the udbs for processing, with the cpu turned off manual register entry any interrupt any (program- mable) all regulators available. digital and analog regulators can be disabled if external regulation used. sleep all subsystems automatically disabled manual register entry comparator, picu, i 2 c, rtc, ctw, lvd ilo/khzeco both digital and analog regulators buzzed. digital and analog regulators can be disabled if external regulation used. hibernate all subsystems automatically disabled lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled configuration and memory contents retained manual register entry picu only hibernate regulator active. table 6-3. power modes wakeup time and power consumption sleep modes wakeup time current (typ) code execution digital resources analog resources clock sources available wakeup sources reset sources active ? 3.1 ma [7] yes all all all ? all alternate active ? ?user defined all all all ? all sleep <25 s 2 a no i 2 c comparator ilo/khzeco comparator, picu, i 2 c, rtc, ctw, lvd xres, lvd, wdr hibernate <200 s 300 na no none none none picu xres note 7. bus clock off. execute from cpu instruction buffer at 6 mhz. see table 11-2 on page 56
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 26 of 109 figure 6-5. power mode transitions 6.2.1.1 active mode active mode is the primary oper ating mode of the device. when in active mode, the active configuration template bits control which available resources are enabled or disabled. when a resource is disabled, the digital clocks are gated, analog bias currents are disabled, and leakage currents are reduced as appropriate. user firmware can dynamically control subsystem power by setting and clearing bits in the active configuration template. the cpu can disable itself, in which case the cpu is automatically reenabled at the next wakeup event. when a wakeup event occurs, the global mode is always returned to active, and the cpu is automatically enabled, regardless of its template setting s. active mode is the default global power mode upon boot. 6.2.1.2 alternate active mode alternate active mode is very sim ilar to active mode. in alternate active mode, fewer subsystems are enabled, to reduce power consumption. one possible configuration is to turn off the cpu and flash, and run peripherals at full speed. 6.2.1.3 sleep mode sleep mode reduces power consumption when a resume time of 15 s is acceptable. the wake time is used to ensure that the regulator outputs are stable enough to directly enter active mode. 6.2.1.4 hibernate mode in hibernate mode nearly all of the internal functions are disabled. internal voltages are reduced to the minimal level to keep vital systems alive. config uration state is preserved in hibernate mode and sram memory is retained. gpios configured as digital outputs maintain their previous values and external gpio pin interrupt settings are preserved. the device can only return from hibernate mode in response to an external i/o interrupt. the resume time from hibernate mode is less than 100 s. to achieve an extremely low current, the hibernate regulator has limited capacity. this limits the frequency of any signal present on the input pins; no gpio should toggle at a rate greater than 10 khz while in hibernate mode. if pins must be toggled at a high rate while in a low power mode, use sleep mode instead. 6.2.1.5 wakeup events wakeup events are configurable and can come from an interrupt or device reset. a wakeup event restores the system to active mode. firmware enabled interrupt sources include internally generated interrupts, power super visor, central timewheel, and i/o interrupts. internal interrupt sources can come from a variety of peripherals, such as analog comparators and udbs. the central timewheel provides periodic interrupts to allow the system to wake up, poll periphe rals, or perform real-time functions. reset event sources include the external reset i/o pin (xres), wdt, and precision reset (pres). 6.2.2 boost converter applications that use a supply voltage of less than 1.71 v, such as single cell battery supplies, may use the on-chip boost converter. the boost converter may also be used in any system that requires a higher operating voltage than the supply provides. for instance, this includes driving 5.0 v lcd glass in a 3.3 v system. the boost converter accept s an input voltage as low as 0.5 v. with one low cost inductor it produces a selectable output voltage sourcing enough current to operate the psoc and other on-board components. the boost converter accepts an input voltage vbat from 0.5 v to 3.6 v, and can start up with vbat as low as 0.5 v. the converter provides a user configurable output voltage of 1.8 to 5.0 v (vboost). vbat is typically less than vboost; if vbat is greater than or equal to vboost, then vboost will be the same as vbat. the block can deliver up to 75 ma (iboost) depending on configuration. four pins are associated with the boost converter: vbat, vssb, vboost, and ind. the boosted ou tput voltage is sensed at the vboost pin and must be connected directly to the chip?s supply inputs. an inductor is connect ed between the vbat and ind pins. you can optimize the inductor value to increase the boost converter efficiency based on input voltage, output voltage, current and switching frequency. figure 6-6. application for boost converter active manual hibernate alternate active sleep psoc v boost ind v bat v ssb v ssd v dda v ddd v ssa 22 f 0.1 f 22 f 10 h optional schottky diode. only required when vdd >3.6v.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 27 of 109 the switching frequency is set to 400 khz using an oscillator in the boost converter block. the vboost is limited to 4 vbat. the boost converter can be operated in two different modes: active and sleep. active mode is the normal mode of operation where the boost regulator active ly generates a regulated output voltage. the boost typically draws 250 a in active mode and 25 a in sleep mode. the boost operating modes must be used in conjunction with chip power modes to minimize total power consumption. ta b l e 6 - 4 lists the boost power modes available in different chip power modes. if the boost converter is not used, tie the vbat, vssb, and vboost pins to ground and leave the ind pin unconnected. 6.3 reset cy8c52lp has multiple internal and external reset sources available. the reset sources are: ? power source monitoring: the analog and digital power voltages, vdda, vddd, vcca, and vccd are monitored in several different modes during power up, active mode, and sleep mode (buzzing). if any of the voltages goes outside predetermined ranges then a rese t is generated. the monitors are programmable to generate an interrupt to the processor under certain conditions before reaching the reset thresholds. ? external: the device can be reset from an external source by pulling the reset pin (xres) low. the xres pin includes an internal pull up to vddio1. vddd, vdda, and vddio1 must all have voltage applied before the part comes out of reset. ? watchdog timer: a watchdog time r monitors the execution of instructions by the processor. if the watchdog timer is not reset by firmware within a certain period of time, the watchdog timer generates a reset. ? software: the device can be reset under program control. figure 6-7. resets the term system reset indicates that the processor as well as analog and digital peripherals and registers are reset. a reset status register shows some of the resets or power voltage monitoring interrupts. the program may examine this register to detect and report certain exceptio n conditions. this register is cleared after a power-on reset. for details see the technical reference manual. 6.3.1 reset sources 6.3.1.1 power voltage level monitors ? ipor - initial power-on-reset at initial power on, ipor monitors the power voltages v ddd , v dda , v ccd and v cca . the trip level is not precise. it is set to approximately 1 volt, which is below the lowest specified operating voltage but high enough for the internal circuits to be reset and to hold their reset state. the monitor generates a reset pulse that is at least 150 ns wide. it may be much wider if one or more of the voltages ramps up slowly. if after the ipor triggers either v ddx drops back below the trigger point, in a non-monotonic fashion, it must remain below that point for at least 10 s. the hysteresis of the ipor trigger point is typically 100 mv. after boot, the ipor circuit is disabled and voltage supervision is handed off to the precise low-voltage reset (pres) circuit. ? pres - precise low-voltage reset this circuit monitors the outputs of the analog and digital internal regulators after power up. the regulator outputs are compared to a precise reference voltage. the response to a pres trip is identica l to an ipor reset. in normal operating mode, the program cannot disable the digital pres circuit. the analog regulator can be disabled, which also disables the analog portion of the pres. the pres circuit is disabled automatica lly during sleep and hibernate modes, with one exception: during sleep mode the regulators are periodically activated (buzzed) to provide supervisory table 6-4. chip and boost power modes compatibility chip power modes boost power modes chip-active or alternate active mode boost must be operated in its active mode. chip-sleep mode boost can be operated in either active or sleep mode. in boost sleep mode, the chip must wake up periodically for boost active-mode refresh. chip-hibernate mode boost can be operated in either active or sleep mode. however, it is recommended not to use the boost with chip hibernate mode due to the higher current consumption. in boost sleep mode, the chip must wake up periodically for boost active-mode refresh. reset controller watchdog timer external reset power voltage level monitors software reset register vddd vdda reset pin system reset processor interrupt
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 28 of 109 services and to reduce wakeup time. at these times the pres circuit is also buzzed to allow periodic voltage monitoring. after pres has been deasserted, at least 10 s must elapse before it can be reasserted. ? alvi, dlvi, ahvi - analog/digital low voltage interrupt, analog high voltage interrupt interrupt circuits are available to detect when vdda and vddd go outside a voltage range. for ahvi, v dda is compared to a fixed trip level. for alvi and dlvi, vdda and vddd are compared to trip levels that are programmable, as listed in ta b l e 6 - 5 . alvi and dlvi can also be configured to generate a device reset instead of an interrupt. the monitors are disabled until after ipor. during sleep mode these circuits are periodically acti vated (buzzed). if an interrupt occurs during buzzing then the system first enters its wakeup sequence. the interrupt is then recognized and may be serviced. the buzz frequency is adjustable, and should be set to be less than the minimum time that any voltage is expected to be out of range. for details on how to adjust the buzz frequency, see the trm. 6.3.1.2 other reset sources ? xres - external reset psoc 5lp has either a single gpio pin that is configured as an external reset or a dedicated xres pin. either the dedicated xres pin or the gpio pin, if configured, holds the part in reset while held active (low). the response to an xres is the same as to an ipor reset. the external reset is active low. it includes an internal pull up resistor. xres is active during sleep and hibernate modes. after xres has been deasserted, at least 10 s must elapse before it can be reasserted. ? sres - software reset a reset can be commanded under program control by setting a bit in the software reset regist er. this is done either directly by the program or indirectly by dma access. the response to a sres is the same as after an ipor reset. another register bit exists to disable this function. ? wres - watchdog timer reset the watchdog reset detects when the software program is no longer being executed correctly. to indicate to the watchdog timer that it is running correctly , the program must periodically reset the timer. if the timer is not reset before a user-specified amount of time, then a reset is generated. note ipor disables the watchdog function. the program must enable the watchdog function at an appropriate point in the code by setting a register bit. wh en this bit is set, it cannot be cleared again except by an ipor power on reset event. 6.4 i/o system and routing psoc i/os are extremely flexible. every gpio has analog and digital i/o capability. all i/os have a large number of drive modes, which are set at por. psoc also provides up to four individual i/o voltage domains through the vddio pins. there are two types of i/o pins on every device; those with usb provide a third type. both gpio and special i/o (sio) provide similar digital functionality. the primary differences are their analog capability and drive strength. devices that include usb also provide two usbio pins that support specific usb functionality as well as limited gpio capability. all i/o pins are available for use as digital inputs and outputs for both the cpu and digital peripherals. in addition, all i/o pins can generate an interrupt. the flexible and advanced capabilities of the psoc i/o, combined with any signal to any pin routability, greatly simplify circuit design and board layout. all gpio pins can be used for analog input, capsense [8] , and lcd segment drive, while sio pins are used for voltages in excess of vdda and for programmable output voltages. ? features supported by both gpio and sio: ? user programmable port reset state ? separate i/o supplies and voltages for up to four groups of i/o ? digital peripherals use dsi to connect the pins ? input or output or both for cpu and dma ? eight drive modes ? every pin can be an interrupt source configured as rising edge, falling edge or both edges. if required, level sensitive interrupts are supported through the dsi ? dedicated port interrupt vector for each port ? slew rate controlled digital output drive mode ? access port control and configurat ion registers on either port basis or pin basis ? separate port read (ps) and writ e (dr) data registers to avoid read modify write errors ? special functionality on a pin by pin basis ? additional features only provided on the gpio pins: ? lcd segment drive on lcd equipped devices ? capsense [8] ? analog input and output capability ? continuous 100 a clamp current capability ? standard drive strength down to 1.71 v ? additional features only provided on sio pins: ? higher drive strength than gpio ? hot swap capability (5 v tolerance at any operating vdd) ? programmable and regulated high input and output drive levels down to 1.2 v ? no analog input, capsense, or lcd capability ? over voltage tolerance up to 5.5 v ? sio can act as a general purpose analog comparator table 6-5. analog/digital low voltage interrupt, analog high voltage interrupt interrupt supply normal voltage range available trip settings dlvi vddd 1.71 v-5.5 v 1.70 v-5.45 v in 250 mv increments alvi vdda 1.71 v-5.5 v 1.70 v-5.45 v in 250 mv increments ahvi vdda 1.71 v-5.5 v 5.75 v note 8. gpios with opamp outputs are not recommended for use with capsense.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 29 of 109 ? usbio features: ? full speed usb 2.0 compliant i/o ? highest drive strength for general purpose use ? input, output, or both for cpu and dma ? input, output, or both for digital peripherals ? digital output (cmos) drive mode ? each pin can be an interrupt source configured as rising edge, falling edge, or both edges figure 6-8. gpio block diagram drive logic prt[x]dm0 prt[x]dr pin digital output path digital input path prt[x]slw lcd logic & mux prt[x]dm1 prt[x]dm2 prt[x]lcd_en prt[x]lcd_com_seg analog analog mux analog global digital system output 0 1 prt[x]byp prt[x]bie bidirectional control capsense global control switches pin interrupt signal digital system input prt[x]ps prt[x]ctl input buffer disable display data interrupt logic picu[x]inttype[y] picu[x]intstat vddio vddio vddio slew cntl lcd bias bus 5 prt[x]amux prt[x]ag 1 caps[x]cfg1 oe in prt[x]sync_out prt[x]dbl_sync_in picu[x]intstat naming convention ?x? = port number ?y? = pin number 0 1 0 1
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 30 of 109 figure 6-9. sio input/output block diagram figure 6-10. usbio block diagram drive logic prt[x]dm0 prt[x]dr pin digital output path digital input path prt[x]slw prt[x]dm1 prt[x]dm2 digital system output 0 1 prt[x]byp prt[x]bie bidirectional control pin interrupt signal digital system input prt[x]ps input buffer disable interrupt logic picu[x]inttype[y] picu[x]intstat slew cntl oe in prt[x]sync_out prt[x]dbl_sync_in picu[x]intstat prt[x]sio_diff buffer thresholds driver vhigh prt[x]sio_cfg prt[x]sio_hyst_en naming convention ?x? = port number ?y? = pin number reference level reference level drive logic prt[15]dr1[7,6] pin digital output path digital input path digital system output 0 1 prt[15]byp pin interrupt signal digital system input usbio_cr1[0,1] interrupt logic picu[15]inttype[y] picu[15]intstat in prt[15]dbl_sync_in picu[15]intstat naming convention ?y? = pin number vddd vddd vddd 5 k 1.5 k d+ pin only prt[15]dm1[6] usbio_cr1[5] usb or i/o d+ 1.5 k d+ 5 k d+ open drain prt[15]sync_out usb sie control for usb mode usb receiver circuitry vddd prt[15]ps[6,7] usbio_cr1[2] d- 5 k prt[15]dm1[7] d- open drain prt[15]dm0[6] prt[15]dm0[7]
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 31 of 109 6.4.1 drive modes each gpio and sio pin is individually configurable into one of the eight drive modes listed in ta b l e 6 - 6 . three configuration bits are used for each pin (dm[2:0]) and set in the prtxdm[2:0] registers. figure 6-11 depicts a simplified pin view based on each of the eight drive modes. ta b l e 6 - 6 shows the i/o pin?s drive state based on the port data register value or digital array signal if bypass mode is selected. note that the actual i/o pin voltage is determined by a combination of the selected drive mode and the load at the pin. for example, if a gpio pin is configured for resistive pull up mode and driven high while the pin is floating, the voltage measured at the pin is a high logic state. if the same gpio pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state. figure 6-11. drive mode table 6-6. drive modes diagram drive mode prtxdm2 prtxdm1 prtxdm0 prtxdr = 1 prtxdr = 0 0 high impedance analog 0 0 0 high-z high-z 1 high impedance digital 0 0 1 high-z high-z 2 resistive pull-up [9] 0 1 0 res high (5k) strong low 3 resistive pull-down [9] 0 1 1 strong high res low (5k) 4 open drain, drives low 1 0 0 high-z strong low 5 open drain, drive high 1 0 1 strong high high-z 6 strong drive 1 1 0 strong high strong low 7 resistive pull-up and pull-down [9] 1 1 1 res high (5k) res low (5k) high impedance analog ps dr ps dr ps dr 0. high impedance digital 1. resistive pull-up 2. resistive pull-down 3. open drain , drives low 4. open drain , drives high 5. strong drive 6. resistive pull-up and pull-down 7. vddio pin pin pin vddio pin pin pin pin pin ps dr ps dr ps dr ps dr ps dr vddio vddio vddio note 9. resistive pull up and pull down are not avai lable with sio in regulated output mode.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 32 of 109 the usbio pins (p15[7] and p15[6]), when enabled for i/o mode, have limited drive mode control. the drive mode is set using the prt15.dm0[7, 6] register. a resistive pull option is also avail able at the usbio pins, which can be enabled using the prt15.dm1 [7, 6] register. when enabled for usb mode, the drive mode control has no impact on the configuration of the usb pins. unlike the g pio and sio configurations, the port wide configuration registers do not configure the usb drive mode bits. table 6-7 shows the drive mode configuration for the usbio pins. ? high impedance analog the default reset state with both the output driver and digital input buffer turned off. this prevents any current from flowing in the i/o?s digital input buffer due to a floating voltage. this state is recommended for pins that are floating or that support an analog voltage. high impedance analog pins do not provide digital input functionality. to achieve the lowest chip current in sleep modes, all i/os must either be configured to the high impedance analog mode, or have their pins driven to a power supply rail by the psoc device or by external circuitry. ? high impedance digital the input buffer is enabled for digital signal input. this is the standard high impedance (hiz) state recommended for digital inputs. ? resistive pull up or resistive pull down resistive pull up or pull down, respectively, provides a series resistance in one of the data states and strong drive in the other. pins can be used for digital input and output in these modes. interfacing to mechanical switches is a common application for these modes. resistive pull up and pull down are not available with sio in regulated output mode. ? open drain, drives high and open drain, drives low open drain modes provide hi gh impedance in one of the data states and strong drive in the ot her. pins can be used for digital input and output in these modes. a common application for these modes is driving the i 2 c bus signal lines. ? strong drive provides a strong cmos output dr ive in either high or low state. this is the standard out put mode for pins. strong drive mode pins must not be used as inputs under normal circumstances. this mode is often used to drive digital output signals or external fets. ? resistive pull up and pull down similar to the resistive pull up and resistive pull down modes except the pin is always in series with a resistor. the high data state is pull up while the low data state is pull down. this mode is most often used when other signals that may cause shorts can drive the bus. resistive pull up and pull down are not available with sio in regulated output mode. 6.4.2 pin registers registers to configure and interact with pins come in two forms that may be used interchangeably. all i/o registers are available in the standard port form, where each bit of the register correspond s to one of the port pins. this register form is efficient for quickly reconfiguring multiple port pins at the same time. i/o registers are also available in pin form, which combines the eight most commonly used port regist er bits into a single register for each pin. this enables very fast configuration changes to individual pins with a single register write. 6.4.3 bidirectional mode high speed bidirectional capability allows pins to provide both the high impedance digital drive mode for input signals and a second user selected drive mode su ch as strong drive (set using prtxdm[2:0] registers) for output signals on the same pin, based on the state of an auxiliary control bus signal. the bidirectional capability is useful for processor busses and communications interfaces such as the spi slave miso pin that requires dynamic hardware control of the output buffer. the auxiliary control bus routes up to 16 udb or digital peripheral generated output enable signals to one or more pins. 6.4.4 slew rate limited mode gpio and sio pins have fast and slow output slew rate options for strong and open drain drive m odes, not resistive drive modes. because it results in reduced emi, the slow edge rate option is recommended for signals that are not speed critical, generally less than 1 mhz. the fast slew rate is for signals between 1 mhz and 33 mhz. the slew rate is individually configurable for each pin, and is set by the prtxslw registers. table 6-7. usbio drive modes (p15[7] and p15[6]) prt15.dm1[7,6] pull up enable prt15.dm0[7,6] drive mode enable prt15.dr[7,6] = 1 prt15.dr[7,6] = 0 description 0 0 high z strong low open drain, strong low 0 1 strong high strong low strong outputs 1 0 res high (5k) strong low resistive pull up, strong low 1 1 strong high strong low strong outputs
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 33 of 109 6.4.5 pin interrupts all gpio and sio pins are able to generate interrupts to the system. all eight pins in each po rt interface to their own port interrupt control unit (picu) and associated interrupt vector. each pin of the port is independently configurable to detect rising edge, falling edge, both edge interrupts, or to not generate an interrupt. depending on the configured mode for each pin, each time an interrupt event occurs on a pin, its corresponding status bit of the interrupt status register is set to ?1? and an interrupt request is sent to the interrupt controller. each picu has its own interrupt vector in the interrupt controll er and the pin status register providing easy determination of the interrupt source down to the pin level. port pin interrupts remain active in all sleep modes allowing the psoc device to wake from an externally generated interrupt. while level sensitive interrupts are not directly supported; udbs provide this functionality to the system when needed. 6.4.6 input buffer mode gpio and sio input buffers can be configured at the port level for the default cmos input thresholds or the optional lvttl input thresholds. all input buffers incorporate schmitt triggers for input hysteresis. additionally, individual pin input buffers can be disabled in any drive mode. 6.4.7 i/o power supplies up to four i/o pin power supplie s are provided depending on the device and package. each i/o supply must be less than or equal to the voltage on the chip?s analog (vdda) pin. this feature allows you to provide different i/o voltage levels for different pins on the device. refer to the specific device package pinout to determine vddio capability for a given port and pin. the sio port pins support an additional regulated high output capability, as described in adjustable output level . 6.4.8 analog connections these connections apply only to gpio pins. all gpio pins may be used as analog inputs or outputs. the analog voltage present on the pin must not exceed the vddio supply voltage to which the gpio belongs. each gpio may connect to one of the analog global busses or to one of the analog mux buses to connect any pin to any internal analog resource such as adc or comparators. in addition, one select pin provides direct connection to the high current dac. 6.4.9 capsense this section applies only to gp io pins. all gpio pins may be used to create capsense buttons and sliders [10] . see the ?capsense? section on page 49 fo r more information. 6.4.10 lcd segment drive this section applies only to gp io pins. all gpio pins may be used to generate segment and common drive signals for direct glass drive of lcd glass. see the ?lcd direct drive? section on page 48 for details. 6.4.11 adjustable output level this section applies only to sio pins. sio port pins support the ability to provide a regulated high output level for interface to external signals that are lower in voltage than the sio?s respective vddio. sio pins are individually configurable to output either the standard vddio level or the regulated output, which is based on an internally generated reference. typically the voltage dac (vdac) is used to generate the reference (see figure 6-12 ). the dac on page 49 has more details on vdac use and reference routing to the sio pins. resistive pull up and pull down drive modes are not available with sio in regulated output mode. 6.4.12 adjustable input level this section applies only to sio pins. sio pins by default support the standard cmos and lvttl input levels but also support a differential mode with program mable levels. sio pins are grouped into pairs. each pair sh ares a reference generator block which, is used to set the digital input buffer reference level for interface to external signals that differ in voltage from vddio. the reference sets the pins voltage threshold for a high logic level (see figure 6-12 ). available input thresholds are: ? 0.5 vddio ? 0.4 vddio ? 0.5 vref ? vref typically the voltage dac (vdac) generates the vref reference. the dac on page 49 has more details on vdac use and reference routing to the sio pins. note 10. gpios with opamp outputs are not recommended for use with capsense.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 34 of 109 figure 6-12. sio reference for input and output 6.4.13 sio as comparator this section applies only to sio pins. the adjustable input level feature of the sios as explained in the adjustable input level section can be used to construct a comparator. the threshold for the comparator is provided by the sio's reference generator. the reference generator has the option to set the analog signal routed through the analog global line as threshold for the comparator. note that a pair of sio pins share the same threshold. the digital input path in figure 6-9 on page 30 illustrates this functionality. in the figure, ?refe rence level? is the analog signal routed through the analog glob al. the hysteresis feature can also be enabled for the input buffer of the sio, which increases noise immunity for the comparator. 6.4.14 hot swap this section applies only to sio pins. sio pins support ?hot swap? capability to plug into an application without loading the signals that are connected to the sio pins even when no power is applied to the psoc device. this allows the unpowered psoc to maintain a high impedance load to the external device while also preventing the psoc from being powered through a sio pin?s protection diode. powering the device up or down while connected to an operational i2c bus may cause tr ansient states on the sio pins. the overall i2c bus design should take this into account. 6.4.15 over voltage tolerance all i/o pins provide an over voltage tolerance feature at any operating vdd. ? there are no current limitations fo r the sio pins as they present a high impedance load to the external circuit. ? the gpio pins must be limited to 100 a using a current limiting resistor. gpio pins clamp the pi n voltage to approximately one diode above the vddio supply. ? in case of a gpio pin configured for analog input/output, the analog voltage on the pin must not exceed the vddio supply voltage to which the gpio belongs. a common application for this feat ure is connection to a bus such as i 2 c where different devices are running from different supply voltages. in the i 2 c case, the psoc chip is configured into the open drain, drives low mode for the sio pin. this allows an external pull up to pull the i 2 c bus voltage above the psoc pin supply. for example, the psoc chip could operate at 1.8 v, and an external device could run from 5 v. note that the sio pin?s vih and vil levels are determi ned by the associated vddio supply pin. the sio pin must be in one of the following modes: 0 (high impedance analog), 1 (high impedance digital), or 4 (open drain drives low). see figure 6-11 for details. absolute maximum ratings for the device must be observed for all i/o pins. 6.4.16 reset configuration while reset is active all i/os are reset to and held in the high impedance analog state. after rese t is released, the state can be reprogrammed on a port-by-port basis to pull down or pull up. to ensure correct reset operation, the port reset configuration data is stored in special nonvolatile regi sters. the stored reset data is automatically transferred to the port reset configuration registers at reset release. 6.4.17 low power functionality in all low power modes the i/o pins retain their state until the part is awakened and changed or reset. to awaken the part, use a pin interrupt, because the port interrupt logic continues to function in all low power modes. 6.4.18 special pin functionality some pins on the device include additional special functionality in addition to their gpio or sio functionality. the specific special function pins are listed in ?pinouts? on page 6. the special features are: ? digital ? 4- to 25-mhz crystal oscillator ? 32.768-khz crystal oscillator ? wake from sleep on i 2 c address match. any pin can be used for i 2 c if wake from sleep is not required. ? jtag interface pins ? swd interface pins ? swv interface pins ? traceport interface pins ? external reset ? analog ? high current idac output ? external reference inputs 6.4.19 jtag boundary scan the device supports standard jtag boundary scan chains on all pins for board level test. pin drive logic driver vhigh reference generator sio_ref digital input digital output input path output path vinref voutref
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 35 of 109 7. digital subsystem the digital programmable system creates applicat ion specific combinations of both standard and advanced digital peripherals and custom logic functions. these peripherals and logic are then interconnected to each other and to any pin on the device, providing a high level of design flexibility and ip security. the features of the digital programmable system are outlined here to provide an overview of capabilities and architecture. you do not need to interact directly with the programmable digital system at the hardware and regi ster level. psoc creator provides a high level schematic capture graphical interface to automatically place and route resources similar to plds. the main components of the digital programmable system are: ? universal digital blocks (udb) - these form the core functionality of the digital pr ogrammable system. udbs are a collection of uncommitted logic (pld) and structural logic (datapath) optimized to create all common embedded peripherals and customized functio nality that are application or design specific. ? universal digital block array - udb blocks are arrayed within a matrix of programmable interconnect. the udb array structure is homogeneous and allows for flexible mapping of digital functions onto the array. the array supports extensive and flexible routing interconnects between udbs and the digital system interconnect. ? digital system interconnect (dsi) - digital signals from udbs, fixed function peripherals, i/o pi ns, interrupts, dma, and other system core signals are attached to the dsi to implement full featured device connectivity. the dsi allows any digital function to any pin or other feature rout ability when used with the udb array. figure 7-1. cy8c52lp digital programmable architecture 7.1 example peripherals the flexibility of the cy8c52lp family?s udbs and analog blocks allow you to create a wide range of components (peripherals). the most common peripherals were built and characterized by cypress and are shown in the pso c creator component catalog. however, you may also create your own custom components using psoc creator. using psoc creator, you may also create their own components for reuse within their organization, for example sensor interfaces, proprietary algorithms, and display interfaces. the number of components available through psoc creator is too numerous to list in the da tasheet, and the list is always growing. an example of a component available for use in cy8c52lp family, but, not explicitly called out in this datasheet is the uart component. 7.1.1 example digital components the following is a sample of the digital components available in psoc creator for the cy8c52lp family. the exact amount of hardware resources (udbs, rout ing, ram, flash) used by a component varies with the features selected in psoc creator for the component. ? communications ? i 2 c ? uart ? spi ? functions ? emif ? pwms ? timers ? counters ? ? logic ? not ? or ? xor ? and 7.1.2 example analog components the following is a sample of the analog components available in psoc creator for the cy8c52lp family. the exact amount of hardware resources (sc/ct blo cks, routing, ra m, flash) used by a component varies with t he features selected in psoc creator for the component. ? adc ? successive approximation (sar adc) ? dacs ? current ? voltage ? pwm ? comparators io port digital core system and fixed function peripherals udb array udb array io port io port io port dsi routing interface dsi routing interface digital core system and fixed function peripherals udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb udb
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 36 of 109 7.1.3 example system function components the following is a sample of the system function components available in psoc creator for the cy8c52lp family. the exact amount of hardware resources ( udbs, routing, ram, flash) used by a component varies with t he features selected in psoc creator for the component. ? capsense ? lcd drive ? lcd control ? filters 7.1.4 designing with psoc creator 7.1.4.1 more than a typical ide a successful design tool allows for the rapid development and deployment of both simple and complex designs. it reduces or eliminates any learning curve. it makes the integration of a new design into the production stream straightforward. psoc creator is that design tool. psoc creator is a full featur ed integrated development environment (ide) for hardware and software design. it is optimized specifically for psoc devices and combines a modern, powerful software development platform with a sophisticated graphical design tool. this unique combination of tools makes psoc creator the most flexible embedded design platform available. graphical design entry simplifie s the task of configuring a particular part. you can select the required functionality from an extensive catalog of components and place it in your design. all components are parameterized and have an editor dialog that allows you to tailor functionality to your needs. psoc creator automatically config ures clocks and routes the i/o to the selected pins and then generates apis to give the application complete control over the hardware. changing the psoc device configuration is as simple as adding a new component, setting its parameters, and rebuilding the project. at any stage of development you are free to change the hardware configuration and even the target processor. to retarget your application (hardware and software) to new devices, even from 8- to 32-bit families, just select the new device and rebuild. you also have the ability to change the c compiler and evaluate an alternative. components are designed for portability and are validated against all devices, from all families, and against all supported tool chains. switching compilers is as easy as editing the from the project options an d rebuilding the application with no errors from the genera ted apis or boot code. 7.1.4.2 component catalog the component catalog is a repository of reusable design elements that select device functionality and customize your psoc device. it is populated wit h an impressive selection of content; from simple primitives such as logic gates and device registers, through the digital timers, counters and pwms, plus analog components such as adc and dac, and communication protocols such as i 2 c and usb. see ?example peripherals? section on page 35 for more details about available peripherals. all content is fully characteri zed and carefully documented in datasheets with code examples, ac/dc specifications, and user code ready apis. 7.1.4.3 design reuse the symbol editor gives you the ability to develop reusable components that can significantly re duce future design time. just draw a symbol and associate that symbol with your proven design. psoc creator allows fo r the placement of the new symbol anywhere in the component catalog along with the content provided by cypress. yo u can then reuse your content as many times as you want, and in any number of projects, without ever having to revisit t he details of the implementation. 7.1.4.4 software development anchoring the tool is a modern, highly customizable user interface. it includes project m anagement and integrated editors for c and assembler source code, as well the design entry tools. project build control leverages compiler technology from top commercial vendors such as arm ? limited, keil?, and codesourcery (gnu). free versions of keil c51 and gnu c compiler (gcc) for arm, with no rest rictions on code size or end product distribution, are includ ed with the tool distribution. upgrading to more optimizing compilers is a snap with support for the professional keil c51 product and arm realview? compiler. 7.1.4.5 nonintrusive debugging with jtag (4-wire) and swd (2-wire) debug connectivity available on all devices, the psoc creator debugger offers full control over the target device with minimum intrusion. breakpoints and code execution commands are all readily available from toolbar buttons and an impressive lineup of windows?register, locals, watch, call stack, memory and peripherals ? make for an unparalleled level of visibility into the system. psoc creator contains all the tools necessary to complete a design, and then to maintain and extend that design for years to come. all steps of the design flow are carefully integrated and optimized for ease-of-use and to maximize productivity.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 37 of 109 7.2 universal digital block the universal digital block (udb ) represents an evolutionary step to the next generation of psoc embedded digital peripheral functionality. the architecture in first generation psoc digital blocks provides coarse progra mmability in which a few fixed functions with a small number of options are available. the new udb architecture is the optima l balance between configuration granularity and efficient implementation. a cornerstone of this approach is to provide the ability to customize the devices digital operation to match application requirements. to achieve this, udbs consist of a combination of uncommitted logic (pld), structured logic (dat apath), and a flexible routing scheme to provide interconnect between these elements, i/o connections, and other peripherals. udb functionality ranges from simple self contained functions that are implemented in one udb, or even a portion of a udb (unused resources are available for other functions), to more complex functions that require multiple udbs. examples of basic functions are timers, counters, crc generators, pwms, dead band generators, and communications functions, such as uarts, spi, and i 2 c. also, the pld blocks and conn ectivity provide fu ll featured general purpose programmable logic within the limits of the available resources. figure 7-2. udb block diagram the main component blocks of the udb are: ? pld blocks: there are two small plds per udb. these blocks take inputs from the routing array and form registered or combinational sum-of-products logic. plds are used to implement state machines, state bits, and combinational logic equations. pld configuration is automatically generated from graphical primitives. ? datapath module: this 8-bit wide datapat h contains structured logic to implement a dynamically configurable alu, a variety of compare configurations and co ndition generation. this block also contains input/output fifos, which are the primary parallel data interface between the cpu/dma system and the udb. ? status and control module: the primary role of this block is to provide a way for cpu firmware to interact and synchronize with udb operation. ? clock and reset module: this block provides the udb clocks and reset selection and control. 7.2.1 pld module the primary purpose of the pld blocks is to implement logic expressions, state machines, sequencers, look up tables, and decoders. in the simple st use model, consider the pld blocks as a standalone resource onto which general purpose rtl is synthesized and mapped. the more common and efficient use model is to create digital func tions from a combination of pld and datapath blocks, where the pld implements only the random logic and state portion of the function while the datapath (alu) implements the more structured elements. figure 7-3. pld 12c4 structure one 12c4 pld block is shown in figure 7-3 . this pld has 12 inputs, which feed across eight product terms. each product term (and function) can be from 1 to 12 inputs wide, and in a given product term, the true (t) or complement (c) of each input can be selected. the product terms are summed (or function) to create the pld outputs. a sum can be from 1 to 8 product terms wide. the 'c' in 12c4 indicates that the width of the or gate (in this case 8) is constant across all outputs (rather than variable as in a 22v10 device). this pla like structure gives maximum flexibility and insures that all inputs and outputs are permutable for ease of allocation by the software tools. there are two 12c4 plds in each udb. 7.2.2 datapath module the datapath contains an 8-bit si ngle cycle alu, with associated compare and condition generation logic. this datapath block is optimized to implement embedded functions, such as timers, counters, integrators, pwms, prs, crc, shifters and dead band generators and many others. pld 12c4 (8 pts) pld 12c4 (8 pts) datapath clock and reset control routing channel datapath chaining pld chaining status and control pt0 in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc tc pt1 pt2 pt3 pt4 pt5 pt6 pt7 tttttttt tttttttt tttttttt tttttttt and array or array mc0 mc1 mc2 out0 out1 out2 out3 mc3 carry in carry out
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 38 of 109 figure 7-4. datapath top level 7.2.2.6 working registers the datapath contains six primary working registers, which are accessed by cpu firmware or dma during normal operation. 7.2.2.7 dynamic datapath configuration ram dynamic configuration is the ability to change the datapath function and internal configuration on a cycle-by-cycle basis, under sequencer control. this is implemented using the 8-word 16-bit configuration ram, wh ich stores eight unique 16-bit wide configurations. the address input to this ram controls the sequence, and can be routed from any block connected to the udb routing matrix, most typicall y pld logic, i/o pins, or from the outputs of this or other datapath blocks. alu the alu performs eight general purpose functions. they are: ? increment ? decrement ? add ? subtract ? logical and ? logical or ? logical xor ? pass, used to pass a value through the alu to the shift register, mask, or another udb register independent of the alu operation, these functions are available: ? shift left ? shift right ? nibble swap ? bitwise or mask a0 a1 d0 d1 pi alu mask shift data registers output muxes f1 f0 fifos accumulators po a0 a1 d0 d1 output to programmable routing chaining control store ram 8 word x 16 bit parallel input/output (to/from programmable routing) input from programmable routing input muxes to/from next datapath to/from previous datapath datapath control phub system bus r/w access to all registers conditions: 2 compares, 2 zero detect, 2 ones detect overflow detect 6 6 table 7-1. working datapath registers name function description a0 and a1 accumulators these are sources and sinks for the alu and also sources for the compares. d0 and d1 data registers these are sources for the alu and sources for the compares. f0 and f1 fifos these are the primary interface to the system bus. they can be a data source for the data registers and accumulators or they can capture data from the accumu- lators or alu. ea ch fifo is four bytes deep.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 39 of 109 7.2.2.8 conditionals each datapath has two compar es, with bit masking options. compare operands include the two accumulators and the two data registers in a variety of configurations. other conditions include zero detect, all ones detect, and overflow. these conditions are the primary datapat h outputs, a selection of which can be driven out to the udb routing matrix. conditional computation can use the built in chaining to neighboring udbs to operate on wider data widths without the need to use routing resources. 7.2.2.9 variable msb the most significant bit of an arithmetic and shift function can be programmatically specified. this supports variable width crc and prs functions, and in conjunction with alu output masking, can implement arbitrary width timers, counters and shift blocks. 7.2.2.10 built in crc/prs the datapath has built in support for single cycle cyclic redundancy check (crc) computation and pseudo random sequence (prs) generation of arbitrary width and arbitrary polynomial. crc/prs functions longer than 8 bits may be implemented in conjunction with pld logic, or built in chaining may be use to extend the func tion into neighboring udbs. 7.2.2.11 input/output fifos each datapath contains two four-byte deep fifos, which can be independently configured as an i nput buffer (system bus writes to the fifo, datapath internal reads the fifo), or an output buffer (datapath internal writes to the fifo, the system bus reads from the fifo). the fifos generat e status that are selectable as datapath outputs and can theref ore be driven to the routing, to interact with sequencer s, interrupts, or dma. figure 7-5. example fifo configurations 7.2.2.12 chaining the datapath can be configured to chain conditions and signals such as carries and shift data with neighboring datapaths to create higher precision arithm etic, shift, crc/prs functions. 7.2.2.13 time multiplexing in applications that are over sa mpled, or do not need high clock rates, the single alu block in the datapath can be efficiently shared with two sets of register s and condition generators. carry and shift out data from the alu are registered and can be selected as inputs in subsequent cycles. this provides support for 16-bit functions in one (8-bit) datapath. 7.2.2.14 datapath i/o there are six inputs and six outputs that connect the datapath to the routing matrix. inputs fr om the routing provide the configuration for the datapath oper ation to perform in each cycle, and the serial data inputs. inputs can be routed from other udb blocks, other device peripherals, device i/o pins, and so on. the outputs to the routing can be selected from the generated conditions, and the serial data outputs. outputs can be routed to other udb blocks, device per ipherals, interrupt and dma controller, i/o pins, and so on. 7.2.3 status and control module the primary purpose of this circuitry is to coordinate cpu firmware interaction with internal udb operation. figure 7-6. status and control registers the bits of the control register, which may be written to by the system bus, are used to drive into the routing matrix, and thus provide firmware with the opportunity to control the state of udb processing. the status register is read-only and it allows internal udb state to be read out onto th e system bus directly from internal routing. this allows firm ware to monitor the state of udb processing. each bit of these registers has programmable connections to the routing matr ix and routing connections are made depending on the requirem ents of the application. 7.2.3.15 usage examples as an example of control input, a bit in the control register can be allocated as a function enable bit. there are multiple ways to enable a function. in one method the control bit output would be routed to the clock control block in one or more udbs and serve as a clock enable for the selected udb blocks. a status example is a case where a pld or datapath block generated a condition, such as a ?compare true? condi tion that is captured and latched by the status register and then read (and cleared) by cpu firmware. 7.2.3.16 clock generation each subcomponent block of a udb including the two plds, the datapath, and status and control, has a clock selection and control block. this promotes a fine granularity with respect to allocating clocking resources to udb component blocks and allows unused udb resources to be used by other functions for maximum system efficiency. system bus f0 f1 system bus a0/a1/alu d0/d1 a0/a1/alu system bus f1 a0/a1/alu f0 d0 system bus f1 a0 d1 a1 f0 tx/rx dual capture dual buffer routing channel 8-bit status register (read only) 8-bit control register (write/read) system bus
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 40 of 109 7.3 udb array description figure 7-7 shows an example of a 16 udb array. in addition to the array core, there are a dsi ro uting interfaces at the top and bottom of the array. other interfac es that are not explicitly shown include the system inte rfaces for bus and cl ock distribution. the udb array includes multiple horizontal and vertical routing channels each comprised of 96 wires. the wire connections to udbs, at horizontal/vertical inte rsection and at the dsi interface are highly permutable providing ef ficient automatic routing in psoc creator. additionally the routing allows wire by wire segmentation along the vertical and horizontal routing to further increase routing flexibility and capability. figure 7-7. digital system interface structure 7.3.1 udb array programmable resources figure 7-8 shows an example of how functions are mapped into a bank of 16 udbs. the primary programmable resources of the udb are two plds, one datapath and one status/control register. these resources are allocated independently, because they have independently selectable clocks, and therefore unused blocks are allocated to ot her unrelated functions. an example of this is the 8-bit time r in the upper left corner of the array. this function only requires one datapath in the udb, and therefore the pld resources may be allocated to another function. a function such as a quadrature decoder may require more pld logic than one udb can supply and in this case can utilize the unused pld blocks in the 8-bit timer udb. programmable resources in the udb array are generally homogeneous so functions can be mapped to arbitrary boundaries in the array. figure 7-8. functi on mapping example in a bank of udbs 7.4 dsi routing interface description the dsi routing interface is a c ontinuation of the horizontal and vertical routing channels at t he top and bottom of the udb array core. it provides general purpose programmable routing between device peripherals, including udbs, i/os, analog peripherals, interrupts, dma and fixed function peripherals. figure 7-9 illustrates the concept of the digital system interconnect, which connects t he udb array routing matrix with other device peripherals. any digital core or fixed function peripheral that needs programmable routing is connected to this interface. signals in this category include: ? interrupt requests from all digital peripherals in the system. ? dma requests from all digital peripherals in the system. ? digital peripheral data signals that need flexible routing to i/os. ? digital peripheral data signals that need connections to udbs. ? connections to the interrupt and dma controllers. ? connection to i/o pins. ? connection to analog system digital signals. udb udb hv b udb udb hv a udb udb hv b hv a udb udb hv a udb udb hv b udb udb hv a hv b hv b hv a hv b hv a hv a hv b hv a hv b udb udb udb udb system connections system connections udb udb hv b udb udb hv a udb udb hv b hv a udb hv a udb hv b udb hv a hv b udb udb udb udb udb udb uart logic 12-bit pwm i2c slave 8-bit spi 12-bit spi logic 8-bit timer 16-bit pyrs udb 8-bit timer quadrature decoder 16-bit pwm sequencer
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 41 of 109 figure 7-9. digital system interconnect interrupt and dma routing is very flexible in the cy8c52lp programmable architecture. in addition to the numerous fixed function peripherals that can gen erate interrupt requests, any data signal in the udb array routing can also be used to generate a request. a single peripheral may generate multiple independent interrupt requests simplifying system and firmware design. figure 7-10 shows the structure of the idmux (interrupt/dma multiplexer). figure 7-10. interrupt and dma processing in the idmux 7.4.1 i/o port routing there are a total of 20 dsi routes to a typical 8-bit i/o port, 16 for data and four for drive strength control. when an i/o pin is connected to the routing, there are two primary connections available, an input and an output. in conjunction with drive strength c ontrol, this can implement a bidirectional i/o pin. a data output signal has the option to be single synchronized (pipelined) and a data input signal has the option to be double synchronized. the synchronization clock is the system clock (see figure 6-1 ). normally all inputs from pins are synchronized as this is requi red if the cpu interacts with the signal or any signal derived from it. asynchronous inputs have rare uses. an example of this is a feed through of combinational pld logic from input pins to output pins. figure 7-11. i/o pin synchronization routing figure 7-12. i/o pin output connectivity there are four more dsi connections to a given i/o port to implement dynamic output enab le control of pins. this connectivity gives a range of options, from fully ganged 8-bits controlled by one signal, to up to four individually controlled pins. the output enable signal is useful for creating tristate bidirectional pins and buses. figure 7-13. i/o pin output enable connectivity udb array digital system routing i /f digital system routing i /f interrupt controller i2c i/o port pins dma controller i/o port pins delta sigma adc comparators dacs sc/ct blocks global clocks emif global clocks timer counters sar adc dma termout (irqs) dma controller interrupt controller fixed function irqs edge detect edge detect irqs udb array fixed function drqs drqs interrupt and dma processing in idmux 0 1 2 3 0 1 2 do di port i pin 0 do pin1 do pin2 do pin3 do pin4 do pin5 do pin6 do pin7 do 8 io data output connections from the udb array digital system interface port i pin 0 oe pin1 oe pin2 oe pin3 oe pin4 oe pin5 oe pin6 oe pin7 oe 4 io control signal connections from udb array digital system interface
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 42 of 109 7.5 usb psoc includes a dedicated full-speed (12 mbps) usb 2.0 transceiver supporting all four usb transfer types: control, interrupt, bulk, and isochronous. psoc creator provides full configuration support. usb interfaces to hosts through two dedicated usbio pins, which are detailed in the ?i/o system and routing? section on page 28. usb includes the following features: ? eight unidirectional data endpoints ? one bidirectional control endpoint 0 (ep0) ? shared 512-byte buffer for the eight data endpoints ? dedicated 8-byte buffer for ep0 ? three memory modes ? manual memory management with no dma access ? manual memory management with manual dma access ? automatic memory management with automatic dma access ? internal 3.3 v regula tor for transceiver ? internal 48 mhz osc illator that auto locks to usb bus clock, requiring no external crystal for usb (usb equipped parts only) ? interrupts on bus and each endpoint event, with device wakeup ? usb reset, suspend, and resume operations ? bus powered and self powered modes figure 7-14. usb 7.6 timers, counters, and pwms the timer/counter/pwm peripheral is a 16-bit dedicated peripheral providing three of the most common embedded peripheral features. as almost all embedded systems use some combination of timers, counters, and pwms. four of them have been included on this psoc device family. additional and more advanced functionality timers, counters, and pwms can also be instantiated in universal digita l blocks (udbs) as required. psoc creator allows you to choose the timer, counter, and pwm features that they require. the tool set utilizes the most optimal resources available. the timer/counter/pwm peripheral can select from multiple clock sources, with input and ou tput signals connected through the dsi routing. dsi routing allows input and output connections to any device pin and any internal digital signal accessible through the dsi. each of the four instances has a compare output, terminal count output ( optional complementary compare output), and programmable interrupt request line. the timer/counter/pwms are configurab le as free running, one shot, or enable input controlled. the peripheral has timer reset and capture inputs, and a kill input for control of the comparator outputs. the peripheral suppor ts full 16-bit capture. timer/counter/pwm features include: ? 16-bit timer/counter/pwm (down count only) ? selectable clock source ? pwm comparator (configurable for lt, lte, eq, gte, gt) ? period reload on start, reset, and terminal count ? interrupt on terminal count, compare true, or capture ? dynamic counter reads ? timer capture mode ? count while enable signal is asserted mode ? free run mode ? one shot mode (stop at end of period) ? complementary pwm outputs with deadband ? pwm output kill figure 7-15. timer/counter/pwm s i e (serial interface engine) 48 mhz imo arbiter 512 x 8 sram usb i/o d+ d? interrupts system bus external 22 resistors timer / counter / pwm 16-bit clock reset enable capture kill irq compare tc / compare!
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 43 of 109 7.7 i 2 c the i 2 c peripheral provides a synchronous two wire interface designed to interface the psoc device with a two wire i 2 c serial communication bus. it is compatible [11] with i 2 c standard-mode, fast-mode, and fast-mode plus devices as defined in the nxp i2c-bus specification and user manual (um10204). the i2c bus i/o may be implemented with gpio or sio in open-drain modes. additional i 2 c interfaces can be instantiated using universal digital blocks (udbs) in psoc creator, as required. to eliminate the need for excessive cpu intervention and overhead, i 2 c specific support is provided for status detection and generation of framing bits. i 2 c operates as a slave, a master, or multimaster (slave and master) [12] . in slave mode, the unit always listens for a start condition to begin sending or receiving data. master mode supplies the ab ility to generate the start and stop conditions and initiate transactions. multimaster mode provides clock synchronization and arbitration to allow multiple masters on the same bus. if ma ster mode is enabled and slave mode is not enabled, the block does not generate interrupts on externally generated start conditions. i 2 c interfaces through the dsi routing and allows direct connections to any gpio or sio pins. i 2 c provides hardware address detect of a 7-bit address without cpu intervention. additionally the device can wake from low power modes on a 7-bit hardware address match. if wakeup functionality is required, i 2 c pin connections are limited to the two special sets of sio pins. i 2 c features include: ? slave and master, transmitter, and receiver operation ? byte processing for low cpu overhead ? interrupt or polling cpu interface ? support for bus speeds up to 1 mbps ? 7 or 10-bit addressing (10-bit addressing requires firmware support) ? smbus operation (through firmware support - smbus supported in hardware in udbs) ? 7-bit hardware address compare ? wake from low power modes on address match ? glitch filtering (active and alternate-active modes only) data transfers follow the format shown in figure 7-16 . after the start condition (s), a slave address is sent. this address is 7 bits long followed by an eighth bit which is a data direction bit (r/w) - a 'zero' indicates a transmission (write), a 'one' indicates a request for data (read). a data transfer is always terminated by a stop condition (p) generated by the master. figure 7-16. i 2 c complete transfer timing notes 11. the i 2 c peripheral is non-compliant with the nxp i 2 c specification in the following ar eas: analog glitch filter, i/o v ol /i ol , i/o hysteresis. the i 2 c block has a digital glitch filter (not available in sleep mode). the fast-mode minimu m fall-time specification can be met by setting the i/os to sl ow speed mode. see the i/o electrical specifications in ?inputs and outputs? section on page 62 for details. 12. fixed-block i 2 c does not support undefined bus conditions , nor does it support repeated start in sl ave mode. these conditions should be avoid ed, or the udb-based i 2 c component should be used instead. sda scl 1 - 7 8 9 1 - 7 8 9 1 - 7 8 9 start condition address r/w ack data ack data ack stop condition
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 44 of 109 8. analog subsystem the analog programmable system creates application specific combinations of both standard and advanced analog signal processing blocks. these blocks are then interconnected to each other and also to any pin on the device, providing a high level of design flexibility and ip security. the features of the analog subsystem are ou tlined here to provide an overview of capabilities and architecture. ? flexible, configurable analog routin g architecture provided by analog globals, analog mux bus, and analog local buses ? successive approximation (sar) adc ? one 8-bit dac that provides either voltage or current output ? two comparators with optional connection to configurable lut outputs ? capsense subsystem to enabl e capacitive touch sensing ? precision reference for generating an accurate analog voltage for internal analog blocks figure 8-1. analog subsystem block diagram analog interface cmp cmp capsense subsystem dsi array clock distribution decimator config & status registers phub cpu comparators gpio port gpio port dac a n a l o g r o u t i n g a n a l o g r o u t i n g sar adc precision reference
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 45 of 109 the psoc creator software program provides a user-friendly interface to configure the analog connections between the gpio and various analog resources and also connections from one analog resource to another. psoc creator also provides component libraries that allow you to configure the various analog blocks to perfo rm application specific functions. the tool also generates api interface libra ries that allow you to write firmware that allows the communication between the analog peripheral and cpu/memory. 8.1 analog routing the psoc 5lp family of devices has a flexible analog routing architecture that provides the capability to connect gpios and different analog blocks, and also route signals between different analog blocks. one of the strong points of this flexible routing architecture is that it allows dynamic routing of input and output connections to the di fferent analog blocks. for information on how to make pin selections for optimal analog routing, refer to the application note, an58304 - psoc? 3 and psoc? 5 - pin selection for analog designs. 8.1.1 features ? flexible, configurable anal og routing architecture ? 16 analog globals (ag) and two analog mux buses (amuxbus) to connect gpios and the analog blocks ? each gpio is connected to one analog global and one analog mux bus ? 8 analog local buses (abus) to route signals between the different analog blocks ? multiplexers and switches for in put and output selection of the analog blocks 8.1.2 functional description analog globals (ags) and analog mux buses (amuxbus) provide analog connectivity between gpios and the various analog blocks. there are 16 ags in the psoc 5lp family. the analog routing architecture is divided into four quadrants as shown in figure 8-2 . each quadrant has four analog globals (agl[0..3], agl[4..7], agr[0..3 ], agr[4..7]). each gpio is connected to the corresponding ag through an analog switch. the analog mux bus is a shared routing resource that connects to every gpio through an analog switch. there are two amuxbus routes in psoc 5lp, one in the left half (amuxbusl) and one in the right half (amuxbusr), as shown in figure 8-2 . analog local buses (abus) are routing resources located within the analog subsystem and are us ed to route signals between different analog blocks. there are eight abus routes in psoc 5lp, four in the left half (abusl [0:3]) and four in the right half (abusr [0:3]) as shown in figure 8-2 . using the abus saves the analog globals and analog mux buses from being used for interconnecting t he analog blocks. multiplexers and switches exist on the various buses to direct signals into and out of the analog blocks. a multiplexer can have only one connection on at a time, whereas a switch can have multiple connections on simultaneously. in figure 8-2 , multiplexers are indicated by grayed ovals and switches are indicated by transparent ovals.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 46 of 109 figure 8-2. cy8c52lp analog interconnect vddio0 sio p12[3] sio p12[2] gpio p15[3] gpio p15[2] sio p12[1] sio p12[0] gpio p3[7] gpio p3[6] vddio3 vccd vssd vddd gpio p6[0] gpio p6[3] gpio p6[2] gpio p6[1] gpio p15[4] gpio p15[5] gpio p2[0] gpio p2[4] gpio p2[3] gpio p2[2] gpio p2[1] vddio2 gpio p2[5] gpio p2[7] gpio p2[6] sio p12[4] sio p12[5] gpio p6[4] gpio p6[5] gpio p6[6] gpio p6[7] vddio1 sio p12[6] sio p12[7] usb io p15[6] usb io p15[7] vddd vssd vccd gpxt p15[0] gpxt p15[1] gpio p3[5] gpio p3[4] gpio p3[3] gpio p3[2] gpio p3[1] agr[4] agr[7] agr[6] agr[5] agl[0] agl[3] agl[2] agl[1] agr[0] agr[3] agr[2] agr[1] *** * * * * * * * * * denotes pins on all packages v0 i0 vidac 76543210 76543210 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 agl[4] agl[7] agl[6] agl[5] agl[0] agl[3] agl[2] agl[1] agr[0] agr[3] agr[2] agr[1] agr[4] agr[7] agr[6] agr[5] notes: amuxbusr amuxbusl i0 rev #60 10-feb-2012 vssa vssd vcca gpio p0[5] * gpio p0[7] * gpio p1[3] gpio p1[2] gpio p1[1] gpio p1[0] * * * * gpio p1[4] * gpio p1[5] * gpio p1[6] * gpio p1[7] * gpio p5[7] gpio p5[6] gpio p5[5] gpio p5[4] gpio p4[4] gpio p4[7] gpio p4[6] gpio p4[5] gpio p5[2] gpio p5[3] gpio p5[1] gpio p5[0] gpio p4[3] gpio p4[2] abusl0 * * ** * * * * * * * * * * * agl[4] agl[7] agl[6] agl[5] gpio p4[0] gpio p4[1] amuxbusl amuxbusr amuxbusl amuxbusr amuxbusl amuxbusr abusl1 abusl2 abusl3 abusr3 abusr2 abusr1 abusr0 exvrefl exvrefr ind vssb vboost xres vssd * * * * vbat gpio p3[0] gpio p0[6] * lpf in0 out0 in1 out1 mux group switch group connection large ( ~200 ohms) small ( ~870 ohms ) switch resistance vss ref ts adc gpio p0[0] * gpio p0[1] * gpio p0[2] * gpio p0[3] * gpio p0[4] * amuxbusr amuxbusl analog globals analog bus 0123 3210 analog bus analog globals refbufr refbufl in out ref in out ref vssa capsense vssa sar adc vp (+) vn (-) exvrefl2 exvrefl1 refs vrefhi_out exvrefl1 exvrefl2 refbuf_vref1 (1.024v) refbuf_vref2 (1.2v) dac_vref (0.256v) sar_vref2 (1.2v) sar_vref1 (1.024v) abuf_vref_int (1.024v) 3210 0123 lcd signals are not shown. * : vdda * vbe vdda vdda/2 refmux[2:0] dac0 sar0 refsel[1:0] abuf_vref_int (1.024v) refbuf_vref1 (1.024v) refbuf_vref2 (1.2v) refsel[1:0] swout swin swout swin swinn swinp swinp swinp swinn swinp swinn lpf en_resvda comp0 comp1 comparator + - + - cmp1_vref cmp1_vref cmp1_vref refbufl_ cmp refbufr_ cmp swinn cmp0_vref (1.024v) vref_cmp1 (0.256v) vdda cmp_muxvn[1:0] bg_vda_res_en vdda/2 bg_vda_swabusl0 to preserve detail of this image, this image is best vi ewed with a pdf display program or printed on 11? 17? paper.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 47 of 109 8.2 successive approximation adc the psoc 5lp family of devices has a sar adc. this adc is 12-bit at up to 1 msps, with single-ended or differential inputs, making it useful for a wide variety of sampling and control applications. 8.2.1 functional description in a sar adc an analog input signal is sampled and compared with the output of a dac. a binary search algorithm is applied to the dac and used to determine the output bits in succession from msb to lsb. a block diagram of the sar adc is shown in figure 8-3 . figure 8-3. sar adc block diagram the input is connected to the analog globals and muxes. the frequency of the clock is 18 times the sample rate; the clock rate ranges from 1 to 18 mhz. 8.2.2 conversion signals writing a start bit or assertion of a start of frame (sof) signal is used to start a conversion. sof can be used in applications where the sampling period is longer than the conversion time, or when the adc needs to be synchronized to other hardware. this signal is optional and does not need to be connected if the sar adc is running in a continuous mode. a digital clock or udb output can be used to drive this input. when the sar is first powered up or awakened from any of the sleeping modes, there is a power up wait time of 10 s before it is ready to start the first conversion. when the conversion is complete, a status bit is set and the output signal end of frame (eof ) asserts and remains asserted until the value is read by either the dma controller or the cpu. the eof signal may be used to trigger an interrupt or a dma request. 8.2.3 operational modes a one_shot control bit is used to set the sar adc conversion mode to either continuous or one conversion per sof signal. dma transfer of continuous samples, without cpu intervention, is supported. 8.3 comparators the cy8c52lp family of devices contains two comparators in a device. comparators have these features: ? input offset factory trimmed to less than 5 mv ? rail-to-rail common mode input range (v ssa to v dda ) ? speed and power can be traded off by using one of three modes: fast, slow, or ultra low power ? comparator outputs can be routed to look up tables to perform simple logic functions and then can also be routed to digital blocks ? the positive input of the comp arators may be optionally passed through a low pass filter. two filters are provided ? comparator inputs can be connected to gpio or dac output 8.3.1 input and output interface the positive and negative inputs to the comparators come from the analog global buses, the analog mux line, the analog local bus and precision reference through multiplexers. the output from each comparator could be routed to any of the two input luts. the output of that lut is routed to the ud b digital system interface. s/ h dac array vin vrefp vrefn comparator sar digital d0:d11 clock autozero reset clock d0:d11 power filtering power ground vrefp vrefn
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 48 of 109 figure 8-4. analog comparator 8.3.2 lut the cy8c52lp family of devices contains two luts. the lut is a two input, one output lookup table that is driven by one or two of the comparators in the chip. th e output of any lut is routed to the digital system interface of the udb array. from the digital system interface of the udb a rray, these signals can be connected to udbs, dma contro ller, i/o, or the interrupt controller. the lut control word written to a register sets the logic function on the output. the available lut functions and the associated control word is shown in table 8-1 . 8.4 lcd direct drive the psoc lcd driver system is a highly configurable peripheral designed to allow psoc to directly drive a broad range of lcd glass. all voltages are generated on chip, eliminating the need for external components. with a high multiplex ratio of up to 1/16, the cy8c52lp family lcd driver system can drive a maximum of 736 segments. the psoc lcd driver module was also designed with the conservative power budget of portable devices in mind, enabling different lcd drive modes and power down modes to conserve power. psoc creator provides an lcd segment drive component. the component wizard provides easy and flexible configuration of lcd resources. you can specify pins for segments and commons along with other options. the software configures the device to meet the required specifications. this is possible because of the programmability inherent to psoc devices. key features of the psoc lcd segment system are: ? lcd panel direct driving ? type a (standard) and type b (low power) waveform support ? wide operating voltage range support (2 v to 5 v) for lcd panels ? static, 1/2, 1/3, 1/4, 1/5 bias voltage levels ? internal bias voltage generation through internal resistor ladder ? up to 62 total common and segment outputs ? up to 1/16 multiplex for a ma ximum of 16 backplane/common outputs ? up to 62 front plane/segment outputs for direct drive ? drives up to 736 total segments (16 backplane 46 front plane) ? up to 64 levels of soft ware controlled contrast ? ability to move display data from memory buffer to lcd driver through dma (without cpu intervention) anaif + _ + _ comp0 comp1 4 lut0 lut1 lut2 lut3 4 4 4 4 4 4 4 from analog routing from analog routing udbs table 8-1. lut function vs. program word and inputs control word output (a and b are lut inputs) 0000b false (?0?) 0001b a and b 0010b a and (not b ) 0011b a 0100b (not a ) and b 0101b b 0110b a xor b 0111b a or b 1000b a nor b 1001b a xnor b 1010b not b 1011b a or (not b ) 1100b not a 1101b (not a ) or b 1110b a nand b 1111b true (?1?)
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 49 of 109 ? adjustable lcd refresh rate from 10 hz to 150 hz ? ability to invert lcd display for negative image ? three lcd driver drive modes, allowing power optimization figure 8-5. lcd system 8.4.1 lcd segment pin driver each gpio pin contains an lcd driver circuit. the lcd driver buffers the appropriate output of the lcd dac to directly drive the glass of the lcd. a register setting determines whether the pin is a common or segment. the pin?s lcd driver then selects one of the six bias voltages to drive the i/o pin, as appropriate for the display data. 8.4.2 display data flow the lcd segment driver system reads display data and generates the proper output voltages to the lcd glass to produce the desired image. display data resides in a memory buffer in the system sram. each time you need to change the common and segment driver voltages, the next set of pixel data moves from the memory buffer into the port data registers via dma. 8.4.3 udb and lcd segment control a udb is configured to generate the global lcd control signals and clocking. this set of signals is routed to each lcd pin driver through a set of dedicated lcd global routing channels. in addition to generating the global lcd control signals, the udb also produces a dma request to initiate the transfer of the next frame of lcd data. 8.4.4 lcd dac the lcd dac generates the cont rast control and bias voltage for the lcd system. the lcd dac produces up to five lcd drive voltages plus ground, based on the selected bias ratio. the bias voltages are driven out to gpio pins on a dedicated lcd bias bus, as required. 8.5 capsense the capsense system provides a versatile and efficient means for measuring capacitance in applications such as touch sense buttons, sliders, proximity det ection, etc. the capsense system uses a configuration of system resources, including a few hardware functions primarily targeted for capsense. specific resource usage is detailed in the capsense component in psoc creator. a capacitive sensing method using a delta-sigma modulator (csd) is used. it provides capacitance sensing using a switched capacitor technique with a delta-sigma modulator to convert the sensing current to a digital code. 8.6 temp sensor die temperature is used to establish programming parameters for writing flash. die temperatur e is measured using a dedicated sensor based on a forward biased transistor. the temperature sensor has its own auxiliary adc. 8.7 dac the cy8c32 parts contain a dac. the dac is 8-bit and can be configured for either voltage or current output. the dac supports capsense, power supply regulation, and waveform generation. the dac has the following features: ? adjustable voltage or current output in 255 steps ? programmable step size (range selection) ? eight bits of calibration to correct 25% of gain error ? source and sink option for current output ? 8-msps conversion rate for current output ? 1-msps conversion rate for voltage output ? monotonic in nature ? data and strobe inputs can be provided by the cpu or dma, or routed directly from the dsi ? dedicated low-resistance output pin for high-current mode lcd driver block udb dma display ram lcd dac pin global clock phub
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 50 of 109 figure 8-6. dac block diagram 8.7.1 current dac the idac can be configured for the ranges 0 to 31.875 a, 0 to 255 a, and 0 to 2.04 ma. the idac can be configured to source or sink current. 8.7.2 voltage dac for the vdac, the current dac output is routed through resistors. the two ranges available for the vdac are 0 to 1.02 v and 0 to 4.08 v. in voltage mode any load connected to the output of a dac should be purely capacitive (the output of the vdac is not buffered). 9. programming, debug interfaces, resources the cortex-m3 has internal debugging components, tightly integrated with the cp u, providing the following features: ? jtag or swd access ? fpb block for implementing breakpoints and code patches ? dwt block for implementing watc hpoints, trigger resources, and system profiling ? etm for instruction trace ? itm for support of printf-style debugging psoc devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. four interfaces are available: jtag, swd, swv, and traceport. jtag and swd support all programming and debug features of the device. jt ag also supports standard jtag scan chains for board level test and chaining multiple jtag devices to a single jtag connection. the swv and traceport provide trace output from the dwt, etm, and itm. traceport is faster but us es more pins. swv is slower but uses only one pin. for more information on psoc 5 programming, refer to the application note psoc 5 device programming specifications. cortex-m3 debug and trace functionality enables full device debugging in the final system using the stan dard production device. it does not require special interfaces, debugging pods, simulators, or emulators. only the standard programming connections are required to fully support debug. the psoc creator ide software provides fully integrated programming and debug support for psoc devices. the low cost miniprog3 programmer and debugger is designed to provide full programming and debug support of psoc devices in conjunction with the psoc creator ide. psoc jtag, swd, and swv interfaces are fully compatible with industry standard third party tools. all cortex-m3 debug and trace modules are disabled by default and can only be enabled in firmware. if not enabled, the only way to reenable them is to erase the entire device, clear flash protection, and reprogram the de vice with new firmware that enables them. disabling debug and trace features, robust flash protection, and hiding custom analog and digital functionality inside the psoc device provide a level of security not possible with multichip application solutions. additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device. permanently disabling interfaces is not recommended in most applications because the designer then cannot access the device later. because all programming, debug, and test interfaces are disabled when device security is enabled, psocs with device security enabled may not be returned for failure analysis. reference ? source ? scaler ? i source ? range ? 1x , ? 8x , ? 64x i sink ? range ???? 1x , ? 8x , ? 64x ? r ? ? 3r ? ? vout ? ? iout ? ?
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 51 of 109 9.1 jtag interface the ieee 1149.1 compliant jtag interface exists on four or five pins (the ntrst pin is optional). the jtag clock frequency can be up to 12 mhz, or 1/3 of the cpu clock frequency for 8 and 16-bit transfers, or 1/5 of the cpu clock frequency for 32-bit transfers, whichever is least. by default, the jtag pins are enabled on new devices but the jt ag interface can be disabled, allowing these pins to be used as general purpose i/o (gpio) instead. the jtag interface is used for programming the flash memory, debugging, i/o scan chains, and jtag device chaining. figure 9-1. jtag interface connections between psoc 5lp and programmer tck ? (p1[1] tms ? (p1[0]) ?? 5 gnd gnd tck tms ?? 5 xres host programmer psoc 5 tdo tdi (p1[4]) tdi tdo (p1[3]) ntrst ? 6 ntrst (p1[5]) 6 1 the voltage levels of host programmer and the psoc 5 voltage domains involved in programming should be same. the port 1 jtag pins, xres pin (xres_n or p1[2]) are powered by v ddio1 . so, v ddio1 of psoc 5 should be at same voltage level as host v dd . rest of psoc 5 voltage domains ( ? v ddd , ? v dda , ? v ddio0 , ? v ddio2 , ? v ddio3 ) need not be at the same voltage level as host programmer. 2 vdda must be greater than or equal to all other power supplies (vddd, vddio?s) in psoc 5. 3 for power cycle mode programming, xres pin is not required. but the host programmer must have the capability to toggle power (vddd, vdda, all vddio?s) to psoc 5. this may typically require external interface circuitry to toggle power which will depend on the programming setup. the power supplies can be brought up in any sequence, however, once stable, vdda must be greater than or equal to all other supplies. 4 for jtag programming, device reset can also be done wi thout connecting to the xres pin or power cycle mode by using the tms,tck,tdi, tdo pins of psoc 5, and writing to a specific register. but this requires that the dps setting in nvl is not equal to ?debug ports disabled?. 5 by default, psoc 5 is configured for 4-wire jtag mode unless user changes the dps setting. so the tms pin is unidirectional. but if the dps setting is changed to non-jtag mode, the tms pin in jtag is bi-directional as the swd protocol has to be used for acquiring the psoc 5 device initially. after switching from swd to jtag mode, the tms pin will be uni-directional. in such a case, unidirectional buffer should not be used on tms line. 6 ntrst jtag pin (p1[5]) cannot be used to reset the jtag tap controlller during first time programming of psoc 5 as the default setting is 4-wire jtag (ntrst disabled). use the tms, tck pins to do a reset of jtag tap controller. v ddd , ? v dda , ? v ddio0 , ? v ddio1 , ? v ddio2 , ? v ddio3 1, 2, 3, 4 v ssd , ? v ssa xres ? or ? p1[2] ? 4 v dd v dd
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 52 of 109 9.2 swd interface the swd interface is the prefe rred alternative to the jtag interface. it requires only two pins instead of the four or five needed by jtag. swd provides all of the programming and debugging features of jtag at the same speed. swd does not provide access to scan chains or device chaining. the swd clock frequency can be up to 1/3 of the cpu clock frequency. swd uses two pins, either two of the jtag pins (tms and tck) or the usbio d+ and d- pins. the usbio pins are useful for in system programming of usb so lutions that would otherwise require a separate programming connector. one pin is used for the data clock and the other is used for data input and output. swd can be enabled on only one of the pin pairs at a time. this only happens if, within 8 s (key window) after reset, that pin pair (jtag or usb) receives a predetermined sequence of 1s and 0s. swd is used for debugging or for programming the flash memory. the swd interface can be enabled from the jtag interface or disabled, allowing its pins to be used as gpio. unlike jtag, the swd interface can always be reacquired on any device during the key window. it can then be used to reenable the jtag interface, if desired. when using swd or jtag pins as standard gpio, make sure that the gpio functionality and pcb circuits do not interfere with swd or jtag use. figure 9-2. swd interface connections between psoc 5lp and programmer v ssd , ? v ssa v ddd , ? v dda , ? v ddio0 , ? v ddio1 , ? v ddio2 , ? v ddio3 1, 2, 3 swdck ? (p1[1] ? or ? p15[7]) swdio ? (p1[0] ? or ? p15[6]) xres ? or ? p1[2] ?? 3 gnd gnd swdck swdio xres host programmer psoc 5 v dd 1 the voltage levels of the host programmer and the psoc 5 voltage domains involved in programming should be the same. xres pin (xres_n or p1[2]) is powered by v ddio1 . the usb swd pins are powered by v ddd . so for programming using the usb swd pins with xres pin, the v ddd , v ddio1 ? of psoc 5 should be at the same voltage level as host v dd . rest of psoc 5 voltage domains ( ? v dda , ? v ddio0 , ? v ddio2 , ? v ddio3 ) need not be at the same voltage level as host programmer. the port 1 swd pins are powered by v ddio1 . so v ddio1 of psoc 5 should be at same voltage level as host v dd for port 1 swd programming. rest of psoc 5 voltage domains ( ? v ddd , ?? v dda , ? v ddio0 , ? v ddio2 , ? v ddio3 ) need not be at the same voltage level as host programmer. 2 vdda must be greater than or equal to all other power supplies (vddd, vddio?s) in psoc 5. 3 for power cycle mode programming, xres pin is not required. but the host programmer must have the capability to toggle power (vddd, vdda, all vddio?s) to psoc 5. this may typically require external interface circuitry to toggle power which will depend on the programming setup. the power supplies can be brought up in any sequence, however, once stable, vdda must be greater than or equal to all other supplies. v dd
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 53 of 109 9.3 debug features the cy8c52lp supports the following debug features: ? halt and single-step the cpu ? view and change cpu and peri pheral registers, and ram addresses ? six program address breakpoints and two literal access breakpoints ? data watchpoint events to cpu ? patch and remap instruction from flash to sram ? debugging at the full speed of the cpu ? compatible with psoc creator and miniprog3 programmer and debugger ? standard jtag programming and debugging interfaces make cy8c52lp compatible with other popular third-party tools (for example, arm / keil) 9.4 trace features the following trace feat ures are supported: ? instruction trace ? data watchpoint on access to data address, address range, or data value ? trace trigger on data watchpoint ? debug exception trigger ? code profiling ? counters for measuring clock cycles, folded instructions, load/store operations, sleep cycles, cycles per instruction, interrupt overhead ? interrupt events trace ? software event monitoring, ?printf-style? debugging 9.5 swv and traceport interfaces the swv and traceport interfaces provide trace data to a debug host via the cypress minipr og3 or an external trace port analyzer. the 5 pin traceport is used for rapid transmission of large trace streams. the single pin swv mode is used to minimize the number of trace pi ns. swv is shared with a jtag pin. if debugging and tracing are done at the same time then swd may be used with either swv or traceport, or jtag may be used with traceport, as shown in table 9-1 . 9.6 programming features the jtag and swd interfaces provide full programming support. the entire device can be erased, programmed, and verified. designers can increase flas h protection levels to protect firmware ip. flash protection can only be reset after a full device erase. individual flash blocks can be erased, programmed, and verified, if block security settings permit. 9.7 device security psoc 5lp offers an advanced security feature called device security, which permanently disables all test, programming, and debug ports, protecting your application from external access. the device security is activate d by programming a 32-bit key (0x50536f43) to a write once latch (wol). the write once latch is a type of nonvolatile latch (nvl). the cell itself is an nvl with additional logic wrapped around it. each wol device contains four bytes (32 bits) of data. the wrapper outputs a ?1? if a super-majority (28 of 32) of its bits match a pre-determined pattern (0x50536f43); it outputs a ?0? if this majority is not reached. when the output is 1, the write once nv latch locks the part out of debug and test modes; it also permanently gates off the ability to erase or alter the contents of the latch. matching all bits is in tentionally not r equired, so that single (or few) bit failures do not deassert the wol output. the state of the nvl bits after wafer processing is truly random with no tendency toward 1 or 0. the wol only locks the part af ter the correct 32-bit key (0x50536f43) is loaded into the nvl's volatile memory, programmed into the nvl's nonvolat ile cells, and the part is reset. the output of the wol is only sampled on reset and used to disable the access. this pr ecaution prevents anyone from reading, erasing, or altering the contents of the internal memory. you can write the key into the wol to lock out external access only if no flash protection is set (see ?flash security? section on page 17). however, after setting the values in the wol, you still have access to the part until it is reset. therefore, you can write the key into the wol, program the flash protection data, and then reset the part to lock it. if the device is protected with a wol setting, cypress cannot perform failure analysis and, th erefore, cannot accept rmas from customers. the wol can be read out via serial wire debug (swd) port to electrically identify protected parts. you can write the key in wol to lock out external access only if no flash protection is set. for more information on how to take full advantage of the security features in psoc see the psoc 5 trm. disclaimer note the following details of the fl ash code protection features on cypress devices. cypress products meet the specifications contained in their particular cypress datasheets. cypress believes that its family of table 9-1. debug configurations debug and trace configuration gpio pins used all debug and trace disabled 0 jtag 4 or 5 swd 2 swv 1 traceport 5 jtag + traceport 9 or 10 swd + swv 3 swd + traceport 7 table 9-1. debug configurations debug and trace configuration gpio pins used
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 54 of 109 products is one of the most secu re families of its kind on the market today, regardless of how they are used. there may be methods, unknown to cypress, that can breach the code protection features. any of these methods, to our knowledge, would be dishonest and possibly illegal. neither cypress nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? cypress is willing to work with the customer who is concerned about the integrity of their code . code protection is constantly evolving. we at cypress are committed to continuously improving the code protecti on features of our products. 10. development support the cy8c52lp family has a rich set of documentation, development tools, and online resources to assist you during your development process. visit psoc.cypress.com/ getting-started to find out more. 10.1 documentation a suite of documentation, to ensure that you can find answers to your questions quickly, supports the cy8c52lp family. this section contains a list of some of the key documents. software user guide : a step-by-step guide for using psoc creator. the software user guide shows you how the psoc creator build process works in detail, how to use source control with psoc creator, and much more. component datasheets : the flexibility of psoc allows the creation of new peripherals (components) long after the device has gone into production. component datasheets provide all of the information needed to select and use a particular component, including a functional description, api documentation, example code, and ac/dc specifications. application notes : psoc application notes discuss a particular application of psoc in depth; examples include brushless dc motor control and on-chip filtering. application notes often include example projects in addition to the application note document. technical reference manual : psoc creator makes designing with psoc as easy as dragging a peripheral onto a schematic, but, when low level details of the psoc device are required, use the technical reference manual (trm) as your guide. note visit www.arm.com for detailed documentation about the cortex-m3 cpu. 10.2 online in addition to print documentation, the cypress psoc forums connect you with fellow psoc user s and experts in psoc from around the world, 24 hours a day, 7 days a week. 10.3 tools with industry standard cores, programming, and debugging interfaces, the cy8c52lp family is part of a development tool ecosystem. visit us at www.cypress.com/go/psoccreator for the latest information on the revolutionary, easy to use psoc creator ide, supported third party compilers, programmers, debuggers, and development kits.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 55 of 109 11. electrical specifications specifications are valid for ?40 c t a 85 c and t j 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. the unique flexibility of the psoc udbs and analog blocks enable many functions to be implemented in psoc creator components, see the component datasheets for full ac /dc specifications of indi vidual functions. see the ?example peripherals? section on page 35 for further expl anation of psoc creator components. 11.1 absolute maximum ratings table 11-1. absolute maximum ratings dc specifications [13] parameter description conditions min typ max units v dda analog supply voltage relative to v ssa ?0.5 ? 6 v v ddd digital supply voltage relative to v ssd ?0.5 ? 6 v v ddio i/o supply voltage relative to v ssd ?0.5 ? 6 v v cca direct analog core voltage input ?0.5 ? 1.95 v v ccd direct digital core voltage input ?0.5 ? 1.95 v v ssa analog ground voltage v ssd ? 0.5 ? v ssd + 0.5 v v gpio [14] dc input voltage on gpio includes signals sourced by v dda and routed internal to the pin. v ssd ? 0.5 ? v ddio + 0.5 v v sio dc input voltage on sio output disabled v ssd ? 0.5 ? 7 v output enabled v ssd ? 0.5 ? 6 v v ind voltage at boost converter input 0.5 ? 5.5 v v bat boost converter supply v ssd ? 0.5 ? 5.5 v i vddio current per v ddio supply pin ? ? 100 ma i gpio gpio current ?30 ? 41 ma i sio sio current ?49 ? 28 ma i usbio usbio current ?56 ? 59 ma lu latch up current [15] ?140 ? 140 ma esd hbm electrostatic discharge voltage human body model 2000 ? ? v esd cdm electrostatic discharge voltage charge device model 500 ? ? v notes 13. usage above the absolute ma ximum conditions listed in table 11-1 may cause permanent damage to the device. ex posure to absolute maximum conditions for extended periods of time may affect device reliability. the maxi mum storage temperature is 150 c in compliance with jedec stan dard jesd22-a103, high temperature storage life. when used below absolute maximum cond itions but above normal operatin g conditions, the device may not operate to specification. 14. the v ddio supply voltage must be greater than the maximum voltage on the associated gpio pins. maximum voltage on gpio pin v ddio v dda 15. meets or exceeds jedec spec eia/jesd78 ic latch-up test.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 56 of 109 11.2 device level specifications specifications are valid for ?40 c t a 85 c and t j 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. unless otherwise specified, all charts and graphs show typical values. 11.2.1 device level specifications table 11-2. dc specifications parameter description conditions min typ max units v dda analog supply voltage and input to analog core regulator analog core regulator enabled 1.8 ? 5.5 v v dda analog supply voltage, analog regulator bypassed analog core regulator disabled 1.71 1.8 1.89 v v ddd digital supply volt age relative to v ssd digital core regulator enabled 1.8 ? v dda [16] v v ddd digital supply voltage, digital regulator bypassed digital core regulator disabled 1.71 1.8 1.89 v v ddio [17] i/o supply voltage relative to v ssio 1.71 ? v dda [16] v v cca direct analog core voltage input (analog regulator bypass) analog core regulator disabled 1.71 1.8 1.89 v v ccd direct digital core voltage input (digital regulator bypass) digital core regulator disabled 1.71 1.8 1.89 v active mode i dd [18] sum of digital and analog i ddd + i dda . i ddiox for i/os not included. imo enabled, bus clock and cpu clock enabled. cpu executing complex program from flash v ddx = 2.7 v to 5.5 v; f cpu = 3 mhz [19] t = ?40 c ? 1.9 3.8 ma t = 25 c ? 1.9 3.8 t = 85 c ? 23.8 v ddx = 2.7 v to 5.5 v; f cpu = 6 mhz t = ?40 c ? 3.1 5 t = 25 c ? 3.1 5 t = 85 c ? 3.2 5 v ddx = 2.7 v to 5.5 v; f cpu = 12 mhz [19] t = ?40 c ? 5.4 7 t = 25 c ? 5.4 7 t = 85 c ? 5.6 7 v ddx = 2.7 v to 5.5 v; f cpu = 24 mhz [19] t = ?40 c ? 8.9 10.5 t = 25 c ? 8.9 10.5 t = 85 c ? 9.1 10.5 v ddx = 2.7 v to 5.5 v; f cpu = 48 mhz [19] t = ?40 c ? 15.5 17 t = 25 c ? 15.4 17 t = 85 c ? 15.7 17 v ddx = 2.7 v to 5.5 v; f cpu = 62 mhz t = ?40 c ? 18 19.5 t = 25 c ? 18 19.5 t = 85 c ? 18.5 19.5 v ddx = 2.7 v to 5.5 v; f cpu = 74 mhz t = ?40 c ? 26.5 30 t = 25 c ? 26.5 30 t = 85 c ? 27 30 v ddx = 2.7 v to 5.5 v; f cpu = 80 mhz, imo = 3 mhz with pll t = ?40 c ? 22 25.5 t = 25 c ? 22 25.5 t = 85 c ? 22.5 25.5 notes 16. the power supplies can be brought up in any sequence however once stable v dda must be greater than or equal to all other supplies. 17. the v ddio supply voltage must be greater than the maximum voltage on the associated gpio pins. maximum voltage on gpio pin v ddio v dda . 18. the current consumption of additional per ipherals that are implemented only in pr ogrammed logic blocks can be found in their respective datasheets, available in psoc creator, the integrated design environment. to estimate total cu rrent, find cpu current at frequency of interest and add periph eral currents for your particular system from the device datasheet and component datasheets. 19. based on device characteriza tion (not production tested).
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 57 of 109 i dd [20] sleep mode [21] cpu = off rtc = on (= eco32k on, in low-power mode) sleep timer = on (= ilo on at 1khz) [22] wdt = off i 2 c wake = off comparator = off por = on boost = off sio pins in single ended input, unregulated output mode v dd = v ddio = 4.5?5.5 v t = ?40 c ? 1.9 3.1 a t = 25 c ? 2.4 3.6 t = 85 c ? 516 v dd = v ddio = 2.7?3.6 v t = ?40 c ? 1.7 3.1 t = 25 c ? 23.6 t = 85 c ? 4.2 16 v dd = v ddio = 1.71?1.95 v t = ?40 c ? 1.6 3.1 t = 25 c ? 1.9 3.6 t = 85 c ? 4.2 16 comparator = on cpu = off rtc = off sleep timer = off wdt = off i2c wake = off por = on boost = off sio pins in single ended input, unregulated output mode v dd = v ddio = 2.7?3.6 v [23] t = 25 c ? 34.2 a i2c wake = on cpu = off rtc = off sleep timer = off wdt = off comparator = off por = on boost = off sio pins in single ended input, unregulated output mode v dd = v ddio = 2.7?3.6 v [23] t = 25 c ? 1.7 3.6 a hibernate mode hibernate mode current all regulators and oscillators off. sram retention gpio interrupts are active boost = off sio pins in single ended input, unregulated output mode v dd = v ddio = 4.5?5.5 v t = ?40 c ? 0.2 2 a t = 25 c ? 0.24 2 t = 85 c ? 2.6 15 v dd = v ddio = 2.7?3.6 v t = ?40 c ? 0.11 2 t = 25 c ? 0.3 2 t = 85 c ? 215 v dd = v ddio = 1.71?1.95 v t = ?40 c ? 0.9 2 t = 25 c ? 0.11 2 t = 85 c ? 1.8 15 i ddar [23] analog current consumption while device is reset v dda 3.6 v ? 0.3 0.6 ma v dda > 3.6 v ? 1.4 3.3 ma i dddr [23] digital current consumption while device is reset v ddd 3.6 v ? 1.1 3.1 ma v ddd > 3.6 v ? 0.7 3.1 ma i dd_prog [23] current consumption while device programming. sum of digital, analog, and i/os: i ddd + i dda + i ddiox ?1521ma table 11-2. dc specifications (continued) parameter description conditions min typ max units notes 20. the current consumption of additional peri pherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in psoc creator, the integrated design environmen t. to estimate total current, find cpu current at frequency of interest and add p eripheral currents for your particular system from the device datash eet and component datasheets. 21. if v ccd and v cca are externally regulated, the voltage difference between v ccd and v cca must be less than 50 mv. 22. sleep timer generates periodic interrupts to wake up the cpu. this specification applies only to those times that the cpu is off. 23. based on device characterization (not producti on tested). usbio pins tied to ground (vssd).
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 58 of 109 figure 11-1. active mode current vs f cpu , v dd = 3.3 v, temperature = 25 c figure 11-2. i dd vs frequency at 25 c figure 11-3. active mode current vs temperature and f cpu , v dd = 3.3 v figure 11-4. active mode current vs v dd and temperature, f cpu = 24 mhz 15 20 25 n t, ma 0 5 10 0 20406080 curre n cpu frequency, mhz
0.4 0.5 0.6 0.7 a /mhz 0 0.1 0.2 0.3 0 20406080 i dd , m a bus clock, mhz 15 20 25 t, ma 80 mhz 24 mhz 0 5 10 -40-20 0 20406080 curren temperature, c 6 mhz 6 8 10 t, ma 85 c 25 c 0 2 4 1.522.533.544.555.5 curren v dd , v -40 c note 24. based on device characterization (not production tested). table 11-3. ac specifications parameter description conditions min typ max units f cpu cpu frequency 1.71 v v ddd 5.5 v dc ? 80.01 mhz f busclk bus frequency 1.71 v v ddd 5.5 v dc ? 80.01 mhz s vdd v dd ramp rate ? ? 0.066 v/s t io_init [24] time from v ddd /v dda /v ccd /v cca ipor to i/o ports set to their reset states ? ? 10 s t startup [24] time from v ddd /v dda /v ccd /v cca pres to cpu executing code at reset vector v cca /v dda = regulated from v dda /v ddd , no pll used, fast imo boot mode (48 mhz typ.) ? ? 33 s v cca /v ccd = regulated from v dda /v ddd , no pll used, imo boot mode (12 mhz typ.) ? ? 66 s t sleep [24] wakeup from sleep mode ? application of non-lvd interrupt to beginning of execution of next cpu instruction ? ? 25 s t hibernate [24] wakeup form hibernate mode ? application of external interrupt to beginning of execution of next cpu instruction ??150s
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 59 of 109 11.3 power regulators specifications are valid for ?40 c t a 85 c and t j 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. 11.3.1 digital core regulator figure 11-5. analog and digital regulators, v cc vs v dd , 10 ma load figure 11-6. digital regulator psrr vs frequency and v dd 11.3.2 analog core regulator figure 11-7. analog regulator psrr vs frequency and v dd table 11-4. digital core regulator dc specifications parameter description conditions min typ max units v ddd input voltage 1.8 ? 5.5 v v ccd output voltage ? 1.80 ? v regulator output capacitor 10%, x5r ceramic or better. the two v ccd pins must be shorted t ogether, with as short a trace as possible, see power system on page 24 0.9 1 1.1 f 60 80 100 r , db 0 20 40 0.1 1 10 100 1000 psr r frequency, khz vdd=4.5v vdd=3.6v vdd=2.7v table 11-5. analog core regulator dc specifications parameter description conditions min typ max units v dda input voltage 1.8 ? 5.5 v v cca output voltage ? 1.80 ? v regulator output capacitor 10%, x5r ceramic or better ? 1 ? f 60 80 100 r , db 0 20 40 0.1 1 10 100 1000 psr r frequency, khz vdd=4.5v vdd=3.6v vdd=2.7v
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 60 of 109 11.3.3 inductive boost regulator. table 11-6. inductive boost regulator dc specifications [25] unless otherwise specified, ope rating conditions are: l boost = 10 h, c boost = 22 f || 0.1 f, 2 < v bat :v out 4 . parameter description conditions min typ max units v bat input voltage, includes startup voltage [26] i out < 7.5 ma, v out = 1.8 v nominal 0.5 ? 0.6 v external diode required if v bat < 0.9 v 0.6 ? 3.6 v i out load current, steady state [26] v bat = 1.6 ? 3.6 v, v out = 1.6 ? 3.6 v ? ? 75 ma v bat = 1.6 ? 3.6 v, v out = 3.6 ? 5.0 v, external diode ??50ma v bat = 0.5 ? 1.6 v, v out = 1.6 ? 3.6 v ? ? 15 ma v bat = 0.5 ? 1.6 v, v out = 3.6 ? 5.0 v, external diode ??15ma i lpk inductor peak current ? ? 700 ma i q quiescent current boost active mode ? 250 ? a boost sleep mode, i out < 1 a ? 25 ? a v out boost output voltage [27] 1.8 v nominal 1.71 1.8 1.89 v 1.9 v nominal 1.81 1.90 2.00 v 2.0 v nominal 1.90 2.00 2.10 v 2.4 v nominal 2.28 2.40 2.52 v 2.7 v nominal 2.57 2.70 2.84 v 3.0 v nominal 2.85 3.00 3.15 v 3.3 v nominal 3.14 3.30 3.47 v 3.6 v nominal, external diode required 3.42 3.60 3.78 v 5.0 v nominal, external diode required 4.75 5.00 5.25 v v out : v bat ratio of v out to v bat ?? 4ratio reg load load regulation ? ? 5 % reg line line regulation ? ? 5 % notes 25. based on device characteri zation (not production tested). 26. for vbat 0.9 v or vout 3.6 v, an external diode is required. 27. if powering the psoc from boost with vbat = 0.5 v, the imo must be 3 mhz at startup.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 61 of 109 figure 11-8. efficiency vs i out v boost = 3.3 v, l boost = 10 h [29] figure 11-9. efficiency vs i out v boost = 3.3 v, l boost = 22 h [29] table 11-7. inductive boost regulator ac specifications parameter description conditions min typ max units v ripple ripple voltage (peak-to-peak) [28] l boost = 10 h, c boost = 22 f || 0.1 f, 2 < v bat :v out 4, iout = 10 ma ??100mv notes 28. based on device characterizati on (not production tested). 29. typical example. actual efficiency may vary depending on exte rnal component selection, pcb layout, and other design paramete rs. table 11-8. recommended external components for boost circuit parameter description conditions min typ max units l boost boost inductor 4.7 10 22 h c boost filter capacitor [28] l boost = 4.7 h ? 10 ? f l boost = 10 h ? 22 ? f l boost = 22 h ? 22 ? f i f external schottky diode average forward current 1? ? a v r 20 ? ? v 80 82 84 86 88 90 0 10 20 30 40 50 60 70 efficiency, % i out , ma vbat = 2.8 vbat = 2.4 vbat = 1.8 80 82 84 86 88 90 0 10 20 30 40 50 60 70 efficiency, % i out , ma vbat = 2.8 vbat = 2.4 vbat = 1.8
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 62 of 109 11.4 inputs and outputs specifications are valid for ?40 c t a 85 c and t j 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. unless otherwise specified, all charts and graphs show typical values. when the power supplies ramp up, there are low-im pedance connections between each gpio pin and its v ddio supply. this causes the pin voltages to track v ddio until both v ddio and v dda reach the ipor voltage, which can be as high as 1.45 v. at that point the low-impedance connections no longer exist, and the pins change to their normal nvl settings. also, if v dda is less than v ddio , a low-impedance path may exist between a gpio and v dda , causing the gpio to track v dda until v dda becomes greater than or equal to v ddio . 11.4.1 gpio table 11-9. gpio dc specifications parameter description conditions min typ max units v ih input voltage high threshold cmos input, prt[x]ctl = 0 0.7 v ddio ??v v il input voltage low threshold cmo s input, prt[x]ctl = 0 ? ? 0.3 v ddio v v ih input voltage high threshold lvttl input, prt[x]ctl = 1,v ddio < 2.7 v 0.7 v ddio ??v v ih input voltage high threshold lvttl input, prt[x]ctl = 1, v ddio 2.7 v 2.0 ? ? v v il input voltage low threshold lvttl input, prt[x]ctl = 1,v ddio < 2.7 v ? ? 0.3 v ddio v v il input voltage low threshold lvttl input, prt[x]ctl = 1, v ddio 2.7 v ??0.8v v oh output voltage high i oh = 4 ma at 3.3 v ddio v ddio ? 0.6 ? ? v i oh = 1 ma at 1.8 v ddio v ddio ? 0.5 ? ? v v ol output voltage low i ol = 8 ma at 3.3 v ddio ??0.6v i ol = 3 ma at 3.3 v ddio ??0.4v i ol = 4 ma at 1.8 v ddio ??0.6v rpullup pull up resistor 3.5 5.6 8.5 k rpulldown pull down resistor 3.5 5.6 8.5 k i il input leakage current (absolute value) [30] 25 c, v ddio = 3.0 v ? ? 2 na c in input capacitance [30] p0.0, p0.1, p0.2, p3.6, p3.7 ? 17 20 pf p0.3, p0.4, p3.0, p3.1, p3.2 ? 10 15 pf p0.6, p0.7, p15.0, p15.6, p15.7 [31] ?712pf all other gpios ? 5 9 pf v h input voltage hysteresis (schmitt-trigger) [30] ?40?mv idiode current through protection diode to v ddio and v ssio ? ? 100 a rglobal resistance pin to analog global bus 25 c, v ddio = 3.0 v ? 320 ? rmux resistance pin to analog mux bus 25 c, v ddio = 3.0 v ? 220 ? notes 30. based on device characterizati on (not production tested). 31. for information on designing with psoc 3 os cillators, refer to the application note, an54439 - psoc ? 3 and psoc 5 external oscillator .
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 63 of 109 figure 11-10. gpio output high voltage and current figure 11-11. gpio output low voltage and current note 32. based on device characterization (not production tested). table 11-10. gpio ac specifications [32] parameter description conditions min typ max units trisef rise time in fast strong mode 3.3 v v ddio cload = 25 pf ? ? 6 ns tfallf fall time in fast strong mode 3.3 v v ddio cload = 25 pf ? ? 6 ns trises rise time in slow strong mode 3.3 v v ddio cload = 25 pf ? ? 60 ns tfalls fall time in slow strong mode 3.3 v v ddio cload = 25 pf ? ? 60 ns fgpioout gpio output operating frequency 2.7 v < v ddio < 5.5 v, fast strong drive mode 90/10% v ddio into 25 pf ? ? 33 mhz 1.71 v < v ddio < 2.7 v, fast strong drive mode 90/10% v ddio into 25 pf ? ? 20 mhz 3.3 v < v ddio < 5.5 v, slow strong drive mode 90/10% v ddio into 25 pf ? ? 7 mhz 1.71 v < v ddio < 3.3 v, slow strong drive mode 90/10% v ddio into 25 pf ? ? 3.5 mhz fgpioin gpio input operating frequency 90/10% v ddio ??64mhz
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 64 of 109 11.4.2 sio table 11-11. sio dc specifications parameter description conditions min typ max units vinmax maximum input voltage all allowed values of v ddio and vddd, see section 11.1 ??5.5v vinref input voltage reference (differential input mode) 0.5 ? 0.52 v ddio v voutref output voltage reference (regulated output mode) v ddio > 3.7 1 ? v ddio ? 1 v v ddio < 3.7 1 ? v ddio ? 0.5 v v ih input voltage high threshold gpio mode cmos input 0.7 v ddio ??v differential input mode [33] hysteresis disabled sio_ref + 0.2 ? ? v v il input voltage low threshold gpio mode cmos input ? ? 0.3 v ddio v differential input mode [33] hysteresis disabled ? ? sio_ref ? 0.2 v v oh output voltage high unregulated mode i oh = 4 ma, v ddio = 3.3 v v ddio ? 0.4 ? ? v regulated mode [33] i oh = 1 ma sio_ref ? 0.65 ? sio_ref + 0.2 v i oh = 0.1 ma sio_ref ? 0.3 ? sio_ref + 0.2 v no load, i oh = 0 sio_ref ? 0.1 ? sio_ref + 0.1 v v ol output voltage low v ddio = 3.30 v, i ol = 25 ma ? ? 0.8 v v ddio = 3.30 v, i ol = 20 ma ? ? 0.4 v v ddio = 1.80 v, i ol = 4 ma ? ? 0.4 v rpullup pull up resistor 3.5 5.6 8.5 k rpulldown pull down resistor 3.5 5.6 8.5 k i il input leakage current (absolute value) [34] v ih < v ddsio 25 c, v ddsio = 3.0 v, v ih = 3.0 v ? ? 14 na v ih > v ddsio 25 c, v ddsio = 0 v, v ih = 3.0 v ? ? 10 a c in input capacitance [34] ??9pf v h input voltage hysteresis (schmitt-trigger) [34] single ended mode (gpio mode) ? 115?mv differential mode ? 50 ? mv idiode current through protection diode to v ssio ??100a notes 33. see figure 6-9 on page 30 and figure 6-12 on page 34 for more information on sio reference. 34. based on device characterization (not production tested).
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 65 of 109 figure 11-12. sio output high voltage and current, unregulated mode figure 11-13. sio output low voltage and current, unregulated mode figure 11-14. sio output high voltage and current, regulat- ed mode
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 66 of 109 figure 11-15. sio output rise and fall times, fast strong mode, v ddio = 3.3 v, 25 pf load figure 11-16. sio output rise and fall times, slow strong mode, v ddio = 3.3 v, 25 pf load note 35. based on device characterization (not production tested). table 11-12. sio ac specifications [35] parameter description conditions min typ max units trisef rise time in fast strong mode (90/10%) cload = 25 pf, v ddio = 3.3 v ? ? 12 ns tfallf fall time in fast strong mode (90/10%) cload = 25 pf, v ddio = 3.3 v ? ? 12 ns trises rise time in slow strong mode (90/10%) cload = 25 pf, v ddio = 3.0 v ? ? 75 ns tfalls fall time in slow strong mode (90/10%) cload = 25 pf, v ddio = 3.0 v ? ? 60 ns fsioout sio output operating frequency 2.7 v < v ddio < 5.5 v, unregulated output (gpio) mode, fast strong drive mode 90/10% v ddio into 25 pf ? ? 33 mhz 1.71 v < v ddio < 2.7 v, unregu- lated output (gpi o) mode, fast strong drive mode 90/10% v ddio into 25 pf ? ? 16 mhz 3.3 v < v ddio < 5.5 v, unregulated output (gpio) mode, slow strong drive mode 90/10% v ddio into 25 pf ? ? 5 mhz 1.71 v < v ddio < 3.3 v, unregu- lated output (gpio) mode, slow strong drive mode 90/10% v ddio into 25 pf ? ? 4 mhz 2.7 v < v ddio < 5.5 v, regulated output mode, fast strong drive mode output continuously switching into 25 pf ??20mhz 1.71 v < v ddio < 2.7 v, regulated output mode, fast strong drive mode output continuously switching into 25 pf ??10mhz 1.71 v < v ddio < 5.5 v, regulated output mode, slow strong drive mode output continuously switching into 25 pf ??2.5mhz fsioin sio input operating frequency 1.71 v < v ddio < 5.5 v 90/10% v ddio ??66mhz
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 67 of 109 11.4.3 usbio for operation in gpio mode, the standard range for v ddd applies, see device level specifications on page 56. table 11-13. sio comparator specifications [36] parameter description conditions min typ max units vos offset voltage v ddio = 2 v ? ? 68 mv v ddio = 2.7 v ? ? 72 v ddio = 5.5 v ? ? 82 tcvos offset voltage drift with temp ? ? 250 v/c cmrr common mode rejection ratio v ddio = 2 v 30 ? ? db v ddio = 2.7 v 35 ? ? v ddio = 5.5 v 40 ? ? tresp response time ? ? 30 ns table 11-14. usbio dc specifications parameter description conditions min typ max units rusbi usb d+ pull-up resistance [36] with idle bus 0.900 ? 1.575 k rusba usb d+ pull-up resistance [36] while receiving traffic 1.425 ? 3.090 k vohusb static output high [36] 15 k 5% to vss, internal pull-up enabled 2.8 ? 3.6 v volusb static output low [36] 15 k 5% to vss, internal pull-up enabled ? ? 0.3 v vihgpio input voltage high, gpio mode [36] v ddd = 1.8 v 1.5 ? ? v v ddd = 3.3 v 2 ? ? v v ddd = 5.0 v 2 ? ? v vilgpio input voltage low, gpio mode [36] v ddd = 1.8 v ? ? 0.8 v v ddd = 3.3 v ? ? 0.8 v v ddd = 5.0 v ? ? 0.8 v vohgpio output voltage high, gpio mode [36] i oh = 4 ma, v ddd = 1.8 v 1.6 ? ? v i oh = 4 ma, v ddd = 3.3 v 3.1 ? ? v i oh = 4 ma, v ddd = 5.0 v 4.2 ? ? v volgpio output voltage low, gpio mode [36] i ol = 4 ma, v ddd = 1.8 v ? ? 0.3 v i ol = 4 ma, v ddd = 3.3 v ? ? 0.3 v i ol = 4 ma, v ddd = 5.0 v ? ? 0.3 v vdi differential input sensitivity |(d+)?(d?)| ? ? 0.2 v vcm differential input common mode range 0.8 ? 2.5 v vse single ended receiver threshold 0.8 ? 2 v rps2 ps/2 pull-up resistance [36] in ps/2 mode, with ps/2 pull-up enabled 3 ? 7 k rext external usb series resistor [36] in series with each usb pin 21.78 (?1%) 22 22.22 (+1%) zo usb driver output impedance [36] including rext 28 ? 44 c in usb transceiver input capacitance ? ? 20 pf i il input leakage current (absolute value) [36] 25 c, v ddd = 3.0 v ? ? 2 na note 36. based on device characte rization (not production tested).
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 68 of 109 figure 11-17. usbio output high voltage and current, gpio mode figure 11-18. usbio output low voltage and current, gpio mode note 37. based on device characte rization (not production tested). table 11-15. usbio ac specifications [37] parameter description conditions min typ max units tdrate full-speed data rate average bit rate 12 ? 0.25% 12 12 + 0.25% mhz tjr1 receiver data jitter tolerance to next transition ?8 ? 8 ns tjr2 receiver data jitter tolerance to pair transition ?5 ? 5 ns tdj1 driver differential jitter to next transition ?3.5 ? 3.5 ns tdj2 driver differential jitter to pair transition ?4 ? 4 ns tfdeop source jitter for di fferential transition to se0 transition ?2 ? 5 ns tfeopt source se0 interval of eop 160 ? 175 ns tfeopr receiver se0 interval of eop 82 ? ? ns tfst width of se0 interval during differential transition ? ? 14 ns fgpio_out gpio mode outpu t operating frequency 3 v v ddd 5.5 v ? ? 20 mhz v ddd = 1.71 v ? ? 6 mhz tr_gpio rise time, gpio mode, 10%/90% v ddd v ddd > 3 v, 25 pf load ? ? 12 ns v ddd = 1.71 v, 25 pf load ? ? 40 ns tf_gpio fall time, gpio mode, 90%/10% v ddd v ddd > 3 v, 25 pf load ? ? 12 ns v ddd = 1.71 v, 25 pf load ? ? 40 ns
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 69 of 109 figure 11-19. usbio output rise and fall times, gpio mode, v ddd = 3.3 v, 25 pf load 11.4.4 xres 11.5 analog peripherals specifications are valid for ?40 c t a 85 c and t j 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. 11.5.1 voltage reference table 11-16. usb driver ac specifications [38] parameter description conditions min typ max units tr transition rise time ? ? 20 ns tf transition fall time ? ? 20 ns tr rise/fall time matching v usb_5 , v usb_3.3 , see usb dc specifications on page 85 90% ? 111% vcrs output signal crossover voltage 1.3 ? 2 v note 38. based on device characterization (not production tested). table 11-17. xres dc specifications parameter description conditions min typ max units v ih input voltage high threshold 0.7 v ddio ??v v il input voltage low threshold ? ? 0.3 v ddio v rpullup pull up resistor 3.5 5.6 8.5 k c in input capacitance [38] ?3 pf v h input voltage hysteresis (schmitt-trigger) [38] ?100?mv idiode current through protection diode to v ddio and v ssio ??100a table 11-18. xres ac specifications [38] parameter description conditions min typ max units t reset reset pulse width 1 ? ? s table 11-19. voltage reference specifications parameter description conditions min typ max units v ref precision reference voltage initial trimming, 25 c 1.013 (?1%) 1.024 1.035 (+1%) v
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 70 of 109 11.5.2 sar adc figure 11-22. sar adc dnl vs output code, bypassed internal reference mode figure 11-23. sar adc inl vs output code, bypassed internal reference mode table 11-20. sar adc dc specifications parameter description conditions min typ max units resolution ? ? 12 bits number of channels ? single-ended ? ? no of gpio number of channels ? differential differential pair is formed using a pair of neighboring gpio. ??no of gpio/2 monotonicity [39] yes ? ? ge gain error [40] external reference ? ? 0.1 % v os input offset voltage ? ? 2 mv i dd current consumption [39] ?? 1 ma input voltage range ? single-ended [39] v ssa ?v dda v input voltage range ? differential [39] v ssa ?v dda v psrr power supply rejection ratio [39] 70 ? ? db cmrr common mode rejection ratio 70 ? ? db inl integral non linearity [39] v dda 1.71 to 5.5 v, 1 msps, v ref 1 to 5.5 v, bypassed at extref pin ??+2/?1.5lsb v dda 2.0 to 3.6 v, 1 msps, v ref 2 to v dda , bypassed at extref pin ??1.2lsb v dda 1.71 to 5.5 v, 500 ksps, v ref 1 to 5.5 v, bypassed at extref pin ??1.3lsb dnl differential non linearity [39] v dda 1.71 to 5.5 v, 1 msps, v ref 1 to 5.5 v, bypassed at extref pin ??+2/?1lsb v dda 2.0 to 3.6 v, 1 msps, v ref 2 to v dda , bypassed at extref pin no missing codes ??1.7/?0.99lsb v dda 1.71 to 5.5 v, 500 ksps, v ref 1 to 5.5 v, bypassed at extref pin no missing codes ? ? +2/?0.99 lsb r in input resistance [39] ?180 ? k ? notes 39. based on device characteriza tion (not production tested). 40. for total analog system idd < 5 ma, depending on package used. with higher total analog system currents it is recommended th at the sar adc be used in differential mode. 0 0.5 1 , lsb -1 -0.5 0 -2048 0 2048 dnl code (12 bit) 0 0.5 1 l sb -1 -0.5 0 -2048 0 2048 inl, l code (12 bit)
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 71 of 109 figure 11-24. sar adc i dd vs sps, v dda = 5 v, continuous sample mode, extern al reference mode figure 11-25. sar adc noise hi stogram, 100 ksps, internal reference no bypass figure 11-26. sar adc noise histogram, 1 msps, internal reference bypassed note 41. based on device characteriza tion (not production tested). 0.3 0.4 0.5 t, ma 0 0.1 0.2 0 250 500 750 1000 curren sample rate, ksps table 11-21. sar adc ac specifications [41] parameter description conditions min typ max units fclk sar clock frequency 1 ? 18 mhz tc conversion time one conversion requires 18 sar clocks. maximum sample rate is 1 msps 1 ? 18 s startup time ? ? 10 s sinad signal-to-noise ratio 68 ? ? db thd total harmonic distortion ? ? 0.02 % 60 80 100 % 0 20 40 1021 1022 1023 1024 1025 % counts, 12 bit 60 80 100 % 0 20 40 1022 1023 1024 1025 1026 % counts, 12 bit
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 72 of 109 figure 11-27. sar adc noise histogram, 1 msps, external reference 11.5.5 analog globals 60 80 100 % 0 20 40 1020 1021 1022 1023 1024 % counts, 12 bit table 11-22. analog globals dc specifications parameter description conditions min typ max units rppag resistance pin-to-pin through p2[4], agl0, dsm inp, agl1, p2[5] [42, 44] v dda = 3.0 v ? 1500 2200 v dda = 1.71 v ? 1200 1700 rppmuxbus resistance pin-to-pin through p2[3], amuxbusl, p2[4] [43, 44] v dda = 3.0 v ? 700 1100 v dda = 1.71 v ? 600 900 table 11-23. analog globals ac specifications parameter description conditions min typ max units inter-pair crosstalk for analog routes [44] 106??db bwag analog globals 3 db bandwidth [44] v dda = 3.0 v, 25 c ? 26 ? mhz notes 42. based on device characteriza tion (not production tested). 43. the resistance of the analog global and analog mux bus is high if v dda 2.7 v, and the chip is in either sleep or hibernate mode. use of analog global and analog mux bus under these condit ions is not recommended. 44. pin p6[4] to del-sig adc input; calculated, not measured.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 73 of 109 11.5.6 comparator notes 45. the recommended procedure for using a custom trim va lue for the on-chip comparators are found in the trm. 46. based on device characteri zation (not production tested). table 11-24. comparator dc specifications [45, 46] parameter description conditions min typ max units v os input offset voltage in fast mode factory trim, v dda > 2.7 v, v in 0.5 v ?10mv input offset voltage in slow mode factory trim, v in 0.5 v ? 9 mv v os input offset voltage in fast mode custom trim ? ? 4 mv input offset voltage in slow mode custom trim ? ? 4 mv v os input offset voltage in ultra low power mode ?12 ? mv tcvos temperature coefficient, input offset voltage v cm = v dda / 2, fast mode ? 63 85 v/c v cm = v dda / 2, slow mode ? 15 20 v hyst hysteresis hysteresis enable mode ? 10 32 mv v icm input common mode voltage high current / fast mode v ssa ?v dda v low current / slow mode v ssa ?v dda v ultra low power mode v ssa ?v dda ? 1.15 v cmrr common mode rejection ratio ? 50 ? db i cmp high current mode/fast mode ? ? 400 a low current mode/slow mode ? ? 100 a ultra low power mode ? 6 ? a table 11-25. comparator ac specifications [45, 46] parameter description conditions min typ max units t resp response time, high current mode 50 mv overdrive, measured pin-to-pin ? 75 110 ns response time, low current mode 50 mv overdrive, measured pin-to-pin ? 155 200 ns response time, ultra low power mode 50 mv overdrive, measured pin-to-pin ?55 ? s
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 74 of 109 11.5.7 current digital-to-analog converter (idac) all specifications are based on use of t he low-resistance idac output pins (see pin descriptions on page 10 for details). see the idac component data sheet in psoc creator for fu ll electrical specifications and apis. unless otherwise specified, all charts and graphs show typical values. table 11-26. idac dc specifications parameter description conditions min typ max units resolution ? ? 8 bits i out output current at code = 255 range = 2.04 ma, code = 255, v dda 2.7 v, rload = 600 ? ?2.04 ? ma range = 2.04 ma, high mode, code = 255, v dda 2.7 v, rload = 300 ?2.04 ? ma range = 255 a, code = 255, rload = 600 ?255 ? a range = 31.875 a, code = 255, rload = 600 ? 31.875 ? a monotonicity ? ? yes ezs zero scale error ? 0 1 lsb eg gain error range = 2.04 ma ? ? 2.5 % range = 255 a ? ? 2.5 % range = 31.875 a ? ? 3.5 % tc_eg temperature coefficient of gain error range = 2.04 ma ? ? 0.045 % / c range = 255 a ? ? 0.045 % / c range = 31.875 a ? ? 0.05 % / c inl integral nonlinearity sink mode, range = 255 a, codes 8?255, rload = 2.4 k , cload = 15 pf ?0.91 lsb source mode, range = 255 a, codes 8?255, rload = 2.4 k , cload = 15 pf ?1.21.6 lsb source mode, range = 31.875 a, codes 8?255, rload = 20 k ? , cload = 15 pf [47] ?0.92 lsb sink mode, range = 31.875 a, codes 8?255, rload = 20 k ? , cload = 15 pf [47] ?0.92 lsb source mode, range = 2.04 ma, codes 8?255, rload = 600 ? , cload = 15 pf [47] ?0.92 lsb sink mode, range = 2.04 ma, codes 8?255, rload = 600 ? , cload = 15 pf [47] ?0.61 lsb note 47. based on device characte rization (not production tested).
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 75 of 109 dnl differential nonlinearity sink mode, range = 255 a, rload = 2.4 k , cload = 15 pf ?0.31 lsb source mode, range = 255 a, rload = 2.4 k , cload = 15 pf ?0.31 lsb source mode, range = 31.875 a, rload = 20 k ? , cload = 15 pf [48] ?0.21 lsb sink mode, range = 31.875 a, rload = 20 k ? , cload = 15 pf [48] ?0.21 lsb source mode, range = 2.0 4 ma, rload = 600 ? , cload = 15 pf [48] ?0.21 lsb sink mode, range = 2.0 4 ma, rload = 600 ? , cload = 15 pf [48] ?0.21 lsb vcompliance dropout voltage, source or sink mode voltage headroom at max current, rload to v dda or rload to v ssa , v diff from v dda 1? ? v i dd operating current, code = 0 slo w mode, source mode, range = 31.875 a ? 44 100 a slow mode, source mode, range = 255 a, ? 33 100 a slow mode, source mode, range = 2.04 ma ? 33 100 a slow mode, sink mode, range = 31.875 a ? 36 100 a slow mode, sink mode, range = 255 a ? 33 100 a slow mode, sink mode, range = 2.04 ma ? 33 100 a fast mode, source mode, range = 31.875 a ? 310 500 a fast mode, source mode, range = 255 a ? 305 500 a fast mode, source mode, range = 2.04 ma ? 305 500 a fast mode, sink mode, range = 31.875 a ? 310 500 a fast mode, sink mode, range = 255 a ? 300 500 a fast mode, sink mode, range = 2.04 ma ? 300 500 a table 11-26. idac dc specifications (continued) parameter description conditions min typ max units note 48. based on device characte rization (not production tested).
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 76 of 109 figure 11-28. idac inl vs input code, range = 255 a, source mode figure 11-29. idac inl vs input code, range = 255 a, sink mode figure 11-30. idac dnl vs input code, range = 255 a, source mode figure 11-31. idac dnl vs input code, range = 255 a, sink mode figure 11-32. idac inl vs temperature, range = 255 a, fast mode figure 11-33. idac dnl vs temperature, range = 255 a, fast mode 0 0.5 1 l sb -1 -0.5 0 0 32 64 96 128 160 192 224 256 inl, l code, 8-bit 0 0.5 1 l sb -1 -0.5 0 0 32 64 96 128 160 192 224 256 inl, l code, 8-bit 0 0.25 0.5 lsb -0.5 -0.25 0 0 32 64 96 128 160 192 224 256 dnl, code, 8-bit 0 0.25 0.5 lsb -0.5 -0.25 0 0 32 64 96 128 160 192 224 256 dnl, code, 8-bit 05 0.75 1 l sb source mode sink mode 0 0.25 0 . 5 -40-20 0 20406080 inl, l temperature, c 0.3 0.4 0.5 lsb source mode sink mode 0 0.1 0.2 -40-20 0 20406080 dnl, temperature, c
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 77 of 109 figure 11-34. idac full scal e error vs temperature, range = 255 a, source mode figure 11-35. idac full s cale error vs temperature, range = 255 a, sink mode figure 11-36. idac operating current vs temperature, range = 255 a, code = 0, source mode figure 11-37. idac operatin g current vs temperature, range = 255 a, code = 0, sink mode 0 0.5 1 error, % -1 -0.5 0 -40-20 0 20406080 full scale temperature, c 0 0.5 1 error, % -1 -0.5 0 -40-20 0 20406080 full scale temperature, c 200 250 300 350 current, a fast mode slow mode 0 50 100 150 -40-20 0 20406080 operating c temperature, c slow mode 200 250 300 350 c urrent, a fast mode slow mode 0 50 100 150 -40-20 0 20406080 operating c temperature, c slow mode note 49. based on device characte rization (not production tested). table 11-27. idac ac specifications [49] parameter description conditions min typ max units f dac update rate ? ? 8 msps t settle settling time to 0.5 lsb range = 31.875 a, full scale transition, fast mode, 600 15-pf load ? ? 125 ns range = 255 a, full scale transition, fast mode, 600 15-pf load ? ? 125 ns current noise range = 255 a, source mode, fast mode, v dda = 5 v, 10 khz ?340 ?pa/sqrthz
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 78 of 109 figure 11-38. idac step response, codes 0x40 - 0xc0, 255 a mode, source mode, fast mode, v dda = 5 v figure 11-39. idac glitch re sponse, codes 0x7f - 0x80, 255 a mode, source mode, fast mode, v dda = 5 v figure 11-40. idac psrr vs frequency figur e 11-41. idac current noise, 255 a mode, source mode, fast mode, v dda = 5 v 11.5.8 voltage digital to analog converter (vdac) see the vdac component datasheet in psoc creato r for full electrical specifications and apis. unless otherwise specified, all charts and graphs show typical values. 150 200 250 a 0 50 100 00.511.52 iout, time, s 128 130 132 134 a 120 122 124 126 00.511.52 iout, time, s 20 30 40 50 60 p srr, db 0 10 20 0.1 1 10 100 1000 10000 p frequency, khz 255 a, code 0x7f 255 a, code 0xff 100 1000 10000 q rthz 1 10 100 0.01 0.1 1 10 100 pa / s q frequency, khz table 11-28. vdac dc specifications parameter description conditions min typ max units resolution ? 8 ? bits inl1 integral nonlinearity 1 v scale ? 2.1 2.5 lsb inl4 integral nonlinearity [50] 4 v scale ? 2.1 2.5 lsb dnl1 differential nonlinearity 1 v scale ? 0.3 1 lsb dnl4 differential nonlinearity [50] 4 v scale ? 0.3 1 lsb rout output resistance 1 v scale ? 4 ? k 4 v scale ? 16 ? k v out output voltage range, code = 255 1 v scale ? 1.02 ? v 4 v scale, v dda = 5 v ? 4.08 ? v note 50. based on device characte rization (not production tested).
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 79 of 109 figure 11-42. vdac inl vs input code, 1 v mode fi gure 11-43. vdac dnl vs input code, 1 v mode figure 11-44. vdac inl vs temperature, 1 v mode fi gure 11-45. vdac dnl vs temperature, 1 v mode monotonicity ? ? yes ? v os zero scale error ? 0 0.9 lsb eg gain error 1 v scale ? ? 2.5 % 4 v scale ? ? 2.5 % tc_eg temperature coefficient, gain error 1 v scale ? ? 0.03 %fsr / c 4 v scale ? ? 0.03 %fsr / c i dd operating current [51] slow mode ? ? 100 a fast mode ? ? 500 a table 11-28. vdac dc specifications (continued) parameter description conditions min typ max units 0 0.5 1 l sb -1 -0.5 0 0 32 64 96 128 160 192 224 256 inl, l code, 8-bit 0 0.25 0.5 lsb -0.5 -0.25 0 0 32 64 96 128 160 192 224 256 dnl, code, 8-bit note 51. based on device characte rization (not production tested). 05 0.75 1 l sb 0 0.25 0 . 5 -40-20 0 20406080 inl, l temperature, c 0.3 0.4 0.5 lsb 0 0.1 0.2 -40-20 0 20406080 dnl, temperature, c
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 80 of 109 figure 11-46. vdac full scal e error vs temperature, 1 v mode figure 11-47. vdac full scal e error vs temperature, 4 v mode figure 11-48. vdac operating cu rrent vs temperature, 1v mode, slow mode figure 11-49. vdac operating current vs temperature, 1 v mode, fast mode 05 0.75 1 error, % 0 0.25 0 . 5 -40-20 0 20406080 full scale temperature, c 1 1.5 2 error, % 0 0.5 1 -40-20 0 20406080 full scale temperature, c note 52. based on device characte rization (not production tested). 30 40 50 c urrent, a 0 10 20 -40-20 0 20406080 operating c temperature, c 200 300 400 c urrent, a 0 100 200 -40-200 20406080 operating c temperature, c table 11-29. vdac ac speciications [52] parameter description conditions min typ max units f dac update rate 1 v scale ? ? 1000 ksps 4 v scale ? ? 250 ksps tsettlep settling time to 0.1%, step 25% to 75% 1 v scale, cload = 15 pf ? 0.45 1 s 4 v scale, cload = 15 pf ? 0.8 3.2 s tsettlen settling time to 0.1%, step 75% to 25% 1 v scale, cload = 15 pf ? 0.45 1 s 4 v scale, cload = 15 pf ? 0.7 3 s voltage noise range = 1 v, fast mode, v dda = 5 v, 10 khz ?750 ?nv/sqrthz
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 81 of 109 figure 11-50. vdac step response, codes 0x40 - 0xc0, 1 v mode, fast mode, v dda = 5 v figure 11-51. vdac glitch resp onse, codes 0x7f - 0x80, 1 v mode, fast mode, v dda = 5 v figure 11-52. vdac psrr vs frequency figure 11-53. vdac voltage noise, 1 v mode, fast mode, v dda = 5 v 05 0.75 1 t, v 0 0.25 0 . 5 00.511.52 vout time, s 0.52 0.54 t, v 0.48 0.5 0 0.5 1 1.5 2 vout time, s 20 30 40 50 p srr, db 0 10 0.1 1 10 100 1000 p frequency, khz 4 v, code 0x7f 4 v, code 0xff 1000 10000 100000 q rthz 10 100 1000 0.01 0.1 1 10 100 nv/s q frequency, khz
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 82 of 109 11.5.9 temperature sensor 11.5.10 lcd direct drive note 53. based on device characte rization (not production tested). table 11-30. temperature sensor specifications parameter description conditions min typ max units temp sensor accuracy range: ?40 c to +85 c ? 5 ? c table 11-31. lcd direct drive dc specifications [53] parameter description conditions min typ max units i cc lcd block (no glass) device sleep mode with wakeup at 400hz rate to refresh lcd, bus, clock = 3mhz, vddio = vdda = 3v, 8 commons, 16 segments, 1/5 duty cycle, 40 hz frame rate, no glass connected ?81 ? a i cc_seg current per segment driver strong drive mode ? 260 ? a v bias lcd bias range (v bias refers to the main output voltage(v0) of lcd dac) v dda 3 v and v dda v bias 2? 5v lcd bias step size v dda 3 v and v dda v bias ? 9.1 v dda ?mv lcd capacitance per segment/common driver drivers may be combined ? 500 5000 pf maximum segment dc offset vdda 3v and vdda vbias ? ? 20 mv i out output drive current per segment driver) v ddio = 5.5v, strong drive mode 355 ? 710 a table 11-32. lcd direct drive ac specifications [53] parameter description conditions min typ max units f lcd lcd frame rate 10 50 150 hz
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 83 of 109 11.6 digital peripherals specifications are valid for ?40 c t a 85 c and t j 100 c, except where no ted. specifications are valid for 1.71 v to 5.5 v, except where noted. 11.6.1 timer the following specifications apply to the ti mer/counter/pwm peripheral in timer mode. timers can also be implemented in udbs; f or more information, see the timer component datasheet in psoc creator. 11.6.2 counter the following specifications apply to the timer/counter/pwm per ipheral, in counter mode. counters can also be implemented in udbs; for more information, see the count er component datasheet in psoc creator. table 11-33. timer dc specifications [54] parameter description conditions min typ max units block current consumption 16-bit timer, at listed input clock frequency ???a 3 mhz ? 15 ? a 12 mhz ? 60 ? a 48 mhz ? 260 ? a 80 mhz ? 360 ? a table 11-34. timer ac specifications [54] parameter description conditions min typ max units operating frequency dc ? 80.01 mhz capture pulse width (internal) [55] 15 ? ? ns capture pulse width (external) 30 ? ? ns timer resolution [55] 15 ? ? ns enable pulse width [55] 15 ? ? ns enable pulse width (external) 30 ? ? ns reset pulse width [55] 15 ? ? ns reset pulse width (external) 30 ? ? ns notes 54. based on device characterization (not production tested). 55. for correct operation, the minimum timer/counter/ pwm input pulse width is the period of bus clock. table 11-35. counter dc specifications [54] parameter description conditions min typ max units block current consumption 16-bit c ounter, at listed input clock frequency ???a 3 mhz ? 15 ? a 12 mhz ? 60 ? a 48 mhz ? 260 ? a 80 mhz ? 360 ? a table 11-36. counter ac specifications [54] parameter description conditions min typ max units operating frequency dc ? 80.01 mhz capture pulse [55] 15 ? ? ns resolution [55] 15 ? ? ns pulse width [55] 15 ? ? ns pulse width (external) 30 ns
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 84 of 109 11.6.3 pulse width modulation the following specifications apply to the timer/counter/pwm per ipheral, in pwm mode. pwm components can also be implemented in udbs; for more information, see the pwm component datasheet in psoc creator. 11.6.4 i 2 c enable pulse width [56] 15 ? ? ns enable pulse width (external) 30 ? ? ns reset pulse width [56] 15 ? ? ns reset pulse width (external) 30 ? ? ns table 11-36. counter ac specifications [54] (continued) parameter description conditions min typ max units table 11-37. pwm dc specifications [57] parameter description conditions min typ max units block current consumption 16-bit pwm, at listed input clock frequency ???a 3 mhz ? 15 ? a 12 mhz ? 60 ? a 48 mhz ? 260 ? a 80 mhz ? 360 ? a table 11-38. pwm ac specifications [57] parameter description conditions min typ max units operating frequency dc ? 80.01 mhz pulse width [56] 15 ? ? ns pulse width (external) 30 ? ? ns kill pulse width [56] 15 ? ? ns kill pulse width (external) 30 ? ? ns enable pulse width [56] 15 ? ? ns enable pulse width (external) 30 ? ? ns reset pulse width [56] 15 ? ? ns reset pulse width (external) 30 ? ? ns notes 56. for correct operation, the minimum timer/counter/ pwm input pulse width is the period of bus clock. 57. based on device characterization (not production tested). table 11-39. fixed i 2 c dc specifications [57] parameter description conditions min typ max units block current consumption enabled, configured for 100 kbps ? ? 250 a enabled, configured for 400 kbps ? ? 260 a table 11-40. fixed i 2 c ac specifications [57] parameter description conditions min typ max units bit rate ? ? 1 mbps
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 85 of 109 11.6.5 usb note 58. based on device characterization (not production tested). table 11-41. usb dc specifications parameter description conditions min typ max units v usb_5 device supply for usb operation usb configured, usb regulator enabled 4.35 ? 5.25 v v usb_3.3 usb configured, usb regulator bypassed 3.15 ? 3.6 v v usb_3 usb configured, usb regulator bypassed [58] 2.85 ? 3.6 v i usb_configured device supply current in device active mode, bus clock and imo = 24 mhz v ddd = 5 v, f cpu = 1.5 mhz ? 10 ? ma v ddd = 3.3 v, f cpu = 1.5 mhz ? 8 ? ma i usb_suspended device supply current in device sleep mode v ddd = 5 v, connected to usb host, picu configured to wake on usb resume signal ?0.5 ? ma v ddd = 5 v, disconnected from usb host ?0.3 ? ma v ddd = 3.3 v, connected to usb host, picu configured to wake on usb resume signal ?0.5 ? ma v ddd = 3.3 v, disconnected from usb host ?0.3 ? ma
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 86 of 109 11.6.6 universal digital blocks (udbs) psoc creator provides a library of pre-built and tested standard digital peripherals (uart, spi, lin, prs, crc, timer, counter, pwm, and, or, and so on) that are mapped to the udb array. see the component datasheets in psoc creato r for full ac/dc specification s, apis, and example code. figure 11-54. clock to output performance note 59. based on device characte rization (not production tested). table 11-42. udb ac specifications [59] parameter description conditions min typ max units datapath performance f max_timer maximum frequency of 16-bit timer in a udb pair ? ? 67.01 mhz f max_adder maximum frequency of 16-bit adder in a udb pair ? ? 67.01 mhz f max_crc maximum frequency of 16-bit crc/prs in a udb pair ? ? 67.01 mhz pld performance f max_pld maximum frequency of a two-pass pld function in a udb pair ? ? 67.01 mhz clock to output performance t clk_out propagation delay for clock in to data out, see figure 11-54 . 25 c, v ddd 2.7 v ? 20 25 ns t clk_out propagation delay for clock in to data out, see figure 11-54 . worst-case placement, routing, and pin selection ? ? 55 ns
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 87 of 109 11.7 memory specifications are valid for ?40 c t a 85 c and t j 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. 11.7.1 flash 11.7.2 eeprom note 60. see psoc 5 device programming specifications for a description of a low-overhead method of programming psoc 5 flash. table 11-43. flash dc specifications parameter description conditions min typ max units erase and program voltage v ddd pin 1.71 ? 5.5 v table 11-44. flash ac specifications parameter description conditions min typ max units t write row write time (erase + program) ? 15 20 ms t erase row erase time ? 10 13 ms row program time ? 5 7 ms t bulk bulk erase time (256 kb) ? ? 140 ms sector erase time (16 kb) ? ? 15 ms t prog total device programming time no overhead [60] ? 5 7.5 seconds flash data retention time, retention period measured from last erase cycle average ambient temp. t a 55 c, 100 k erase/program cycles 20 ? ? years average ambient temp. t a 85 c, 10 k erase/program cycles 10 ? ? table 11-45. eeprom dc specifications parameter description conditions min typ max units erase and program voltage 1.71 ? 5.5 v table 11-46. eeprom ac specifications parameter description conditions min typ max units t write single row erase/wr ite cycle time ? 10 20 ms eeprom data retention time, retention period measured from last erase cycle average ambient temp, t a 25 c, 1m erase/program cycles 20 ? ? years average ambient temp, t a 55 c, 100 k erase/program cycles 20 ? ? average ambient temp. t a 85 c, 10 k erase/program cycles 10 ? ?
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 88 of 109 11.7.3 nonvolatile latches (nvl) 11.7.4 sram table 11-47. nvl dc specifications parameter description conditions min typ max units erase and program voltage v ddd pin 1.71 ? 5.5 v table 11-48. nvl ac specifications parameter description conditions min typ max units nvl endurance programmed at 25 c 1k ? ? program/ erase cycles programmed at 0 c to 70 c 100 ? ? program/ erase cycles nvl data retention time average ambient temp. t a 55 c 20 ? ? years average ambient temp. t a 85 c 10 ? ? years note 61. based on device characte rization (not production tested). table 11-49. sram dc specifications parameter description conditions min typ max units v sram sram retention voltage [61] 1.2 ? ? v table 11-50. sram ac specifications parameter description conditions min typ max units f sram sram operating frequency dc ? 80.01 mhz
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 89 of 109 11.7.5 external memory interface figure 11-55. asynchronous write and read cycle timing, no wait states table 11-51. asynchronous write and read timing specifications [62] parameter description conditions min typ max units fbus_clock bus clock frequency [63] ??33mhz tbus_clock bus clock period [64] 30.3 ? ? ns twr_setup time from em_data valid to rising edge of em_we and em_ce tbus_clock ? 10 ? ? ns trd_setup time that em_data must be valid before rising edge of em_oe 5??ns trd_hold time that em_data must be valid after rising edge of em_oe 5??ns tbus_clock bus clock em_addr em_ce em_we em_oe em_data write cycle read cycle minimum of 4 bus clock cycles between successive emif accesses trd_setup trd_hold twr_setup notes 62. based on device characterization (not production tested). 63. emif signal timings are limited by gpio frequency limitations. see ?gpio? section on page 62. 64. emif output signals are generally sync hronized to bus clock, so emif signal timings are dependent on bus clock frequency.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 90 of 109 figure 11-55. synchronous write and read cycle timing, no wait states table 11-52. synchronous write and read timing specifications [65] parameter description conditions min typ max units fbus_clock bus clock frequency [66] ??33mhz tbus_clock bus clock period [67] 30.3 ? ? ns twr_setup time from em_data valid to rising edge of em_clock tbus_clock ? 10 ? ? ns trd_setup time that em_data must be valid before rising edge of em_oe 5??ns trd_hold time that em_data must be valid after rising edge of em_oe 5??ns tbus_clock bus clock em_addr em_ce em_adsc em_clock em_we em_oe em_data trd_setup trd_hold write cycle read cycle minimum of 4 bus clock cycles between successive emif accesses twr_setup notes 65. based on device characterization (not production tested). 66. emif signal timings are limited by gpio frequency limitations. see ?gpio? section on page 62. 67. emif output signals are generally sync hronized to bus clock, so emif signal timings are dependent on bus clock frequency.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 91 of 109 11.8 psoc system resources specifications are valid for ?40 c t a 85 c and t j 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. 11.8.1 por with brown out for brown out detect in regulated mode, v ddd and v dda must be 2.0 v. brown out detect is not available in externally regulated mode. 11.8.2 voltage monitors notes 68. based on device characterization (not production tested). 69. this value is calculated, not measured. table 11-53. precise low-voltage reset (pres) with brown out dc specifications parameter description conditions min typ max units presr rising trip voltage factory trim 1.64 ? 1.68 v presf falling trip voltage 1.62 ? 1.66 v table 11-54. power on reset (p or) with brown ou t ac specifications [68] parameter description conditions min typ max units pres_tr [69] response time ? ? 0.5 s v ddd /v dda droop rate sleep mode ? 5 ? v/sec table 11-55. voltage monitors dc specifications parameter description conditions min typ max units lvi trip voltage lvi_a/d_sel[3:0] = 0000b 1.68 1.73 1.77 v lvi_a/d_sel[3:0] = 0001b 1.89 1.95 2.01 v lvi_a/d_sel[3:0] = 0010b 2.14 2.20 2.27 v lvi_a/d_sel[3:0] = 0011b 2.38 2.45 2.53 v lvi_a/d_sel[3:0] = 0100b 2.62 2.71 2.79 v lvi_a/d_sel[3:0] = 0101b 2.87 2.95 3.04 v lvi_a/d_sel[3:0] = 0110b 3.11 3.21 3.31 v lvi_a/d_sel[3:0] = 0111b 3.35 3.46 3.56 v lvi_a/d_sel[3:0] = 1000b 3.59 3.70 3.81 v lvi_a/d_sel[3:0] = 1001b 3.84 3.95 4.07 v lvi_a/d_sel[3:0] = 1010b 4.08 4.20 4.33 v lvi_a/d_sel[3:0] = 1011b 4.32 4.45 4.59 v lvi_a/d_sel[3:0] = 1100b 4.56 4.70 4.84 v lvi_a/d_sel[3:0] = 1101b 4.83 4.98 5.13 v lvi_a/d_sel[3:0] = 1110b 5.05 5.21 5.37 v lvi_a/d_sel[3:0] = 1111b 5.30 5.47 5.63 v hvi trip voltage 5.57 5.75 5.92 v table 11-56. voltage monitors ac specifications parameter description conditions min typ max units lvi_tr [69] response time ? ? 1 s
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 92 of 109 11.8.3 interrupt controller 11.8.4 jtag interface figure 11-56. jtag interface timing notes 70. arm cortex-m3 nvic spec. visit www.arm.com for detailed documentation about the cortex-m3 cpu. 71. based on device characterization (not production tested). 72. f_tck must also be no more than 1/3 cpu clock frequency. table 11-57. interrupt co ntroller ac specifications parameter description conditions min typ max units delay from interrupt signal input to isr code execution from main line code [70] ? ? 12 tcy cpu delay from interrupt signal input to isr code execution from isr code (tail-chaining) [70] ? ? 6 tcy cpu table 11-58. jtag interface ac specifications [71] parameter description conditions min typ max units f_tck tck frequency 3.3 v v ddd 5v ? ? 12 [72] mhz 1.71 v v ddd < 3.3 v ? ? 7 [72] mhz t_tdi_setup tdi setup before tck high (t/10) ? 5 ? ? ns t_tms_setup tms setup before tck high t/4 ? ? t_tdi_hold tdi, tms hold after tck high t = 1/f_tck max t/4 ? ? t_tdo_valid tck low to tdo valid t = 1/f_tck max ? ? 2t/5 t_tdo_hold tdo hold after tck high t = 1/f_tck max t/4 ? ? t_ntrst minimum ntrst pulse width f_tck = 2 mhz 8 ? ? ns tdi tck t_tdi_setup tdo (1/f_tck) t_tdi_hold t_tdo_valid t_tdo_hold tms t_tms_setup t_tms_hold
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 93 of 109 11.8.5 swd interface figure 11-57. swd interface timing 11.8.6 tpiu interface swdio (psoc input) swdck t_swdi_setup swdio (psoc output) (1/f_swdck) t_swdi_hold t_swdo_valid t_swdo_hold table 11-59. swd interface ac specifications [73] parameter description conditions min typ max units f_swdck swdclk frequency 3.3 v v ddd 5v ? ? 12 [74] mhz 1.71 v v ddd < 3.3 v ? ? 7 [74] mhz 1.71 v v ddd < 3.3 v, swd over usbio pins ??5.5 [74] mhz t_swdi_setup swdio input setup before swdck high t = 1/f_swdck max t/4 ? ? t_swdi_hold swdio input hold after swdck high t = 1/f_swdck max t/4 ? ? t_swdo_valid swdck high to swdio output t = 1/f_swdck max ? ? t/2 t_swdo_hold swdio output hold after swdck high t = 1/f_swdck max 1 ? ? ns notes 73. based on device characterization (not production tested). 74. f_swdck must also be no more than 1/3 cpu clock frequency. 75. traceport signal frequency and bit rate are limited by gpio output frequency, see table 11-10 on page 63 . table 11-60. tpiu interface ac specifications [73] parameter description conditions min typ max units traceport (traceclk) frequency ? ? 33 [75] mhz swv bit rate ? ? 33 [75] mbit
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 94 of 109 11.9 clocking specifications are valid for ?40 c t a 85 c and t j 100 c, except where noted. specificat ions are valid for 1.71 v to 5.5 v, except where noted. unless otherwise specified, all charts and graphs show typical values. 11.9.1 internal main oscillator figure 11-58. imo current vs. frequency table 11-61. imo dc specifications [76] parameter description conditions min typ max units icc_imo supply current 74.7 mhz ? ? 730 a 62.6 mhz ? ? 600 a 48 mhz ? ? 500 a 24 mhz ? usb mode with oscillator locking to usb bus ? ? 500 a 24 mhz ? non-usb mode ? ? 300 a 12 mhz ? ? 200 a 6 mhz ? ? 180 a 3 mhz ? ? 150 a 400 500 600 700 n t, a 0 100 200 300 0 1020304050607080 curre n frequency, mhz note 76. based on device characterization (not production tested). table 11-62. imo ac specifications parameter description conditions min typ max units f imo imo frequency stability (with factory trim) 74.7 mhz ?7 ? 7 % 62.6 mhz ?7 ? 7 % 48 mhz ?5 ? 5 % 24 mhz ? non-usb mode ?4 ? 4 % 24 mhz ? usb mode with oscillator locking to usb bus ?0.25 ? 0.25 % 12 mhz ?3 ? 3 % 6 mhz ?2 ? 2 % 3 mhz ?2 ? 2 % tstart_imo startup time [76] from enable (during normal system operation) ??13s
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 95 of 109 figure 11-59. imo frequency variation vs. temperature figure 11-60. imo frequency variation vs. v cc jp-p jitter (peak to peak) [77] f = 24 mhz ? 0.9 ? ns f = 3 mhz ? 1.6 ? ns jperiod jitter (long term) [77] f = 24 mhz ? 0.9 ? ns f = 3 mhz ? 12 ? ns table 11-62. imo ac specifications (continued) parameter description conditions min typ max units note 77. based on device characterization (not production tested).
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 96 of 109 11.9.2 internal low-speed oscillator figure 11-61. ilo frequency variation vs. temperature figure 11-62. ilo frequency variation vs. v dd table 11-63. ilo dc specifications parameter description conditions min typ max units i cc operating current [78] f out = 1 khz ? ? 1.7 a f out = 33 khz ? ? 2.6 a f out = 100 khz ? ? 2.6 a leakage current [78] power down mode ? ? 15 na table 11-64. ilo ac specifications [79] parameter description conditions min typ max units tstart_ilo startup time, all frequencies turbo mode ? ? 2 ms f ilo ilo frequencies 100 khz 45 100 200 khz 1 khz 0.5 1 2 khz 0 25 50 i ation -50 -25 0 -40-20 0 20406080 % var i temperature, c 100 khz 1 khz 0 10 20 i ation -20 -10 0 1.5 2.5 3.5 4.5 5.5 % var i v ddd , v 100 khz 1 khz notes 78. this value is calculated, not measured. 79. based on device characterization (not production tested).
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 97 of 109 11.9.3 mhz external crystal oscillator for more information on crystal or ceramic resonator sele ction for the mhzeco, refer to application note an54439: psoc 3 and psoc 5 external oscillators . 11.9.4 khz external crystal oscillator 11.9.5 external clock reference 11.9.6 phase-locked loop table 11-65. mhzeco ac specifications parameter description conditions min typ max units f crystal frequency range 4 ? 25 mhz table 11-66. khzeco dc specifications [80] parameter description conditions min typ max units i cc operating current low power mode; cl = 6 pf ? 0.25 1.0 a dl drive level ? ? 1 w table 11-67. khzeco ac specifications [80] parameter description conditions min typ max units f frequency ? 32.768 ? khz t on startup time high power mode ? 1 ? s table 11-68. external clock reference ac specifications [80] parameter description conditions min typ max units external frequency range 0 ? 33 mhz input duty cycle range measured at v ddio /2 30 50 70 % input edge rate v il to v ih 0.5 ? ? v/ns table 11-69. pll dc specifications parameter description conditions min typ max units i dd pll operating current in = 3 mhz, out = 80 mhz ? 650 ? a in = 3 mhz, out = 24 mhz ? 200 ? a in = 3 mhz, out = 67 mhz ? 400 ? a table 11-70. pll ac specifications parameter description conditions min typ max units fpllin pll input frequency [81] 1?48mhz pll intermediate frequency [82] output of prescaler 1 ? 3 mhz fpllout pll output frequency [81] 24 ? 80 mhz lock time at startup ? ? 250 s jperiod-rms jitter (rms) [80] ??250ps notes 80. based on device characterization (not production tested). 81. this specification is guaranteed by testing the pll across the specified range using the imo as the source for the pll. 82. pll input divider, q, must be set so that the input fre quency is divided down to the intermediate frequency range. value for q ranges from 1 to 16.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 98 of 109 12. ordering information in addition to the features listed in table 12-1 , every cy8c52lp device includes: up to 256 kb flash, 64 kb sram, 2 kb eeprom, a precision on-chip voltage reference, precision o scillators, flash, ecc, dma, a fixed function i 2 c, jtag/swd programming and debug, external memory interface, boost, and more. in addition to these features, the flexible udbs and analog subsection suppo rt a wide range of peripherals. to assist you in selecting the i deal part, psoc creator makes a part recommendation after you choo se the components required by your application. all cy8c52lp derivatives incorporat e device and flash security in user-selectable security levels; see the trm for details. table 12-1. cy8c52lp family with arm cortex-m3 cpu part number mcu core analog digital i/o [84] package jtag id [85] cpu speed (mhz) flash (kb) sram (kb) eeprom (kb) lcd segment drive adc dac comparators sc/ct analog blocks opamps dfb capsense udbs [83] 16-bit timer/pwm fs usb total i/o gpio sio usbio cy8c5268lti-lp030 67 256 64 2 ? 1x12-bit sar 1 2 0 0 ? ? 24 4 ? 48 38 8 2 68-qfn 0x2e11e069 CY8C5268AXI-LP047 67 256 64 2 ? 1x12-bit sar 1 2 0 0 ? ? 24 4 ? 72 62 8 2 100-tqfp 0x2e12f069 cy8c5267axi-lp051 67 128 32 2 ? 1x12-bit sar 1 2 0 0 ? ? 24 4 ? 72 62 8 2 100-tqfp 0x2e133069 cy8c5267lti-lp089 67 128 32 2 ? 1x12-bit sar 1 2 0 0 ? ? 24 4 ? 48 38 8 2 68-qfn 0x2e159069 cy8c5266lti-lp029 67 64 16 2 ? 1x12-bit sar 1 2 0 0 ? ? 20 4 ? 48 38 8 2 68-qfn 0x2e11d069 cy8c5266axi-lp033 67 64 16 2 ? 1x12-bit sar 1 2 0 0 ? ? 20 4 ? 72 62 8 2 100-tqfp 0x2e121069 cy8c5266axi-lp132 67 64 16 2 ? 1x12-bit sar 1 2 0 0 ? ? 20 4 ? 70 62 8 0 100-tqfp 0x2e184069 cy8c5266lti-lp150 67 64 16 2 ? 1x12-bit sar 1 2 0 0 ? ? 20 4 ? 46 38 8 0 68-qfn 0x2e196069 cy8c5265lti-lp050 67 32 8 2 ? 1x12-bit sar 1 0 0 0 ? ? 20 4 ? 48 38 8 2 68-qfn 0x2e132069 cy8c5265axi-lp056 67 32 8 2 ? 1x12-bit sar 1 0 0 0 ? ? 20 4 ? 72 62 8 2 100-tqfp 0x2e138069 cy8c5265lti-lp058 67 32 8 2 ? 1x12-bit sar 1 2 0 0 ? ? 20 4 ? 48 38 8 2 68-qfn 0x2e13a069 cy8c5265axi-lp082 67 32 8 2 ? 1x12-bit sar 1 2 0 0 ? ? 20 4 ? 72 62 8 2 100-tqfp 0x2e152069 cy8c5287axi-lp095 80 256 64 2 ? 1x12-bit sar 1 2 0 0 ? ? 24 4 ? 72 62 8 2 100-tqfp 0x2e15f069 cy8c5288lti-lp090 80 256 64 2 ? 1x12-bit sar 1 2 0 0 ? ? 24 4 ? 48 38 8 2 68-qfn 0x2e15a069 notes 83. udbs support a wide variety of functiona lity including spi, lin, uart, timer, coun ter, pwm, prs, and others. individual func tions may use a fraction of a udb or multiple udbs. multiple functions can share a single udb. see example peripherals on page 35 for more information on how udbs can be used. 84. the i/o count includes all types of digital i/o: gpio, sio, and the two usb i/o. see i/o system and routing on page 28 for details on the functionality of each of these types of i/o. 85. the jtag id has three major fields. the most significant nibble (left digit) is the version, followed by a 2 byte part numbe r and a 3 nibble manufacturer id.
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 99 of 109 12.1 part numbering conventions psoc 5lp devices follow the part numbering convention described here. all fields are single character alphanumeric (0, 1, 2, ?, 9, a, b, ?, z) unless stated otherwise. cy8cabcdefg-lpxxx ? a: architecture ? 3: psoc 3 ? 5: psoc 5 ? b: family group within architecture ? 2: cy8c52lp family ? 4: cy8c54lp family ? 6: cy8c56lp family ? 8: cy8c58lp family ? c: speed grade ? 6: 67 mhz ? 8: 80 mhz ? d: flash capacity ? 5: 32 kb ? 6: 64 kb ? 7: 128 kb ? 8: 256 kb ? ef: package code ? two character alphanumeric ? ax: tqfp ? lt: qfn ? pv: ssop ? fn: csp ? g: temperature range ? c: commercial ? i: industrial ? a: automotive ? xxx: peripheral set ? three character numeric ? no meaning is associated with these three characters all devices in the psoc 5lp cy8c52lp family comply to rohs-6 specifications, demonstrating the commitment by cypress to lead-free products. lead (pb) is an alloying element in solder s that has resulted in environment al concerns due to potential to xicity. cypress uses nickel-palladium-gold (nipdau) technology for the majority of leadframe-based packages. a high level review of the cypress pb-free position is available on our website. specific package information is also available . package material declaration datasheets (pmdds) identify all substanc es contained within cypress packages. pmdds also confirm the absence of many banned substances. the info rmation in the pmdds will help cypress cust omers plan for recycling or other ?end of life? requirements. architecture cypress prefix family group within architecture speed grade flash capacity package code temperature range peripheral set 5: psoc 5 8: 80 mhz 8: 256 kb ax: tqfp, pv:ssop i: industrial examples cy8c 5 2 x a 8 8ix lpx -x 2: cy8c52 family /pv
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 100 of 109 13. packaging figure 13-1. 68-pin qfn 8x8 with 0.4 mm pitch package outline (sawn version) table 13-1. package characteristics parameter description conditions min typ max units t a operating ambient temperature ?40 25 85 c t j operating junction temperature ?40 ? 100 c t ja package ja (68-pin qfn) ? 15 ? c/watt t ja package ja (100-pin tqfp) ? 34 ? c/watt t jc package jc (68-pin qfn) ? 13 ? c/watt t jc package jc (100-pin tqfp) ? 10 - c/watt table 13-2. solder reflow peak temperature package maximum peak temperature maximum time at peak temperature 68-pin qfn 260 c 30 seconds 100-pin tqfp 260 c 30 seconds table 13-3. package moisture sensitivity level (msl), ipc/jedec j-std-2 package msl 68-pin qfn msl 3 100-pin tqfp msl 3 001-09618 *e
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 101 of 109 figure 13-2. 100-pin tqfp (14 14 1.4 mm) package outline 51-85048 *i
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 102 of 109 14. acronyms table 14-1. acronyms us ed in this document acronym description abus analog local bus adc analog-to-digital converter ag analog global ahb amba (advanced microcontroller bus archi- tecture) high-performance bus, an arm data transfer bus alu arithmetic logic unit amuxbus analog mu ltiplexer bus api application programming interface apsr application program status register arm ? advanced risc machine, a cpu architecture atm automatic thump mode bw bandwidth cmrr common-mode rejection ratio cpu central processing unit crc cyclic redundancy check, an error-checking protocol dac digital-to-analog converter, see also idac, vdac dfb digital filter block dio digital input/output, gpio with only digital capabilities, no analog. see gpio. dma direct memory access, see also td dnl differential nonlinearity, see also inl dnu do not use dr port write data registers dsi digital system interconnect dwt data watchpoint and trace ecc error correcting code eco external crystal oscillator eeprom electrically erasable programmable read-only memory emi electromagnetic interference emif external memory interface eoc end of conversion eof end of frame epsr execution program status register esd electrostatic discharge etm embedded trace macrocell fir finite impulse response, see also iir fpb flash patch and breakpoint fs full-speed gpio general-purpose input/output, applies to a psoc pin hvi high-voltage interrupt, see also lvi, lvd ic integrated circuit idac current dac, see also dac, vdac ide integrated development environment i 2 c, or iic inter-integrated circuit, a communications protocol iir infinite impulse response, see also fir ilo internal low-speed oscillator, see also imo imo internal main oscillator, see also ilo inl integral nonlinearity, see also dnl i/o input/output, see also gpio, dio, sio, usbio ipor initial power-on reset ipsr interrupt program status register irq interrupt request itm instrumentation trace macrocell lcd liquid crystal display lin local interconnect network, a communications protocol. lr link register lut lookup table lvd low-voltage detect, see also lvi lvi low-voltage interrupt, see also hvi lvttl low-voltage transistor-transistor logic mac multiply-accumulate mcu microcontroller unit miso master-in slave-out nc no connect nmi nonmaskable interrupt nrz non-return-to-zero nvic nested vectored interrupt controller nvl nonvolatile latch, see also wol opamp operational amplifier pal programmable array logic, see also pld pc program counter pcb printed circuit board pga programmable gain amplifier phub peripheral hub phy physical layer table 14-1. acronyms us ed in this document (continued) acronym description
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 103 of 109 15. reference documents psoc? 3, psoc? 5 architecture trm psoc? 5 registers trm picu port interrupt control unit pla programmable logic array pld programmable logic device, see also pal pll phase-locked loop pmdd package material declaration datasheet por power-on reset pres precise low-voltage reset prs pseudo random sequence ps port read data register psoc ? programmable system-on-chip? psrr power supply rejection ratio pwm pulse-width modulator ram random-access memory risc reduced-instruct ion-set computing rms root-mean-square rtc real-time clock rtl register transfer language rtr remote transmission request rx receive sar successive approximation register sc/ct switched capaci tor/continuous time scl i 2 c serial clock sda i 2 c serial data s/h sample and hold sio special input/output, gpio with advanced features. see gpio. snr signal-to-noise ratio soc start of conversion sof start of frame table 14-1. acronyms us ed in this document (continued) acronym description spi serial peripheral interface, a communications protocol sr slew rate sram static random access memory sres software reset swd serial wire debug, a test protocol swv single-wire viewer td transaction descriptor, see also dma thd total harmonic distortion tia transimpedance amplifier trm technical reference manual ttl transistor-transistor logic tx transmit uart universal asynchronous transmitter receiver, a communications protocol udb universal digital block usb universal serial bus usbio usb input/output, psoc pins used to connect to a usb port vdac voltage dac, see also dac, idac wdt watchdog timer wol write once latch, see also nvl wres watchdog timer reset xres external reset i/o pin xtal crystal table 14-1. acronyms us ed in this document (continued) acronym description
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 104 of 109 16. document conventions 16.1 units of measure table 16-1. units of measure symbol unit of measure c degrees celsius db decibels ff femtofarads hz hertz kb 1024 bytes kbps kilobits per second khr kilohours khz kilohertz k kilohms ksps kilosamples per second lsb least significant bit mbps megabits per second mhz megahertz m megaohms msps megasamples per second a microamperes f microfarads h microhenrys s microseconds v microvolts w microwatts ma milliamperes ms milliseconds mv millivolts na nanoamperes ns nanoseconds nv nanovolts ohms pf picofarads ppm parts per million ps picoseconds s seconds sps samples per second sqrthz square root of hertz vvolts table 16-1. units of measure (continued) symbol unit of measure
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 105 of 109 appendix: csp package summary general description this section contains preliminary data on the cy8c58 device in a 99-pin csp package. electrical specifications the following specifications show differences in el ectrical specifications for csp package devices. pinout ta b l e 2 shows the pinout for the 99-pin c sp package. since there are four v ddio pins, the set of i/o pins associated with any v ddio may sink up to 100 ma total, same as for the 100-pin and 68-pin devices. table 1. electrical specifications parameter description conditions min typ max units tbd table 2. csp pinout ball name ball name ball name ball name e5 p2[5] l2 vio1 b2 p3[6] c8 vio0 g6 p2[6] k2 p1[6] b3 p3[7] d7 p0[4] g5 p2[7] c9 p4[2] c3 p12[0] e7 p0[5] h6 p12[4] e8 p4[3] c4 p12[1] b9 p0[6] k7 p12[5] k1 p1[7] e3 p15[2] d8 p0[7] l8 p6[4] h2 p12[6] e4 p15[3] d9 p4[4] j6 p6[5] f4 p12[7] a1 nc f8 p4[5] h5 p6[6] j1 p5[4] a9 nc f7 p4[6] j5 p6[7] h1 p5[5] l1 nc e6 p4[7] l7 vssb f3 p5[6] l9 nc e9 vccd k6 ind g1 p5[7] a3 vcca f9 vssd l6 vboost g2 p15[6] a4 vssa g9 vddd k5 vbat f2 p15[7] b7 vssa h9 p6[0] l5 vssd e2 vddd b8 vssa g8 p6[1] l4 xres_n f1 vssd c7 vssa h8 p6[2] j4 p5[0] e1 vccd a5 vdda j9 p6[3] k4 p5[1] d1 p15[0] a6 vssd g7 p15[4] k3 p5[2] d2 p15[1] b5 p12[2] f6 p15[5] l3 p5[3] c1 p3[0] a7 p12[3] f5 p2[0] h4 p1[0] c2 p3[1] c5 p4[0] j7 p2[1] j3 p1[1] d3 p3[2] d5 p4[1] j8 p2[2] h3 p1[2] d4 p3[3] b6 p0[0] k9 p2[3] j2 p1[3] b4 p3[4] c6 p0[1] h7 p2[4] g4 p1[4] a2 p3[5] a8 p0[2] k8 vio2 g3 p1[5] b1 vio3 d6 p0[3]
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 106 of 109 csp ordering information packaging table 3. csp part number mcu core analog digital i/o cpu speed (mhz) flash (kb) sram (kb) eeprom (kb) lcd segment drive adc dac comparators sc/ct analog blocks opamps dfb capsense udbs(96) 16-bit timer/pwm fs usb can 2.0b total i/o gpio sio usb i/o package jtag id[101] cy8c5288fni-lp213 80 256 64 2 4 1x12-bit sar 1 2 0 0 ? 4 24 4 4 ? 72 62 8 2 99 wlcsp 0x2e1d5069 table 4. package characteristics parameter description conditions min typ max units t a operating ambient temperature ?40 25 85 c t j operating junction temperature ?40 ? 100 c t ja package ja (99-pin csp) ? 16.5 ? c/watt t jc package jc (99-pin csp) ? 0.1 ? c/watt table 5. solder reflow peak temperature package maximum peak temperature maximum time at peak temperature 99-pin csp 255 30 s table 6. package moisture sensitivity level (msl), ipc/jedec j-std-2 package msl 99-pin csp msl1
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 107 of 109 figure 2. wlcsp package (5.192 5.940 0.6 mm) 001-88034 **
psoc ? 5lp: cy8c52lp family datasheet document number: 001-84933 rev. *e page 108 of 109 17. revision history description title: psoc ? 5lp: cy8c52lp family datasheet programmable system-on-chip (psoc ? ) document number: 001-84933 revision ecn orig. of change submission date description of change ** 3825653 mkea 12/07/2012 datasheet for new cy8c52lp family. *a 3897878 mkea 02/07/2013 removed preliminary status updated characterization footnotes in electrical specifications . updated conditions for sar adc inl and dnl specifications in table 11-20 updated table 11-64 (ilo ac specifications). changed "udb configuration" to "udb working registers? in ta b l e 5 - 5 . removed references to can. updated vref accuracy. updated inl vidac spec. removed drift specs from voltage reference specifications . *b 3902085 mkea 02/12/2013 changed hibernate wakeup time from 125 s to 200 s in ta b l e 6 - 3 and table 11-3 . *c 4114902 mkea 09/30/2013 added information about 1 kb cache in features . added warning on reset devices in the eeprom section. added dbgen field in ta b l e 5 - 3 . deleted statement about repeat start from the i 2 c section. removed t stg spec from ta b l e 11 - 1 and added a note clarifying the maximum storage temperature range. updated chip idd, regulator, sar adc, idac, and vdac graphs. added min and max values for the regulator output capacitor parameter. updated c in specs in gpio dc specifications and sio dc specifications . updated rise and fall time specs in fast strong mode in table 11-10 , and deleted related graphs. updated voltage reference specifications and imo ac specifications . updated 100-tqfp package diagram. added appendix for csp package (preliminary. *d 4225729 mkea 12/20/2013 added sio comparator specifications. changed t hibernate max value from 200 to 150. updated csp package and ordering information. added 80 mhz parts in table 12-1. *e 4386988 mkea 05/22/2014 updated general description and features . added more information and psoc creator sections. updated jtag ids in ordering information . updated 100-tqfp package diagram.
document number: 001-84933 rev. *e revised may 22, 2014 page 109 of 109 capsense ? , psoc ? 3, psoc ? 5, and psoc ? creator? are trademarks and psoc ? is a registered trademark of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i2c components from cypress or one of its sublic ensed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by philips. arm is a registered trademark, and keil, and realview are trademarks, of arm limited. all products and company names mentioned in this document may be the trad emarks of their respective holders. psoc ? 5lp: cy8c52lp family datasheet ? cypress semiconductor corporation, 2012-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. 18. sales, solutions , and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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