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| 250 ksps, 12 - bit impedance converter, network analyzer data sheet ad5934 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog d evices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2005 C 2012 analog devices, inc. all rights reserved. features programmable output peak - to - peak excitation voltage to a max imum frequency of 100 khz programmable frequency sweep capability with serial i 2 c interface frequency resolution of 27 bits (<0.1 hz) impe dance measurement range from 1 k ? to 10 m? capab le of measuring 100 ? to 1 k? with additional circuitry phase measurement capability system accuracy of 0.5% 2.7 v to 5.5 v power supply operation temperature range : ? 40 c to +125 c 16- lead ssop package applications electrochemical analysis bioelectric al impedance analysis impedance spectroscopy complex impedance measurement corrosion monitoring and protection equipment biomedical and automotive sensors proximity sensing nondestructive testing material property analysis fuel/battery cell condition monit oring general description the ad5934 is a high precision impedance converter system solution that combines an on - board frequency generator with a 12- bit, 250 ksps, analog - to - digital converter (adc). the frequ ency generator allows an external complex impedance to be excited with a known frequency. the response signal from the impedance is sampled by the on - board adc and a discrete fourier transform (dft) is processed by an on - board dsp engine. the dft algorithm returns a real (r) and imaginary (i) data - word at each output frequency. once calibrated, the magnitude of the impedance and relative phase of the impedance at each frequency point along the sweep is easily calculated using the following two equations: ma gnitude = 22 ir + phase = t an ?1 ( i / r ) a similar device , available from analog devices, inc., is t he ad5933 , which is a 2.7 v to 5.5 v , 1 msps, 12 - bit impedance converter , with an internal temperature sensor, available in a 16- lead ssop. functional block dia gram adc (12 bits) vdd/2 dds core (27 bits) dac v bias z() i 2 c interface imaginary register gain real register 1024-point dft lpf scl sda dvdd avdd mclk agnd dgnd r out vout ad5934 rfb vin 05325-001 figure 1.
ad5934 data sheet rev. c | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 i 2 c serial interface timing characteristics .............................. 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 11 system description ......................................................................... 12 transmit stage ............................................................................. 13 frequency sweep command sequence ................................... 14 receive stage ............................................................................... 14 dft operation ........................................................................... 14 impedance calculation .................................................................. 15 magnitude calculation .............................................................. 15 gain factor calculation ............................................................ 15 impedance calculation using gain factor ............................. 15 gain factor variation with frequency .................................... 15 2- point calibration ..................................................................... 16 2- point gain factor calculation .............................................. 16 gain factor setup configuration ............................................. 16 gain factor recalculation ......................................................... 16 gain factor temperature variation ......................................... 17 impedance error ......................................................................... 17 measuring the phase across an impedance ........................... 17 performing a frequency sweep .................................................... 19 register map ................................................................................... 20 control register (register address 0x80, register address 0x81) ............................................................................................. 20 start frequency register (register address 0x82, register address 0x83, register address 0x84) .................................... 21 frequency increment register (r egister address 0x85, register address 0x86, register address 0x87) ..................... 21 number of increments register (register address 0x88, register address 0x89) .............................................................. 22 number of settling time cycles register (register address 0x8a, register address 0x8b) .................................................. 22 status register (register address 0x8f) .................................. 22 real and imaginary data registers (16 bits register address 0x94, register address 0x95, register address 0x96, register address 0x97) .............................................................................. 23 serial bus interface ......................................................................... 24 general i 2 c timing .................................................................... 24 writing/reading to the ad5934 .............................................. 25 block write .................................................................................. 25 read operations ......................................................................... 26 typical applications ....................................................................... 27 measuring small i mpedances ................................................... 27 biomedical: noninvasive blood impedance measurement .. 28 sensor/complex impedance measurement ............................ 29 electro - impedance spectroscopy ............................................. 29 layout and configuration ............................................................. 30 power supply bypassing and grounding ................................ 30 outline dimensions ....................................................................... 31 ordering guide .......................................................................... 31 data sheet ad5934 rev. c | page 3 of 32 revision history 7 /12 rev. b to re v. c changes to pin 10, description column, table 4 and pin 11, description column, table 4 ........................................................... 8 changes to table 6 .......................................................................... 18 deleted choosing a reference for the ad5934 and table 17; renumbered sequentially .............................................................. 30 2/12 rev. a to rev. b deleted evaluation board ................................................. unive rsal changes to impedance error section ........................................... 17 5 /8 rev. 0 to rev. a changes to layout .............................................................. universal changes to features section, general description section, and figure 1 ............................................................................................... 1 deleted table 1; renumbered sequentially ................................... 1 changes to table 1 ............................................................................ 4 changes to table 2 ............................................................................ 6 chang es to figure 3 and table 4 ..................................................... 8 changes to system description section and figure 14 .............. 12 changes to figure 16 ...................................................................... 13 changes to frequency sweep command sequence section and receive stage section ...................................................................... 14 changes to gain factor calculation section and impedance calculatio n using gain factor section ........................................ 15 changes to figure 20 ...................................................................... 16 changes to impedance error section ........................................... 17 add ed measuring the phase across an impedance section ..... 19 add ed figure 28 and figure 29; renumbered sequentially ...... 20 added table 6 ; renumbered sequentially ................................... 20 delete d table 8 ................................................................................ 19 deleted table 1 0 and table 1 1 ....................................................... 20 changes to table 9 .......................................................................... 22 deleted table 14, table 1 6, and table 1 7 ..................................... 22 changes to status register (register address 0x8f) section .... 24 added measuring small impedances section, figure 37, and table 16 ............................................................................................. 29 changes to ta ble 1 7 ........................................................................ 32 add ed evaluation board section .................................................. 34 add ed figure 40 .............................................................................. 35 add ed figure 41 .............................................................................. 36 add ed figure 4 2 .............................................................................. 37 add ed figure 4 3 .............................................................................. 38 add ed table 1 8 ................................................................................ 39 changes to ordering guide ........................................................... 40 6/05 revision 0: initial version ad5934 data sheet rev. c | page 4 of 32 specifications vdd = 3.3 v, mclk = 16.776 mhz, 2 v p - p output excitation voltage @ 30 khz, 200 k? connected between pin 5 and pin 6 ; f eedback resistor = 200 k? connected between pin 4 and pin 5 ; pga gain = 1 , unless otherwise noted . table 1 . y version 1 parameter min typ max uni t test conditions/comments system impedance range 1 k 10 m ? 100 ? to 1 k ? requires extra buffer circuitry, see measuring small impedances section total system accuracy 0.5 % 2 v p - p output excitation voltage at 30 kh z, 200 k? connected bet ween pin 5 and pin 6 system impedance error drift 30 ppm/c transmit stage output frequency range 2 1 100 khz output frequency resolution 0.1 hz <0.1 hz resolution achievable using direct digital synthesis ( dds ) tec hniques mclk frequency 16.776 mhz maximum system clock frequency transmit output voltage range 1 ac output excitation voltage 3 1.98 v p -p refer to figure 4 for output voltage distribution dc bias 4 1.48 v dc b ias of the ac excitation signal ; s ee figure 5 dc output impedance 200 ? t a = 25c short - circuit current to ground at vout 5.8 ma t a = 25c range 2 ac output excitation voltage 3 0.97 v p -p see figure 6 dc bias 4 0.76 v dc bias of output excitation signal ; s ee figure 7 dc output impedance 2.4 k? short - circuit current to ground at vout 0.25 ma range 3 ac output excitation voltage 3 0.383 v p -p see figure 8 dc bias 4 0.31 v dc bias of output excitation signal ; s ee figure 9 dc output impedance 1 k? short - circuit current to ground at vout 0.20 ma range 4 ac output excitation voltage 3 0.198 v p -p see figure 10 dc bias 4 0.173 v dc bias of output excitation signal ; s ee figure 11 dc output impedance 600 ? short - circuit current to ground at vout 0.15 ma system ac characteristics signal -to - noise ratio 60 db total harmonic distortion ?52 db spurious - free dynamic range wide band (0 mhz to 1 mhz) ?56 db narrow b and (5 khz) ?8 5 db data sheet ad5934 rev. c | page 5 of 32 y version 1 parameter min typ max uni t test conditions/comments receive stage input leakage current 1 na to vin pin input capacitance 5 0.01 pf pin capacitance between vout and gnd feedback capacitance , c fb 3 pf feedback capacitance around current - to - voltage amplifier; appears in parallel with fee dback resistor analog - to - digital converter 5 resolution 12 b its sampling rate 250 ksps adc throughput rate logic inputs input high voltage , v ih 0.7 vdd input low voltage , v il 0.3 vdd input current 6 1 a t a = 25 input capacitance 7 pf t a = 25c power requirements vdd 2.7 5.5 v i dd , normal mode 10 15 ma vdd = 3.3 v 17 25 ma vdd = 5.5 v i dd , standby mode 7 ma vdd = 3.3 v; see the control register section 9 ma vdd = 5.5 v i dd , power - down mode 0.7 5 a vdd = 3.3 v 1 8 a vdd = 5.5 v 1 temperature range for y version = ?40 c to +125c, typical at + 25c. 2 the lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the ad5934. 3 the peak - to - peak value of the ac outp ut excitation voltage scales with supply voltage according to the following formula. vdd is the supply voltage. output excitation voltage (v p - p) = [2/3.3] vdd 4 the dc bias value of the output excitation voltage scales with supply voltage according to the following formula. vdd is the supply voltage. output excitation voltage (v p - p) = [2/3.3] vdd 5 guaranteed by design or characterization, not production tested. input capacitance at the vout pin is equal to pin capacitanc e divided by open - loop gain of current - to - voltage amplifier. 6 the accumulation of the currents into pin 8, pin 15, and pin 16. ad5934 data sheet rev. c | page 6 of 32 i 2 c serial interface timing characteristic s vdd = 2.7 v to 5.5 v ; all specifications t min to t max , unless otherwise noted (see fi gure 2 ). table 2 . parameter 1 limit at t min , t max unit description f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd, sta , start/repeated start condition hold time t 5 100 ns min t su, dat , data setup time t 6 2 0.9 s max t hd, dat , data hold time 0 s min t hd, dat , data hold time t 7 0.6 s min t su, sta , setup time for repeated start t 8 0.6 s min t su, sto , stop condition s etup time t 9 1.3 s min t buf , bus free time between a stop and a start condition t 10 300 ns max t r , rise time of sda when transmitting 0 ns min t r , rise time of scl and sda when receiving (cmos compatible) t 11 300 ns max t f , fall time of scl and sda when transmitting 0 ns min t f , fall time of sda when receiving (cmos compatible) 250 ns max t f , fall time of sda when receiving 20 + 0.1 c b 3 ns min t f , fall time of scl and sda when transmitting c b 400 pf max capacitive load for each bus line 1 guaranteed by design and characterization, not production tested . 2 a master device must provide a hold time of at least 300 ns for the sda signal (referred to v ih min of the scl signal) to bridge the undefined falling edge of scl. 3 c b is the total capacitance of one bus line in pf. note that t r and t f a re measured between 0.3 vdd and 0.7 vdd. 05325-002 scl sda start condition repeated start condition stop condition t 9 t 3 t 10 t 11 t 4 t 4 t 6 t 2 t 5 t 7 t 8 t 1 figure 2. i 2 c interface timing diagram data sheet ad5934 rev. c | page 7 of 32 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating dvdd to gnd ?0.3 v to + 7.0 v avdd1 to gnd ?0.3 v to +7.0 v avdd2 to gnd ?0. 3 v to +7.0 v sda/scl to gnd ?0.3 v to vdd + 0.3 v vout to gnd ?0.3 v to vdd + 0.3 v vin to gnd ?0.3 v to vdd + 0.3 v mclk to gnd ?0.3 v to vdd + 0.3 v operating temperature s extended industrial range (y g rade) ?40c to +125c storage temperature range ?65c to +160c maximum junction temperature 150c ssop package , thermal impedance ja 139c/w jc 136c/w reflow soldering (pb - free) peak temperature 260c time at peak temperature 10 sec to 40 sec stresses above those listed under ab solute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposu re to absolute maximum rating conditions for extended periods may affect device reliability. esd caution ad5934 data sheet rev. c | page 8 of 32 pin configuration an d function descriptions nc 1 nc 2 nc 3 rfb 4 scl 16 sda 15 agnd2 14 agnd1 13 vin 5 vout 6 nc 7 dgnd 12 avdd2 11 avdd1 10 mclk notes: 1. it is recommended to tie all supply connections (pin 9, pin 10, and pin 11) and run from a single supply between 2.7v and 5.5v. 2. it is also recommended to connect all ground signals together (pin 12, pin 13, and pin 14). 8 dvdd 9 nc = no connect ad5934 top view (not to scale) 05325-003 figure 3 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 to 3, 7 nc no connect . do not connect to this pin. 4 rfb external feedback resistor . c onnect from pin 4 to pin 5 . this pin set s the gain of the current - to - voltag e amplifier on the receive side . 5 vin inp ut to receive transimpedance amplifier . vin p resents a virtual earth voltage of vdd/2 . 6 vout ex citation voltage signal output . 8 mclk the m aster c lock for the s ystem is supplied by the user . 9 dvdd digital supply voltage . 10 avdd1 analog supply volta ge 1 . used for powering the analog core. 11 avdd2 analog supply voltage 2 . used for internal reference s. 12 dgnd digital ground . 13 agnd1 analog ground 1 . 14 agnd2 analog ground 2 . 15 sda i 2 c? data input . 16 scl i 2 c clock input . data sheet ad5934 rev. c | page 9 of 32 typical performance characteristics 35 0 number of devices 30 25 20 15 10 5 2.06 05325-064 voltage (v) 1.92 1.94 1.96 1.98 2.00 2.02 2.04 mean = 1.9824 sigma = 0.0072 figure 4 . range 1 output excitation voltage distribution , vdd = 3.3 v 1.30 1.75 05325-072 voltage (v) 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 mean = 1.4807 sigma = 0.0252 0 number of devices 30 25 20 15 10 5 figure 5 . range 1 dc bias distribution , vdd = 3.3 v 30 0 number of devices 25 20 15 10 5 05325-066 voltage (v) 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 mean = 0.9862 sigma = 0.0041 figure 6 . range 2 output ex citation voltage distribution , vdd = 3.3 v 0.68 0.86 05325-073 voltage (v) 0.70 0.72 0.74 0.76 0.78 0.80 0.82 0.84 mean = 0.7543 sigma = 0.0099 30 0 number of devices 25 20 15 10 5 figure 7 . range 2 dc bias distribution , vdd = 3.3 v 30 0 0.370 0.400 05325-077 voltage (v) number of devices 25 20 15 10 5 0.375 0.380 0.385 0.390 0.395 mean = 0.3827 sigma = 0.00167 figure 8 . range 3 output excitation voltage distribution , vdd = 3.3 v 0.290 0.320 05325-074 voltage (v) 0.295 0.300 0.305 0.310 0.315 mean = 0.3092 sigma = 0.0014 30 0 number of devices 25 20 15 10 5 figure 9 . range 3 dc bias distribution , vdd = 3.3 v ad5934 data sheet rev. c | page 10 of 32 05325-070 voltage (v) 0.192 0.194 0.196 0.198 0.200 0.202 0.204 0.206 mean = 0.1982 sigma = 0.0008 30 0 number of devices 25 20 15 10 5 figure 10 . range 4 output excitation voltage distribution , vdd = 3.3 v 0.160 0.205 05325-075 voltage (v) 0.165 0.170 0.175 0.180 0.185 0.190 0.195 0.200 mean = 0.1792 sigma = 0.0024 30 0 number of devices 25 20 15 10 5 figure 11 . range 4 dc bias distribution , vdd = 3.3 v 15.8 10.8 0 18 05325-088 mclk frequency (mhz) idd (ma) 15.3 14.8 14.3 13.8 13.3 12.8 12.3 1 1.8 1 1.3 avdd1, avdd2, dvdd connected together output excitation frequency = 30khz rfb, z calibration = 100k? 2 4 6 8 10 12 14 16 figure 12 . typical supply current (idd) vs. mclk frequency 0.4 ?1.0 0 400 05325-028 phase (degrees) phase error (degrees) 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 50 100 150 200 250 300 350 vdd = 3.3v t a = 25c f = 32khz figure 13 . typical phase error data sheet ad5934 rev. c | page 11 of 32 te rminology total system accuracy the ad5934 can accurately measure a range of impedance values to les s than 0.5% of the correct impedance value for supply voltages between 2.7 v to 5.5 v. spurious - free dynamic range (sfdr) along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a dds device. the spurious - free dynamic range refers to the largest spur or harmonic present in the band of interest. the wideband sfdr gives the magnitude of the largest harmonic or spur relative to the magnitude of the fun damental frequency in the 0 hz to nyquist bandwidth. the narrow - band sfdr gives the attenuation of the largest spur or harmonic in a bandwidth of 200 khz, about the fundamental frequency. signal -to - noise ratio (snr) snr is the ratio of the rms value of th e measured output signal to the rms sum of all other spectral components below the nyquist frequency. the value for snr is expressed in decibels. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental, where v1 is t he rms amplitude of the fundamental , and v2, v3, v4, v5, and v6 are the rms amplitudes of the second through the sixth harmonics. thd is defined as v1 v6v5v4v3v2 thd 22222 log20) db ( ++++ = ad5934 data sheet rev. c | page 12 of 32 system description adc (12 bits) vdd/2 dds core (27 bits) dac z() i 2 c interface imaginary register real register mac core (1024 dft) lpf scl sda mclk r out vout ad5934 rfb vin 05325-078 programmable gain amplifier 5 1 windowing of data cos sin microcontroller mclk v bias figure 14 . block overview the ad5934 is a high precision , impedance converter system solution that combines an on - board frequency generator with a 12- bit, 250 ksps adc. the frequency generator allows an external complex impedance to be exci ted with a known frequency. the response signal from the impedance is sampled by the on - board adc and dft processed by an on - board dsp engine. the dft algorithm returns both a real (r) and imaginary (i) data - word at each frequency point along the sweep. the impedance magnitude and phase is easily calculated using the following equations: magnitude = 22 ir + phase = t an ?1 ( i / r ) to characterize an impedance profile z( ), generally a frequency sweep is required such as that shown in figure 15 . 05325-033 frequency (hz) impedance (?) figure 15 . impedance vs. frequency profile the ad5934 permits the user to perform a frequency sweep with a user - defined start frequency, frequency resolution , and number of points in the sweep. in addition, the device allows the user to program the peak - to - peak value of the output sinusoidal signal as an excitation to the external unknown impedance connected between the vout and vin pins. table 5 gives the four possible output peak - to - peak voltages and the corresponding dc bias levels for each range for 3.3 v. these values are ratiometric with vdd. so for a 5 v supply: ppv3 3.3 0.5 98.1 ?== 1range forvoltage excitation output ppv24.2 3.3 0.5 48.1 ?== 1range forvoltage bias dcoutput table 5. voltage levels respective bias levels for 3.3 v range no. output excitation voltage amplitude output dc bias level 1 1.98 v p -p 1.48 v 2 0.99 v p -p 0.74 v 3 383 mv p -p 0.31 v 4 198 mv p -p 0.179 v the excitation signal for the tr ansmit stage is provided on - chip using dds techniques that permit subhertz resolution. the receive stage receives the input signal current from the unknown impedance, performs signal processing, and digitizes the result. the clock for the dds is generated from an external reference clock that is provided by the user at mclk. data sheet ad5934 rev. c | page 13 of 32 transmit stage as shown in figure 16 , the transmit stage of the ad5934 is made up of a 27 - bit phase accumulator dds core that provides the outpu t excitation signal at a particular frequency. the input to the phase accumulator is taken from the contents of the start fre quency register (see register address 0x 82, register address 0x83 , and register address 0x 84). although the phase accumulator offers 27 bits of resolution, the start frequency register has the three most significant bits (msbs) set to 0 internally; therefore , the user has the ability to program only the lower 24 bits of the start fr equency register. phase accumulator (27 bits) vout r out dac r(gain) v bias 05325-034 figure 16 . transmit stage the ad5934 offers a frequency resolution programmable by the user down to 0.1 hz. the frequency resolution is programmed via a 24 - bit word loaded serially over the i 2 c interface to the frequency increment register. the frequency sweep is fully described by the programming of three parameters: the start frequency, the frequency increment, and the number of increments. start frequency this is a 24 - bit word that is programmed to the on - board ram at register address 0x82, register address 0x 83, and register address 0x 84 (see the register map section). the required code loaded to the start frequency register is the result of the formula sho wn in equation 1, based on the master clock frequency and the required start frequency output from the dds. 27 2 16 ? ? ? ? ? ? ? ? ? ? ? ? = (1) for example, if the user requires the sweep to begin at 30 khz and has a 16 mhz clock signal connected to mclk , t he code that needs to be programmed is given by 0x3d70a3 2 16 mhz 16 khz 30 27 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = the user programs the value of 0x 3d to register address 0x82, the value 0x 70 to register address 0x 83, and the value 0x a3 to register address 0x84. frequency increment this is a 24 - bit wo rd that is programmed to the on - board ram at register address 0x 85, register address 0x 86, and register address 0x 87 (see the register map section). the required code loaded to the frequency increment register is the result of the formula shown in equation 2, based on the master clock frequency and the required increment frequency output from the dds. 27 2 16 ? ? ? ? ? ? ? ? ? ? ? ? = (2) for example, if the user requires the sweep to have a resolution of 10 hz and has a 16 mhz clock signal connected to mclk, the code that needs to be programmed is given by 0x00053e 16 mhz 16 hz 10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = the user programs the value 0x 00 to register address 0x85, the value 0x 05 to register address 0x 86, and the value 0x 3e to register address 0x87. number of incremen ts this is a 9 - bit word that represents the number of frequency points in the sweep. the number is programmed to the on - board ram at register address 0x 88 and register address 0x 89 (see the register map section). the maximum numb er of points that can be programmed is 511. for example, if the sweep needs 150 points, the user programs the value 0x 00 to register address 0x 88 and the value 0x 96 to register address 0x89. once the three parameter values are programmed, the sweep is ini tiated by issuing a start frequency swe ep command to the control register at register address 0x 80 and register address 0x 81 (see the register map section). bit d 2 in the status register (register address 0x8f) indicates the comp letion of the frequency measurement for each sweep point. incrementing to the next frequency sweep point is under the control of the user. the measured result is stored in the two register groups that follow : 0x94 , 0x 95 (real data) and 0x96 , 0x 97 (imaginar y data) that should be read before issuing an increment frequency command to the c ontrol register to move to the next sweep point. there is the facility to repeat the current frequency point measurement by issuing a repeat frequency command to the c ontrol register. this has the benefit of allowing the user to average successive readings. when the frequency sweep has completed all frequency points, bit d 3 in the s tatus register is set, indicating the completion of the sweep . once this bit is set , further inc rements are disabled. ad5934 data sheet rev. c | page 14 of 32 frequency sweep comm and sequence the following sequence must be followed to implement a frequency sweep : 1. enter standby mode. prior to issuing a start frequency sweep com mand, the device must be placed in standby mode by issuing an e nter standby mode command to the c ontrol register (register address 0x80 and register address 0x81 ). in this mode, the vout and vin pins are connected internally to ground so there is no dc bias across the external impedance or between the impedance and gr ound. 2. enter initialize mode. in general, high q complex circuits require a long time to reach steady state. to facilitate the measurement of such impedances, this mode allows the user full control of the settling time requirement before entering start freq uency sweep mode where the impedance measurement takes place. an initialize with start frequency command to the c ontrol register enters initialize mode. in this mode , the impedance is excited with the programmed start frequency but no measurement takes pla ce. the user times out the required settling time before issuing a start frequency sweep command to the c ontrol register to enter the start frequency sweep mode. 3. enter start frequency sweep mode. the user enters this mode by issuing a start frequency swee p command to the control register. in this mode, the adc starts measuring after the programmed number of settling time cycles elapse s . the user can program an integer number of output frequency cycles (settling time cycles) to register address 0x 8a and reg ister address 0x 8b before beginning the measurement at each frequency point (see figure 24). the dds output signal is passed through a programmable gain stage to generate the four ranges of peak - to - peak output excitation signals l isted in table 5 . the peak - to - peak output excitation voltage is selected by setting bit d10 and bit d9 in the c ontrol register ( see the control register section ) and is made available at the vout pin. receive stage the receive stage comprises a current - to - voltage amplifier, followed by a programmable gain amplifier (pga), antialiasing filter, and adc. the receive stage schematic is shown in figure 17 . the unknown impedance is c onnected between the vout and vin pi ns. the first stage current - to - voltage amplifier configuration means that a voltage present at the vin pin is a virtual ground with a dc value set at vdd/2. the signal current that is developed across the unknown impedan ce flows into the vin pin and develops a voltage signal at the output of the current - to - voltage converter. the gain of the current - to voltage amplifier is determined by a user - selectable feedback resistor connected between pin 4 (rfb) and pin 5 (vin). it is important for the user to choose a feedback resistance value which, in conjunction with the selected gain of the pga stage, maintains the signal within the linear range of the adc (0 v to vdd). 05325-038 5 r r r r c vin vdd/2 rfb adc lpf figure 17 . receive stage the pga allows the user to gain the output of the current - to - voltage amplifier by a factor of 5 or 1 depending upon the status of bit d8 in the c ontrol register (see the register map section register address 0x 80 ). the signal is then lo w- pass filtered and presented to the input of the 12 - bit, 250 ksps adc. the digital data from the adc is passed directly to the dsp core of the ad5934 that performs a dft on the sampled data. dft operation a df t is calculated for each frequency point in the sweep. the ad5934 dft algorithm is represented by ( ) ))sin( ) )(cos( ()( 1023 0 njnnxfx n ? = = where: x ( f ) is the power in the signal at the frequency p oint f . x ( n ) is the adc outpu t. cos( n ) and sin( n) are the sampled test vectors provided by the dds core at the f requency f . the multiplication is accumulated over 1024 samples for each frequency point. the result is stored in two 16 - bit registers representing the real and imaginary components of the result. the data is stored in twos complement format. data sheet ad5934 rev. c | page 15 of 32 impedance calculatio n magnitude calculatio n the first step in the impedance calculation for each frequency point is to calculate the magnitude of the dft at that point. the dft magn itude is given by 22 ir magnitude += where: r is the real number stored at register address 0x 94 and register address 0x95 . i is the imaginary number stored at register address 0x 96 and register address 0x97. for example, assume the results in the r eal data and imaginary data registers are as follows at a frequency point: real data re gister = 0x 038b = 907 decimal imaginary data re gister = 0x 0204 = 516 decimal 1043.506)516 (907 22 =+= magnitude to convert this number into impedance, it must be multiplied by a sc aling factor called the gain factor. the gain factor is calculated during the calibration of the system with a known impedance connected between the vout and vin pins. once the gain factor is calculated, it can be used in the calculation of any unknown imp edance between the vout and vin pins. gain factor calculat ion an example of a gain factor calculation follows, with these assumptions: output excitation voltage = 2 v p -p calibration impedance value, z calibration = 200 k? pga gain = 1 current - to - voltage a mplifier gain resistor = 200 k? calibration frequency = 30 khz the typical contents of the real data and imaginary data registers after a frequency point conversion would then be real data re gister = 0x f 064 = ? 3996 decimal imaginary data re gister = 0x227e = + 8830 decimal ( ) 106.9692)8830(3996 2 2 =+?= magnitude magnitude impedance 1 code admittance factorgain ? ? ? ? ? ? ? ? = ? ? ? ? ? ? = 12 10819.515 106.9692 k200 1 ? = ? ? ? ? ? ? ? ? ? ? ? ? = factorgain impedance calculatio n using gain factor the next example illustrates how the calculated gain factor derived previously is used to measure an unknown impedance. for th is example, assume that the unknown impedance is 510 k?. after measuring the unknown impedance at a frequency of 30 khz, assume that the real data and imaginary data registers contain the following data: real data regi ster = 0x fa 3f = ?1473 decimal imaginary data re gister = 0x 0db3 = + 3507 decima l 3802.863)(3507) 1473) (( 2 2 =+?= magnitude t he measured impedance at the frequency point is then given by magnitude factorgain impedance = 1 3802.863 10 515.819273 1 12 = ? = 509.791 k? gain factor variatio n with frequency because the ad5934 has a finite freq uency response, the gain factor also shows a variation with frequency. this variation in gain factor results in an error in the impedance calculation over a frequency range. figure 18 shows an impedance profile based on a single - point gain factor calculation. to minimize this error, the frequency sweep should be limited to as small a frequency range as possible. 101.5 98.5 54 66 05325-085 frequency (khz) impedance (k?) 101.0 100.5 100.0 99.5 99.0 56 58 60 62 64 vdd = 3.3v calibration frequency = 60khz t a = 25c measured calibration impedance = 100k? figure 18 . impedance profile using a single - point gain factor calculation ad5934 data sheet rev. c | page 16 of 32 2- point calibratio n alternatively , it is possible to minimize this error by assuming that the frequency variation is linear and adjusting the gain factor with a 2 - point calibration. figure 19 shows an impedance profile based on a 2 - point gain fact or calculation. 101.5 98.5 54 66 05325-086 frequency (khz) impedance (k?) 101.0 100.5 100.0 99.5 99.0 56 58 60 62 64 vdd = 3.3v calibration frequency = 60khz t a = 25c measured calibration impedance = 100k? figure 19 . impedance profile using a 2 - point gain factor calculation 2- point gain factor ca lculation this is an example of a 2 - point gain factor calculation assuming the following: output excitation voltage = 2 v p-p calibration impedance value, z unknown = 100.0 k? pga gain = 1 supply voltage = 3.3 v current - to - voltage amplifier gain resistor = 100 k? calibration frequencies = 55 khz and 65 khz typical values of the gain factor calculated at the two calibration f requencies read gain factor calculated at 55 khz is 1.031224 10 ?9 . gain factor calculated at 65 khz is 1.035682 10 ?9 . difference in gain factor ( gf) is 1.035682 10 ?9 ? 1.031224 10 ?9 = 4.458000 10 ?12 . frequency span of sweep ( f) is 10 khz . ther efore , the gain factor re quired at 60 khz is given by 9- 10 1.031224 khz 5 khz 10 12-4.458000e + ? ? ? ? ? ? the required gain factor is 1.033453 10 ?9 . the impedance is calculated as previously described in the impedance calculation section. gain factor set up configuration when calculating the gain factor , it is important that the receive stage is operating in its linear region. this requires careful selection of the excitation signal range, current - to - voltage gain resistor and pga gain. the gain through the system shown in figure 20 is given by output excitation voltage range unknown z resistor setting gain pga gain 05325-089 vin vdd/2 rfb adc lpf z unknown vout current-to-voltage gain setting resistor pga (1 or 5) figure 20 . system voltage gain for this example, assume the following system settings: vdd = 3.3 v gain setting resistor = 200 k? z unknown = 200 k? pga setting = 1 the peak - to - peak voltage presented to the adc input is 2 v p- p. however , had the user chosen a pga gain of 5, the voltage would saturate the adc. gain factor recalcul ation the gain fa ct or must be recalculated for a change in any of the following parameters: ? current - to - voltage gain setting resistor ? output excitation voltage ? pga gain data sheet ad5934 rev. c | page 17 of 32 gain factor temperat ure variation the typical impedance error variation with temperature is in the orde r of 30 ppm/c. figure 21 shows an impedance profile with a variation in temperature for 100 k? impedance using a 2- point gain factor calibration. 101.5 98.5 54 66 05325-087 frequency (khz) impedance (k?) 101.0 100.5 100.0 99.5 99.0 56 58 60 62 64 +125c +25c ?40c vdd = 3.3v calibration frequency = 60khz measured calibration impedance = 100k? figure 21 . impedance profile variation with temperature using a 2- point gain factor ca libration impedance error refer to circuit note cn - 0217 on the ad5933 product page, which highlights a method to improve accuracy. the eval - ad5933ebz board can be used to evaluate the ad5934 performance. measuring the p hase a cross a n i mpedance the ad5934 returns a complex output code made up of a separate real and imaginary component s. the real component is stored at register ad dress 0x94 and register address 0x 95, and the imaginary component is stored at register addre ss 0x96 and register address 0x 97 after each sweep measurement. these correspond to the real and imaginary components of the dft and not the resistive and reactive components of the impedance under test. for example , it is a common misconception to assume that if a user was analyzing a series rc circuit that the real value stored in register address 0x 94 and register address 0x 95 and the imaginary value stored in r egister address 0x 96 and register address 0x97 would correspond to the resistance and capacitive reactance , respectfully. however, t his is incorrect because the magnitude of the impedance (|z|) can be calculated by calculating the magnitude of the real and imaginary components of the dft given by the following formula : 22 ir magnitude += after each measurement , multiply it by the calibration term and invert the product. therefore, t he magnitude of the impedance is given by the following formula: magnitude factorgain impedance = 1 w here the gain factor is given by magnitude impedance 1 code admittance factorgain ? ? ? ? ? ? ? ? = ? ? ? ? ? ? = the user must calibrate the ad5934 system for a know n impedance range to determine the gain factor before any valid measurement can ta ke place. therefore , the user must know the impedance limits of the complex impedance (z unknown ) for the sweep frequency range of interest. the gain factor is simply determined by placing a known impedance between the input/ output of the ad5934 and measuring the resulting magnitude of the code. the ad5934 system gain settings need to be chosen to place the excitation s ignal in the linear region of the on - board adc . because the ad5934 returns a complex output code made up of real and imaginary component s , the user is also able to calculate the phase of the response signal through the signal path of the ad5934 . the phase is given by the following formula: phase (rads) = t an ?1 ( i / r ) (3) the phase measured by equation 3 accounts for the phase shift introduced to the dds output signal as it passes through the internal amplifiers o n the transmit and receive side o f the ad5934 , along with the low - pass filter , and also the impedance connected between the vout and vin pins of the ad5934 . the par ameters of interest for many users are the magnitude of the impedance (|z unknown |) and the i mpedance phase (z?).the measurement of the i mpedance phase (z?) is a 2- step process. the first step involves calculating the ad5934 system phase. the ad5934 system phase can be calculated by placing a resistor across the v out and v in pins of the ad5934 and calculating the phase (us ing equation 3 ) after each measurement point in the sweep. by placing a resistor across the v out and v in pins, there is no additional phase lead or lag introduced to the ad5934 signal path , and the resulting ph ase is due entirely to the internal poles of the ad5934 , that is , the system phase. once the system phase is calibrated using a resistor, the second step involves calculating the phase of any unknown impedance can be calculated by inserting the un known impedance between the v in and v out terminals of the ad5934 and recalculating the new phase (including the phase due to the impedance) using the same formula. the phase of the unknown impedance (z?) is given by z ? = ( unknown ? system ? ) w here : system ? is the phase of the system with a calibration resistor connected between vin and vout. unknown is the phase of the system with the unknown impedance connected between v in and v out . z ? is the phase due to the impedance , that is, the impedance phase. ad5934 data sheet rev. c | page 18 of 32 note that i t is possible to calculate the gain factor and to calibrate the system phase using the same real and imaginary component values when a resistor is connected between the v out and v in pins of the ad5934 , f or e xample , measuring the i mpedance phase (z?) of a capacitor. the excitation signal current leads the excitation signal voltage across a cap acitor by ? 90 degrees . therefore , an approximate ?90 degrees phase difference between the system phase responses measured with a resistor and the system phase responses measured with a capacitive impedance exists. as previously outlined, if the user wants to determine the phase angle of the capacitive impedance (z?) , the user first must determine the system phase response ( system ? ) and subtract this from the phase calculated with the capacitor connected between v out and v in ( unknown ). figure 22 show s the ad5934 system phase response calculated using a 220 k ? calibration resistor (r fb = 220 k , pga = 1) and the repeated phase measurement with a 10 pf capacitive impedan ce. one important point to note about the phase formula used to plot figure 22 is that it uses the arctangent function that returns a phase angle in radians and, therefore, it is necessary to convert from radians to degrees. 0 20 40 60 80 100 120 140 160 180 200 system phase (degrees) 60k 45k 15k 30k 0 75k 90k 105k 120k f re qu ency (hz) 05325-090 220 k? resistor 10 pf c apac it or f igure 22 . system phase response vs. capac itive phase the phase difference ( that is, z?) between the phase response of a capacitor and the system phase response using a resistor is the impedance phase of the capacitor (z?) and is sh own in figure 23 . in addition, when using the real and imaginary values to interpre t the phase at each measurement point, care should be taken when using the arctangent formula. the arctangent function only returns the correct s tandard phase angle when the sign of the real and imaginary values are positive, that is, when the coordinates lie in the first quadrant. the standard angle is taken counterclockwise from the positive real x - axis. if the sign of the real component is posi tive and the sign of the imaginary component is negative, that is, the data lies in the second quadrant, the arctangent formula returns a negative angle, and it is necessary to add an additional 180 to calculate the correct standard angle. likewise, when the real and imaginary components are both negative, that is, when data lies in the third quadrant, t he arctangent formula returns a positive angle, and it is necessary to add an additional 180 to calculate the correct standard phase. when the real compon ent is positive and the imaginary component is negative, that is, the data lies in the fourth quadrant, the arctangent formula returns a negative angle, and it is necessary to add an additional 360 to calculate the correct standard phase. phase (degrees) 60k 45k 15k 30k 0 75k 90k 105k 120k f requ ency (hz) 05325-091 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 figure 23 . phase r esponse of a capacitor therefore , the correct standard phase angle is depend e nt upon the sign of the real and imaginary component s, which is summarized in table 6 . table 6 . phase a ngle real imaginary quadrant phase angle positive positive first ? 180 ) / ( tan 1 ri positive negative second ? ? ? ? ? ? + ? 180 ) / ( tan 180 1 ri negative negative third ? ? ? ? ? ? + ? 180 ) / ( tan 180 1 ri negative positive fourth ? ? ? ? ? ? + ? 180 ) / ( tan 360 1 ri once t he magnitude of the impedance (|z|) and the impedance phase angle (z?, in radians) are correctly calculated , it is possible to determine the magnitude of the real (resistive) and imaginary (reactive) component s of the impedance (z unknown ) by the vector pro jection of the impedance magnitude onto the real and imaginary impedance axis using the following formulas : the real component is given by | z real | = | z | c os( z ?) the i maginary component is given by | z imag | = | z | s in( z ?) data sheet ad5934 rev. c | page 19 of 32 performing a frequency sweep 05325-047 program the ad5934 in t o power-down mode. place the ad5934 in t o s t andb y mode. program frequenc y swee p p arameters in t o rele v ant registers (1) s t art frequenc y register (2) number of increments register (3) frequenc y increment register read v alues from rea l and imagina ry d at a registers. program initialize with s t art frequenc y command t o the contro l register. after a sufficient amount of settling time has elapsed, program s t art frequenc y swee p command in the contro l register. poll s ta tus register t o check if the dft conversion is complete. reset : b y issuing a reset command to the contro l register, the device is placed in s t andb y mode. program the increment frequenc y or the repe a t frequenc y command t o the contro l register. y y y n n poll s ta tus register t o check if frequenc y swee p is complete. figure 24 . frequency sweep flow c hart ad5934 data sheet rev. c | page 20 of 32 register map table 7 . register name register address bits function control 0x80 d15 to d8 read/write 0x81 d7 to d0 read/write start frequency 0x82 d23 to d16 read/write 0x83 d15 to d8 read/write 0x 84 d7 to d0 read/write frequency increment 0x85 d23 to d16 read/write 0x 86 d15 to d8 read/write 0x87 d7 to d0 read/write number of increments 0x 88 d15 to d8 read/write 0x89 d7 to d0 read/write number o f settling time cycles 0x8a d15 to d8 read/write 0x8b d7 to d0 read/write status 0x8f d7 to d0 read only real data 0x94 d15 to d8 read only 0x95 d7 to d0 read only imaginary data 0x96 d15 to d8 read only 0x97 d7 to d0 read only control regis ter ( register address 0x 80, register address 0x 81) the ad5934 contains a 16 - bit control register ( register address 0x80 and register address 0x81) that sets the control modes. the default value of the control r egister upon reset is as follows: d15 to d0 is reset to 0xa000 upon power - up. the four msbs of the c ontrol register are decoded to provide control functions, such as performing a frequency sweep, powering down the part, and controlling various other functi ons defined in the c ontrol register map. the user can choose to write only to register address 0x 80 and to not alter the contents of register address 0x 81. note that the c ontrol register should not be written to as part of a block w rite command. the c ontr ol register also allows the user to program the excitation voltage and set the system clock. a r eset command to the c ontrol register does not reset any programmed values associated with the sweep (that is, start frequency, number of increments, frequency increment). after a r eset command, an i nitialize with start freq uency command must be issued to the c ontrol register to restart the frequency sweep sequence (see figure 24). table 8 . d 10 to d 9 control reg ister map d10 d9 range no. output voltage range 0 0 1 2.0 v p - p typical 0 1 3 200 mv p - p typical 1 0 4 400 mv p - p typical 1 1 2 1.0 v p - p typical table 9 . d11 and d8 to d 0 control register map bits description d11 no operatio n d8 pga gain ; 0 = 5, 1 = 1 d7 reserved; set to 0 d6 reserved; set to 0 d5 reserved; set to 0 d4 reset d3 external system clock; set to 1 internal system clock; set to 0 d2 reserved; set to 0 d1 reserved; set to 0 d0 reserved; set to 0 tabl e 10. d1 5 to d1 2 control register map d15 d14 d13 d12 description 0 0 0 0 no operation 0 0 0 1 initialize with start frequency 0 0 1 0 start frequency sweep 0 0 1 1 increment frequency 0 1 0 0 repeat frequency 1 0 0 0 no opera tion 1 0 0 1 no operation 1 0 1 0 power - down mode 1 0 1 1 standby mode 1 1 0 0 no operation 1 1 0 1 no operation data sheet ad5934 rev. c | page 21 of 32 control register decode initialize with start frequency this command enables the dds to output the programmed start frequency for an in definite time. initially, i t is used to excite the unknown impedance. when the output unknown impedance has settled after a time determined by the user, the user must initiate a start frequency swe ep command to begin the frequency sweep. start frequency sw eep in this mode , the adc starts measuring after the programmed number of settling time cycles has elapsed. the user has the ability to program an integer number of output frequency cycles (settling time cycles) to register address 0x 8a and register addres s 0x8b before the commencement of the measurement at each frequency point (s ee figure 24 ). increment frequency the increment frequ ency command is used to step to the next frequency point in the sweep. this usually happens after d ata from the previous step is transferred and verified by the dsp. when the ad5934 receives this command, it waits for the programmed number of settling time cycles before beginning the adc conversion process. repeat frequency there is the facility to repeat the current frequency point measurement by issuing a repeat frequency command to the c ontrol register. this command allows user s to average successive readings. power - down mode the default state at power - up of the ad5934 is power - down mode. the c ontrol register contains the code 1010 , 0000 , 0000 , 0000 ( 0x a000). in this mode , both the output and input pins , vout and vin, are connected internally to gnd. standby mode this mode p owers up the part for general operation . i n standby mode , the vin and vout pins are internally connected to gnd . reset a r eset command allows the user to interrupt a sweep. the start frequency, number of increments, and frequency incremen t regi ster contents are not overwritten. an initialize with start frequen cy command is required to restart the frequency sweep command sequence. output voltage range the output voltage range allows the user to program the excitation voltage range at vout. pga g ain the pga g ain allows the user to amplify the response signal into the adc by a multiplication factor of 5 or 1. start frequency regi ster ( register address 0x 82, register address 0x 83, register address 0x 84) the start frequency register contains the 24- bit digital representation of the frequency from where the subsequent frequency sweep is initiated. for example, if the user requires the sweep to start from a frequency of 30 khz using a 16.0 mhz clock, the user must program the value 0x 3d to register address 0x82, the value 0x70 to register address 0x 83, and the value 0x a3 to register address 0x 84. doing t his ensures the output frequency starts at 30 khz. the start frequency code is 0x3d70a3 2 16 mhz 16 khz 30 27 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = the default value of the start frequency reg ister upon reset is as follows: d23 to d0 are not reset at power - up. after the reset command, the contents of this register are not reset. frequency increment register ( register address 0x 85, register address 0x 86, register address 0x 87) the frequency inc rement register contains a 24 - bit representation of the frequency increment between consecutive frequency points along the sweep. for example, if the user requires an increment step of 30 hz using a 16.0 mhz clock, the user must program the value 0x 00 to r egister address 0x85, the value 0x 0f to register address 0x86 , and the value 0x ba to register address 0x87. the formula for calculating the frequency increment is given by 0x00053e 2 16 mhz 16 hz 10 27 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = the user programs the value 0x 00 to register address 0x 85, the value 0x 05 to register address 0x 86, and the value 0x 3e to register address 0x 87. the default value of the frequency increment register upon reset is as follows: d23 to d0 are not reset at power - up. after the reset command, the contents of this regis ter are not reset. ad5934 data sheet rev. c | page 22 of 32 number of increments register ( register address 0x 88, register address 0x 89) the default value of the number of increments register upon reset is as follows: d8 to d0 are not reset at power - up. after a reset command, the contents of thi s register are not reset. table 11. number o f increments register reg addr bits description function format 0x88 d15 to d9 dont care read or w rite integer number stored in binary format d8 n umber of increments read or w rite 0x89 d7 to d0 number of increments read or w rite integer number stored in binary format this register determines the number of frequency points in the frequency sweep. the number of frequency points is represented by a 9 - bit word, d8 to d0. d 15 to d 9 a re dont care bits. this register in conjunction with the start frequency register and the frequency increment register determine the frequency sweep range for the sweep operation. the maximum number of increments that can be programmed is 511. number of s ettling time cycles register ( register address 0x 8a, register address 0x 8b) the default value of the number of settling time cycles register upon reset is as follows: d10 to d0 are not reset at power - up. after a reset command, the contents of this register are not reset. this register determines the number of output excitation cycles allowed to passthrough the unknown impedance after receipt of a start frequency sweep , increment frequency , or repeat frequency command, before the adc is triggered to perform a conversion of the response signal. the number of settling time cycles register value determines the delay between a start frequency sweep / increment frequency /repeat frequency command and the time an adc conversion commences. the number of cycles is repr esented by a 9 - bit word, d8 to d0. the value programmed into the number of settling time cycle s register can be increased by a factor of 2 or 4 , depending on the status of b its d10 to d9. the five most significant bits, d15 to d11, are dont care bits. the maximum number of output cycles that can be programmed is 511 4 = 2044 cycles. for example, consider an excitation signal of 30 khz , t he maximum delay between the programming of this frequency and the time that this signal is first sampled by the adc is 511 4 33.33 s = 68.126 ms. the adc takes 1024 samples, and the result is stored as real data and imaginary data in register address 0x 94 to register address 0x 97. the conversion process takes approximately 1 ms using a 16.777 mhz clock. status regis ter ( register address 0x 8f) the s tatus register is used to confirm that particular measurement tests have been successfully completed. each of the bits from d7 to d0 indicate the status of a specific functionality of the ad5934 . bit d0 and bit d4 to bit d7 are treated as dont care bits ; these bits do not indicate the status of any measurement . the status of b it d1 indicates the status of a frequency point impedance measurement. this bit is set when the ad5934 complete s the current frequency point impedance measurement. this bit indicates that there is valid real data and imaginary data in register address 0x 94 to register address 0x 97. this bit is reset on receipt of a start frequency sweep, increment frequency , repeat frequency, or res et command. this bit is also reset at power - up. the status of b it d2 indicates the status of the programmed frequency sweep. this bit is set when all programmed increments to the numbe r of increments register are complete. this bit is reset at power - up and on receipt of a r eset command. table 12. status register 0x8f control word description 0000 0001 reserved 0000 0010 valid real/imaginary data 0000 0100 freq uency sweep complete 0000 1000 reserved 0001 0000 reserved 0010 0000 reserved 0100 0000 reserved 1000 0000 reserved table 13 . number of settling times cycles register register address bits description function format 0x8a d 15 to d11 dont care read or w rite integer number stored in binary format d10 to d9 2- bit decode d10 d9 description 0 0 default 0 1 no of cycles 2 1 0 reserved 1 1 no of cycles 4 d8 msb number of settling time cycles 0x8 b d7 to d0 number of settling time cycles read or w rite data data sheet ad5934 rev. c | page 23 of 32 valid real/imaginary data this bit is set when data processing for the current frequency point is finished, indicating real/imaginary data available for reading. the bit is r eset when a start frequency sweep/increment frequency/repeat frequency dds command is issued. in addition, this bit is reset to 0 when a r eset command is issued to the c ontrol register. frequency sweep complete this bit is set when data processing for the last frequency po int in the sweep is complete. this bit is reset when a start frequency sw eep command is issued to the c ontrol register. this bit is also reset when a r eset command is issued to the c ontrol register. real and imaginary data registers (16 bi ts register add ress 0x 94, register address 0x 95, register address 0x 96, register address 0x 97) these registers contain a digital representation of the real and imaginary components of the impedance measured for the current frequency point. the values are stored in 16 - bit , twos complement format. to convert this number to an actual impedance value, the magnitude , )imaginary (real 2 2 + , must be multiplied by an admittance/code number (called a gain factor) to give the admittance and the result inverted to give the impedan ce. the gain factor varies for each ac excitation voltage/gain combination. the d efault value upon reset: t hese registers are not reset at power - up or on receipt of a r eset command. note that the data in these registers is only valid if bit d1 in the s tat us register is set, indicating that the processing at the current frequency point is complete. ad5934 data sheet rev. c | page 24 of 32 serial bus interface control of the ad5934 is carried out via the i 2 c- compliant serial interface protocol. the ad5934 is connected to this bus as a slave device under the control of a master device. the ad5934 has a 7 - bit serial bus slave address. when the device is pow ered up, it has a default serial bus address, 0001101 ( 0x 0d) . general i 2 c timing figure 25 shows the timing diagram for general read and write operations using the i 2 c- compliant interface. the master initiates data transfer by establishing a start condition, defined as a high - to - low transition on the serial data line (sda) while the serial clock line (scl) remains high. this indicates that a data stream follows. the slave responds to the start condition and shifts in the next 8 bits, consisting of a 7 - bit slave address (msb first) and an r/w bit, which determines the direction of the data transfer , that is, whether data is written to or read from the slave device (0 = write, 1 = read). the slave responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock p ulse. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/w bit is 0, the master writes to the slave device. if the r/w bit is 1, the master reads from the slave device. data is sent over the serial bus in sequences of nine clock pulses, 8 bits of data followed by an acknowledge bit, which can be from the master or slave device. data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low - to - high transition when the clock is high can be interpreted as a stop signal. if the operation is a write operation, the first data byte after the slave address is a command byte. this tells the slave device what to expect next. it may be an instruction telling the slave device to expect a block write, or it may be a register addre ss that tells the slave where subsequent data is to be written. because data can flow in only one direction as defined by the r/w bit, it is not possible to send a command to a slave device during a read operation. before performing a read operation, it is sometimes necessary to perform a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. when all data bytes are read or written, stop conditions are established. in write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device releases the sda line during the low period before the ninth clock pulse, but the slave device does not pull it low. this is known as a no ackn owledge. the master then takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. 0 0 0 1 1 0 1 r/w d7 d6 d5 d4 d3 d2 d1 d0 start condition by master acknowledged by ad5934 slave address byte acknowledged by master/slave scl sda register address 05325-048 figure 25 . timing diagram data sheet ad5934 rev. c | page 25 of 32 writing/reading to t he ad5934 the i 2 c interface specification defines several different protocols for different types of read and write operations. this section describes the protocols used in the ad5934 . the figures in this section use the abbreviations shown in table 14. table 14. i 2 c abbreviation table abbreviation condition s start p stop r read w write a acknowledge a no acknowledge write byte/command byte user command codes the command codes in table 15 are used for reading/writing to the interface. they are explained in detail in this section but are grouped within table 15 for easy reference. table 15 . command codes command code code name code description 1010 0000 block write this command is used when writing multiple bytes to the ram; s ee the block wr ite section . 1010 0001 block read this command is used when reading multiple bytes from ram/memory; s ee the block read section . 1011 0000 address pointer this command enables the user to set the address pointer to any location in the memory ; t he data contains the address of the register to which the pointer should be pointing . write bytecommand byte in this operation , the master device sends a byte of data to the slave device. the write byte can either be a data byte writ e to a re gister address or it can be a command operation. to write data to a register , the command sequence is as follows (see figure 26 ): 1. the master device asserts a start condition on sda. 2. the master sends the 7 - bit slave addre ss followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends a register address. 5. the slave asserts an acknowledge on sda. 6. the master sends a data byte. 7. the slave asserts an acknowledge on sda. 8. the master a sserts a stop condition on sda to end the transaction. s slave address register address register data aw a a p 05325-049 figure 26 . writing register data to register address in the ad5934 , the write byte protocol is also used to set a pointer to a r egister address (see figure 27) . this protocol is used for a subsequent single - byte read from the same address, block read, or block write starting at that address. to set a register pointer, the following sequence is applied: 1. the master device asserts a start condition on sda. 2. the master sends the 7 - bit slave address followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends a pointer command code (see table 15, a n address pointer = 1011 0000). 5. the slave asserts an acknowledge on sda. 6. the master sends a data byte (a register address to where the pointer is to point). 7. the slave asserts an acknowledge on sda. 8. the master asserts a stop condition on sda to end the transaction. s aw a a p pointer command 1011 0000 slave address register address to point to 05325-050 figure 27 . setting address pointer to register address block write in this operation, the master device writes a block of data to a slave device (see figure 28) . the start address f or a block write must previously have been set. in the case of the ad5934 , this is done by setting a pointer to set the register address. 1. the master device asserts a start condition on sda. 2. the master sends the 7- bit slave address followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends an 8 - bit command code (1010 0000) that tells the slave device to expect a block write. 5. the slave asserts an acknowledge on sda . 6. the master sends a data byte that tells the slave device the number of data bytes to be sent to it. 7. the slave asserts an acknowledge on sda. 8. the master sends the data bytes. 9. the slave asserts an acknowledge on sda after each data byte. 10. the master assert s a stop condition on sda to end the transaction. a a a a a s w a p slave address block write number bytes write byte 0 byte 1 byte 2 05325-051 figure 28 . writing a block write ad5934 data sheet rev. c | page 26 of 32 read operations the ad5934 uses two i 2 c read protocols : the receive byte and the block read. r eceive byte in the ad5934 , the receive byte protocol is used to read a single byte of data from a register address whose address has previously been set by setting the address pointer. in this operation, the m aster device receives a single byte from a slave device as follows (see figure 29 ): 1. the master device asserts a start condition on sda. 2. the master sends the 7 - bit slave address followed by the read bit (high). 3. the addres sed slave device asserts an acknowledge on sda. 4. the master receives a data byte. 5. the master asserts a no acknowledge on sda ( the slave needs to check that master has received data). 6. the master asserts a stop condition on sda and the transaction ends. s r a a p slave address register data 05325-052 figure 29 . reading register data block read in this operation, the master device reads a block of data from a slave device (see figure 30) . the start address for a block read must previously have been set b y setting the address pointer . 1. the master device asserts a start condition on sda. 2. the master sends the 7 - bit slave address followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends a command code (1010 00 01) that tells the slave device to expect a block read. 5. the slave asserts an acknowledge on sda. 6. the master sends a byte - count data byte that tells the slave how many data bytes to expect. 7. the slave asserts an acknowledge on sda. 8. the master asserts a rep eat start condition on sda. this is required to set the read bit high. 9. the master sends the 7 - bit slave address followed by the read bit (high). 10. the slave asserts an acknowledge on sda. 11. the master receives the data bytes. 12. the master asserts an acknowledge on sda after each data byte. 13. a no acknowledge is generated after the last byte to signal the end of the read. 14. the master asserts a stop condition on sda to end the transaction. number bytes read s slave address w a block read a a s slave address r a byte 0 a byte 1 a byte 2 a p 05325-053 figure 30 . performing a block read data sheet ad5934 rev. c | page 27 of 32 typical appl ications measuring small impe dances the ad5934 is capable of measuring impedance values up to 10 m if the system gain settings are chosen correctly for the impedance subrange of interest. if the user places a small impedance value (500 over the sweep frequency of interest) between the vout and vi n pins , it results in an increase in signal current flowing through the impedance for a fixed excitation voltage in accordance with ohms law. the output stage of the transmit side amplifier available at the vout pin may not be able to provide the required increase in current through the impedance. to have a unity gain condition about the receive side i - v amplifier, the user needs to have a similar small value of feedback resistance for system calibration as outlined in the gain fac tor setup configuration section. the voltage presented at the vin pin is hard biased at vdd/2 due to the virtual earth on the receive side i - v amplifier. the increased current sink/source requirement placed on the output of the receive side i - v amplifier may also cause the amplifier to operate outside of the linear region. this causes significant errors in subsequent impedance measurements. the value of the output series resistance, r out , (see figure 31) at the vout pin must be taken into account when measuring small impedances (z unknown ), specifically when the value of the output series resistance is comparable to the value of the impedance under test (z unknown ). if the r out value is unac - counted for in the system calibration (that is, the gain factor calculation) when measuring small impedances, there is an introduced error into any subsequent impedance measurement that takes place. the introduced error depends on the relative magnitude of the impedance being tested compared to the value of the output series resistance. 05324-148 pga i-v vdd/2 rfb vin ad8531 ad820 ad8641 ad8627 v dd 20k? 20k? 1f vdd/2 vout r out r fb dds 2v p-p r1 r2 z unknown transmit side output amplifier figure 31 . additional external amplifier circuit for measuring small impedances the value of the output series resistance depends upon the selected output excitation range at vout and has a tolerance from device to device like all discrete resistors manufactured in a silicon fabrication process. typical values of the output series resistance are outlined in table 16 . table 16 . output s eries resistance ( r out ) vs. excitation range parameter value (typ) output series resistance value range 1 2 v p -p 200 ? t yp ical range 2 1 v p -p 2. 4 k ? t yp ical range 3 0.4 v p -p 1. 0 k ? t yp ical range 4 0.2 v p - p 600 ? typ ical therefore, to accurately calibrate the ad5934 to measure small impedances, it is necessary to reduce the signal current by attenuating the excitation voltage sufficiently and also account for the r out value and factor it into the gain fa ctor calculation (see the gain factor calculation section). measuring the r out value during device characterization is achieved by selecting the appropriate output excitation range at vout and sinking and sourcing a known current at the pin (for example, 2 ma) and measuring the change in dc voltage. the output series resistance can be calculated by measuring the inverse of the slope (that is, 1/slope) of the resultant i - v plot. a circuit that helps to minimize the effects of the i ssues previously outlined is shown in figure 31 . the aim of this circuit is to place the ad5934 system gain within its linear range when measuring small impedances by using an additio nal external amplifier circuit along the signal path. the external amplifier attenuates the peak - to - peak excitation voltage at vout by a suitable choice of resistors (r1 and r2), thereby reducing the signal current flowing through the impedance and minimiz ing the effect of the output series resistance in the impedance calculations. in the circuit shown in figure 31 , z unknown recognizes the output series resistance of the external amplifier which is typically much less than 1 with feedback applied depending upon the op amp device used (for example, ad820 , ad8641 , ad8531 ) as well as the load cu rrent, bandwidth, and gain. the key point is that the output impedance of the external amplifier in figure 31 (which is also in series with z unknown ) has a far less significant effect on gain factor calibration and subsequent imp edance readings in comparison to connecting the small impedance directly to the vout pin (and directly in series with r out ). the external amplifier buffers the unknown impedance from the effects of r out and introduces a smaller output impedance in series w ith z unknown . ad5934 data sheet rev. c | page 28 of 32 for example, if the user measures z unknown that is known to have a small impedance value within the range of 90 to 110 over the frequency range of 30 khz to 32 khz, the user may not be in a position to measure r out directly in the fac tory/lab. therefore, the user may choose to add on an extra amplifier circuit like that shown in figure 31 to the signal path of the ad5934 . the user must ensure that the chosen exte rnal amplifier has a sufficiently low output series resistance over the bandwidth of interest in comparison to the impedance range under test (for an op amp selection guide, see www.analog.com/opamps ). most amplifiers from analog devices have a curve of closed - loop output impedance vs. frequency at different amplifier gains to determine the output series impedance at the frequency of interest. the system settings are as follows: vdd = 3.3 v vout = 2 v p -p r2 = 20 k r1 = 4 k gain setting resistor = 500 ? z unknown = 100 ? pga setting = 1 to attenuate the excitation voltage at vout, choose a ratio of r1/r2. with the values of r1 = 4 k and r2 = 20 k, attenuate the signal by 1/5 th of 2 v p - p = 400 mv. the maxim um current flowing through the impedance is 400 mv/ 90 = 4.4 ma. the system is subsequently calibrated using the usual method with a midpoint impedance value of 100 , a calibration resistor, and a feedback resistor at a midfrequency point in the sweep. the dynamic range of the input signal to the receive side of the ad5934 can be improved by increasing the value of the i- v gain resistor at the rfb pin. for example, increasing the i - v gain setting resistor at the rfb pin increases the peak - to - peak signal presented to the adc input from 400 mv (rfb = 100 ) to 2 v p - p (rfb = 500 ). the gain factor calculated is for a 100 resistor connected between vout and vin, assuming the output series resistance of the ex ternal amplifier is small enough to be ignored. when biasing the circuit shown in figure 31 , note that the receive side of the ad5934 is hard - biased about vdd/2 by design. therefore, to prevent the output of the external amplifier (attenuated ad5934 range 1 excitation signal) from saturating the receive side amplifiers of the ad5934 , a voltage e qual to vdd/2 must be applied to the noninverting terminal of the external amplifier. biomedical: noninvas ive blood impedance measurement when a known strain of a virus is added to a blood sample that already contains a virus, a chemical reaction takes pl ace whereby the impedance of the blood under certain conditions changes. by characterizing this effect across different frequencies , it is possible to detect a specific strain of virus. for example, a strain of the disease exhibits a certain characteristic impedance at one frequency but not at another , resulting in the need to sweep different frequencies to check for different viruses. the ad5934 , with its 27 - bit phase accumulator, allows for sub h ert z frequency tuning. the ad5934 can be used to inject a stimulus signal through the blood sample via a probe. the response signal is analyzed and the effective impedance of the blood is tabulated. the ad5934 is ideal for this application because it allows the user to tune to the specific frequency required for each test. probe 2 6 4 adr43x ad5934 top view (not to scale) 10f 0.1f 7v aduc702x top view (not to scale) 1 16 2 15 3 14 4 13 5 6 11 7 10 8 9 rfb 12 05325-057 figure 32 . measuring a blood sample for a strain of virus data sheet ad5934 rev. c | page 29 of 32 sensor/complex imped ance measurement the operational principle of a capacitive proximity sensor is based on the change of a capacitance in a rlc resonant circuit. this leads to changes in the resonant frequency of the rlc circuit, which can be evaluated as shown figure 33. it is first required to tune the rlc circuit to the area of resonance. at the resonant frequency, the impedance of the rlc circuit is at a maximum. therefore, a programmable frequency sweep and tuning capability is required, which is p rovided by the ad5934 . 05325-058 frequency (hz) proximity impedance (?) resonant frequency change in resonance due to approaching object f o figure 33 . detecting a change in resonant frequency an example of the use of this type of sensor is for a train proximity measurement system. the magnetic fie lds of the train approaching on the track change the resonant frequency to an extent that can be characterized. this information can be sent back to a mainframe system to show the train location on the network. another application for the ad5934 is in parked vehicle detection. the ad5934 is placed in an embedded unit connected to a coil of wire underneath the parking location. the ad5934 outputs a single frequency within the 80 khz to 100 khz frequency range, depending upon the wire composition. the wire can be modeled as a resonant circuit. the coil is calibrated with a known impedance value and at a known frequency. the impedance of the loop is monitored constantly. if a car is parked over the coil, the impedance of the coil changes and the ad5934 detects the presence of the car. electro - impedance spectrosco py the ad5934 has found use in the area of corrosion monitoring. corrosion in a metal , such as aluminum, which is used in air craft and ships, requires continuous assessment because the metal is exposed to a wide variety of condi tions , such as temperature and moisture. the ad5934 offers an accurate and compact solution for this type of measurement compared to the large and expensive existing units on the market. mathematically the corr osion of a metal is modeled using a rc network that consists of a resistance, r s , in series with a parallel resistor and capacitor, r p and c p . a system metal would typically have values as follows: r s is 10 ? to 10 k? , r p is 1 k? to 1 m? , and c p is 5 f to 70 f. the frequency range of interest when monitoring corrosion is 0.1 hz to 100 khz. to ensure that the measurement itself does not introduce a corrosive effect, the metal needs to be excited with minimal voltage, typically in the 200 mv region , which the ad5934 is capable of outputting. a n earby processor or control unit, such as the aduc702x , would log a single impedance sweep from 0.1 khz to 100 khz every 10 minutes and download the results back to a cont rol unit. t o achieve system accuracy from the 0.1 khz to 1 khz region, the system clock needs to be scaled down from the 16.776 mhz nominal clock frequency to 500 khz, typically. the clock scaling can be achieved digitally using an external direct digital synthesizer , such as the ad9834 , as a programmable divider that supplies a clock signal to mclk and that can be controlled digitally by the nearby microprocessor. ad5934 data sheet rev. c | page 30 of 32 layout and configura tion power supply bypassing and grou nding when accuracy is important in a circuit, carefully consider the power supply and ground return layout on the board. the printed circuit board (pcb) containing the ad5934 should have s eparate analog and digital sections, each having its own area of the board. if the ad5934 is in a system where other devices require an agnd - to - dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5934 . the power supply to the ad5934 should be bypassed with 10 f and 0.1 f capacitors. the capacitors s hould be physically as close as possible to the device, with the 0.1 f capacitor ideally r ight up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and effective series inductance (esi); common ceramic types of capacitors are suitable. the 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itse lf should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feed - through effects on the board. the best board layout technique is the microstrip technique where t he component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2 - layer board. data sheet ad5934 rev. c | page 31 of 32 outline dimensions compliant t o jedec s t andards mo-150-ac 060106- a 16 9 8 1 6.50 6.20 5.90 8.20 7.80 7.40 5.60 5.30 5.00 sea ting plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarit y 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 34 . 16 - lead shrink small outline package [ssop] (rs - 16) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad5934yrsz ?40c to +125c 16- lead shrink small outline package (ssop) rs -16 ad5934yrsz - reel7 ?40c to +125c 16- lead shrink small outline package (ssop) rs -16 1 z = rohs compliant part. ad5934 data sheet rev. c | page 32 of 32 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the p hilips i 2 c pa tent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? 2005 C 2012 analog devices, inc. all rights reserved. trademarks and register ed trademarks are the property of their respective owners. d05325 -0- 7/12(c) |
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