1. product profile 1.1 general description the blm7g1822s-20pb and BLM7G1822S-20PBG are dual path, 2-stage power mmics using nxp?s state of the art gen7 ldmos technology. these multiband devices are perfectly suited as general purpose driver or small cell final in the frequency range from 1805 mhz to 2170 mhz. available in gull wing or flat lead outline. 1.2 features and benefits ? designed for broadband operation (frequency 1805 mhz to 2170 mhz) ? high path-to-path isolation enabling multiple combinations ? integrated temperature compensated bias ? biasing of individual stages is externally accessible ? integrated esd protection ? excellent thermal stability ? high power gain ? on-chip matching for ease of use ? compliant to directive 2002/ 95/ec, regarding restricti on of hazardous substances (rohs) 1.3 applications ? rf power mmic for w-cdma base stations in the 1805 mhz to 2170 mhz frequency range. possible circuit topologies are the following as also depicted in section 8.1 : ? dual path or single ended ? doherty ? quadrature combined ? push-pull blm7g1822s-20pb; BLM7G1822S-20PBG ldmos 2-stage power mmic rev. 1 ? 19 december 2013 objective data sheet table 1. application performance typical rf performance at t case = 25 ? c; i dq1 = ; i dq2 = . test signal: 3gpp test model 1; 64 dpch; clipping at 46 %; par = 8.4 db at 0.01% probability on ccdf per carrier; carrier spacing = 5 mhz; per sect ion unless otherwise s pecified in a class-ab production circuit. test signal f v ds p l(av) g p ? d acpr (mhz) (v) (w) (db) (%) (dbc) 2-carrier w-cdma 2140 28 0.5 31.5 12
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights re served. objective data sheet rev. 1 ? 19 december 2013 2 of 12 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic 2. pinning information 2.1 pinning 2.2 pin description transparent top view the exposed backside of the package is the ground terminal of the device. fig 1. pin configuration d d d 9 ' 6 $ 9 ' 6 % 9 * 6 $ 9 * 6 % 9 * 6 $ 5 ) b 2 8 7 b $ 9 ' 6 $ 5 ) b 2 8 7 b % 9 ' 6 % 9 * 6 % 5 ) b , 1 b $ 5 ) b , 1 b % q f q f q f q f q f q f s l q l q g h [ table 2. pin description symbol pin description v ds(a1) 1 drain-source voltage of stage a1 v gs(a2) 2 gate-source voltage of stage a2 v gs(a1) 3 gate-source voltage of stage a1 rf_in_a 4 rf input path a n.c. 5 not connected n.c. 6 not connected n.c. 7 not connected n.c. 8 not connected n.c. 9 not connected n.c. 10 not connected rf_in_b 11 rf input path of b v gs(b1) 12 gate-source voltage of stage b1 v gs(b2) 13 gate-source voltage of stage b2 v ds(b1) 14 drain-source voltage of stage b1
blm7g1822s-20pb_s-20pbg all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights re served. objective data sheet rev. 1 ? 19 december 2013 3 of 12 nxp semiconductors blm7g1822s-20pb(g) ldmos 2-stage power mmic 3. ordering information 4. block diagram 5. limiting values [1] continuous use at maximum temperature will affect the reliability, for details refer to the on-line mtf calculator. rf_out_b/v ds(b2) 15 rf output path b / drain-source voltage of stage b2 rf_out_a/v ds(a2) 16 rf output path a / drain-source voltage of stage a2 gnd flange rf ground table 2. pin description ?continued symbol pin description table 3. ordering information type number package name description version blm7g1822s-20pb hsop16f plastic, heatsink small outline package; 16 leads (flat) sot1211-1 BLM7G1822S-20PBG hsop16 plastic, heatsi nk small outline package; 16 leads sot1212-1 fig 2. block diagram d d d 9 ' 6 $ 9 ' 6 % 9 * 6 $ 5 ) b 2 8 7 b $ 9 ' 6 $ 5 ) b 2 8 7 b % 9 ' 6 % 9 * 6 % 5 ) b , 1 b $ 5 ) b , 1 b % 7 ( 0 3 ( 5 $ 7 8 5 ( & |