1. product profile 1.1 general description the BLM7G24S-30BG is a 2-stage power mmic using nxp?s state of the art gen7 ldmos technology. this device is perfectly suited as general purpose driver in the frequency range from 2100 mhz to 2400 mhz. available in gull wing. 1.2 features and benefits ? integrated temperature compensated bias ? biasing of individual stages is externally accessible ? integrated current sense ? integrated esd protection ? excellent thermal stability ? high power gain ? on-chip matching for ease of use (input matched to 50 ? ; output partially matched) ? designed for broadband operation (frequency 2100 mhz to 2400 mhz) ? compliant to directive 2002/ 95/ec, regarding restriction of hazardous substances (rohs) 1.3 applications rf power mmic for w-cdma base stations in the 2100 mhz to 2400 mhz frequency range. BLM7G24S-30BG ldmos 2-stage power mmic rev. 1 ? 4 november 2013 product data sheet table 1. application performance typical rf performance at t case = 25 ? c; i dq1 = 75 ma; i dq2 = 233 ma. test signal: 3gpp test model 1; 64 dpch; clipping at 46 %; par = 8.4 db at 0.01% probability on ccdf per carrier; carrier spacing = 5 mhz; unle ss otherwise specified in a class-ab application circuit. test signal f v ds p l(av) g p ? d acpr (mhz) (v) (w) (db) (%) (dbc) 2-carrier w-cdma 2140 28 1.6 31.5 11.3 ? 43 2-carrier w-cdma 2350 28 1.6 29.3 10.7 ? 42
BLM7G24S-30BG all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 4 november 2013 2 of 19 nxp semiconductors BLM7G24S-30BG ldmos 2-stage power mmic 2. pinning information 2.1 pinning 2.2 pin description transparent top view the exposed backside of the package is the ground terminal of the device. fig 1. pin configuration d d d 9 ' 6 $ q f 9 * 6 6 $ q f 9 ' 6 6 $ 5 ) b 2 8 7 b $ 9 ' 6 $ q f q f 5 ) b , 1 b $ q f 9 * 6 6 $ q f 9 ' 6 6 $ q f q f q f s l q l q g h [ table 2. pin description symbol pin description v ds(a1) 1 drain-source voltage of stage a1 v gss(a2) 2 gate sense fet and gate source voltage of stage a2 v dss(a2) 3 drain sense fet source voltage of stage a2 rf_in_a 4 rf input path a v gss(a1) 5 gate sense fet and gate source voltage of stage a1 v dss(a1) 6 drain sense fet source voltage of stage a1 n.c. 7 not connected n.c. 8 not connected n.c. 9 not connected n.c. 10 not connected n.c. 11 not connected n.c. 12 not connected n.c. 13 not connected n.c. 14 not connected
BLM7G24S-30BG all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 4 november 2013 3 of 19 nxp semiconductors BLM7G24S-30BG ldmos 2-stage power mmic 3. ordering information 4. block diagram 5. limiting values [1] continuous use at maximum temperature will affect the mttf. n.c. 15 not connected rf_out_a/v ds(a2) 16 rf output path a / drain source voltage of stage a2 gnd flange rf ground table 2. pin description ?continued symbol pin description table 3. ordering information type number package name description version BLM7G24S-30BG hsop16 plastic, heatsink small outline package; 16 leads sot1212-1 fig 2. block diagram of BLM7G24S-30BG d d d 9 ' 6 $ q f 9 * 6 6 $ q f 9 ' 6 6 $ 5 ) b 2 8 7 b $ 9 ' 6 $ q f q f 5 ) b , 1 b $ q f 7 ( 0 3 ( 5 $ 7 8 5 ( & |