orderin g numbe r : ena1059a monolithic linear ic for tv audio/video switch la72730 overview the la72730 is an audio/video switch for tv. functions ? audio : possible to change 4 channel 2, alc output, 4db amplifier monitor output ? vi deo : possible to change 4 channel, 6db amplifier ? con trol : i 2 c (slave address : 92h) specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max pin 8 7.0 v allowable power dissipation pd max ta 70 c 300 mw operating temperature topr -20 to +70 c storage temperature tstg -55 to +150 c recommended operating conditions at ta = 25 c parameter symbol conditions ratings unit recommended operating voltage v cc pin 8 5.0 v operating voltage range v cc op pin 8 4.5 to 5.5 v specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 21010 sy / 52108 ms pc 20080514-s00004 no.a1059-1/8
la72730 electrical characteristics at ta = 25 c, v dd = 5.0 v ratings parameter symbol conditions min typ max unit current dissipation i cc v cc = 5v , no signal 15.2 18 20.8 ma audio block audio input dc voltage ina no signal pin 1, 2, 3, 4 , 5, 6, 23, 24 dc voltage 2.2 2.4 2.6 v audio output dc voltage oa no signal pin 19, 20 dc voltage 2.2 2.4 2.6 v audio channel bandwidth fa input : 1khz/20khz, -6dbv : pin 19, 20 output -2 0 +2 db audio voltage gain (audio-out) aa1 f = 1khz, v in = -6dbv, pin 19, 20 output -0.3 0.0 +0.3 db audio voltage gain (monitor-out) aa2 f = 1khz, v in = -6dbv, pin 12, 16 output 3.5 4.0 4.5 db audio input dynamic range (audio-out) da1 f = 1khz, thd = 1% pin 19, 20 output -3.0 -1.0 dbv audio input dynamic range (monitor-out) da2 f = 1khz, thd = 1% pin 13, 16 output -5.0 -3.0 dbv audio channel psrr psa v cc = 5v+1vp -p, sine wave (50hz) 35 50 db audio channel input impedance ria 80 100 120 k audio channel output impedance roa 150 200 250 audio channel crosstalk cta f = 1khz 65 80 db audio channel s/n sna filt er = din/audio 70 85 db audio channel thd thda f = 1khz, v in = -6dbv 0.15 0.3 % alc detect level-1 alc1 -10.5 -9 -7.5 dbv alc detect level-2 alc2 -15.5 -14 -12.5 dbv alc detect level-3 alc3 -13.5 -12 -10.5 dbv alc detect level-4 alc4 -19.5 -18 -16.5 dbv video block video input dc voltage inv 1.44 1.6 1.76 v video output dc voltage ov 1.26 1.4 1.54 v video channel bandwidth fv -3db frequency 10 mhz video signal voltage gain av f = 500khz, v in = 1vp-p 5.0 6.0 7.0 db video input dynamic range dv f = 100khz, thd 1% 2.0 2.5 vp-p video channel psrr psv v cc = 5v+1vp -p, sine wave (50hz) 35 50 db video channel input impedance riv 8.0 10 12.0 k video channel output impedance rov 30 40 50 video channel crosstalk ctv f = 3.58mhz, v in = 1vp-p 45 60 db video channel noise snv bandwidth 10mhz 55 60 db package dimensions unit : mm (typ) 3067b 1 12 24 13 21.0 3.9 max 0.51min 3.3 0.95 6.4 7.62 0.25 1.78 0.48 0.9 (0.71) (3.25) sanyo : dip24s(300mil) no.a1059-2/8
la72730 block diagram + + 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 l in -1 0.1f l in -2 0.1f l in -tv 0.1f r in -tv 0.1f 47f + + 47f + 10f + 10f v in -tv audio l out audio r out 220f 75 75 4db alc filt l monitor out nc sda scl l in -3 0.1f r in -1 0.1f r in -2 0.1f + 10f + 10f video out r in -3 0.1f v in -1 v cc 10f v cc 5v 47f 0.1f 100h + v in -2 10f + v in -3 10f + 10f + gnd r monitor out 4db 6db buff buff reg det mode select alc alc no.a1059-3/8
la72730 i 2 c bit pattarn d8 d7 d6 d5 d4 d3 d2 d1 condition * 0 0 av in-tv 0 1 av in-1 1 0 av in-2 1 1 av in-3 * 0 norma 1 mute 0 0 alc level-1 (-9dbv) 0 1 alc level-2 (-14dbv) * 1 0 alc level-3 (-12dbv) 1 1 alc level-4 (-18dbv) * 0 alc-on 1 alc-off 0 prohibit * 1 fix * 0 fix 1 prohibit ?*? : shows initial condition. slave address : 92h (1001 0010) ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 10 5 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 5 10 0 15 ? 30 ? 20 ? 25 ? 15 ? 10 ? 5 ? 15 ? 10 ? 5 ? 20 0 input ? dbv output ? dbv ? 30 ? 25 0 input ? dbv output ? dbv line-out monitor monitor alc-off alc-3 alc-2 alc-4 alc-1 no.a1059-4/8
la72730 test circuit + + 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 l in -1 0.1f 620 l in -2 0.1f 620 l in -tv 0.1f 620 r in -tv 0.1f 1f + 1f 620 v in -tv audio l out audio r out 0.1f 75 4db alc filt l monitor out nc sda scl l in -3 0.1f 620 r in -1 0.1f 620 r in -2 0.1f 620 video out r in -3 0.1f 620 v in -1 v cc 0.1f 75 v cc 5v 47f 0.1f v in -2 0.1f 75 gnd v in -3 0.1f 75 r monitor out 4db 6db buff buff reg det mode select alc alc no.a1059-5/8
la72730 pin functions dc : voltage pin no. pin name function ac : level equivalent circuit 1 2 3 4 5 6 23 24 pia_l1 pia_l2 pia_l3 pia_r1 pia_r2 pia_r3 pia_rtv pia_ltv audio input dc : 2.4v 50k 50k 7 9 11 21 piv_1 piv_2 piv_3 piv_tv video input dc : 1.6v 500 8 v cc 10 gnd 12 16 pomonitr pomonitl monitor output dc : 2.4v 200 13 piscl serial clock input 1k 14 pisda serial data input 1k 17 poalcfil alc detect filter 2k 150 continued on next page no.a1059-6/8
la72730 continued from preceding page. dc : voltage pin no. pin name function ac : level equivalent circuit 18 povideo video output dc : 1.4v 19 20 poalcr poalcl audio output dc : 2.4v 200 10k 22 pcreg reference voltage dc : 2.4v 500 10k 9.6k 1k i 2 c bus serial interface specification (1) data transfer manual this ic adopts control method (i 2 c-bus) with serial data, and controlled by two terminals which called scl (serial clock) and sda (serial data).at first, set up *1 the condition of starting data transfer, and after that, input 8 bit data to sda terminal with synchronized scl terminal clock. the orde r of transferring is first, msb (the most scale of bit), and save the order. the 9th bit takes ack (acknowledge) peri od, during scl terminal takes ?h?, this ic pull down the sda terminal. after transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition, thus the transfer comes to close. *1 defined by sda fall down scl during ?h? period. *2 defined by sda rise up scl during ?h? period. (2) transfer data format after transfer start cond ition , transfers slave address (92h : 1001 0010 ) to sda terminal, control data, then, stop condition (see figure 1). slave address is made up of 7bits, *3 8th bit shows the direction of transferring data, but this ic does not have read mode, so that this bit fix to ?l?. data works with all of bit, transfer the stop condition before stop 8bit transfer, an d to stop transfer, it will be canceled the transfer dates. *3 it is called r/w bit. fig.1 data structure start condition slave address r/w l ack control data ack stop condition (3) initialize this ic is initialized for circuit protection. initial condition is shown on bitmap. no.a1059-7/8
la72730 reference parameter symbol min max unit low level input voltage v il -0.5 1.5 v high level input voltage v ih 2.5 5.5 v low level output current i ol 3.0 ma scl clock frequency f scl 0 100 khz set-up time for a repeated start condition t su : s ta 4.7 s hold time start condition. after this peri od, the first clock pulse is generated t hd : s ta 4.0 s low period of the scl clock t low 4.7 s rise time of both sda and sdl signals t r 0 1.0 s high period of the scl clock t high 4.0 s fall time of both sda and sdl signals t f 0 1.0 s data hold time t hd : dat 0 s data set-up time t su : dat 250 ns set-up time for stop condition t su : sto 4.0 s bus free time between a stop and start condition t buf 4.7 s definition of timing t hd:sta t su:sta t low t r t f t high t hd:data t su:dat t su:sto t buf scl sda sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of february, 2 010. specifications and information herein are subject to change without notice. ps no.a1059-8/8
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