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september 2013 rev 4 1/31 31 vn5050j-e single channel high side driver for automotive applications features main ? inrush current active management by power limitation ? very low stand-by current ? 3.0v cmos compatible input ? optimized electromagnetic emission ? very low electromag netic susceptibility ? in compliance with the 2002/95/ec european directive diagnostic functions ? open drain status output ? on state open load detection ? off state open load detection ? thermal shutdown indication protections ? undervoltage shut-down ? overvoltage clamp ? output stuck to v cc detection ? load current limitation ? self limiting of fast thermal transients ? protection against loss of ground and loss of v cc ? thermal shut down ? reverse battery protection (see figure 27 ) ? electrostatic discharge protection application all types of resistive, inductive and capacitive loads description the vn5050j-e is a monolithic device made using stmicroelectronics vipower technology. it is intended for driving re sistive or inductive loads with one side connected to ground. active v cc pin voltage clamp protects the device against low energy spikes (see iso7637 transient compatibility table). the de vice detects open load condition both in on and off state, when stat_dis is left open or driven low. output shorted to v cc is detected in the off state. when stat_dis is driven high, the status pin is in a high impedance condition.output current limitation protects the device in overload condition. in case of long duration overload, the device limits the dissipated power to safe level up to thermal shut-down intervention.thermal shut- down with automatic restart allows the device to recover normal operation as soon as fault condition disappears. max supply voltage v cc 41v operating voltage range v cc 4.5 to 36v max on-state resistance (per ch.) r on 50 m ? current limitation (typ) i limh 19 a off state supply current i s 2 a (1) (1) typical value with all loads connected. powersso-12 table 1. device summary package order codes tube tape & reel powersso-12 vn5050j-e vn5050jtr-e www.st.com
contents vn5050j-e 2/31 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 gnd protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20 3.1.1 solution 1: resistor in the ground line (rgnd only) . . . . . . . . . . . . . . . . 20 3.1.2 solution 2: diode (dgnd) in the ground line . . . . . . . . . . . . . . . . . . . . . 21 3.2 load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 mcu i/os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 maximum demagnetization energy (vcc = 13.5v) . . . . . . . . . . . . . . . . . 23 4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 powersso-12? thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
vn5050j-e list of tables 3/31 list of tables table 2. pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. suggested connections for unused and n.c. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. switching (vcc = 13v; tj = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 8. status pin (v sd =0v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 9. protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 10. openload detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 11. logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 12. truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 13. electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 14. thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15. powersso-12? mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
list of figures vn5050j-e 4/31 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. high level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 14. status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 15. status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 16. on state resistance vs v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 17. status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 18. openload on state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 19. openload off state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 20. i lim vs t case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 21. turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 22. undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 23. turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 24. stat_dis clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 25. high level stat_dis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 26. low level stat_dis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 27. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 28. open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 29. maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 30. powersso-12? pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 31. rthj-amb vs. pcb copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 24 figure 32. powersso-12? thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 25 figure 33. thermal fitting model of a single channel hsd in powersso-12? . . . . . . . . . . . . . . . . . 25 figure 34. powersso-12? package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 35. powersso-12? tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 36. powersso-12? tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
vn5050j-e block diagram and pin description 5/31 1 block diagram and pin description figure 1. block diagram table 2. pin function name function v cc battery connection. output power output. gnd ground connection. must be reverse battery protected by an external diode/resistor network. input voltage controlled input pin with hysteres is, cmos compatible. controls output switch state. status open drain digital diagnostic pin. stat_dis active high cmos compatible pin, to disable the status pin. logic undervoltage overtemp. i lim pwclamp gnd input output driver v cc clamp v dslim stat_dis status openload on openload off pwr lim v cc
block diagram and pin description vn5050j-e 6/31 figure 2. configuration diagram (top view) note: the above pin configuration reflects the changes notified with pcn-apg-bod/07/2886. the new pinout is backaward compatible with existing pcb layouts where pins #1 and #6 are connected to vcc and/or pins #7 and 12 are connected to output. for new pcb designs, these pins should be left unconnected. powersso-12 ta b = v cc n.c. output output output n.c. output 12 11 10 9 8 7 1 2 3 4 5 6 n.c. n.c. input status_dis gnd status table 3. suggested connections for unused and n.c. pins connection / pin status n.c. output input stat_dis floating x x x x x to ground n.r. (1) (1) not recommended. xn.r. through 10k ?? resistor through 10k ?? resistor
vn5050j-e electrical specifications 7/31 2 electrical specifications figure 3. current and voltage conventions note: v f = v out - v cc during reverse battery condition. 2.1 absolute maximum ratings stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implie d. exposure to the conditions in table below for extended periods may affect device reliability. refer al so to the stmicroelectronics sure program and other relevant quality document. i gnd v cc gnd output stat_dis i sd input i in v sd v in i out v out status i stat v stat v cc i s v f table 4. absolute maximum ratings symbol parameter value unit v cc dc supply voltage 41 v - v cc reverse dc supply voltage 0.3 v - i gnd dc reverse ground pin current 200 ma i out dc output current internally limited a - i out reverse dc output current 12 a i in dc input current +10 / -1 ma i stat dc status current +10 / -1 ma i stat_dis dc status disable current +10 / -1 ma e max maximum switching energy (l=3mh; r l =0 ? ; v bat =13.5v; t jstart =150oc; i out = i liml (typ.) ) 104 mj
electrical specifications vn5050j-e 8/31 2.2 thermal data v esd electrostatic discharge (human body model: r=1.5k ?? c=100pf) v esd charge device model (cdm-aec-q100-011) 750 v t j junction operating temperature -40 to 150 c t stg storage temperature - 55 to 150 c table 4. absolute maximum ratings (continued) symbol parameter value unit table 5. thermal data symbol parameter value unit r thj-case thermal resistance junction-case (max.) (with one channel on) 2.7 c/w r thj-amb thermal resistance junction-ambient (max.) see figure 31 c/w
vn5050j-e electrical specifications 9/31 2.3 electrical characteristics values specified in th is section are for 8v electrical specifications vn5050j-e 10/31 table 8. status pin (v sd =0v) symbol parameter test conditions min. typ. max. unit v stat status low output voltage i stat = 1.6 ma, v sd =0v 0.5 v i lstat status leakage current normal operation or v sd =5v, ? v stat = 5v 10 a c stat status pin input capacitance normal operation or v sd =5v, ? v stat = 5v 100 pf v scl status clamp voltage i stat = 1ma i stat = -1ma 5.5 -0.7 7v v table 9. protections (1) (1) to ensure long term reliability under heavy overload or s hort circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. if the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. symbol parameter test conditions min. typ. max. unit i limh dc short circuit current v cc = 13v 5vt tsd (see figure 4 )20s v demag turn-off output voltage clamp i out =2a; v in =0; l=6mh v cc -41 v cc -46 v cc -52 v v on output voltage drop limitation i out = 0.1a; t j = -40c...+150c (see figure 6 ) 25 mv
vn5050j-e electrical specifications 11/31 table 10. openload detection symbol parameter test conditions min. typ. max. unit i ol openload on state detection threshold v in = 5v ,8v electrical specifications vn5050j-e 12/31 figure 4. status timings truth table table 12. truth table conditions input output status (v sd =0v) (1) (1) if the v sd is high, the status pin is in a high impedance. normal operation l h l h h h current limitation l h l x h h overtemperature l h l l h l undervoltage l h l l x x output voltage > v ol l h h h lv h output current < i ol l h l h h (2) l (2) the status pin becomes hi gh with a delay equal to t pol after input falling edge. v in v stat t pol open load status timing (without external pull-up) i out < i ol v out < v ol t dol(on) v in v stat open load status timing (with external pull-up) i out < i ol v out > v ol t dol(on) v in v stat over temp status timing t sdl t sdl t j > t tsd v in v stat t dstkon output stuck to v cc i out > i ol v out > v ol t dol(on)
vn5050j-e electrical specifications 13/31 figure 5. switching characteristics figure 6. output voltage drop limitation v out dv out /dt (on) t r 80% 10% t f dv out /dt (off) t d(off) t d(on) input t t 90% t won t woff v on i out v cc -v out t j =150 o c t j =25 o c t j =-40 o c v on /r on(t)
electrical specifications vn5050j-e 14/31 table 13. electrical transient requirements iso 7637-2: 2004(e) test pulse test levels number of pulses or test times burst cycle/pulse repetition time delays and impedance iii iv 1 -75v -100v 5000 pulses 0.5 s 5 s 2 ms, 10 ? 2a +37v +50v 5000 pulses 0.2 s 5 s 50 s, 2 ? 3a -100v -150v 1h 90 ms 100 ms 0.1 s, 50 ? 3b +75v +100v 1h 90 ms 100 ms 0.1 s, 50 ? 4-6v-7v1 pulse 100 ms, 0.01 ? 5b (2) +65v +87v 1 pulse 400 ms, 2 ? iso 7637-2: 2004(e) test pulse test level results (1) (1) the above test levels must be considered referred to v cc = 13.5v except for pulse 5b. iii iv 1c c 2a c c 3a c c 3b c c 4c c 5b (2) (2) valid in case of external load dump clamp: 40v maximum referred to ground. cc class contents c all functions of the device are performed as designed after exposure to disturbance. e one or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to pro per operation without replacing the device.
vn5050j-e electrical specifications 15/31 figure 7. waveforms status input normal operation undervoltage v cc v usd v usdhyst input status load current load current stat_dis stat_dis undefined open load without external pull-up status input status input open load with external pull-up load voltage load voltage v ol v out >v ol stat_dis stat_dis load current i out v ol stat_dis i out >i ol t dstkon t pol overload operation input status t tsd t r t j load current stat_dis t rs i limh i liml thermal cycling power limitation current limitation shorted load normal load
electrical specifications vn5050j-e 16/31 2.4 electrical characteristics curves figure 8. off state output current figure 9. high level input current figure 10. input clamp voltage figure 11. input high level figure 12. input low level figure 13. input hysteresis voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.125 0.25 0.375 0.5 0.625 0.75 0.875 1 iloff1 (ua) off state vcc=13v vin=vout=0v -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 lih (ua) vin=2.1v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 6 6.25 6.5 6.75 7 7.25 7.5 7.75 8 vicl (v) lin=1ma -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.5 1 1.5 2 2.5 3 3.5 4 vih (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.5 1 1.5 2 2.5 3 3.5 4 vil (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 vihyst (v)
vn5050j-e electrical specifications 17/31 figure 14. status low output voltage on state resistance vs t case figure 15. status leakage current figure 16. on state resistance vs v cc figure 17. status clamp voltage figure 18. openload on state detection threshold -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 vstat (v) istat=1.6ma -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 10 20 30 40 50 60 70 80 90 100 ron (mohm) iout=2a vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0.025 0.03 0.035 0.04 0.045 0.05 0.055 ilstat (ua) vstat=5v 0 5 10 15 20 25 30 35 40 vcc (v) 0 10 20 30 40 50 60 70 80 90 100 ron (mohm) tc= 150c tc= 125c tc= 25c tc= -40c -50 -25 0 25 50 75 100 125 150 175 tc ( c) 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 vscl (v) istat=1ma -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 10 20 30 40 50 60 70 80 90 100 iol (ma) vin=5v
electrical specifications vn5050j-e 18/31 figure 19. openload off state voltage detection threshold figure 20. i lim vs t case figure 21. turn-on voltage slope figure 22. undervoltage shutdown figure 23. turn-off voltage slope figure 24. stat_dis clamp voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c) 1 1.5 2 2.5 3 3.5 4 4.5 5 vol (v) vin=0v -50 -25 0 25 50 75 100 125 150 175 tc ( c) 5 7.5 10 12.5 15 17.5 20 22.5 25 ilimh (a) vcc=13v -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 100 200 300 400 500 600 700 800 900 1000 dvout/dt(on) (v/ms) vcc=13v ri=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 2 4 6 8 10 12 14 vusd (v) -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 100 200 300 400 500 600 700 800 900 1000 dvout/dt(off) (v/ms) vcc=13v ri=6.5ohm -50 -25 0 25 50 75 100 125 150 175 tc ( c) 0 2 4 6 8 10 12 14 vsdcl(v) isd=1ma
vn5050j-e electrical specifications 19/31 figure 25. high level stat_dis voltage figure 26. low level stat_dis voltage -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 1 2 3 4 5 6 7 8 vsdh(v) -50 -25 0 25 50 75 100 125 150 175 tc ( c ) 0 1 2 3 4 5 6 7 8 vsdl(v)
application information vn5050j-e 20/31 3 application information figure 27. application schematic 3.1 gnd protection networ k against reverse battery 3.1.1 solution 1: resist or in the ground line (r gnd only) this can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. 1. r gnd ? 600mv / (i s(on)max ). 2. r gnd ???? v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. power dissipation in r gnd (when v cc <0: during reverse battery situations) is: p d = (-v cc ) 2 /r gnd this resistor can be shared amongst several different hsds. please note that the value of this resistor should be calculated with formula (1) where i s(on)max becomes the sum of the maximum on-state currents of the different devices. please note that if the microprocessor ground is not shared by the device ground then the r gnd will produce a shift (i s(on)max * r gnd ) in the input thresholds and the status output values. this shift will vary depending on how ma ny devices are on in the case of several high side drivers sharing the same r gnd . if the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then st suggest s to utilize solution 2 (see below). v cc gnd output d gnd r gnd d ld ? c +5v v gnd stat_dis input r prot r prot r prot +5v status
vn5050j-e application information 21/31 3.1.2 solution 2: diode (d gnd ) in the ground line a resistor (r gnd =1k ??? should be inserted in parallel to d gnd if the device drives an inductive load. this small signal diode can be safely shared amongst several different hsds. also in this case, the presence of the grou nd network will produce a shift ( ? 600mv) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. this shift will not vary if more than one hsd shares t he same diode/resistor network. 3.2 load dump protection d ld is necessary ( voltage transient suppressor ) if the load dump peak voltage exceeds the v cc max dc rating. the same applies if the device is subject to transients on the v cc line that are greater than the ones shown in the iso 7637-2: 2004(e) table. 3.3 mcu i/os protection if a ground protection network is used and negative transient are present on the v cc line, the control pins will be pulled negative. st suggests to insert a resistor (r prot ) in line to prevent the c i/os pins to latch-up. the value of these resistors is a compromise between the leakage current of ? c and the current required by the hsd i/os (input levels compatibilit y) with the latch-up limit of ? c i/os. -v ccpeak /i latchup ? r prot ? (v oh c -v ih -v gnd ) / i ihmax calculation example: for v ccpeak = - 100v and i latchup ? 20ma; v oh c ? 4.5v 5k ? ? r prot ? 180k ? . recommended values: r prot =10k ? . 3.4 open load detection in off state off state open load detection requires an external pull-up resistor (r pu ) connected between output pin and a positive supply voltage (v pu ) like the +5v line used to supply the microprocessor. the external resistor has to be selected according to the following requirements: 1. no false open load indication when load is connected: in this case we have to avoid v out to be higher than v olmin ; this results in the following condition ? v out =(v pu /(r l +r pu ))r l application information vn5050j-e 22/31 the values of v olmin , v olmax and i l(off2) are available in the electrical characteristics section. figure 28. open load detection in off state v ol v batt. v pu r pu r l r driver + logic + - input status v cc out ground i l(off2)
vn5050j-e application information 23/31 3.5 maximum demagnetization energy (v cc = 13.5v) figure 29. maximum turn off current versus inductance note: values are generated with r l =0 ?? in case of repetitive pulses, t jstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves a and b. 1 10 100 0,1110100 l (mh) i (a) c: t jstart = 125c repetitive pulse a: t jstart = 150c single pulse b: t jstart = 100c repetitive pulse demagnetization demagnetization demagnetization t v in , i l a b c
package and pcb thermal data vn5050j-e 24/31 4 package and pcb thermal data 4.1 powersso-12 ? thermal data figure 30. powersso-12 ? pc board note: layout condition of r th and z th measurements (pcb: double layer, thermal vias, fr4 area= 77mm x 86mm,pcb thickness=1.6mm, cu thickness=70 m (front and back side), copper areas: from minimum pad lay-out to 8cm 2 ). figure 31. r thj-amb vs. pcb copper area in open box free air condition 35 40 45 50 55 60 65 0246810 rthj_amb(c/ w) pcb cu heatsink area (cm^ 2)
vn5050j-e package and pcb thermal data 25/31 figure 32. powersso-12? thermal impedance junction ambient single pulse equation 1: pulse calculation formula where ? = t p /t figure 33. thermal fitting model of a single channel hsd in powersso-12? (a) (a )the fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during ther mal shutdown) are not triggered. 0,1 1 10 100 0,001 0,01 0,1 1 10 100 1000 time ( s) zth (c/ w) footprint 8 cm 2 2 cm 2 z th ? r th ? z thtp 1 ? ? ?? + ? =
package and pcb thermal data vn5050j-e 26/31 table 14. thermal parameter area/island (cm 2 ) footprint 2 8 r1 (c/w) 0.7 r2 (c/w) 2.8 r3 (c/w) 3 r4 (c/w) 8 8 7 r5 (c/w) 22 15 10 r6 (c/w) 26 20 15 c1 (w.s/c) 0.001 c2 (w.s/c) 0.0025 c3 (w.s/c) 0.0166 c4 (w.s/c) 0.2 0.1 0.1 c5 (w.s/c) 0.27 0.8 1 c6 (w.s/c) 3 6 9
vn5050j-e package and packing information 27/31 5 package and packing information 5.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second-level interconnect. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. ? the maximum ratings related to soldering conditions are also marked on the inner box label. ? ecopack is an st trademark. ecopack specifications are available at: www.st.com. 5.2 package mechanical data figure 34. powersso-12? package dimensions
package and packing information vn5050j-e 28/31 table 15. powersso-12? mechanical data symbol millimeters min. typ. max. a 1.250 1.620 a1 0.000 0.100 a2 1.100 1.650 b 0.230 0.410 c 0.190 0.250 d 4.800 5.000 e 3.800 4.000 e0.800 h 5.800 6.200 h 0.250 0.500 l 0.400 1.270 k0 8 x 2.200 2.800 y 2.900 3.500 ddd 0.100
vn5050j-e package and packing information 29/31 5.3 packing information figure 35. powersso-12 ? tube shipment (no suffix) figure 36. powersso-12 ? tape and reel shipment (suffix ?tr?) all dimensions are in mm. base q.ty 100 bulk q.ty 2000 tube length ( 0.5) 532 a1.85 b6.75 c ( 0.1) 0.6 a c b base q.ty 2500 bulk q.ty 2500 a (max) 330 b (min) 1.5 c ( 0.2) 13 f20.2 g (+ 2 / -0) 12.4 n (min) 60 t (max) 18.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 12 tape hole spacing p0 ( 0.1) 4 component spacing p 8 hole diameter d ( 0.05) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.1) 5.5 compartment depth k (max) 4.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed
revision history vn5050j-e 30/31 6 revision history table 16. document revision history date revision changes 30-mar-2006 1 initial release. 13-sep-2007 2 document reformatted and restructured. contents and lists of tables and figures added. figure 2: configuration diagram (top view) updated: pins 1-6-7- 12 n.c. (not connected). table 4: absolute maximum ratings : e max entries updated. table 13: electrical transient requirements :test level values iii and iv for test pulse 5b and notes updated. section 3.5: maximum demagnetization energy (vcc = 13.5v) added. figure 33: thermal fitting model of a single channel hsd in powersso-12? : note added table 15: powersso-12? mechanical data : slug dimensions (x,y) corrected 10-dec-2007 3 figure 2: configuration diagram (top view) : added note. updated section 4.1: powers so-12? thermal data : ? changed figure 31: rthj-amb vs. pcb copper area in open box free air condition . ? changed figure 32: powersso-12? thermal impedance junction ambient single pulse . ? updated ta b l e 14: thermal parameter : r1 value changed from 0.6 to 0.7 c/w. r3 value changed from 6.5 to 3 c/w. r4 values changed from 10 /10 /9 to 8 /8 /7 c/w. c3 value changed from 0.022 to 0.0166 w.s/c. 25-sep-2013 4 updated disclaimer.
vn5050j-e 31/31 ? please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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