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  1. general description the 74ahc32-q100; 74ahct32-q100 is a high -speed si-gate cmos device and is pin compatible with low-power schottky ttl (l sttl). it is specified in compliance with jedec standard no. 7-a. the 74ahc32-q100; 74ahct32-q100 provides the 2-input or function. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? balanced propagation delays ? all inputs have schmitt-trigger actions ? inputs accept voltages higher than v cc ? input levels: ? for 74ahc32-q100: cmos level ? for 74ahct32-q100: ttl level ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 74ahc32-q100; 74ahct32-q100 quad 2-input or gate rev. 1 ? 26 march 2013 product data sheet
74ahc_ahct32_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 26 march 2013 2 of 15 nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74ahc32-q100 74ahc32d-q100 ? 40 ? c to +125 ? c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74ahc32pw-q100 ? 40 ? c to +125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74AHC32BQ-Q100 ? 40 ? c to +125 ? c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 ? 3 ? 0.85 mm sot762-1 74ahct32-q100 74ahct32d-q100 ? 40 ? c to +125 ? c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74ahct32pw-q100 ? 40 ? c to +125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74ahct32bq-q100 ? 40 ? c to +125 ? c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 ? 3 ? 0.85 mm sot762-1 fig 1. logic symbol fig 2. iec logic symbol mna242 1a 1b 1y 2 1 3 2a 2b 2y 5 4 6 3a 3b 3y 10 9 8 4a 4b 4y 13 12 11 mna243 3 1 1 1 1 2 1 6 5 4 8 10 9 11 13 12 fig 3. logic diagram (one gate) mna241 a b y
74ahc_ahct32_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 26 march 2013 3 of 15 nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate 5. pinning information 5.1 pinning 5.2 pin description (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 4. pin configuration so14 and tssop14 fig 5. pin configuration dhvqfn14 
             
 

  
          
 
 
 
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    #$ %& table 2. pin description symbol pin description 1a 1 data input 1b 2 data input 1y 3 data output 2a 4 data input 2b 5 data input 2y 6 data output gnd 7 ground (0 v) 3y 8 data output 3a 9 data input 3b 10 data input 4y 11 data output 4a 12 data input 4b 13 data input v cc 14 supply voltage
74ahc_ahct32_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 26 march 2013 4 of 15 nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate 6. functional description [1] h = high voltage level; l = low voltage level; x = don?t care. 7. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] for so14 packages: above 70 ? c the value of p tot derates linearly at 8 mw/k. for tssop14 packages: above 60 ? c the value of p tot derates linearly at 5.5 mw/k. for dhvqfn14 packages: above 60 ? c the value of p tot derates linearly at 4.5 mw/k. 8. recommended operating conditions table 3. function table [1] input output na nb ny lll xhh hxh table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +7.0 v v i input voltage ? 0.5 +7.0 v i ik input clamping current v i < ? 0.5 v [1] ? 20 - ma i ok output clamping current v o < ? 0.5 v or v o > v cc + 0.5 v [1] ? 20 +20 ma i o output current v o = ? 0.5 v to (v cc + 0.5 v) ? 25 +25 ma i cc supply current - +75 ma i gnd ground current ? 75 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = ? 40 ? cto+125 ?c [2] - 500 mw table 5. operating conditions symbol parameter conditions min typ max unit 74ahc32-q100 v cc supply voltage 2.0 5.0 5.5 v v i input voltage 0 - 5.5 v v o output voltage 0 - v cc v t amb ambient temperature ? 40 +25 +125 ?c ? t/ ? v input transition rise and fall rate v cc = 3.0 v to 3.6 v - - 100 ns/v v cc = 4.5 v to 5.5 v - - 20 ns/v
74ahc_ahct32_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 26 march 2013 5 of 15 nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate 9. static characteristics 74ahct32-q100 v cc supply voltage 4.5 5.0 5.5 v v i input voltage 0 - 5.5 v v o output voltage 0 - v cc v t amb ambient temperature ? 40 +25 +125 ?c ? t/ ? v input transition rise and fall rate v cc = 4.5 v to 5.5 v - - 20 ns/v table 5. operating conditions ?continued symbol parameter conditions min typ max unit table 6. static characteristics at recommended operating conditions; voltag es are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ? c ? 40 ? cto+85 ?c ? 40 ? cto+125 ?c unit min typ max min max min max 74ahc32-q100 v ih high-level input voltage v cc =2.0v 1.5 - - 1.5 - 1.5 - v v cc =3.0v 2.1 - - 2.1 - 2.1 - v v cc = 5.5 v 3.85 - - 3.85 - 3.85 - v v il low-level input voltage v cc = 2.0 v - - 0.5 - 0.5 - 0.5 v v cc = 3.0 v - - 0.9 - 0.9 - 0.9 v v cc = 5.5 v - - 1.65 - 1.65 - 1.65 v v oh high-level output voltage v i =v ih or v il i o = ? 50 ? a; v cc = 2.0 v 1.9 2.0 - 1.9 - 1.9 - v i o = ? 50 ? a; v cc = 3.0 v 2.9 3.0 - 2.9 - 2.9 - v i o = ? 50 ? a; v cc = 4.5 v 4.4 4.5 - 4.4 - 4.4 - v i o = ? 4.0 ma; v cc = 3.0 v 2.58 - - 2.48 - 2.40 - v i o = ? 8.0 ma; v cc = 4.5 v 3.94 - - 3.80 - 3.70 - v v ol low-level output voltage v i =v ih or v il i o =50 ? a; v cc = 2.0 v - 0 0.1 - 0.1 - 0.1 v i o =50 ? a; v cc = 3.0 v - 0 0.1 - 0.1 - 0.1 v i o =50 ? a; v cc = 4.5 v - 0 0.1 - 0.1 - 0.1 v i o =4.0ma; v cc = 3.0 v - - 0.36 - 0.44 - 0.55 v i o =8.0ma; v cc = 4.5 v - - 0.36 - 0.44 - 0.55 v i i input leakage current v i = 5.5 v or gnd; v cc =0vto5.5v - - 0.1 - 1.0 - 2.0 ? a i cc supply current v i =v cc or gnd; i o =0a; v cc =5.5v - - 2.0 - 20 - 40 ? a c i input capacitance v i =v cc or gnd - 3 10 - 10 - 10 pf c o output capacitance -4-----pf
74ahc_ahct32_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 26 march 2013 6 of 15 nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate 10. dynamic characteristics 74ahct32-q100 v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 - - 2.0 - 2.0 - v v il low-level input voltage v cc = 4.5 v to 5.5 v - - 0.8 - 0.8 - 0.8 v v oh high-level output voltage v i =v ih or v il ; v cc =4.5v i o = ? 50 ? a 4.4 4.5 - 4.4 - 4.4 - v i o = ? 8.0 ma 3.94 - - 3.80 - 3.70 - v v ol low-level output voltage v i =v ih or v il ; v cc =4.5v i o =50 ? a - 0 0.1 - 0.1 - 0.1 v i o = 8.0 ma - - 0.36 - 0.44 - 0.55 v i i input leakage current v i = 5.5 v or gnd; v cc =0vto5.5v - - 0.1 - 1.0 - 2.0 ? a i cc supply current v i =v cc or gnd; i o =0a; v cc =5.5v - - 2.0 - 20 - 40 ? a ? i cc additional supply current per input pin; v i =v cc ? 2.1 v; other pins at v cc or gnd; i o =0a; v cc = 4.5 v to 5.5 v - - 1.35 - 1.5 - 1.5 ma c i input capacitance v i =v cc or gnd - 3 10 - 10 - 10 pf c o output capacitance -4-----pf table 6. static characteristics ?continued at recommended operating conditions; voltag es are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ? c ? 40 ? cto+85 ?c ? 40 ? cto+125 ?c unit min typ max min max min max table 7. dynamic characteristics voltages are referenced to gnd (ground = 0 v); for test circuit see figure 7 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ? c ? 40 ? c to +125 ?c unit min typ [1] max min max min max 74ahc32-q100 t pd propagation delay na, nb to ny; see figure 6 [2] v cc = 3.0 v to 3.6 v c l = 15 pf - 3.9 7.9 1.0 9.5 1.0 10.0 ns c l = 50 pf - 5.6 11.4 1.0 13 1.0 14.5 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 2.8 5.5 1.0 6.5 1.0 7.0 ns c l = 50 pf - 4.1 7.5 1.0 8.5 1.0 9.5 ns c pd power dissipation capacitance f i = 1 mhz; v i =gndtov cc [3] -10- - - - -pf
74ahc_ahct32_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 26 march 2013 7 of 15 nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate [1] typical values are measured at nominal supply voltage (v cc = 3.3 v and v cc =5.0v). [2] t pd is the same as t plh and t phl . [3] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l ? v cc 2 ? f o ) = sum of the outputs. 11. waveforms 74ahct32-q100; v cc =4.5vto5.5v t pd propagation delay na, nb to ny; see figure 6 [2] c l = 15 pf - 3.1 6.9 1.0 8.0 1.0 9.0 ns c l = 50 pf - 4.3 7.9 1.0 9.0 1.0 10.0 ns c pd power dissipation capacitance f i = 1 mhz; v i =gndtov cc [3] -12- - - - -pf table 7. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v); for test circuit see figure 7 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ? c ? 40 ? c to +125 ?c unit min typ [1] max min max min max measurement points are given in table 8 . v ol and v oh are typical voltage output levels that occur with the output load. fig 6. input to output propagation delays mna224 na, nb input ny output t plh t phl gnd v i v m v m v oh v ol table 8. measurement points type input output v m v m 74ahc32-q100 0.5 ? v cc 0.5 ? v cc 74ahct32-q100 1.5 v 0.5 ? v cc
74ahc_ahct32_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 26 march 2013 8 of 15 nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate test data is given in table 9 . definitions test circuit: r t = termination resistance should be equal to output impedance z o of the pulse generator. c l = load capacitance including jig and probe capacitance. fig 7. test circuit for measuring switching times 001aah768 t w t w t r t r t f v m v i negative pulse gnd v i positive pulse gnd 10 % 90 % 90 % 10 % v m v m v m t f v cc dut r t v i v o c l g table 9. test data type input load test v i t r , t f c l 74ahc32-q100 v cc ? 3.0ns 15pf, 50pf t plh , t phl 74ahct32-q100 3.0 v ? 3.0ns 15pf, 50pf t plh , t phl
74ahc_ahct32_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 26 march 2013 9 of 15 nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate 12. package outline fig 8. package outline sot108-1 (so14) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1
74ahc_ahct32_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 26 march 2013 10 of 15 nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate fig 9. package outline sot402-1 (tssop14) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index
74ahc_ahct32_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 26 march 2013 11 of 15 nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate fig 10. package outline sot762-1 (dhvqfn14) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.1 2.9 d h 1.65 1.35 y 1 2.6 2.4 1.15 0.85 e 1 2 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot762-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot762-1 dhvqfn14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 26 13 9 8 7 1 14 x d e c b a 02-10-17 03-01-27 terminal 1 index area ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
74ahc_ahct32_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 26 march 2013 12 of 15 nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate 13. abbreviations 14. revision history table 10. abbreviations acronym description cdm charged device model cmos complementary metal-oxide semiconductor dut device under test esd electrostatic discharge hbm human body model lsttl low-power schottky transistor-transistor logic mil military mm machine model table 11. revision history document id release date data sheet status change notice supersedes 74ahc_ahct32_q100 v.1 20130326 product data sheet - -
74ahc_ahct32_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 26 march 2013 13 of 15 nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74ahc_ahct32_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved . product data sheet rev. 1 ? 26 march 2013 14 of 15 nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74ahc32-q100; 74ahct32-q100 quad 2-input or gate ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 26 march 2013 document identifier: 74ahc_ahct32_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 functional description . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 recommended operating conditions. . . . . . . . 4 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 5 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 6 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 13 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 16 contact information. . . . . . . . . . . . . . . . . . . . . 14 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15


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