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this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this procuts. no rights under any patent accompany the sales o f the product. 1/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology features general description block diagram ? ieee802.3 clause 9 and ieee802.3u cluse 27 compliant. ? provide 4 rmii (reduced media independent interface) ports and 1 mii port. ? provide 2 inter_repeater stacking bus for 10m and 100m port expansion each. ? support stacking to 4 units without any external arbitration logic ( if use external arbitration logic, theoretically can stack to 6 units and up) . ? build_in 2 port switch controller, support up to 2048 mac addresses filtering database. ? optional back_pressure flow control ? optional up_link_switch port function (in slave hub), support 100fx 2km distance extension in 100fd mode. ? meet class_2 repeater specification for 100m_hub. ? use simple and low cost asynchronous sram (high speed asram 128k*8 : one pcs only) ? 128 pin pqfp package, 5v operation voltage. 5 port 10m/100m hub with 2 port switch the MTD655 is a highly integrated, 10m/ 100m dual speed hub with build_in 2 port switch. support 4 rmii ports and 1 mii port for 10m/ 100m operation, and meet 100m_hub class_2 spec when connect with external phyceivers. the MTD655 provides two inter-repeater stacking bus for 10m and 100m expansion each, easily stack to 4 units without any external arbi- tration logic. if using external arbitration logic and proper bus driver, can stack to 6 units and up. the build_in 2 port switch, support 2k mac addresses filtering, and use low cost asynchro- nous high speed sram (128k*8) one pcs only for packet buffering. this 2 port switch can also be configured to be up_link switch when hub is under slave mode. the MTD655 also support an simple and effective led display function, provide 10m_col, 100m_col, memory_test_fail, and per port?s parti- tion status. asram interface rmii4 rmii3 rmii2 rmii1 mii0 10m hub 100m hub two port switch uplink switch enable(10/100,fd/hd) 10m_hd 100m_hd port switch logic 10m inter hub bus 100m inter hub bus
this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this procuts. no rights under any patent accompany the sales o f the product. 2/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology system diagram MTD655 MTD655 physceiver quad physceiver asram (128kx8) 10m inter hub bus 100m inter hub bus 10m inter hub bus 100m inter hub bus MTD655 MTD655 10m inter hub bus 100m inter hub bus 10m inter hub bus 100m inter hub bus mii0 rmii1-4 db25 connector transformer quad transformer rj45 rj45
3/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology 1.0 pin connection 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 a 1 1 a 5 a 9 a 6 a 8 a 7 a 1 3 a 1 2 w e b a 1 4 g n d a 1 5 a 1 6 i r e q 1 0 _ o u t i r e q 1 0 _ i n 0 i r e q 1 0 _ i n 1 i r e q 1 0 _ i n 2 i c o l b 1 0 i a c k b 1 0 i c l k 1 0 g n d i d a t 1 0 i r e q 1 0 0 _ o u t i r e q 1 0 0 _ i n 0 i r e q 1 0 0 _ i n 1 i r e q 1 0 0 _ i n 2 i c o l b 1 0 0 i a c k b 1 0 0 g n d i c l k 1 0 0 v c c i d a t 1 0 0 _ 0 i d a t 1 0 0 _ 1 i d a t 1 0 0 _ 2 i d a t 1 0 0 _ 3 i m a s t e r f d 4 u p s w e n vcc a4 gnd oeb a3 a10 a2 a1 d7 a0 d6 d0 d5 d1 gnd d4 d2 d3 vcc sysclk gnd leddat ledclk mdc mdio rstb 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 g n d n c v c c n c n c g n d g n d s p d 0 t x d 0 _ 3 t x d 0 _ 2 n c t x c l k 0 g n d g n d r x c l k 0 t x d 0 _ 1 t x d 0 _ 0 t x e n 0 r x d 0 _ 0 r x d 0 _ 1 g n d n c n c n c g n d g n d r x d 0 _ 2 r x d 0 _ 3 r x d v 0 c r s 0 v c c g n d c r s d v 1 t x d 1 _ 1 t x d 1 _ 0 t x e n 1 r x d 1 _ 0 r x d 1 _ 1 MTD655 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 spd1 spd2 spd3 spd4 gnd vcc rxd4_1 rxd4_0 txen4 txd4_0 txd4_1 crsdv4 rxd3_1 rxd3_0 txen3 txd3_0 txd3_1 crsdv3 gnd vcc rxd2_1 rxd2_0 txen2 txd2_0 txd2_1 crsdv2
4/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology 1.0 pin descriptions mii port interface pins (port0) name pin number i/o descriptions rxd0_0 rxd0_1 rxd0_2 rxd0_3 19 20 27 28 i i i i port0 mii receive data bit_0. port0 mii receive data bit_1. port0 mii receive data bit_2. port0 mii receive data bit_3. crs0 30 i port0 mii asynchronous carrier indicator from phy device. rxdv0 29 i port0 mii synchronous receive data valid signal from phy device. rxclk0 15 i port0 mii receive clock. txen0 18 o port0 mii transmit enable signal. txd0_0 txd0_1 txd0_2 txd0_3 17 16 10 9 o o o o port0 mii transmit data bit_0. port0 mii transmit data bit_1. port0 mii transmit data bit_2. port0 mii transmit data bit_3. txclk0 12 i port0 mii transmit clock. rmii port interface pins (port1 ~port4) name pin number i/o descriptions crsdv1 33 i port1 rmii receive interface signal, crsdv1 is asserted high when port1 media is non_idle. rxd1_0 rxd1_1 37 38 i i port1 rmii receive data bit_0. port1 rmii receive data bit_1. txen1 36 o port1 rmii transmit enable signal. txd1_0 txd1_1 35 34 o o port1 rmii transmit data bit_0. port1 rmii transmit data bit_1. crsdv2 39 i port2 rmii receive interface signal, crsdv2 is asserted high when port2 media is non_idle. rxd2_0 rxd2_1 43 44 i i port2 rmii receive data bit_0. port2 rmii receive data bit_1. txen2 42 o port2 rmii transmit enable signal. txd2_0 txd2_1 41 40 o o port2 rmii transmit data bit_0. port2 rmii transmit data bit_1. crsdv3 47 i port3 rmii receive interface signal, crsdv3 is asserted high when port3 media is non_idle. rxd3_0 rxd3_1 51 52 i i port3 rmii receive data bit_0. port3 rmii receive data bit_1. txen3 50 o port3 rmii transmit enable signal. txd3_0 txd3_1 49 48 o o port3 rmii transmit data bit_0. port3 rmii transmit data bit_1. crsdv4 53 i port4 rmii receive interface signal, crsdv4 is asserted high when port4 media is non_idle.
5/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology note: asynchronous sram acess time: 10/12 ns (max) rxd4_0 rxd4_1 57 58 i i port4 rmii receive data bit_0. port4 rmii receive data bit_1. txen4 56 o port4 rmii transmit enable signal. txd4_0 txd4_1 55 54 o o port4 rmii transmit data bit_0. port4 rmii transmit data bit_1. high speed asynchronous sram interface pins name pin number i/o descriptions web 94 o asram control pin for write (low active). oeb 106 o asram control pin for read (low active). d[7:0] 111,113,115, 118,120,119, 116,114 i/o asram data bus a[16:0] 90,91,93,96, 95,102,108, 100,98,97,99 ,101,104,107 ,109,110,112 o asram address bus 10m inter-bus interface pins name pin number i/o descriptions imaster 67 i master hub selection: when high: means hub internal inter_bus arbiter is enabled and hub internal two_port switch is well conneted to 10m_hub core and 100m_hub core . when low: means hub internal inter_bus arbiter is disabled and hub internal two_port switch is not connected to 10m_hub core and 100m_hub core. iackb10 84 i/o 10m inter-bus port access acknowledge signal (low active). for master hub, this pin is output; for slave hub is input, or while ext_arb jumper was set to ?1?, this pin is input from an external arbitration device. icolb10 85 i/o 10m inter-bus collision signal (low active). for master hub, this pin can output multi hub collision event to inform all slave hub ; for slave hub, this pin is an input, or while ext_arb jumper was set to ?1?, this pin is input from an external arbitration device. ireq10_in0 88 i 10m inter-bus port access request input. ireq10_in1 87 i 10m inter-bus port access request input. ireq10_in2 86 i 10m inter-bus port access request input. ireq10_out 89 o 10m inter-bus port access request output. rmii port interface pins (port1 ~port4) name pin number i/o descriptions
6/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology iclk10 83 i/o 10m inter-bus port clock. idat10 81 i/o 10m inter-bus port data bit 100m inter-bus interface pins name pin number i/o descriptions iackb100 75 i/o 100m inter-bus port access acknowledge signal (low active). for master hub, this pin is output; for slave hub is input, or while ext_arb jumper was set to ?1?, this pin is input from an external arbitration device. icolb100 76 i/o 100m inter-bus collision signal (low active). for master hub, this pin can output multi hub collision event to inform all slave hub ; for slave hub, this pin is an input, or while ext_arb jumper was set to ?1?, this pin is input from an external arbitration device. ireq100_in0 79 i 100m inter-bus port access request input. ireq100_in1 78 i 100m inter-bus port access request input. ireq100_in2 77 i 100m inter-bus port access request input. ireq100_out 80 o 100m inter-bus port access request output. iclk100 73 i/o 100m inter-bus port clock. idat100_0 71 i/o 100m inter-bus port data bit 0. idat100_1 70 i/o 100m inter-bus port data bit 1. idat100_2 69 i/o 100m inter-bus port data bit 2. idat100_3 68 i/o 100m inter-bus port data bit 3. led interface pins name pin number i/o descriptions leddat 124 i/o led display serial data out; mapping for ledclk signal?s burst clock , its serial out data sequence is : ( first bit be shifted out is from b00, and end of burst bit is b23) b00: *********** b08: 10hub_col b16: ************ b01: ********** b09: 100hub_col b17: ************ b02: ********** b10: asram_test_fail b18: ************ b03: port0 partition b11: port0 partition b19: port0 rx_activity b04: port1 partition b12: port1 partition b20: port1 rx_activity b05: port2 partition b13: port2 partition b21: port2 rx_activity b06: port3 partition b14: port3 partition b22: port3 rx_activity b07: port4 partition b15: port4 partition b23: port4 rx_activity ledclk 125 i/o led display clock signal, the signal is a discontinued clock for led data serial shift out. every clock burst have 24 cycles ( period : 160 ns), and the clock burst will be repeated with every 42ms. 10m inter-bus interface pins name pin number i/o descriptions
7/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology miscellaneous pins name pin number i/o descriptions rstb 128 i system reset input, low active. sysclk 122 i 50mhz system clock input mdc 126 i/o mii management clock inout mdio 127 i/o mii management data inout upswen 65 i up_link switch port enabling : one of internal two_port switch port will connect to 100m_hub domain, and another port will redirect to rmii port4. fd4 66 i when up_link switch port enabling, this pin is port4?s full_deplex indi- cator, input from phy. when hign , indicate port4 in running on full_duplex mode. when low, indicate on half_duplex mode. spd0 8 i port0 speed indicator, input from phy. spd0 input low: 100m , input high: 10m. spd1 64 i port1 speed indicator, input from phy. spd1 input low: 100m , input high: 10m. spd2 63 i port2 speed indicator, input from phy. spd2 input low: 100m , input high: 10m. spd3 62 i port3 speed indicator, input from phy. spd3 input low: 100m , input high: 10m. spd4 61 i port4 speed indicator, input from phy. spd4 input low: 100m , input high: 10m. nc_pin 2,4,5,11,22, 23,24 nc no connection pins vcc 3,31,45,59, 72,103,121 pwr power pins gnd 1,6,7,13,14, 21,25,26,32, 46,60,74,82, 92,105,117, 123 gnd ground pins
8/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology power on configuration set up table name pin number i/o descriptions nc_11 11 i/o port0 mii interface enable : ( power on external jumper configuration ) - pin floating : port0 mii interface disable (change to be rmii interface) , not suit for 5 ports daul speed hub application. - external pull_high: port0 mii interface enable. txen0 18 i/o back_pressure disable : ( power on external jumper configuration ) - external pull_low (default ) : normal mode (back_pressure enbale) - external pull_high: back_pressure disable txen2 42 i/o auto mii_setting bypass : ( power on external jumper configuration ) - external pull_low (default ) : normal mode ( auto mii_setting); after power_on, MTD655 will auto setup phy devices be forced in half_ duplex mode for repeater apllication. - external pull_high: auto mii_setting bypass mdc 126 i/o 1522 bytes packet accept enable : ( power on external jumper configura- tion ) - external pull_low (default ) : normal mode ( <=1518 bytes packet accept) - external pull_high: <= 1522 bytes packet accept ledclk 125 i/o hub dealy enhance : ( power on external jumper configuration ) - external pull_low (default ) : nomal hub propagation delay mode. - external pull_high: enhanced hub propagational delay mode, for cov- ering long latency phy devices). leddat 124 i/o external arbiter enable : ( power on external jumper configuration ) - external pull_low (default ) : normal mode (inter_repeater bus use internal arbiter) - external pull_high: inter_repeater bus use external arbiter .
9/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology 2.0 MTD655 functional descriptions the MTD655 is conformed to ieee802.3 chapter 9 and ieee802.3u clause 27 specifications. the MTD655 provides 4 redused mii interfaces, 1 mii interface and an embedded two port switch to con- struct a 10m/100m dual speed hub application. two inter-bus are also provided for stackable 10m/ 100m dual speed hub application. the MTD655 functions are described as followMTD655s: 2.1 repeat and data handling 4 independent rmii ports and 1 mii port integrated with ieee802.3 chapter 9 and ieee802.3u clause 27 repeater functions simultaneously. MTD655 embedded two hub cores (10m and 100m) ,and each dedicated rmii or mii interface port can get per port?s speed information from per port speed input pin, and then MTD655 will switch individual port to their appropriated hub core functions (10m or 100m). the MTD655 receive packets from each rmii and mii ports, and redirect port?s input packet to 10m or 100m hub core according each port?s speed. the internal ieee802.3 chapter 9 or ieee802.3u clause 27 repeater main state machine will starts to repeat the input packet to all ports except the input port. if larger than or equal to two ports have input packet simultaneously, this will be treated as a collision, and MTD655 will assert an arbitrary jam pattern to all ports? output until collision event disappear and net- work is idle. 2.2 partition the MTD655 provides 10m/100m auto partition/reconnection functions to guarantee the network seg- ment performance by means of dectecting a consecutive collisions. each dedicated rmii or mii port has implement a individual 10m/100m auto partition/reconnection state machine. if port?s consecutive collision number over or equal to cclimit (10m cclimit default is 32, 100m cclimit default is 64), this port will be partitioned. reconnection will occurs after a larger than 512 bit time packet was received or transmitted from this partitioned port without any collision. when port is under partition state, MTD655 will not accept any input messages from this port (just mon- itor input message), but will continue output repeated messages to this partition port. some new partition criterions are also implement, such as long_collision_partition event, jabber_partition event. in 10m/100m partition state machine, longer than 1024 bit time continueous col- lision will force port enter partition state. in 100m partition state machine, if port enter jabber_on state, this port will be partitioned. in 10m, jabber_partition function is not implemented. 2.3 jabber the jabber protect function is used to prevent an illegally long packet reception. after the MTD655 received a longer than 65536 +/- 6.25% bit times packet, this receive port?s receive/transmit path will be inhibited until carrier is no longer detected. 2.4 mii setting due to hub is an half duplex device, the MTD655 need to force all connected phsical devices to work in half duplex environment. the MTD655 will setting all phy?s smi register 4?s half/full duplex bit during power on, and than restart auto-negotiation procedure to work in half duplex mode, and the phy?s device id should be set by pcb maker from 5?h07 - 5?h0b(port0-4). 2.5 inter-bus interface two inter-bus interface are provided by the MTD655, one is 10m inter-bus interface, the other is 100m inter-bus interface. the inter-bus interface is designed for stackable hub application. for each domain, up to 4 MTD655s can be stacked through this inter-bus without any external arbitration logic. the inter- bus interface includes imaster, idata (100m: use idat<3:0>, 10m: use only idat), reqout, reqin0-2, iclk, iackb, icolb pins. imaster decide which MTD655 can arbitrate the inter-bus, and only one MTD655?s imaster can be tie high in a stackable hub. idata are synchronous with iclk. the MTD655 output reqout to inform inter-bus interface that it need the inter-bus right. when iackb is asserted by inter-bus master after reqout asserted, the MTD655 which asserted reqout will get the bus right and put the transmit data into idata. if the MTD655 did not assert
10/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology reqout , but iackb is asserted, means this MTD655 can get data from idata bus. when only one MTD655 output reqout to inter-bus interface, iackb will be asserted by inter-bus master device, if larger than two MTD655?s reqout were asserted, inter-bus master will not assert iackb , but will assert icolb to inform all the connected MTD655s. the inter-bus interface can also be programmed to ext_arb mode, using leddat pin?s jumper set- ting. in this mode, inter-bus interface need an external arbitration logic to arbitrate inter-bus operation. and in this mode, the stackable capability is not limitted by the MTD655?s reqin pins number. 2.6 10m/100m packet switch the MTD655 inplements a 10/100m two port switch for 10m/100m packet switching. total 2k address entrys are provided for packets? sa learning and da routing; and alsoprovide automatic aging function ( aging time = 300secs). the input packet from 10mhub ( or 100m hub) will be stored to external memory first, while packet is good for forward ( crc chech ok, 64bytes < length > 1518bytes, and not local packets ) , than forward this packet to 100m hub (or 10m hub). 2.7 uplink switch port the MTD655 can config one switch port as an uplink switch port. when upswen pin is high, and imaster pin is low, one of the intenal switch port is connect to 100m hub, the other is connected to rmii port 4. in uplink switch mode, port 4 can work in 10m/100m(from spd4 pin), half/full duplex(from fd4 pin) mode. 2.8 memory interface the MTD655 use asynchronous sram as two port switchs? packet buffers, total has 128k byte exter- nal memory for packet buffering. 2.9 mii management the MTD655 can be managed through mdc, mdio pins. the MTD655 implements 3 mii registers for function control and status report (see section 4.0 on page ). the management frame format is compliant to ieee802.3u clause 22, and the device id is fixed to 5?h1f internally. 2.10 led display the MTD655 implements three display modes, port rx activity, 10/100m domain collision, port parti- tion. the led data pin leddat is high actived. one strobe pin ledclk(24 burst clock/per 42ms) is used to latch serial leddat information, and user can shift the latched data into byte aligned shift register to drive leds. 3.0 registers the MTD655 implements 3 mii registers, define as following tables: table 1. mii registers reg no bits name r/w descriptions default 0 ctlreg0 r/w control register 0 0 reserved. 1?b0 1 dispar10 set this bit will disable 10m hub core partition function. 1?b0 2 dispar100 set this bit will disable 100m hub core partition function. 1?b0 3 disjab10 set this bit will disable 10m hub core jabber function. 1?b0 4 disjab100 set this bit will disable 100m hub core jabber function. 1?b0 5-8 reserved 4?b000 9 cclimit100 set "1" will program 100m partition cclimit to 128. 1?b0(64)
11/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology "r/w" means read/writable. 10 cclimit10 set "1" will program 10m partition cclimit to 64. 1?b0(32) 11-15 reserved 2?b00 1 ctlreg1 r/w control register 1 16?h0000 0-7 disport set bits "1" disable port 0-7 rmii ports. 8?h000 8-15 reserved. 2 reserved 3 reserved 4 agereg r/w age register table 1. mii registers reg no bits name r/w descriptions default
12/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology 4.0 electrical characteristics 4.1 absolute maximum ratings 4.2 recommended operating conditions 4.3 dc electrical characteristics (under recommended operating conditions and vcc = 4.75 ~ 5.25v, tj = 0 to +115 o c) symbol parameter rating unit v cc power supply voltage -0.3 to 6.0 v v in input voltage -0.3 to vcc+0.3 v v out output voltage -0.3 to vcc+0.3 v t stg storage temperature -55 to 150 o c symbol parameter min. typ. max. unit v cc commercial power supply voltage 4.75 5 5.25 v industrial power supply voltage 4.5 5 5.5 v v in input voltage 0 - vcc v t opr commercial junction operating temperature 0 25 115 o c industrial junction operating temperature -40 25 125 o c symbol parameter conditions min. typ. max. unit i il input leakage current no pull-up or down -1 1 ua i oz tri-state leakage current -10 10 ua c in input capacitance 3 pf c out output capacitance 3 pf c bid3 bi-direction buffer capacitance 3 pf v il input low voltage cmos 0.3*vcc v v ih input high voltage cmos 0.7*vcc v v oh output high voltage i ol =2,4,8,12,16,24ma 0.4 v v ol output low voltage i oh =2,4,8,12,16,24ma 3.5 v r i input pull-up/down resistance v il =0v or v ih =v cc 50 kohm
13/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology 4.4 electrical characteristics symbol parameter min. typ. max. unit note t1 rmii input setup time 1 ns t2 rmii input hold time 1 ns t3 rmii output setup time 3 ns t4 rmii output hold time 5 ns symbol parameter min. typ. max. unit note t5 mii input setup time 10 ns t6 mii input hold time 10 ns t7 mii output setup time 3 ns t8 mii output hold time 5 ns figure 1. rmii timing refclk crsdv txen txd[1:0] rxd[1:0] t1 t2 t3 t4 valid valid figure 2. mii timing rxclk0 crs0/rxdv0 txen0 txd0[3:0] rxd0[3:0] t5 t6 t7 t8 valid valid txclk0
14/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology symbol parameter min. typ. max. unit note t9 web pulse width 11.5 16 ns t10 oeb pulse width 20 ns t11 write address setup time 10 18.5 ns t12 write address hold time 1.5 7 ns t13 write data setup time 10 12 ns t14 write data hold time 1 4 ns t15 read address setup time 19.5 ns t16 read address hold time 0 ns symbol parameter min. typ. max. unit note t17 inter-bus output setup time(100m) 15 20 ns inter-bus output setup time(10m) 50 ns t18 inter-bus output hold time(100m) 20 25 ns inter-bus output hold time(10m) 50 ns figure 3. memory interface timing web a[16:0] t13 t9 t11 t12 valid oeb t10 valid d[7:0] valid valid t14 t15 t16 figure 4. inter-bus interface timing i iclk100, t17 t18 idata100, valid idat10 iclk10
15/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology note 1 : in 10m/100m inter-bus interface, t19-t22 have the same value. symbol parameter min. typ. max. unit note t19 inter-bus master reqout asserted to iackb asserted propogation delay 7 20 ns 1 t20 inter-bus master reqout deas- serted to iackb deasserted propo- gation delay 0 1 5 ns 1 t21 inter-bus master reqin asserted to iackb deasserted(icolb asserted) propogation delay(soj) 5 17 ns 1 t22 inter-bus master reqout deas- serted to iackb asserted(icolbde- asserted) propogation delay(eoj) 0 1 5 ns 1 figure 5. inter-bus interface timing ii imaster reqout100, reqin100, iackb100, icolb100, t19 t21 t20 t22 reqout10 reqin10 iackb10 icolb10 figure 6. inter-bus interface timing iii imaster reqout100, reqin100, iackb100, icolb100, t23 t25 t24 t26 reqout10 reqin10 iackb10 icolb10
16/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology note 2 : in 10m/100m inter-bus interface, t23-t26 have the same value. symbol parameter min. typ. max. unit note t23 inter-bus slave reqout asserted to iackb asserted propogation delay 5 20 ns 2 t24 inter-bus slave reqout deasserted to iackb deasserted propogation delay 5 20 ns 2 t25 inter-bus slave reqin asserted to iackb deasserted(icolb asserted) propogation delay(soj) 5 20 ns 2 t26 inter-bus slave reqout deasserted to iackb asserted(icolbdeas- serted) propogation delay(eoj) 5 20 ns 2 symbol parameter min. typ. max. unit note t27 mdc clock cycle 400 ns t28 mdio input setup time 10 ns t29 mdio input hold time 10 ns t30 mdio output setup time 182 194 ns t31 mdio output hold time 206 218 ns figure 7. mii management timing mdc t28 t29 mdio valid mdc t30 t31 mdio valid t27 input timing output timing
17/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology symbol parameter min. typ. max. unit note t32 24 led burst clocks duration 3.84 us t33 led burst clock cycle time 42 ms t34 led burst clock cycle 160 ns t35 leddat to ledclk setup time 80 ns t36 leddat to ledclk setup time 80 ns figure 8. led output timing ledclk leddat .... .... ledclk t32 t33 t34 t35 t36
18/18 MTD655 revision 2.0 17/03/2000 MTD655 myson technology 5.0 128 pin pqfp package data 103 128 1 38 39 64 65 102 seating plane see detail a a a 1 a 2 e b d 1 d e 1 e l l1 z detail a note: 1.dimension d1 & e1 do not include mold protrusion. but mold mismatch is included. allowable protrusion is .25mm/.010? per side. 2.dimension b does not include dambar protrusion. allowable dambar protru- sion .08mm/.003?. total in excess of the b dimemsion at maximum material condition. dambar cannot be located on the lower radius or the foot. 3.controlling dimension : millimeter. symbol dimension in inch dimension in mm min norm max min norm max a - - 0.134 - - 3.40 a1 0.010 - - 0.25 - - a2 0.107 0.112 0.117 2.73 2.85 2.97 b 0.007 0.009 0.011 0.17 0.22 0.27 c 0.004 - 0.008 0.09 - 0.20 d 0.906 0.913 0.921 23.00 23.20 23.40 d 1 0.783 0.787 0.791 19.90 20.00 20.10 e 0.669 0.677 0.685 17.00 17.20 17.40 e 1 0.547 0.551 0.555 13.90 14.00 14.10 e 0.020 bsc 0.50 bsc l 0.029 0.035 0.041 0.73 0.88 1.03 l1 0.063 bsc 1.60 bsc y - - 0.004 - - 0.10 z 0 o - 7 o 0 o - 7 o y see detail b detail b c b with plating base metal gage plane

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