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P3P623S00b/e timing-safe? peak emi reduction ic ?2010 scillc. all rights reserved. p u blication order number: november 2010 C rev. 1.1 P3P623S00/d general features clock distribution with timing-safe? peak emi r eduction input frequency range: 20mhz - 50mhz 2 different spread selection options spread spectrum can be turned on/off external input-output delay control option supply voltage: 3.3v0.3v P3P623S00b: 8 pin soic P3P623S00e:16 pin tssop the first true drop-in solution functional description P3P623S00b/e is a versatile, 3.3v zero-delay buffer de signed to distribute timing-safe? clocks with peak emi reduction. P3P623S00b is an eight-pin version, accepts one reference input and drives out one low-skew timing- safe? clock. P3P623S00e accepts one reference input and drives out eight low-skew timing-safe? clocks. P3P623S00b/e has an ss% that selects 2 different deviation and associated input-output skew (t skew ). refer to the spread spectrum control and input-output skew table for details. P3P623S00e has a clkout for adjusting the input-output clock delay, depending upon the value of capacitor connected at this pin to gnd. P3P623S00b/e operates from a 3.3v supply and is available in two different packages, as shown in the ordering information table. application P3P623S00b/e is targeted for use in displays and memory in terface systems. general block diagram *for P3P623S00e -8 clkouts vdd gnd ss% clkin clkout(s)* (ti ming-safe?) pll sson dly_ctrl
p3p62300b/e rev. 1 | page 2 of 11 | www.onsemi.com s pread spectrum frequency generation the clocks in digital systems are typically square waves w ith a 50% duty cycle and as frequencies increase the edge rates also get faster. analysis shows that a square wave is composed of fundamental frequency and harmonics. the fundamental frequency and harmonics generate the energy peaks that become the source of emi. regulatory agencies test electronic equipment by measuring the amount of peak energy radiated from the equipment. in fact, the peak level allowed decreases as the frequency increases. the standard methods of reducing emi are to use shielding, filtering, multi-layer pcbs, etc. these methods are expensive. spread spectrum clocking reduces the peak energy by reducing the q factor of the clock. this is done by slowly modulating the clock frequency. the P3P623S00b/e uses the center modulation spread spectrum technique in which the modulated output frequency varies above and below the reference frequency with a specified modulation rate. with center modulation, the average frequency is the same as the unmodulated frequency and there is no performance degradation zero delay and skew control all outputs should be uniformly loaded to achieve zero d elay between input and output. since the clkout pin is the internal feedback to the pll, its relative loading can adjust the input-output delay. for applications requiring zero input-output delay, all outputs, including clkout, must be equally loaded. even if clkout is not used, it must have a capacitive load equal to that on other outputs, for obtaining zero input-output delay. timing-safe? technology timing-safe? technology is the ability to modulate a c lock source with spread spectrum technology and maintain synchronization with any associated data path.
p3p62300b/e rev. 1 | page 3 of 11 | www.onsemi.com p in configuration for P3P623S00b pin description for P3P623S00b pin # pin name type description 1 clkin 1 i external reference clock input , 5v tolerant input 2 nc no connect 3 ss% 3 i spread spectrum selection. has an internal pull up resistor 4 gnd p ground 5 sson 3 i spread spectrum enable and disable option. when sson is high, the spread spectrum is enabled and when low, it turns off the spread spectrum. has an internal pull up resistor 6 clkout 2 o buffered clock output 4 7 vdd p 3.3v supply 8 nc no connect notes: 1. weak pull down 2. weak pull-down on all outputs 3. weak pull-up on these inputs 4. buffered clock output is timing-safe? clkin nc 1 2 3 4 5 6 7 8 asm3p623 gnd sson vdd nc ss% clkout P3P623S00b
p3p62300b/e rev. 1 | page 4 of 11 | www.onsemi.com p in configuration pin description for P3P623S00e pin # pin name type description 1 clkin 1 i external reference clock input, 5v tolerant input 2 clkout1 2 o buffered clock output 4 3 v dd p 3.3v supply 4 ss% 3 i spread spectrum selection. refer to the spread spectrum control and input-output skew table. has an internal pull up resistor. 5 gnd p ground 6 clkout2 2 o buffered clock output 4 7 clkout3 2 o buffered clock output 4 8 dly_ctrl o external input-output delay control. 9 sson 3 i spread spectrum enable and disable option. when sson is high, the spread spectrum is enabled and when low, it turns off the spread spectrum. has an internal pull up resistor. 10 clkout4 2 o buffered clock output 4 11 clkout5 2 o buffered clock output 4 12 gnd p ground 13 v dd p 3.3v supply 14 clkout6 2 o buffered clock output 4 15 clkout7 2 o buffered clock output 4 16 clkout 2 o buffered clock output 4 notes: 1. weak pull down 2. weak pull-down on all outputs 3. weak pull-up on these inputs 4. buffered clock output is timing-safe? 1 2 3 4 13 14 15 16 p 3p623s00e 5 6 7 8 9 10 11 12 clkout6 clkout7 clkout4 clkout5 vdd clkout gnd s son dly_ctrl vdd ss% gnd clkout2 clkout3 clkout1 clkin
p3p62300b/e rev. 1 | page 5 of 11 | www.onsemi.com s pread spectrum control and input-output skew table device input frequency ss % deviation input-output skew (t skew ) P3P623S00b/e 32mhz 0 0.25 % 0.125 1 0.50 % 0.25 note: t skew is measured in units of the clock period a bsolute maximum ratings symbol parameter rating unit vdd supply voltage to ground potential -0.5 to +4.6 v vin dc input voltage (clkin) -0.5 to +7 t stg storage temperature -65 to +125 c t s max. soldering temperature (10 sec) 260 c t j junction temperature 150 c t dv static discharge voltage (as per jedec std22- a114-b) 2 kv note: these are stress ratings only and are not implied for functional use. exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. operating conditions parameter description min max unit vdd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) -40 +85 c c l load capacitance 30 pf c in input capacitance 7 pf electrical characteristics parameter description test conditions min typ max unit v il input low voltage 5 0.8 v v ih input high voltage 5 2.0 v i il input low current v in = 0v 50 a i ih input high current v in = vdd 100 a v ol output low voltage 6 i ol = 8ma 0.4 v v oh output high voltage 6 i oh = -8ma 2.4 v i dd supply current unloaded outputs 27 ma z o output impedance 23 w notes: 5. clkin input has a threshold voltage of vdd/2 6. parameter is guaranteed by design and characterization. not 100% tested in production.
p3p62300b/e rev. 1 | page 6 of 11 | www.onsemi.com s witching characteristics parameter test conditions min typ max unit input frequency 20 50 mhz output frequency 30pf load 20 50 mhz duty cycle 6,7 = (t 2 / t 1 ) * 100 measured at vdd/2 40 50 60 % output rise time 7, 8 measured between 0.8v and 2.0v 2.5 ns output fall time 7, 8 measured between 2.0v and 0.8v 2.5 ns output-to-output skew 7, 8 all outputs equally loaded with ssoff 250 ps delay, clkin rising edge to clkout rising edge 8 measured at vdd /2 with ssoff 350 ps device-to-device skew 8 measured at vdd/2 on the clkout pins of the device 700 ps cycle-to-cycle jitter 7, 8 loaded outputs 250 ps pll lock time 8 stable power supply, valid clock presented on clkin pin 1.0 ms note: 7. all parameters specified with 30pf loaded outputs. 8. parameter is guaranteed by design and characterization. not 100% tested in production. switching waveforms d uty cycle timing all outputs rise/fall time t 2 t 1 v dd /2 v dd /2 v dd /2 output t 3 output t 4 0.8v 2v 0.8v 2v
p3p62300b/e rev. 1 | page 7 of 11 | www.onsemi.com o utput - output skew input - output propagation delay device - device skew t 5 output output v dd /2 v dd /2 t 6 output input v dd /2 v dd /2 t 7 clkout, device 1 v dd /2 v dd /2 clkout, device 2
p3p62300b/e rev. 1 | page 8 of 11 | www.onsemi.com in put - output skew test circuit typical example of timing-safe? waveform v dd gnd clkout load output 0.1uf +3.3v 0.1uf +3.3v v dd t skew - one clock cycle n=1 t skew + input timing-safe? output t skew represents input-output skew when spread spectrum is on for example, t skew = 0.125 for an input clock 32mhz, translates in to (1/32mhz) * 0.125=3.90ns input c lkout with ssoff input timing-safe? clkout
p3p62300b/e rev. 1 | page 9 of 11 | www.onsemi.com p ackage information 8-lead (150-mil) soic package d e h d a1 a2 a q l c b e symbol dimensions inches millimeters min max min max a1 0.004 0.010 0.10 0.25 a 0.053 0.069 1.35 1.75 a2 0.049 0.059 1.25 1.50 b 0.012 0.020 0.31 0.51 c 0.007 0.010 0.18 0.25 d 0.193 bsc 4.90 bsc e 0.154 bsc 3.91 bsc e 0.050 bsc 1.27 bsc h 0.236 bsc 6.00 bsc l 0.016 0.050 0.41 1.27 0 8 0 8
p3p62300b/e rev. 1 | page 10 of 11 | www.onsemi.com 1 6-lead tssop (4.40-mm body) d e h d a a1 b e q l c a2 pin 1 id 1 8 9 16 seating plane symbol dimensions inches millimeters min max min max a 0.043 1.20 a1 0.002 0.006 0.05 0.15 a2 0.031 0.041 0.80 1.05 b 0.007 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 d 0.193 0.201 4.90 5.10 e 0.169 0.177 4.30 4.50 e 0.026 bsc 0.65 bsc h 0.252 bsc 6.40 bsc l 0.020 0.030 0.50 0.75 0 8 0 8
p3p62300b/e on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicals must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. u.s patent pending; timing-safe and active bead are trademarks of pulsecore semiconductor, a wholly owned subsidiary of on semiconductor. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution center for on semiconductor p .o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support: 800-282-9855 toll free usa/canada e urope, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative ordering code ordering code marking package type temperature P3P623S00bg-08sr ado 8-pin 150-mil soic-tape & reel, green 0c to +70c P3P623S00bg-08tr ado 8-pin 4.4-mm tssop - tape & reel, green 0c to +70c p3i623s00bg-08tr adp 8-pin 4.4-mm tssop - tape & reel, green -40c to +85c P3P623S00eg-16tr p623 s00e 16-pin 4.4-mm tssop - tape & reel, green 0c to + 70c a microdot placed at the end of last row of marking or just below the last row toward the center of package indicates pb-free

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