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  to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation (http://www.renesas.com) send any inquiries to http://www.renesas.com/inquiry.
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without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. re nesas electronics shall not be in any way liable for any damages or losses incurred by you or third partie s arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intende d where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electr onics data sheets or data books, etc. ?standard?: computers; office equipmen t; communications e quipment; test and measurement equipment; audio and visual equipment; home electronic a ppliances; machine tools; personal electronic equipmen t; and industrial robots. ?high quality?: transportation equi pment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specif ically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support device s or systems), surgical im plantations, or healthcare intervention (e.g. excision, etc.), and any other applicati ons or purposes that pose a di rect threat to human life. 8. you should use the renesas electronics pr oducts described in this document within the range specified by renesas electronics , especially with respect to the maximum ra ting, operating supply voltage range, movement power volta ge range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its produc ts, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate a nd malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physic al injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safe ty design for hardware and software in cluding but not limited to redundancy, fire control and malfunction prevention, appropri ate treatment for aging degradation or an y other appropriate measures. because the evaluation of microcomputer software alone is very difficult , please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesa s electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regul ate the inclusion or use of c ontrolled substances, including wi thout limitation, the eu rohs directive. renesas electronics assumes no liability for damage s or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in w hole or in part, without prio r written consent of renes as electronics. 12. please contact a renesa s electronics sales office if you have any questi ons regarding the informat ion contained in this document or renesas electroni cs products, or if you have any other inquiries. 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mos integrated circuit pd8835 7300 pixels 3 color ccd linear image sensor data sheet document no. s20220ej1v0ds00 (1st edition) date published february 2010 ns printed in japan 2010 description the pd8835 is a very high-speed color ccd (charge coupled device) linear image sensor which changes optical images to electrical signal and has the function of color separation. the pd8835 has the high speed voltage amplifiers, which have four outputs per color, and the hi gh speed registers, so it is possible t hat the image of the high density is read a t very high speed. therefore, it is suit able for very high-speed 600dpi/a3 color digital copiers, color scanners and so on, by the package with heat sink that has high heat radiation. features ? valid photocell : 7300 pixels rgb 3 lines ? photocell?s size : 10 m ? line spacing : 40 m (4 lines) red line - green line, green line - blue line ? color filter : primary colors (r ed, green, and blue), pigment filter light resistance 10 7 lx hour with standard sunlight and ultraviolet cut filter (l40) ? resolution : 24 dot/mm a3 (297 420 mm) size (shorter side) ? data rate : 140 mhz/color max. (35 mhz/ch max.) ? power supply : +10 v and +5 v ? drive clock level : cmos output under 5 v operation ? on-chip circuits : voltage amplifiers reset feed-through level clamp circuit clamp clock generation circuit sample and hold circuit sample and hold clock generation circuit ? output type : 4 outputs / color, front & rear separate type sample and hold mode only ordering information part number package pd8835cu-a ccd linear image sensor 56-pin plastic dip with heat sink (15.24 mm (600)), 1.778 mm pitch remark "-a" indicates pb-free (this product does not c ontain pb in external electrode and other parts).
block diagram pd8835 2 data sheet s20220ej1v0ds 9 2l 8 r gnd 46 gnd 39 gnd 11 gnd 18 20 2l 21 r 36 v od 2 37 v od 2 34 v od 2 35 v od 2 49 v od 2 48 v od 2 51 v od 2 50 v od 2 hs-v dd 15 42 43 14 2 17 1 16 1 13 2 12 v od 1 10 v od 1 19 gnd 52 gnd 33 sh cp clock gen. v dd 7 cp sh clock gen. v dd 22 gnd 6 v sub 24 gnd 27 v sub 5 gnd 2 gnd 55 tg 47 tg 38 gnd 30 v out r3 25 (red-odd) v out b4 32 (blue-even) v out b2 (blue-even) 53 v out b1 (blue-odd) 54 v out b3 31 (blue-odd) voltage amp. transfer gate transfer gate photocell ( blue ) photocell ( blue ) s3650 s3650 d62 d1 s1 d1 d62 s1 ??? ??? ccd analog shift register ccd analog shift register transfer gate transfer gate ccd analog shift register ccd analog shift register voltage amp. voltage amp. voltage amp. v out g 1 ( green-od d ) 56 v out g2 (green-even) 1 v out g3 29 (green-odd) v out g4 28 (green-even) transfer gate transfer gate photocell ( green ) photocell ( green ) s3650 s3650 d62 d1 s1 d1 d62 s1 ??? ??? ccd analog shift register ccd analog shift register transfer gate transfer gate ccd analog shift register ccd analog shift register volta g e am p . voltage amp. voltage amp. voltage amp. v out r2 (red-even) 3 v out r1 (red-odd) 4 v out r4 26 (red-even) transfer gate transfer gate photocell ( red ) photocell ( red ) s3650 s3650 d62 d1 s1 d1 d62 s1 ??? ??? ccd analog shift register ccd analog shift register transfer gate transfer gate ccd analog shift register ccd analog shift register voltage amp. voltage amp. voltage amp. voltage amp. gnd 23 40 1 41 2 44 2 45 1
3 pd8835 data sheet s20220ej1v0ds pin configuration (top view) ccd linear image sensor 56-pin plastic dip wi th heat sink (15.24 mm (600)) 1.778 mm pitch 27 28 15 16 17 18 19 20 21 22 23 24 25 26 30 29 42 41 40 39 38 37 36 35 34 33 32 31 13 14 1 2 3 4 5 6 7 8 9 11 12 10 ground output signal (green rear odd) heat sink vdd shift register clock 2 shift register clock 1 ground transfer gate clock output unit drain voltage 2 output signal (blue rear odd) output signal (blue rear even) output unit drain voltage 2 output unit drain voltage 2 output unit drain voltage 2 ground ground output signal (green rear even) heat sink vdd last stage shift register clock 2l substrate voltage shift re gister clock 1 reset gate clock ground ground output unit drain voltage 1 shift register clock 2 output signal (red rear even) output signal (red rear odd) heat sink vdd output signal (green front odd) output signal (blue front even) ground shift register clock 2 ground ground shift register clock 1 output signal (blue front odd) output unit drain voltage 2 transfer gate clock output unit drain voltage 2 output unit drain voltage 2 output unit drain voltage 2 2 gnd hs-v dd v out -g1 gnd v out -b1 v out -b2 gnd v od 2 v od 2 v od 2 v od 2 1 tg shift register clock 1 heat sink vdd shift register clock 2 output unit drain voltage 1 output signal (green front even) ground output signal (red front even) output signal (red front odd) ground digital power supply reset gate clock substrate voltage last stage shift register clock 2l ground 45 44 43 56 55 54 53 52 51 50 49 48 47 46 v od 1 2 1 hs-v dd v out -g2 gnd v out -r2 v out -r1 v sub gnd v dd r 2l gnd v out -r4 gnd v out -g4 hs-v dd 1 2 gnd v od 1 2l r v dd gnd v sub v out -r3 gnd v out -b3 v out -g3 hs-v dd 2 1 gnd tg v od 2 v od 2 v od 2 v od 2 gnd v out -b4 blue red green 1 1 1 7300 7300 7300 digital power supply
4 pd8835 data sheet s20220ej1v0ds photocell structure diagram photocell array structure diagram 9 m 10 m 1 m channel stopper aluminum shield 10 m 4 line space (40 m) 4 line space (40 m) blue pixels green pixels red pixels 10 m 10 m
5 pd8835 data sheet s20220ej1v0ds absolute maximum ratings parameter symbol ratings unit output drain voltage v od1 , v od2 ?0.3 to +12.0 v digital power supply v dd ?0.3 to +8.0 v substrate voltage v sub ?0.3 to +8.0 v heat sink v dd hs-v dd ?0.3 to +8.0 v voltage difference between v dd and v sub v dd -v sub ?0.5 to +0.5 v shift register clock voltage v 1 , v 2 ?0.3 to +8.0 v last stage shift register clock voltage v 2l ?0.3 to +8.0 note 1 v reset gate clock voltage v r ?0.3 to +8.0 note 1 v transfer gate clock voltage v tg ?0.3 to +8.0 v operating ambient temperature note 2 t a 0 to +60 ? c package surface temperature note 3 t pkg 0 to +75 ? c storage temperature t stg ?40 to +100 ? c notes 1. be careful so that the voltage of v 2l and v r are not beyond v dd + 0.3v. 2. the operating ambient temperature t a is defined as an atmosphere te mperature in a point 10 mm away on the circuit board, and 10 mm away from the short si de of package pin 1. refer to the below figure. 3. the package surface temperature t pkg is defined as a surface temperatur e of package short side of pin1. refer to the below figure. caution product quality may suffer if the absolute m aximum rating is exceeded ev en momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended power on/off sequence the power on/off sequence is not limited. but, when v od1 and v od2 are powered, avoid v sub and v dd being unsettled (i.e. high impedance). prevent v dd and v sub from being powered on/off separately. t pkg t a pin1 10 mm 10 mm
6 pd8835 data sheet s20220ej1v0ds recommended operating conditions parameter symbol min. typ. max. unit output drain voltage v od1 , v od2 9.5 10.0 10.5 v digital power supply v dd 4.75 5.0 5.4 v substrate voltage v sub 4.75 5.0 5.4 v heat sink v dd hs-v dd 4.75 5.0 5.4 v voltage difference between v dd and v sub v dd -v sub -0.3 0.0 0.3 v shift register clock high level v 1h , v 2h 4.75 5.0 6.0 v shift register clock low level v 1l , v 2l -0.3 0.0 0.3 v last stage shift register clock high level v 2lh 4.75 5.0 v dd +0.3 v last stage shift register clock low level v 2ll -0.3 0.0 0.3 v reset gate clock high level v rh 4.75 5.0 v dd +0.3 v reset gate clock low level v rl -0.3 0.0 0.3 v transfer gate clock high level v tgh 4.75 5.0 6.0 v transfer gate clock low level v tgl -0.3 0.0 0.3 v shift register clock amplitude v p-p 1 , v p-p 2 4.75 5.0 6.3 v transfer gate clock amplitude v p-p tg 4.75 5.0 6.3 v signal output data rate f r 0.1 1 35 mhz clock rate f 1 , f 2 0.1 1 35 mhz
7 pd8835 data sheet s20220ej1v0ds electrical characteristics t a = +25 c, v od1 = v od2 = +10 v, v dd = v sub = +5 v, f r = 1 mhz, data rate = 1 mhz, storage time = 10 ms, input clock = 5 vp-p light source (except response2): 3200 k halogen lamp + c-500s (infrared cut filter, t = 1 mm) + ha-50 (heat absorbing filter, t = 3 mm) parameter symbol test conditions min. typ. max. unit saturation voltage v sat 1.2 1.5 ? v red se(r) ? 0.14 ? green se(g) ? 0.16 ? saturation exposure blue se(b) ? 0.3 ? lx?s prnu1( - ) ? 6 18 photo response non-uniformity prnu1(+) v out = 1 v ? 6 11 % average dark signal ads light shielding ? 0.1 5.0 mv dark signal non-uniformity dsnu light shielding ? 2.0 10.0 mv power consumption (v od1 ) p od1 ? 790 950 power consumption (v od2 ) p od2 ? 960 1150 power consumption (v dd ) p dd f r = 35 mhz ? 69 90 power consumption (v sub ) p sub ? 1 20 total power consumption p w f r = 35 mhz ? 1820 2210 mw output impedance z o ? 0.15 0.4 k red r r 7.8 10.5 13.2 green r g 6.9 9.2 11.5 response1 blue r b 3.75 5.0 6.25 v/lx?s red r r ? (9.8) ? green r g ? (9.0) ? response2 (corresponding value from response1) blue r b a light source + cm500s ? (4.5) ? v/lx ? s red ? 610 ? green ? 535 ? response peak blue ? 460 ? nm image lag il v out = 1 v ? 1 20 mv offset level v os 4.0 5.0 6.0 v ts1 2 3 4 output settling time note ts2 v out = 1 v 5.5 7 8.5 ns ri v out = 1 v ? 2.0 10.0 % register imbalance ri-fr v out = 1 v ? 2.0 10.0 % total transfer efficiency tte v out = 1 v, f 1 = 35 mhz 94 98 ? % dr1 v sat /dsnu ? 750 ? dynamic range dr2 v sat / dark ? 1875 ? times light shielding random noise dark ? 0.8 ? mv note definitions of ts1 and ts2 are indicated in the timing chart 2 .
8 pd8835 data sheet s20220ej1v0ds input pin capacitance (v od1 = v od2 = +10 v, v dd = v sub = +5 v) parameter symbol pin name pin no. min. typ. max. unit 13 215 240 265 16 215 240 265 40 215 240 265 1 45 215 240 265 c 1 total 860 960 1060 pf 12 215 240 265 17 215 240 265 41 215 240 265 2 44 215 240 265 shift register clock pin capacitance note c 2 total 860 960 1060 pf 9 11 12 13 last stage shift register clock pin capacitance c 2l 2l 20 11 12 13 pf 8 11 12 13 reset gate clock pin capacitance c r r 21 11 12 13 pf 38 2 3 4 transfer gate clock pin capacitance c tg tg 47 2 3 4 pf note c 1 and c 2 are equivalent capacitance with driving device, including the co-capacitance between 1 and 2. pin 13, 16, 40 and 45 ( 1) are connected inside of the device. pin 12, 17, 41 and 44 ( 2) are also connected inside of the device.
pd8835 9 data sheet s20220ej1v0ds timing chart 1 v out 1, 3 93(d59) 95(d61) 97(s1) 99(s3) 3745(s3649) 3743(s3647) 37(d3) 87(d53) 31 33 1 91(d57) 3 89(d55) 35(d1) note 2 invalid cell (3pixels/ch) valid cell (1825pixels/ch) dummy cell (17pixels/ch) optical black (28pixels/ch) b note 1 a r 2l 2 1 v out before s&h (internal waveform) tg v out 2, 4 94(d60) 96(d62) 98(s2) 100(s4) 3746(s3650) 3744(s3648) 38(d4) 88(d54) 32 34 2 92(d58) 4 90(d56) 36(d2) notes 1. 2. set the r to low level during this period a. refer to timing chart 3 during this period b.
pd8835 10 data sheet s20220ej1v0ds timing chart 2 notes 1. ?10%? and ?90%? are defined as a rati o against the amplit ude of the clock. 2. ts2 is defined by earlier timing of either r or 2l. 3. t 2l-sh is a period between external 2l and internal sh. the design value of t 2l-sh is 0 ns. v sh + ? v out 1 ? v out 4 (after emitter-follower) v out = 1.0 v dark level note 2 10% r 2 90% 10% t7 90% 10% t6 1 90% 10% t6 90% 10% t7 10% 2l 90% 10% t6l 90% 10% t8 t20 10% t9 90% t10 10% 10% t18 t21 90% internal sh 10% t 2l-sh 10 mv ts1 100% 0% 10% ts2 note 3 n ote 1
11 pd8835 data sheet s20220ej1v0ds timing chart 3 (the period b of timing chart 1) symbol min. typ. max. unit t1 100 200 1000 ns t2, t4 0 10 ? ns t3 1000 2000 5000 ns t5 300 500 5000 ns t6, t7 0 10 ? ns t6l, t7l 0 3 10 ns t8, t10 0 3 10 ns t9 2 t note /4 ? ns t11 300 500 5000 ns t18 3 t note /4 ? ns t20 10 t note /2 ? ns t21 0 t9 ? ns note ?t? means 1 period. t9 t5 90% 10% r 90% 10% 2 2l 1 10% t1 90% tg t2 90% 10% t4 90% 10% t3 note ?10%? and ?90%? are defined as a rati o against the amplit ude of the clock. n ote
12 pd8835 data sheet s20220ej1v0ds cross points ( 1, 2) cross points ( 1, 2l) cross points remark adjust cross points of ( 1, 2) and ( 1, 2l) with an input resistance of each pin. clock high and low level width symbol min. typ. max. unit t30 3 ? ? ns t34 10 ? ? ns t35 3 ? ? ns 2 1 0.5 v or more 0.5 v or more 1 2 1 2l t34 +0.25 v t30 t30 t35 4.5 v 4.5 v 2l 1 0.5 v or more 0 v or more 4.25 v
13 pd8835 data sheet s20220ej1v0ds definitions of characteristics 1. saturation voltage: v sat the output signal voltage at whic h the response linearity is lost 2. saturation exposure: se product of intensity of illuminati on (lx) and storage time (s) when saturation of output voltage occurs 3. photo response non-uniformity: prnu1 the output signal non-uniformity of all the valid pixels w hen the photosensitive su rface is applied with the light of uniform illumination. this is calculated by the followi ng formula, and it is defined by each twelve of them. prnu1 (%) = x 100 x x j : output voltage of valid pixel number j x : maximum of | x j ? x | 1825 j=1 x j x = 1825 register dark dc level v out x x prnu1 ( - ) prnu1(+) 4. average dark signal: ads average output signal voltage of all the valid pixels at light shielding. this is calculated by the following formula, and it is defined by each twelve of them. a ds (mv) = d j : dark signal of valid pixel number j 1825 1825 j=1 d j 5. dark signal non-uniformity: dsnu absolute maximum of the difference between ads and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. this is calculated by the following formula, and it is defined by each twelve of them. dsnu (mv) : maximum of | dj ? ads | j = 1 to 1825 dj : dark signal of valid pixel number j register dark dc level a ds dsnu v out
14 pd8835 data sheet s20220ej1v0ds 6. output impedance: z o impedance of the output pi ns viewed from outside 7. response: r output voltage divided by exposure (lx ? s) note that the response varies with a li ght source (spectral characteristic). 8. image lag: il the rate between the last output voltage and t he next one after read out the data of a line v out tg light v out on off v 1 il (mv) = v 1 9. register imbalance: ri, ri-fr ri is the rate of the difference bet ween the averages of the out put voltage of odd pixels and even pixels, against the average output voltage of all the valid pixels. the ri is calculated between v out1 and v out2 and between v out 3 and v out 4. the ri-fr is defined as ri between front and rear. ri (%) = 100 n j=1 v j n 1 n 2 (v 2j ? 1 ? v 2j ) j=1 2 n n : number of valid pixels (1 to 1825) v j : output voltage of each pixel v out (f) : average output voltage of v out 1 and v out 2 v out (r) : average output voltage of v out 3 and v out 4 (vout(f) + vout(r))/2 v out (f) ? v out (r) ri ?fr(%) = 100
15 pd8835 data sheet s20220ej1v0ds 10. random noise (light shielding): dark light shielding random noise dark is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding). this is measured by the dc leve l sampling of only the signal level, not by cds (correlated double sampling). (mv) = 100 i=1 (vi ? v) 2 100 100 i=1 vi v = 100 1 , vi : a valid pixel output signal among all of the valid pixels for each color. v out line1 v 1 line2 v 2 line100 v 100 11. total transfer efficiency: tte tte is the total transfer rate of ccd analog shift r egister. this is calculated by the following. tte (%) = (1 - vb/average output of all the valid pixels) 100 vb vb: the spilt pixel output (3747th pixel) 3743 3745 3747
16 pd8835 data sheet s20220ej1v0ds standard characteristic curves (nominal) total spectral response characteristics without ir cut filter and heat absorbing filter t a =25  0 20 40 60 80 100 120 400 500 600 700 800 900 wavelength(nm) repsponse ratio(%) blue green red green blue total spectral response characteristics (without ir cut filter and heat absorbing filter at t a = 25 c) 0.1 0.25 0.5 1 2 4 8 50 10 0 20 30 60 40 operating ambient temperature t a ( c) relative output voltage dark output temperature characteristic 1 5 10 relative output voltage storage time output voltage characteristics (t a =25 c) 0.1 0.2 1 2 storage time (ms) wavelength (nm) 400 500 600 700 800 900 100 80 60 40 20 0 response ratio (%)
17 pd8835 data sheet s20220ej1v0ds application circuit example 42 40 38 36 34 32 30 41 39 37 35 33 31 29 56 54 52 50 48 46 44 55 53 51 49 47 45 43 hs-v dd 1 tg v od 2 v od 2 v out -b4 gnd 2 gnd v od 2 v od 2 gnd v out -b3 v out -g3 v out -g1 v out -b1 gnd v od 2 v od 2 gnd 2 gnd v out -b2 v od 2 v od 2 tg 1 hs-v dd hs-v dd 2 v od 1 r v out -r3 gnd 1 gnd 2l v dd v sub v out -r4 v out -g4 15 17 19 21 23 25 27 16 18 20 22 24 26 28 v out -g2 v out -r2 v sub v dd 2l gnd 1 gnd v out -r1 gnd r v od 1 2 hs-v dd 1 3 5 7 9 11 13 2 4 6 8 10 12 14 g1 b1 b2 b4 b3 g3 g4 r3 r4 g2 r2 r1 + +5 v + +5 v + +5 v + +5 v + +5 v + +5 v + +5 v + +10 v inverters: 74ac04 inverters: 74ac04 note 2 note 2 note3 no te 1 note 1 gnd notes 1. 2. 3. arrange capacitors near each power supply pins (v od 1, v od 2) to prevent the interference between v od 1 and v od 2. v dd and v sub are also the same. connect three inverters for each terminal of 1 and 2. hs-v dd pins are used to fix the heat sink voltage. set hs-v dd to v sub in common on the circuit board. b1 to b4, g1 to g4, and r1 to r4 equivalent circuit ccd v out +10 v + 1 k
18 pd8835 data sheet s20220ej1v0ds package drawing
19 pd8835 data sheet s20220ej1v0ds recommended soldering conditions when soldering this product, it is highly recomm ended to observe the conditions as shown below. if other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. type of through-hole device pd8835cu-a: ccd linear image sensor 56-pin plastic di p with heat sink (15.24 mm (600)) 1.778 mm pitch process conditions partial heating method pin temperature: 380c or bel ow, heat time: 3 seconds or less (per pin). cautions 1. during assembly care should be taken to prevent solder or fl ux from contacting the glass cap. the optical characteristics could be degraded by such contact. 2. soldering by the solder flow method may ha ve deleterious effects on prevention of glass cap soiling and heat resistance. so the method cannot be guaranteed. notes of handling the packages the application of an excessive load to the package may c ause the package to warp or break, or cause chips to come off internally. particular care should be taken w hen mounting the package on the ci rcuit board. you should not reform the lead frame. we recommend to use a ic-inserter when you assemble to pcb. for this product, the reference value for the three-point bending strength note is 280[n ]. avoid imposing a load, however, on the inside portion as viewed from the face on which the window (glass) is bonded to the package body. note three-point bending strength test distance between supports: 70 mm, suppor t r: r2 mm, loading rate: 0.5 mm/min. 70 mm 70 mm load load
20 pd8835 data sheet s20220ej1v0ds notes of handling 1. mounting of the package the application of an excessive load to the package may c ause the package to warp or break, or cause chips to come off internally. particular care should be taken when mounting the package on the circuit board. don?t have any object come in contact with glass cap. you shoul d not reform the lead frame. we recommend to use an ic- inserter when you assemble it to pcb. also, be care that any of the following can c ause the package to crack or dust to be generated. 1. applying heat to the external leads for an extended period of time with soldering iron. 2. rapid cooling or heating 3. applying repetitive bending st ress to the external leads. 2. glass cap don?t either touch glass cap surface by hand or have any object come in contact with glass cap surface. care should be taken to avoid mechanical or thermal shock becaus e the glass cap is easily to damage. for dirt stuck through electricity ionized air is recommended. 3. operate and storage environments operate in clean environments. ccd im age sensors are precise optical equipm ent that should not be subject to mechanical shocks. exposure to high te mperatures or humidity will affect t he characteristics. so avoid storage or usage in such conditions. keep in a case to protect from dust and dirt. dew condensation may occur on ccd image sensors when the devices are transported from a low- temperature environment to a high-te mperature environment. avoid such rapid temperature changes. for more detail, refer to our document ?r eview of quality and reliability handbook? (c12769e) 4. electorostatic breakdown ccd image sensor is protected against static electricity, but destruction due to static electricity is something detected. before handling, be sure to take the following protective measures. 1. ground the tools such as soldering ir on, radio cutting pliers of or pincer. 2. install a conductive mat or on the floor or working table to prevent the generati on of static electricity. 3. either handle bare handed or use non char geable gloves, clothes or material. 4. ionized air is recommended for discharge when handling ccd image sensor. 5. for the shipment of mounted substrates, use box treated for prevention of static charges. 6. anyone who is handling ccd image s ensors, mounting them on pcb or testing or inspecting pcbs on which semiconductor devices have been mount ed must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1m .
21 pd8835 data sheet s20220ej1v0ds notes for cmos devices (1) voltage application waveform at input pin: wa veform distortion due to input noise or a reflected wave may cause malfunction. if t he input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period w hen the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cm os device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resistor if there is a possibility that it w ill be an output pin. all handling related to unused pins must be judged separately for each devic e and according to related specifications governing the device. (3) precaution against esd: a strong electric fiel d, when exposed to a mos dev ice, can cause destruction of the gate oxide and ultimately degr ade the device operation. steps mu st be taken to stop generation of static electricity as much as possible, and quickly dissi pate it when it has occurr ed. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electric ity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be gr ounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be ta ken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not nece ssarily define the initial st atus of a mos device. immediately after the power source is turned on, devic es with reset functions have not yet been initialized. hence, power-on does not guar antee output pin levels, i/o settings or cont ents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed imm ediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device t hat uses different power supplies for the internal operation and external interface, as a rule, switch on the external power s upply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences ma y result in the application of an overvoltage to the internal element s of the device, causing malfuncti on and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related spec ifications governi ng the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abno rmal current that passes in the device at this time may cause degradation of internal elements. i nput of signals during the power off state must be judged separately for each device and according to related s pecifications gover ning the device.
pd8835 ? the information in this document is current as of february, 2010. the information is subjec t to change without notice. for actual design-in, refer to the latest pub lications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electroni cs products. not all products and/or types are ava ilable in every country. please check with a n nec electronics sales representative for av ailability and additional information. ? no part of this document may be copied or reproduced in any fo rm or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility fo r any errors that may appear in this document. ? nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights o f third parties by or arising from the use of nec electronics pr oducts listed in this document or any other liability arising fro m the use of such products. no license, expre ss, implied or otherwise, is granted under any patents, copyrights or other intellectua l property rights of nec electronics or others. ? descriptions of circuits, software and other related informat ion in this document are provi ded for illustrative purposes in semiconductor product operation and app lication examples. the incorporation of t hese circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by cu stomers or third parties arising from the use of these circuits, software and information. ? while nec electronics endeavors to enhance the quality, reliab ility and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons aris ing from defects in nec electronics products , customers must incorporate sufficient safety measures in their design, such as redundanc y, fire-containment and anti-failure features. ? nec electronics products are classified into the following th ree quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer-designated "quality assurance program" for a specific application. the re commended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electroni cs product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurem ent equipment, audio and visual equipment, home electronic appliances, ma chine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti- crime systems, safety equipment and medical equipment ( not specifically designed for life support). "specific": aircraft, aerospace equipm ent, submersible repeaters, nuclear reacto r control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unl ess otherwise expressly spec ified in nec electronics data sheets or data books, etc. if customers wish to use ne c electronics products in applications not intended by nec electronics, they must contact an nec electronics sales repr esentative in advance to deter mine nec electronics' willingness to support a given application. (note 1) "nec electronics" as used in th is statement means nec electronics corpor ation and also includes its majority-owned subsidiaries. (note 2) "nec electronics products" m eans any product developed or manufactured by or for nec electronics (as defined above). (m8e0909e)


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