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? semiconductor components industries, llc, 2015 november, 2015 ? rev. 1 1 publication order number: tcc?206/d TCC-206 six-output ptic control ic introduction tcc?206 is a six?output high?voltage digital to analog control ic specifically designed to control and bias on semiconductor?s passive tunable integrated circuits (ptics). these tunable capacitor control circuits are intended for use in mobile phones and dedicated rf tuning applications. the implementation of on semiconductor?s tunable circuits in mobile phones enables significant improvement in terms of antenna radiated performance. the tunable capacitors are controlled through a bias voltage ranging from 1 v to 24 v. the tcc?206 high?voltage ptic control ic has been specifically designed to cover this need, providing six independent high?voltage outputs that control up to six different tunable ptics in parallel. the device is fully controlled through a multi?protocol digital interface. key features ? controls on semiconductor?s ptic tunable capacitors ? compliant with timing needs of cellular and other wireless system requirements ? integrated boost converter with 6 programmable dac outputs (up to 24 v) ? low power consumption ? auto?detection of spi (30? or 32?bit) or mipi rffe interfaces (1.8 v) ? available in wlcsp (rdl ball arrays) ? compliant with mipi 26 mhz read?back ? this is a pb?free device typical applications ? multi?band, multi?standard, advanced and simple mobile phones ? tunable antenna matching networks ? compatible with closed?loop and open?loop antenna tuner applications www. onsemi.com see detailed ordering and shipping information on page 32 o f this data sheet. ordering information marking diagram wlcsp4 case 567jv a = assembly location l = wafer lot y = year w = work week = pb?free package xxxx alyw
tcc?206 www. onsemi.com 2 figure 1. control ic functional block diagram 7?bit dac vio gndio avdd l_boost vhv vreg gnd_boost cs clk data trig outa otp level shifter vio por vreg por start reference interface registers booster outb outc regulator 4 bit dac bandgap gnda atest vio_on por_vreg 8 8 8 ibias_start/vref_start vio avdd vreg vhv outd oute outf 8 8 8 idb0 7?bit dac 7?bit dac 7?bit dac 7?bit dac 7?bit dac figure 2. die bump side view
tcc?206 www. onsemi.com 3 rdl pin out table 1. pad descriptions rdl name type description max voltage (note 1) a1 outf aoh high voltage output f vhv a2 vreg ao regulator output 2 a3 gnd_boost p ground for booster 0 a4 vhv aoh / aih boost high voltage can be forced externally 28 b1 oute aoh high voltage output e vhv b2 atest ao analog test out (note 4) vreg b3 avdd p analog supply 5.5 b4 l_boost aoh boost inductor 28 c1 outd aoh high voltage output d vhv c2 idb0 di mipi rffe id bit 0 (note 3) vio c3 gnda p analog ground 0 c4 trig dio trigger signal input (note 2) vio d1 outc aoh high voltage output c vhv d2 gndio p digital io ground vio d3 cs di chip select for spi vio d4 clk di mipi rffe / spi clock vio e1 outb aoh high voltage output b vhv e2 outa aoh high voltage output a vhv e3 vio p digital io supply 2 e4 data dio digital io (spi and mipi rffe) vio 1. for information only. 2. to be grounded when not in use. 3. this pin has to be connected to either gndio or vio level, even if only spi protocol is used. never let it float. 4. to be grounded in normal operation. electrical performance specifications table 2. absolute maximum ratings symbol parameter rating unit avdd analog supply voltage ?0.3 to +6.0 v vio io reference supply voltage ?0.3 to +2.2 v v i/o input voltage logic lines (data, clk, cs) ?0.3 to vio + 0.3 v v (sub)hvh vhv maximum voltage ?0.3 to 30 v v esd (hbm) human body model, jesd22?a114, all i/o 2,000 v v esd (mm) machine model, jesd22?a115 200 v t stg storage temperature ?55 to +150 c t amb_op_max max operating ambient temperature without damage +110 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected.
tcc?206 www. onsemi.com 4 table 3. recomended operating conditions symbol parameter rating unit min typ max t amb_ op operating ambient temperature ?30 ? +85 c t j_ op operating junction temperature ?30 ? +125 c avdd analog supply voltage 2.3 ? 5.5 v vio io reference supply voltage 1.62 ? 1.98 v functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. table 4. dc characteristics (t a = ?30 to +85 c; v outx = 15 v for each output; 2.3 v tcc?206 www. onsemi.com 5 table 4. dc characteristics (t a = ?30 to +85 c; v outx = 15 v for each output; 2.3 v tcc?206 www. onsemi.com 6 theory of operation overview the control ic outputs are directly controlled by programming the six dacs (dac a, dac b, dac c, dac d, dac e and dac f) through the digital interface. the dac stages are driven from a reference voltage, generating an analog output voltage driving a high?voltage amplifier supplied from the boost converter (see figure 1 ? control ic functional block diagram). the control ic output voltages are scaled from 0 v to 24 v, with 128 steps of 188 mv ((2 x 24 / 255 v) = 0.188235 v). the nominal control ic output can be approximated to 188 mv x (dac value). for performance optimization the boost output voltage (vhv) can be programmed to levels between 13 v and 28 v via the dac_boost register (4 bits with 1 v steps). the startup default level for the boosted voltage is vhv = 24 v. for proper operation and to avoid saturation of the output devices and noise issues it is recommended to operate the boosted vhv voltage at least 2 v above the highest programmed v out voltage of any of the six outputs. operating modes the following operating modes are available: 1. shutdown mode: all circuit blocks are off, the dac outputs are disabled and placed in high z state and current consumption is limited to minimal leakage current. the shutdown mode is entered upon initial application of avdd or upon vio being placed in the low state. the contents of the registers are not maintained in shutdown mode. 2. startup mode: startup is only a transitory mode. startup mode is entered upon a vio high state. in startup mode all registers are reset to their default states, the digital interface is functional, the boost converter is activated, outputs out a, out b, out c, out d, out e and out f are disabled and the dac outputs are placed in a high z state. control software can request a full hardware and register reset of the tcc?206 by sending an appropriate pwr_mode command to direct the chip from either the active mode or the low power mode to the startup mode. from the startup mode the device automatically proceeds to the active mode. 3. active mode: all blocks of the tcc?206 are activated and the dac outputs are fully controlled through the digital interface, dacs remain off until enabled. the dac settings can be dynamically modified and the hv outputs will be adjusted according to the specified timing diagrams. each dac can be individually controlled and/or switched off according to application requirements. active mode is automatically entered from the startup mode. active mode can also be entered from the low power mode under control software command. 4. low power mode: in low power mode the serial interface stays enabled, the dac outputs are disabled and are placed in a high z state and the boost voltage circuit is disabled. control software can request to enter the low power mode from the active mode by sending an appropriate pwr_mode command. the contents of all registers are maintained in the low power mode. shutdown startup (registers reset) active low power (user defined) pwr_mode = 0b10 vdda = 0 figure 3. modes of operation battery insertion (user defined) pwr_mode = 0b01 automatic vio = high vio = low vio = low pwr_mode = 0b00 pwr_mode = 0b01
tcc?206 www. onsemi.com 7 avdd power?on reset (por) upon application of avdd the tcc?206 will be in shutdown mode. all circuit blocks are off and the chip draws only minimal leakage current. vio power?on reset and startup conditions a high level on vio places the chip in startup mode which provides a por to the tcc?206. por resets all registers to their default settings as described in table 8. vio por also resets the serial interface circuitry. por is not a brown?out detector and vio needs to be brought back to a low level to enable the por to trigger again. table 7. vio power?on reset and startup register default state for vio por comment dac boost [1011] vhv = 24 v power mode [01]>[00] transitions from shutdown to startup and then automatically to active mode dac enable [000000] v out a, b, c, d, e and f disabled dac a output in high?z mode dac b output in high?z mode dac c output in high?z mode dac d output in high?z mode dac e output in high?z mode dac f output in high?z mode vio shutdown a low level at any time on vio places the chip in shutdown mode in which all circuit blocks are off. the contents of the registers are not maintained in shutdown mode. table 8. vio thresholds (avdd from 2.3 v to 5.5 v; t a = ?30 to +85 c unless otherwise specified) parameter description min typ max unit comments viorst vio low threshold ? ? 0.2 v when vio is lowered below this threshold level the chip is reset and placed into the shutdown state power supply sequencing the avdd input is typically directly supplied from the battery an d thus is the first on. after avdd is applied and before vio is applied to the chip, all circuits are in the shutdown stat e and draw minimum leakage cu rrents. upon application of vio, the chip automatically starts up using default settings and is placed in the active state waiting for a command via the serial interface . table 9. timing (avdd from 2.3 v to 5.5 v; v io = 1.8 v; t a = ?30 to +85 c; out a, out b, out c, out d, out e & out f; chv = 22 nf; l boost = 15 h; vhv = 20 v; t urbo?charge mode off unless otherwise specified) parameter description min typ max unit comments t por_ vreg internal bias settling time from shutdown to active mode ? 50 120 s for info only t boost_ start time to charge chv @ 95% of set vhv ? 130 ? s for info only t sd_ to_ act startup time from shutdown to active mode ? 180 300 s t set+ output a, b, c, d, e, f positive settling time to within 5% of the delta voltage, equivalent series load of 5.6 k and 2.7 nf, v out from 2 v to 20 v; 0bh (11d) to 55h (85d) ? 50 60 s voltage settling time connected on v out a, b, c, d, e, f t set? output a, b, c, d, e, f negative settling time to within 5% of the delta voltage, equivalent series load of 5.6 k and 2.7 nf, v out from 20 v to 2 v; 55h (85d) to 0bh (11d) ? 50 60 s voltage settling time connected on v out a, b, c, d, e, f t set+ output a, b, c, d, e, f positive settling time with turbo ? 35 ? s voltage settling time connected on v out a, b, c, d, e, f t set? output a, b, c, d, e, f negative settling time with turbo ? 35 ? s voltage settling time connected on v out a, b, c, d, e, f
tcc?206 www. onsemi.com 8 figure 4. output settling diagram figure 5. startup timing diagram
tcc?206 www. onsemi.com 9 boost control the tcc?206 integrates an asynchronous current control boost converter. it operates in a discontinuous mode and features spread?spectrum circuitry for electro?magnetic interference (emi) reduction. the average boost clock is 2 mhz and the clock is spread between 0.8 mhz and 4 mhz. boost output voltage (vhv) control principle the asynchronous control starts the boost converter as soon as the vhv voltage drops below the reference set by the 4?bit dac and stops the boost converter when the vhv voltage rises above the reference again. due to the slow response time of the control loop, the vhv voltage may drop below the set voltage before the control loop compensates for it. in the same manner, vhv can rise higher than the set value. this effect may reduce the maximum output voltage available. please refer to figure 7 below. the asynchronous control reduces switching losses and improves the output (vhv) regulation of the dc/dc converter under light load, particularly in the situation where the tcc?206 only maintains the output voltages to fixed values. set vhv figure 6. vhv voltage waveform vhv time delay delay chv discharge delay chv recharge boost running high impedance (high z) feature in shutdown mode the out pins are set to a high impedance mode (high z). following is the principle of operation for the control ic: 1. the dac output voltage v out is defined by: v out dac code 255 24 v 2 (eq. 1) 2. the voltage vhv defines the maximum supply voltage of the dac supply output regulator and is set by a 4?bit control. 3. the maximum dac dc output voltage v out is limited to (vhv ? 2 v). 4. the minimum output dac voltage v out is 1.0 v max. figure 7. dac output range example a figure 8. dac output range example b digital interface the control ic is fully controlled through a digital interface (data, clk, cs). the digital interface auto? matically detects and responds to mipi rffe interface commands, 3?wire 30?bit serial interface commands or 3?wire 32?bit serial interface commands. auto?detection is accomplished on a frame by frame basis. the digital interface is described in the following sections of this document, for detailed programming instructions please refer to the programming guide, available by contacting on semiconductor. 3?wire serial interface the 3?wire serial interface operates in a synchronous write?only 3?wire slave mode. 30?bit or 32?bit message length is automatically detected for each frame. if cs changes state before all bits are received then all data bits are ignored. data is transmitted most significant bit first and data is latched on the rising edge of clk. commands are latched on the falling edge of cs.
tcc?206 www. onsemi.com 10 table 10. 3?wire serial interface specification (t a = ?30 to +85 c; 2.3 v < avdd < 5.5 v; v io = 1.8 v; unless otherwise specified) parameter description min typ max unit comments f clk clock frequency ? ? 26 mhz t clk clock period 38.4 ? ? ns n bit bits number ? 30/32 ? bits auto?detection 30?bit or 32?bit t high clock high time 13 ? ? ns t low clock low time 13 ? ? ns tcs setup cs set?up time 5 ? ? ns 70% rising edge of cs to 30% rising edge of first clock cycle tcs hold cs hold time 5 ? ? ns 30% falling edge of last clock cycle to 70% falling edge of cs td setup data set?up time 4 ? ? ns relative to 30% of clk rising edge td hold data hold time 4 ? ? ns relative to 70% of clk ris- ing edge t succ cs low time between successive writes 38.4 ? ? ns 70% falling edge of cs to 70% rising edge of cs t succ cs low time between successive dac update writes 1,500 ? ? ns time between groups of dac update reg [00000] & [00001] writes c clk input capacitance ? ? 5 pf clk pin c data input capacitance ? ? 8.3 pf data pin c cs input capacitance ? ? 5 pf cs pin c trig input capacitance ? ? 10 pf trig pin v ih input logic level high 0.7 x vio ? vio x 0.3 v data, clk, cs v il input logic level low ?0.3 ? 0.3 x vio v data, clk, cs i ih_ data input current high ?2 ? 10 a data i il_ data input current low ?2 ? 1 a data i ih_ clk,cs input current high ?1 ? 10 a clk, cs i il_ clk,cs input current low ?1 ? 1 a clk, cs v tp_ trig positive going threshold volt- age 0.4 x vio ? 0.7 x vio v trig v tn_ trig negative going threshold volt- age 0.3 x vio ? 0.6 x vio v trig v h_ trig hysteresis voltage (v tp ? v tn ) 0.1 x vio ? 0.4 x vio v trig i ih_ trig trig input current high ?2 ? 10 a trig=0.8 x vio i il_ trig trig input current low ?2 ? 1 a trig=0.2 x vio
tcc?206 www. onsemi.com 11 figure 9. 3?wire serial interface signal timing spi frame length decoding 30?bit or 32?bit frame length is automatically detected. the length of the frame is defined by the number of clock rising edges while cs is kept high. the tcc?206 will not respond to a spi command if the length of the frame is not exactly 30 bits or 32 bits. spi registers are write only. spi frame structure table 11. 32 bits frame: address decoding (1, 2, 3, 4, 5 or 6 outputs) h0 h1 r/w a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 0 1 0 1 0 0 1 0 0 x x x x x on semiconductor header r/w device id specific device id register address for operation table 12. 30 bits frame: address decoding (1, 2, 3, 4, 5 or 6 outputs) r/w a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 0 1 0 0 1 0 0 x x x x x r/w device id specific device id register address for operation table 13. 3?wire serial interface address map a4 a3 a2 a1 a0 data[15:8] data[7:0] 0 0 0 0 0 turbo?charge settings for dac a, b, c dac c 0 0 0 0 1 dac b dac a 0 0 0 1 0 turbo?charge settings for dac d, e, f dac f 0 0 0 1 1 dac e dac d 0 0 1 0 0 turbo?charge delay parameters for dac a, b, c turbo threshold delay settings for a, b, c 0 0 1 0 1 turbo?charge delay parameters for dac d, e, f turbo threshold delay settings for a, b, c 1 0 0 0 0 mode select + control ic setup
tcc?206 www. onsemi.com 12 table 13. 3?wire serial interface address map 1 0 0 1 0 reserved reserved to 1 1 1 1 1 turbo?charge mode the tcc?206 control ic has a turbo?char ge mode that significantly shortens the system settling time when changing programming voltages. in turbo?char ge mode the dac output target voltage is temporarily set to either a delta voltage above or a delta voltage below the actual desired target for the tcdly time. it is recommended that v hv be set to 26 v when using t urbo?charge mode. glide mode unlike turbo mode, which is intended to reduce the charging time, the glide mode extends the transition time of each dac output. each dac has an individual control for turbo mode, glide mode or regular voltage switching. the glide mode can be enabled for a particular dac through the index register, by setting dac state to ?1? when glide mode is enabled, turbo mode is off for a particular dac, but one dac can be gliding while the other is turbo. during glide mode the output voltage of a dac is either increased or dec reased to its set end point, in max 255 steps, where each dac time step can be programmed between 2 s to 64 s. for programming the glide mode refer to the application note (coming soon). a programming input is not required to maintain a glide transition, all step controls are maintained by the part. only the inputs to define the glide need to be programmed. rf front?end control interface (mipi rffe interface) the tcc?206 is a read/write slave device which is fully compliant to the mipi alliance specification for rf front?end control interface (rffe) version 1.10.00 26 july 2011. this device is rated at full?speed operation for 1.65 v tcc?206 www. onsemi.com 13 figure 11. mipi?rffe signal timing during master reads from ptic control ic figure 12. bus park cycle timing when mipi?rffe master reads from ptic control ic clk data t read_access t sdataotr t sdataotr t read_access clk data bus park cycle t sdataz
tcc?206 www. onsemi.com 14 table 14. mipi rffe interface specification (t a = ?30 to +85 c; 2.3 v < avdd < 5.5 v; 1.1 v < v io < 1.8 v; unless otherwise specified) parameter description min typ max unit comments f sclk clock full?speed frequency 0.032 ? 26 mhz full?speed operation: 1.65 v < v io < 1.95 v t sclk clock full?speed period 0.038 ? 32 s full?speed operation: 1.65 v < v io < 1.95 v t sclkih clk input high time 11.25 ? ? ns full?speed t sclkil clk input low time 11.25 ? ? ns full?speed v tp positive going threshold voltage 0.4 x vio ? 0.7 x vio v clk, data, trig, 1.2 or 1.8 v bus v tn negative going thresh- old voltage 0.3 x vio ? 0.6 x vio v clk, data, trig, 1.2 or 1.8 v bus v h hysteresis voltage (v tp ? v tn ) 0.1 x vio ? 0.4 x vio v clk, data, trig, 1.2 or 1.8 v bus i ih input current high ?2 ? +10 a trig,sdata = 0.8 x vio ?1 ? +10 a sclk = 0.8 x vio i il input current low ?2 ? +1 a trig,sdata = 0.2 x vio ?1 ? +1 a sclk = 0.2 x vio c clk input capacitance ? ? 5 pf clk pin c data input capacitance ? ? 8.3 pf data pin c trig input capacitance ? ? 10 pf trig pin td setup write data setup time ? ? 1 ns full?speed td hold write data hold time ? ? 5 ns full?speed t read_access read data valid from clk rising edge ? ? 7.11 ns full speed at v io = 1.80 v, +25 c, and max 15 pf load on data pin t read_access read data valid from clk rising edge ? ? 9.11 ns full speed at v io = 1.80 v, +25 c, and max 50 pf load on data pin
tcc?206 www. onsemi.com 15 the control ic contains twenty?four 8?bit registers. register content is described in table 15. some additional registers implemented as provision, are not described in this document. table 15. mipi rffe address map register address description purpose access type size (bits) 0x00 dac configuration (enable mask) high voltage output enable mask write reg0 7 0x01 turbo register dac a, b & c turbo?charge configuration dac a, b & c write 8 0x02 dac a register out a value [6:0], turbo index [7]** write 8 0x03 dac b register out b value [6:0], turbo index [7]** write 8 0x04 dac c register out c value [6:0], turbo index [7]** write 8 0x05 turbo register dac d, e & f turbo?charge configuration dac d,e & f write 8 0x06 dac d register out d value [6:0], turbo index [7]** write 8 0x07 dac e register out e value [6:0], turbo index [7]** write 8 0x08 dac f register out f value [6:0], turbo index [7]** write 8 0x09 wake up wake up controls write 8 0x10 dac boost (vhv) settings for the boost high voltage write 8 0x11 trigger register trigger configuration write 8 0x12 turbo?charge delay dac a, b, c turbo?charge delay steps dac a, b, c write 8 0x13 turbo?charge delay dac a, b, c turbo?charge delay, multiplication dac a, b, c write 8 0x14 turbo?charge delay dac d, e, f turbo?charge delay steps dac d, e, f write 8 0x15 turbo?charge delay dac d, e, f turbo?charge delay multiplication dac d, e, f write 8 0x1a rffe_status rffe status register read/write 8 0x1b rffe_group_sid read/write 8 0x1c power mode and trigger register power mode & trigger control pwr_mode [7:6] trig_reg [5:0] read/write 8 0x1d product id register product number * hard coded into asic read 8 0x1e manufacturer id register mn (10 bits long) manufacturer id[7:0] hard coded into asic read 8 0x1f unique slave identifier register (usid) spare [7:6] [5,4] = manufacturer id [9:8] usid [3:0] read/write 8 0x2c glide timer settings [6:5] turbo and glide control / [4:0] glide timer setting / need extended write for this register write 8 *the second least significant bit can be programmed in otp during manufacture ** the details for configuration of turbo mode should be ascertained from the programming guide, available from on semiconducto r configuration settings table 16. dac configuration (enable mask) at [0x00] defaults shown as (x) bit 6 (1) bit 5 (0) bit 4 (0) bit 3 (0) bit 2 (0) bit 1 (0) bit 0 (0) sse dac e dac f dac a dac b dac c dac d sse = 0 spread spectrum disabled, sse = 1 spread spectrum enabled (default), this controls the average boost clock which is nominally 2 mhz and spread between 0.8 mhz and 3.2 mhz when enabled (default). the hardware does not limit driving more than three dacs at the same time, however it is recommended to have max three dacs changing outputs at one time, no restrictions exist as to which three.
tcc?206 www. onsemi.com 16 table 17. dac mode setup: dac enable bit3 bit2 bit1 dac a dac b dac c 0 0 0 off off off (default) 0 0 1 off off enabled 0 1 0 off enabled off 0 1 1 off enabled enabled 1 0 0 enabled off off 1 0 1 enabled off enabled 1 1 0 enabled enabled off 1 1 1 enabled enabled enabled table 18. dac mode setup: dac enable bit5 bit4 bit0 dac e dac f dac d 0 0 0 off off off (default) 0 0 1 off off enabled 0 1 0 off enabled off 0 1 1 off enabled enabled 1 0 0 enabled off off 1 0 1 enabled off enabled 1 1 0 enabled enabled off 1 1 1 enabled enabled enabled table 19. boost dac mode setup (vhv) at [0x10] (notes 5 and 6) bit 7* bit 6* bit 5* bit 4 bit 3 bit 2 bit 1 bit 0 vhv (v) 0 0 0 1 0 0 0 0 13 0 0 0 1 0 0 0 1 14 0 0 0 1 0 0 1 0 15 0 0 0 1 0 0 1 1 16 0 0 0 1 0 1 0 0 17 0 0 0 1 0 1 0 1 18 0 0 0 1 0 1 1 0 19 0 0 0 1 0 1 1 1 20 0 0 0 1 1 0 0 0 21 0 0 0 1 1 0 0 1 22 0 0 0 1 1 0 1 0 23 0 0 0 1 1 0 1 1 24 (default) 0 0 0 1 1 1 0 0 25 0 0 0 1 1 1 0 1 26 0 0 0 1 1 1 1 0 27 0 0 0 1 1 1 1 1 28 *indicates reserved bits 5. bit 4 is fixed at logic 1 for reverse software compatibility 6. vhv is recommended to be set at vdac max + 2 v for non?turbo operation and +4 when turbo is used.* indicates reserved bits.
tcc?206 www. onsemi.com 17 mipi rffe trig operation the mipi rffe trigger mode can be used as a synchronization signal to ensure that new dac settings are applied to the outputs at appropriate times in the overall transceiver system. when the mipi rffe trig function is enabled via [0x11] bit 4 the requested dac voltage levels are set up in the shadow registers and not transferred to the destination registers until the trigger condition is met. in this manner the change in output voltage levels are synchronized with the mipi rffe trig command. if multiple dac voltage level requests are received before the trig event occurs, only the last fully received dac output voltage level will be applied to the outputs. the trigger configuration also provides for an additional external trig pin to be used as a synchronization signal. the external trig is independent from the built?in triggers available within the mipi rffe interface. when the trig input pin is enabled via [0x11] bit 4 the requested dac voltage levels are set up in the shadow registers and are not transferred to the destination registers until the external trigger condition is met. in this manner the change in output voltage levels are synchronized with the external trig event. the external trig input is referenced to vio. to improve interfacing options the polarity of external trig is programmable via [0x11] bit 1. if the external trigger function is not needed in the application, the trig pin should be grounded and the trig function disabled. when trig pin is disabled by register [0x11] ?trig select? = ?1? (default) and register [0x10] ?trigger mask 0, 1, 2? = ?1?: ? the requested dac voltage levels for dac a, b, c are applied to the outputs all together at the same time, after dac c value is written. this event will not affect the outputs of dac d, e, f. ? the requested dac voltage levels for dac d, e, f are applied to the outputs all together at the same time, after dac f value is written. this event will not affect the outputs of dac a, b, c. ? optionally a configuration register can select the last dac to be written in order to trigger internally the update of all six dacs at the same time. for example the configuration register can select that a write to dac b value will trigger internally the update of all six dacs outputs. table 20. trigger configuration at [0x11] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 res* 0 res* 0 res* 0 trig select 0 = ext trig pin 1 = rffe trigger reserved 0 trig edge 0 = active falling 1 = active rising mask ext trig 1 = mask trig pin *reserved bits table 21. external trigger configuration bit setting at [0x11] bit 4 bit 3 bit 2 bit 1 bit 0 description 0 ? ? x 0 external trigger pin is enabled. sending the rffe message will load a ?shadow? register only. only upon an active signal on external trig pin are the output re- gisters loaded with the new voltage settings which are then applied to the outputs. 1 ? ? x x the mipi rffe trigger is enabled (default) 0 ? ? 0 0 external trig pin signal is active falling 0 ? ? 1 0 external trig pin signal is active rising (default) x ? ? x 0 external trigger pin is not masked x ? ? x 1 mask external trigger pin (default) table 22. power mode and trigger register [0x1c] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pm1 pm0 trigger mask 2 trigger mask 1 trigger mask 0 trigger 2 trigger 1 trigger 0 writing a logic one (?1?) to the bits 0, 1 or 2 (trigger 0, 1 or 2) moves data from the shadow registers into the destination registers. default for bit 0, 1 and 2 is logic low. if trigger mask bit 0, 1 or 2 is set (?1?) the trigger 0, 1 or 2 are disabled respectively and the data goes directly to the destination register. default for bit 3, 4 and 5 is logic low. all three triggers behave in the same way as the external pin trig. when each of these triggers is set using the mipi rffe interface the results are the same as when an active edge is applied to the trig pin when external pin trig is selected
tcc?206 www. onsemi.com 18 table 23. power mode bit setting in register [0x1c] pm1 pm0 state description 0 0 active boost control active, vhv set by digital interface v out a, b, c, d, e, f enabled and controlled by digital interface (default) 0 1 startup boost control active, vhv set by digital interface v out a, b, c, d, e, f disabled 1 0 low power digital interface is active while all other circuits are in low power mode 1 1 reserved state of hardware does not change command sequences ? register 0 write (used to access the register 0 dac configuration ? enable mask). register 0 can be also be accessed using register write or/and extended register write. ? register write (used to access only one register at the time) ? extended register write (used to access a group of contiguous registers with one command) register 0 write command sequence the command sequence starts with a sequence start condition (ssc) which is followed by the register 0 write command frame. this frame contains the slave address, a logic one, and the seven bit word that will be written to register 0. the command sequence is depicted below. figure 13. register 0 write command sequence table 24. mipi rffe command frame for register 0 write command sequence description ssc command frame bp sse & dac configuration 1 0 sa [3,0] 1 sse dac_e dac_f dac_a dac_b dac_c dac_d p bp
tcc?206 www. onsemi.com 19 register write command sequence the write register command sequence may be used to access each register (addresses 0?31). figure 14. register write command sequence table 25. mipi rffe command frame for register write command sentence description ssc command frame data frame bp turbo?charge settings 1 0 sa [3,0] 0 1 0 0 0 0 0 1 p tc_indx_l [7:0] p bp register write dac a 1 0 sa [3,0] 0 1 0 0 0 0 1 0 p tc_indx_l [8] & dac_a [6:0] p bp register write dac b 1 0 sa [3,0] 0 1 0 0 0 0 1 1 p tc_indx_l [9] & dac_b [6:0] p bp register write dac c 1 0 sa [3,0] 0 1 0 0 0 1 0 0 p tc_indx_l [10] & dac_c [6:0] p bp table 26. mipi rffe command frame for register write command sentence description ssc command frame data frame bp turbo?charge settings 1 0 sa [3,0] 0 1 0 0 0 1 0 1 p tc_indx_u [7:0] p bp register write dac d 1 0 sa [3,0] 0 1 0 0 0 1 1 0 p tc_indx_u [8] & dac_d [6:0] p bp register write dac e 1 0 sa [3,0] 0 1 0 0 0 1 1 1 p tc_indx_u [9] & dac_e [6:0] p bp register write dac f 1 0 sa [3,0] 0 1 0 0 1 0 0 0 p tc_indx_u [10] & dac_f [6:0] p bp
tcc?206 www. onsemi.com 20 extended register write command sequence in order to access more than one register in one sequence this message could be used. most commonly it will be used for loading three dac registers at the same time. the four lsbs of the extended register write command frame determine the number of bytes that will be written by the command sequence. a value of 0b0000 would write one byte and a value of 0b1111 would write 16 bytes. if more than one byte is to be written, the register address in the command sequence contains the address of the first extended register that will be written to and the slave?s local extended register address shall be automatically incremented by one for each byte written up to address 0x1f, starting from the address indicated in the address frame. figure 15. extended register write command sequence
tcc?206 www. onsemi.com 21 table 27. extended register write to update dac a, b, c (note 7) description ssc command frame address frame extended register write tc_indx_l and dac a, b, c op code p p 1 0 sa [3,0] 0 0 0 0 0 0 1 1 p 0 0 0 0 0 0 0 1 p data frame data frame data frame data frame bp p p p p bp turbo?charge p dac_a [7,0] p dac_b [7,0] p dac_c [7,0] p bp table 28. extended register write to update dac d, e, f (note 7) description ssc command frame address frame extended register write tc_indx_u and dac d, e, f op code p p 1 0 sa [3,0] 0 0 0 0 0 0 1 1 p 0 0 0 0 0 1 0 1 p data frame data frame data frame data frame bp p p p p bp turbo?charge p dac_d [7,0] p dac_e [7,0] p dac_f [7,0] p bp 7. the six dacs can be updated either all together in the same time by using one extended register write command of 8 bytes, or separately by using two extended register write commands of 4 bytes each, where one command is to update dac a, b, c and the other command to update dac d, e, f. figure 16. register read command sequence table 29. register read command description ssc command frame read mipi?rffe status register 1 0 sa[3:0] 0 1 1 1 1 0 1 0 p bp description data frame read mipi?rffe status register (continued) 0 cfpe cle afpe dfpe rure wure bge bp
tcc?206 www. onsemi.com 22 register details register rffe: rffe_reg_0x00 address rffe a[4:0]: 0x00 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 6 5 4 3 2 1 0 bits ss enable dac e dac f dac a (1) dac b (1) dac c (1) dac d reset w?1 w?0 w?0 w?0 w?0 w?0 w?0 (1) when any of the bits [3:1] are written with ?0?, the corresponding dac is disabled, but the turbo?charge process which is already started, will not be stopped. (2) if all bits [3:1] are ?0?, then incoming dac messages will be ignored, until at least one of [3:1] is set ?1?. bit 6: spread spectrum enable 0: ss disabled 1: ss enabled bit [1]: control dac e 0: off (default) 1: enabled bit [1]: control dac f 0: off (default) 1: enabled bit [3]: control dac a 0: off (default) 1: enabled bit [2]: control dac b 0: off (default) 1: enabled bit [1]: control dac c 0: off (default) 1: enabled bit [1]: control dac d 0: off (default) 1: enabled register rffe: rffe_reg_0x01 address rffe a[4: 0 ]: 0 x01 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits tc_indx_l[7:0] reset w?0 w?0 w?0 w?0 w?0 w?0 w?0 w?0 register rffe: rffe_reg_0x02 address rffe a[4: 0 ]: 0 x02 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits tc_indx_l [8] dac a value [6:0] reset w -0 w -0 w -0 w -0 w -0 w -0 w?0 w?0
tcc?206 www. onsemi.com 23 register rffe: rffe_reg_0x03 address rffe a[4: 0 ]: 0x03 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits tc_indx_l [9] dac b value [6:0] reset w -0 w -0 w -0 w -0 w -0 w -0 w -0 w?0 register rffe: rffe_reg_0x04 address rffe a[4: 0 ]: 0 x04 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits tc_indx_l [10] dac c value [6:0] reset w -0 w -0 w -0 w -0 w -0 w -0 w -0 w -0 register rffe: rffe_reg_0x05 address rffe a[4: 0 ]: 0 x05 (1) reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits tc_indx_u[7: 0 ] reset w -0 w -0 w -0 w -0 w -0 w -0 w -0 w -0 register rffe: rffe_reg_0x06 address rffe a[4: 0 ]: 0 x06 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits tc_indx_u [8] dac d value [6:0] reset w -0 w -0 w -0 w -0 w -0 w -0 w -0 w -0 register rffe: rffe_reg_0x07 address rffe a[4: 0 ]: 0 x07 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits tc_indx_u [9] dac e value [6:0] reset w?0 w?0 w?0 w?0 w?0 w?0 w?0 w?0 register rffe: rffe_reg_0x08 address rffe a[4:0]: 0x08 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits tc_indx_u [10] dac f value [6:0] reset w -0 w -0 w -0 w -0 w -0 w -0 w -0 w -0
tcc?206 www. onsemi.com 24 register rffe: rffe_reg_0x9 address rffe a[4: 0 ]: 0 x09 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits hw wake - up polarity hw wake? up disable dac_wakeup_ctrl turbo latency select reserved boost_en_fast_st (otp duplicated) (2) reset w -0 w - 1 w -0 w -0 w -0 w -0 w -0 w -0 1. changing rffe_reg_0x09 bits [7:5] while chip is in lp std mode does not have effect, until chip returns to active mode because bits [7:5] are shadowed when entering lp std mode. 2. boost_en_fast_st can be set in active or in lp mode bit [7:6]: hw wake ?up pola rity 00: hw wake?up is always active low 01: (default) hw wake?up is always active high 10: hw wake?up has inverted pola rity referred to trig pin: a. when rffe_reg_0x11/trig_sel = 1, hw wake?up is always active low b. when rffe_reg_0x11/trig_sel = 0, hw wake?up is: i. active low if rffe_reg_0x11/trig_edge = 0 ii. active high if rffe_reg_0x11/trig_edge = 1 11: hw wake?up has s ame polarity as trig pin: a. when rffe_reg_0x11/trig_sel = 1, hw wake?up is always active high b. when rffe_reg_0x11/trig_sel = 0, hw wake?up is: i. active high if rffe_reg_0x11/trig_edge = 0 ii. active low if rffe_reg_0x11/trig_edge = 1 bit [5]: hw wake ?up disable 0 : (default) hw wake?up is enabled 1: hw wake?up is disabled bit [4:3]: dac wake?up control applicable to wake?up from lp 00: (default) don?t apply turbo when wake?up from lp 01: always apply turbo up when wake?up from lp. turbo up is calculated based on dac value prior to enter lp std mode. 10: apply turbo up when wake?up from lp when hw wake?up is applied, but don?t apply turbo up when sw wake?up is applied 11: unused note 1: turbo i s not appl i ed after wake?up to the dacs whi ch are programmed with 0x00 in the dac value register note 2: when bi t[4:3] = ?10? or ?01?, then turbo i s appl i ed after wake?up regardl ess if: ? dac values are updated or not ? l ast dac val ue update i s equal wi th ol d dac val ue note 3: when rffe_reg_0x31 / wake?up dac ctrl i s ?0? (default) turbo after wake?up i s appl i ed after fi rst vhv_too_low fal ling edge is detected. when rffe_reg_0x31 / wake?up dac ctrl i s ?1? turbo after wake?up i s appl i ed after rc_clk starts. bit [2]: turbo up latency select when wake?up from lp. this field has no effect when dac_wakeup_ctrl[1:0] = ?00? 0 : (default) turbo up latency is 50us 1: turbo up latency is 100us bit [1]: fast transition to active mode enable 0: (default) slow, current as low as possible in lp mode 1 fast, rc oscillator and ba ndgap stay on, refer to section 5.6.2.4.2 bit [0]: boost fast startup enable 0: (default) startup with selected boost_il_trim 1: startup with boost_il_trim_st[2:0], only if otp[59]=1. the value of boost_il_trim_st[2:0] is applied starting from the moment when rffe_reg_0x1c / power mode filed is written ?00? during lp mode, until first vhv_too_low negative edge is detected.
tcc?206 www. onsemi.com 25 register rffe: rffe_reg_0x10 address rffe a[4: 0 ]: 0x10 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved fixed boost voltage value reset u?0 u?0 u?0 u?1 w?1 w?0 w?1 w?1 bit [3:0]: boost voltage value refer to table 19 for values the mipi rffe trigger modes can be used as a synchronizati on signal to ensure that new dac settings are appli ed to the outputs at appropriate times in the overall transceiver system. when the rffe trig function is enabled via the trig sel bit of rffe_reg_0x11the requested dac voltage levels are set up in the shadow registers and not transferred to the destination registers until the trigger con dition is m et. in this manner the change in output voltage levels are synchronized with the rffe trig command. the trigger configuration also provi des for an external trig pin to be used as a synchronization signal. when the trig input pin is enabled via the trig sel bit of rffe_reg_0x11the requested dac voltage levels are set up in the shadow registers and are not transferred to the destination registers until the external trigger condition is met . in this manner the change in output voltage levels are synchronized with the external trig event. the external trig input is referenced to vio. to improve interfacing options the polarity of external trig is programmable via trig_edge bit of rffe_reg_0x11. when mipi rffe trigger and the external trig input are disabled by mask_ext_trig of rffe_reg_0x11 and trigger_mask[5:3] of rffe_reg_0x1c, the requested dac voltage levels are immediately applied to the outputs and are not synchronized with the rffe trigger modes or the external trig signal. when valid trigger edge occurs, only the completely received messages are subject to be applied to the outputs. a message is considered to be completed, if the trig edge occurs after trig_lat following last sdl clock falling edge in the frame. in figure 17, the last sdl clock cycle in each frame is highlighted gray. the parameter trig_lat is represented as the latency following the sdl last falling edge in the frame until trig edge occurs. as an example, in figure 17 trig edge 3 occurs before trig_lat, following last sdl falling edge in frame of ?message a3?, so trig edge 3 will move ?message a2? to output, instead of ?message a3?. in this case trig edge 3 has the same effect as trig edge 2, which is described below. if trigger edge occurs while a message frame is being received by the slave on the serial bus, than the pending message will not be transferred to the output until next trigger edge occurs after frame transfer is completed. a pending message is considered from the moment ssc cy cle starts, until after trig_lat following last sdl f alling edge in the frame. for example, in figure 17, both trig edge 2 and trig edge 3 occur while ?message a3? is pending. in this case both will have same effect, which is to transfer ?message a2? to the output. ?message a3? will be transferred to the output by trig edge 4, because it occurs after trig_lat. if more than one message was received before a trigger edge, than only the last completed message will be transferred to the output. for example, in figure 17, between trig edge 1 and trig edge 2, there have been two messages sent: ?message a1? and ?message a2?. in this case, ?message a1? will be ignored, and only ?message a2? will be transferred to the output by trig edge 2. figure 17. sequences of triggers and messages to same output
tcc?206 www. onsemi.com 26 in figure 18, trig edge 2, will transfer ?message a2?, ?message b1?, and ?message c1? to the respective outputs, but will ignore ?message a1?. figure 18. sequences of triggers and messages to different outputs table 30. trig_lat parameter timing symbol description min max unit trig_lat latency following the falling edge of last clock cycle of a certain message , until the moment a trig edge is allowed to update the value sent by that message 5 25 ns register rffe: rffe_reg_0x11 address rffe a[4: 0 ]: 0 x11 7 6 5 4 3 2 1 0 bits reserved trig sel reserved trig edge (1) (2) mask ext trig reset u -0 u -0 u -0 w - 1 u?0 u?0 w?1 w?1 (1) following sequence is required when changing the expected polarity of trig pin: a) trig_sel = ?1? (disable trig pin) b) trig_edge = new value c) trig_sel = ?0? (enable trig pin) (2) after power?up, first configure trig_edge, then write trig_sel = ?0? bit 4: trig select 0: use external trig pin. sending the rffe message will load a ?shadow? registers only. only upon an active signal on external trig pin are the output registers loaded with the new voltage settings which are then applied to the outputs. software triggers generated by bits [2:0] of rffe_reg_0x1c are ignored when external trig pin is selected. 1: external trig pin will not be used. (default) bit [1]: trig edge 0: trig pin active falling 1: trig pin active rising (default) bit [0]: mask ext trig 0: external trigger is not masked 1: mask external trigger pin (default) turbo mode timing is controlled by these registers: register rffe: rffe_reg_0x12 address rffe a[4: 0 ]: 0 x12 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved tc_stp_dac_c tc_stp_dac_b tc_stp_dac_a reset u?0 u?0 w?0 w?1 w?0 w?1 w?0 w?1 register rffe: rffe_reg_0x13 address rffe a[4: 0 ]: 0 x13 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode)
tcc?206 www. onsemi.com 27 7 6 5 4 3 2 1 0 bits reserved tcm_c tcm_b tcm_a reset u?0 u?0 w?0 w?0 w?0 w?0 w?0 w?0 register rffe: rffe_reg_0x14 address rffe a[4: 0 ]: 0 x14 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved tc_stp_dac_f tc_stp_dac_e tc_stp_dac_d reset u?0 u?0 w?0 w?1 w?0 w?1 w?0 w?1 register rffe: rffe_reg_0x15 address rffe a[4: 0 ]: 0 x15 reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved tcm_f tcm_e tcm_d reset u?0 u?0 w?0 w?0 w?0 w?0 w?0 w?0 register rffe: rffe_status_0x1a address rffe a[4: 0 ]: 0 x1a reset source: nreset_dig or swr = ?1? or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits swr cfpe cle afpe dfpe rure wure bge reset w?0 r?0 r?0 r?0 r?0 r?0 r?0 r?0 tc_stp_dac_x[1:0] turbo steps for tcdly [us] 00 3 0 1 (default) 5 10 7 11 9 tcm_x[1:0] turbo multiplication factor 00 (default) 4 01 3 10 2 11 1 step ( s) dac state 0 1 2 3 4 5 6 7 8 9 10 11 9 tcdly turbo off 18 27 36 45 54 63 72 81 90 99 7 tcdly turbo off 14 21 28 35 42 49 56 63 70 77 5 (default) tcdly turbo off 10 15 20 25 30 35 40 45 50 55 3 tcdly turbo off 6 9 12 15 18 21 24 27 30 33 the value of turbo time is deducted based on the hardware comparison of new dac value in respect to old dac value, as follows: if dac new > dac old, then tup = tcdly
tcc?206 www. onsemi.com 28 if dac new < dac old, and dac new_divby2 < 21, then tdown = tcdly + tcm * (21 ? dac_new_divby2) if dac new < dac old, and dac new_divby2 > 21, then tdown = tcdly if dac new < dac old, and dac new_divby2 = 21, then tdown = tcdly rffe_status register can be read any time after power?up without the need to enable the read operation as described in section 6.9.5 swr soft?reset mipi?rffe registers write ?1? to this bit to reset all the mipi?rffe registers, except rffe_reg_0x1c, rffe_usid, and rffe_group_sid this bit will always read?back ?0?. the soft reset occurs in the last clock cycle of the mipi?rffe frame which writes ?1? to this bit. right immediately after this frame, all the mipi?rffe registers have the reset value and are ready to be reprogrammed as desired. the otp duplicated registers are reset to the values written in otp. swr can be written only by usid messages. gsid and broadcast frames will be ignored when writing to this register field. rffe_status bits [6:0] are set ?1? by hardware to flag when a certain condition is detected, as described below. rffe_status bits [6:0] cannot be written, but it is cleared to ?0? under following conditions: ? hardware self?reset is applied after rffe_status is read ? when swr is written ?1? with usid frames ? when power mode transitions through startup mode ?01? ? after power?up reset cfpe 1: command frame with parity error received. on the occurrence of this error, the slave will ignore the entire command sequence cle 1: incompatible command length, due to unexpected ssc received before command length to be completed. on the occurrence of this error, the slave will accept write data up to the last correct and complete frame. when mipi?rffe multi?byte read command is detected, the slave will always replay with an extended read command of length of one byte. afpe 1: address frame with parity error received. on the occurrence of this error, the slave will ignore the entire command sequence dfpe 1: data frame with parity error received. rure on the occurrence of this error, the slave will ignore only the erroneous data byte (s) 1: read of non?existent register was detected. on the occurrence of this error, the slave will not respond to the read command frame. when the read operation is not enabled according to section 6.9.5, any read from an address other than 0x1a, will set rure and the slave will not respond to the read command frame. when the read operation is enabled according to section 6.9.5, any read from an unoccupied rffe register address will set rure. wure 1: write to non?existent register was detected. on the occurrence of this error, the slave discards data being written, and on the next received frame, proceeds as normal bge 1: read using the broadcast id was detected on the occurrence of this error, the slave will ignore the entire command sequence
tcc?206 www. onsemi.com 29 register rffe: rffe_group_sid_0x1b address rffe a[4: 0 ]: 0 x1b reset source: nreset_dig or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved reserved reserved reserved gsid[3] gsid[2] gsid[1] gsid[ 0 ] reset 0 0 0 0 w -0 w -0 w -0 w -0 gsid = group slave identifier register note: the gsid[3:0] field can be written directly by messages using usid. note: gsid value is not retained during shutdown power mode. note: gsid value is not affected by swr bit from rffe_status register note: frames using usid = gsid, can write only to rffe_reg_0x1c [7:6] and [2:0]. note: rffe read frames containing gsid will be ignored register rffe: rffe_reg_0x1c address rffe a[4: 0 ]: 0 x1c reset source: nreset_dig or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits power mode (5) trigger mask 2 (1) (2) (3) (4) trigger mask 1 (1) (2) (3) (4) trigger mask 0 (1) (2) (3) (4) trigger 2 trigger 1 trigger 0 reset w?0 w?0 w?0 w?0 w?0 w?0 w?0 w?0 (1) trigger mask bits [5:3] can be changed, either set or cleared, only with an individual message using usid (2) during broadcast mipi?rffe accesses using gsid = ?0000?, trigger bits [2:0] are masked by the pre?existent setting of trigger mask bits [5:3] (3) during individual mipi?rffe accesses using usid, trigger bits [2:0] are masked by the incoming trigger mask bits [5:3] within the same write message to rffe_reg _0x1c register. during individual mipi?rffe accesses using usid, pre?existent setting of trigger mask bits [5:3] is ignored. (4) when rffe_reg_0x11 / trig_sel = ?1? (external trig pin will not be used) and rffe_reg_0x1c/ trigger_mask_2 = ?1? and trigger_mask_1 = ?1? and trigger_mask_0 = ?1?, then dac messages will be sent to dacs immediately after rffe_reg _0x04 is received, without waiting for any trigger (5) power mode field bits [7:6] and triggers bits [2:0] can be changed by either mipi?rffe broadcast messages when usid field within the register write command is 0x0 , or individual messages when usid fields within the register write command is equal with rffe_reg_0x1f[3:0] note: all the 8 bits of rffe_reg_0x1c register bits are not affected by swr bit from rffe_status register bit [7:6]: power mode 00: active mode, defined by following hardware behavior: ? boost control active, vhv set by digital interface ? vout a, b, c enabled and controlled by digital interface 01: startup mode, defined by following hardware behavior: ? boost control active, vhv set by digital interface ? vout a, b, c disabled 10: low power mode when trig pin = low, active mode when trig pin = high. low power mode is defined by following hardware behavior: ? digital interface is active, while all other circuits are in low power mode 11: reserved (state of hardware does not change) bit 5: mask trigger 2 0:trigger 2 not masked. data goes to destination register after bit 2 is written value 1 (default) 1:trigger 2 is masked. data goes directly to the destination register bit 4: mask trigger 1 0:trigger 1 not masked. data goes to destination register after bit 1 is written value 1(default) 1:trigger 1 is masked. data goes directly to the destination register. bit 3: mask trigger 0 0:trigger 0 not masked. data goes to destination register after bit 0 is written value 1(default) 1:trigger 0 is masked. data goes directly to the destination register.
tcc?206 www. onsemi.com 30 bit 2: trigger 2 write 1 to this bit, to move data from shadow registers into destination register. this trigger can be masked by bit 5. bit 1: trigger 1 write 1 to this bit, to move data from shadow registers into destination register. this trigger can be masked by bit 4. bit 0: trigger 0 write 1 to this bit, to move data from shadow registers into destination register. this trigger can be masked by bit 3. all three triggers from register [0x1c] behave in the same way as the external pin trig. when each of these triggers is set using the mipi rffe interface t he results a re the same as when an a ctive voltage level is applied to the trig pin when external pin trig is selected. register rffe: rffe_product_id_0x1d address rffe a[4: 0 ]: 0 x1d reset source: n/a 7 6 5 4 3 2 1 0 bits pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid 0 (1) reset 0 0 1 0 0 1 otp[4] idb 0 pin bits [7:2] are hardcoded in asic bits [1:0] can be programmed in otp during manufacturing the mipi register rffe_product_id can be read in spi mode as described in 6.9.5 register rffe: rffe_manufacturer_id_0x1e address rffe a[4: 0 ]: 0 x1e reset source: n/a 7 6 5 4 3 2 1 0 bits mpn7 mpn6 mpn5 mpn4 mpn3 mpn2 mpn1 mpn0 reset 0 0 1 0 1 1 1 0 register rffe: rffe_usid_0x1f address rffe a[4: 0 ]: 0 x1f reset source: nreset_dig or pwr_mode = ?01? (transition through startup mode) 7 6 5 4 3 2 1 0 bits reserved (2) mpn9 (2) mpn8 (2) usid3 (1) usid2 (1) usid1 (1) usid 0 (1) reset 0 0 0 1 w?0 w?1 w?1 w?1 usid = unique slave identifier register (1) usid field can be changed by: ? mipi?rffe broadcast messages when usid field within the register write command is 0b0000 ? mipi?rffe individual messages when usid field within the register write command equal with content of rffe_reg_0x1f[3:0] (2) in the sequence of writing usid field, the upper [7:4] must match the value 0b0001 hard?coded in the rffe register 0x1f note: usid value is not retained during shutdown power mode. note: usid value is not affected by swr bit from rffe_status register dac update
tcc?206 www. onsemi.com 31 following picture shows tcc?206 and all the necessary external components figure 19. tcc?206 with external components c hv vio vdda l_boost vhv tcc?206 i vio i vdda i ind c boost c vio c vreg vreg v batt v io r filt c vdda l boost i batt out a,b,c,d,e,f c daca,b,c,d,e,f table 31. recommended external bom component description nominal value package recommended p/n c boost boost supply capacitor, 10 v 1 f 0402 tdk: c1005x5r1a105k l boost boost inductor 15 h 0603 tdk: vls2010et?150m, sunlord sph201610h150mt r filt filtering resistor, 5% 3.3 s 0402 vishay : crcw04023r30jned c vio v io supply decoupling, 10 v 100 nf 0201 murata: grm033r61a104me15d c avdd v avdd supply decoupling, 10 v 1 f 0402 tdk: c1005x5r1a105k c vreg v vreg supply decoupling, 10 v 220 nf 0201 tdk: c0603x5r1a224m c hv boost tank capacitor, 50 v 47 nf 1005 murata: grm155c71h473ke19 c daca,b,c,d,e,f decoupling capacitor, 50 v (note 8) 100 pf 0201 murata: grm0335c1h101jd01d 8. recommended for noise reduction only ? not essential
tcc?206 www. onsemi.com 32 tape & reel dimensions figure 20. wlcsp carrier tape drawings figure 21. orientation in tape table 32. ordering information device package shipping ? tcc?206a?rt rdl (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. assembly instructions note: it is recommended that under normal circumstances, this device and associated components should be located in a shielded enclosure.
tcc?206 www. onsemi.com 33 package dimensions wlcsp20 2.187x1.987 case 567jv issue b seating plane 0.05 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 d 2.187 bsc e b 0.23 0.29 e 0.40 bsc 0.65 e d a b pin a1 reference e a 0.05 b c 0.03 c 0.08 c 20x b 4 c b a 0.10 c a1 a c 0.17 0.23 1.987 bsc 0.25 20x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.40 0.40 0.05 c 2x top view side view bottom view note 3 e recommended package outline 123 pitch d e pitch a1 e/2 a2 a2 0.38 ref on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 tcc?206/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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