View FEDL9472-02_8325151.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

semiconducto r FEDL9472-02 issue date: feb. 1, 2008 ml9472 static,1/2duty 60 output lcd driver 1/18 general description the ml9472 is a lcd driver which can directly drive up to 60 segments in the static display mode and up to 120 segments in the 1/2 duty dynamic display mode. features ? operating range supply voltage : 3.0 to 5.5 v operating temperature range : ? 40 to ? 105 ? c ? segment output static display mode : up to 60 segments can be displayed. 1/2 duty : up to 120 segments can be displayed. ? simple interface with microcomputer ? built-in common signal generator ? one-to-one correspondence between input data and output data when input data is at ?h? level : display goes on. when input data is at ?l? level : display goes off. ? test pin for all-on (seg_test) and all-off ( blank ) ? can be cascade-connected ? can be synchronized with the external common signal ? applicable as an output expander ? package 80-pin plastic tqfp (tqfp80-p-1212-0.50-k) (product name: ml9472tb)
FEDL9472-02 lapis semiconductor ml9472 2/18 block diagram 60-dot segment driver 60-bit latch (a) 60-bit latch (b) 60 load 60 60 osc 60-stage shift register (a) 60-stage shift register (b) sync circuit 1/4 or 1/8 data_in clock 60 d/s osc_out osc_out osc_in ext/int 1/2 sync v dd gnd seg_test blank 60-ch data selector common driver seg1 seg60 data_out2 data_out1 v lc1 v lc2 com_a com_b com_out
FEDL9472-02 lapis semiconductor ml9472 3/18 pin configuration (top view) 80-pin plastic tqfp
FEDL9472-02 lapis semiconductor ml9472 4/18 pin description symbol type description osc_in osc_out osc_out i o o pins for oscillation. the oscillator circuit is configured by externally connecting two resistors and a capacitor. make the wiring length as short as possible, because the resistor connected to the osc_in pin has a higher value and the circuit is susceptible to external noise. data_in i serial data input pin. the display goes on when input data is at a ?h? level, and it goes off when input data is at a ?l? level. clock i shift clock input pin. data from the data pin is transferred in synchronization with the rising edge of the shift clock. load i load signal input pin. serially input data is transferred to the 60-bit latch at a ?h? level of this load signal, then held at a ?l? level. blank l input pin that turns off all segments. the entire display goes off when a ?l? level is applied to this pin. the display returns to the previous state when a ?h? level is applied. when seg_test pin is at a ?h? level, the input on this pin is disabled. seg_test l input pin is used to test the segment outputs (seg 1 to seg 60 ). all displays are turned on when ?h? is applied to this pin. the display returns to the previous state when a ?l? level is applied. when this pin is at a ?h? level, the input on the blank pin is disabled. d/s l when ?h? is applied to this pin, the m l9472 operates in the 1/2 duty dynamic display mode. when this pin is set at a ?l? level, the ml9472 operates in the static display mode. ext/int i when the external common signal is used, fix this pin at a ?h? level and input the external common signal from the osc_in pin. the input common signal is used as the internal common signal and is output from the com_out pin through the buffer. when the built-in common signal generator is used, fix this pin at a ?l? level. when the ml9472 is used as an output expander, fix this pin at a ?h? level and the osc_in pin at a ?l? level. the output logic can be reversed with respect to the input data by setting osc_in to a ?h? level. sync i/o this pin is an input/output pin which is used when two or more ml9472s are connected in series (cascade connection) in the 1/2 duty dynamic display mode. all of the involved ml9472?s sync pins should be connected by the common line and they should be pulled up with a common resistor, which makes a phase level of all involved ml9472?s com_a and com_b pins equal. when a single ml9472 is used in the dynamic display mode, sync should be pulled up with a resistor. connect this pin to gnd if any of the following conditions is true: - the ml9472 is operated in the static display mode. - the ml9472 is used as an output expander. data_out1 o the 60 th stage data of the shift register is output from this pin. when two or more m l9472s are connected in series (cascade connection) in the static display mode, this pin should be connected to the next ml9472?s data_in pin. data_out2 o the 120 th stage data of the shift register is output from this pin. when two or more ml9472s are connected in series (cascade connection) in the 1/2 duty dynamic display mode, this pin should be connected to the next ml9472?s data_in pin. com_out o when tow or more m l9472s are connected in series (cascade connection), this pin should be connected with all of the slave ml9472?s osc_in pins.
FEDL9472-02 lapis semiconductor ml9472 5/18 symbol type description com_a com_b o o lcd driving common signals is output from these pins. these pins should be connected to the common side of the lcd panel. - in the static display mode a pulse in phase with the com_out is output from both com_a and com_b. in this case, the high level is v dd , and the low level is v lc2 . - in the 1/2 duty dynamic display mode the com_a and com_b output signals are alternately changed within each com_out output cycle, resulting in alternate repetition of select and non-select modes. seg1 to seg60 o display output pins for lcd. theses pins are connected to the segment side of the lcd panel. for the correspondence between the output of these pins and input data, see section, ?data structure?. v lc1 , v lc2 ? bias pins for lcd driver. through these pins, bias voltages for the lcd are externally supplied. in the static display mode, v lc1 should be open. v lc1 = v dd /2 v dd > v lc1 > v lc2 = gnd v dd , gnd ? supply voltage pin and ground pin. note: built-in schmitt circuit is used for all input pins.
FEDL9472-02 lapis semiconductor ml9472 6/18 absolute maximum ratings parameter symbol condition rating unit supply voltage v dd ta = 25 ?c ? 0.3 to 6.5 v input voltage v i ta = 25 ?c ? 0.3 to v dd ? 0.3 v storage temperature t stg ? ? 55 to 150 ?c power dissipation p d ta ? 105 ?c 650 mw i o1 driver outputs ? 2.0 to 2.0 ma output current i o2 logic outputs ? 2.0 to 2.0 ma recommended operating conditions parameter symbol condition range unit supply voltage v dd ? 3 to 5.5 v lcd driving voltage v lcd v dd - v lc2 3 to v dd v clock frequency f cp ? 0.3 to 4 mhz operating temperature ta ? ? 40 to 105 ?c oscillator circuit p a rameter symbol applicable pin condition min. typ. max. unit oscillator resistance r 0 osc_out ? 56 100 220 k ? oscillator capacitance c 0 osc_out film capacitor 0.001 ? 0.047 ? f current limiting resistance r 1 osc_in r 1 ? 10r 0 560 1000 2220 k ? common signal frequency f com com_a com_b ? 25 ? 150 hz note: see section, ?reference data?, for the resistor and capacitor values in the table. example of an oscillator circuit:
FEDL9472-02 lapis semiconductor ml9472 7/18 electrical characteristics dc characteristics (v dd = 3.0 to 5.5 v, ta = ? 40 to ? 105 ? c, unless otherwise specified) parameter symbol applicable pin condition min. max. unit ?h? input voltage v ih ? 0.8 v dd v dd v ?l? input voltage v il ? gnd 0.2 v dd v ?h? input current i ih v i = v dd ? 1 ? a ?l? input current i il seg_test, blank , load, data_in, clock, d/s, ext/int, osc_in v i = 0 v ? 1 ? ? a v oh1 data_out1 data_out2 com_out i o = ? 100 ? a, v dd = 5.0 v 4.5 ? v ?h? output voltage v oh2 osc_out osc_out i o = ? 200 ? a, v dd = 5.0 v 4.5 ? v v ol1 data_out1 data_out2 com_out i o = 100 ? a, v dd = 5.0 v ? 0.5 v v ol2 osc_out osc_out i o = 200 ? a, v dd = 5.0v ? 0.5 v ?l? output voltage v ol3 sync i o = 250 ? a, v dd = 5.0 v ? 0.8 v v och com_a com_b v dd = 5.0 v, v lc1 = 2.5 v, v lc2 = 0 v, i o = ? 150 ? a 4.8 ? v v ocm com_a com_b v dd = 5.0 v, v lc1 = 2.5 v, v lc2 = 0 v, i o = ? 150 ? a 2.3 2.7 v common output voltage v ocl com_a com_b v dd = 5.0 v, v lc1 = 2.5 v, v lc2 = 0 v, i o = 150 ? a ? 0.2 v v osh i o = ? 30 ? a 4.8 ? v segment output voltage v osl seg 1 - seg 60 v dd = 5.0 v, v lc1 = 2.5 v v lc2 =0 v i o = ? 30 ? a ? 0.2 v output leakage current i lo sync v dd = 5.0 v and v o = 5 v when internal tr is off ? 5 ? a segment output impedance r seg seg 1 ? seg 60 v dd = 5.0 v, v lc1 = 2.5v, v lc2 = 0v ? 10 k ? common output impedance r com com_a com_b v dd = 5.0 v, v lc1 = 2.5v, v lc2 = 0v ? 1.5 k ? static supply current i dd1 v dd fix all input levels at either v dd or gnd ? 100 ? a dynamic supply current i dd2 v dd v dd = 5.0v, no load. r 0 = 100 k ? , c 0 = 0.01 ? f, r 1 = 1 m ? ? 0.5 ma
FEDL9472-02 lapis semiconductor ml9472 8/18 ac characteristics (v dd = 3 to 5.5 v, ta = ? 40 to ? 105 ? c, unless otherwise specified) parameter symbol conditi on min. typ. max. unit clock ?h? time t whc ? 70 ? ? ns clock ?l? time t wlc ? 70 ? ? ns data set-up time t ds ? 50 ? ? ns data hold time t dh ? 50 ? ? ns load ?h? time t whl ? 100 ? ? ns clock-to-load time t cl ? 100 ? ? ns load-to-clock time t lc ? 100 ? ? ns ?h?, ?l? propagation delay time t phl t plh load capacitance of data_out1, data_out2: 15 pf ? ? 0.14 ? s clock rise time, fall time t r1 , t f1 ? ? ? 50 ns sync pulse ?l? time t s ? 0.2 ? ? ? s osc_in input frequency f osc ? ? ? 5 khz
FEDL9472-02 lapis semiconductor ml9472 9/18 power-on/off timing * please start up v lc1 after turning on the v dd power supply. or, please start up at the same time. initial signal timing * after vdd is applied, blank and seg_test should be applied to ?l? level to make all segments off until first group of display data is latched. functional description operation description t h e ml9472 consists of a 120-stage shift register, 120-bit data latch, and 60 pairs of lcd drivers. the display data is input from the data_in pin to the 120-stage shift register at the rising edge of the clock pulse and it is shifted to the 120-bit data latch when the load signal is set at ?h? level, then it is directly output from the 60 pairs of lcd drivers to the lcd panel. input the display data in the order of seg60, seg59, seg58, ?, seg2, seg1. v dd blank seg_test low level v dd terminal voltage v lc1 terminal voltage [time] t ? 0 [voltage] t t
FEDL9472-02 lapis semiconductor ml9472 10/18 com_a, com_b in th e select mode, a signal in phase with the com_out signal is output at ?h? (v dd ) and ?l? (vlc2). in the non-select mode a voltage is output at ?m? (v lc1 ). in the select mode of com_a (non-select mode of com_b), signals that correspond to the 1 st -to 60 th -bit data of the data latch are output to the segment outputs. in the select mode of com_b (non-select mode of com_a), signals that correspond to the 61 st - to 120 th -bit data of the data latch are output to the segment outputs. segn truth table m ode display data in latcha display data in latchb coma comb segn ? ?h? ?h? 0 1 ? ?l? ?l? 1 ? ?h? ?h? 1 static 0 ? ?l? ?l? 0 ?h? ?m? 0 ?l? ?m? 1 ?m? ?h? 0 1 1 ?m? ?l? 1 ?h? ?m? 0 ?l? ?m? 1 ?m? ?h? 1 1 0 ?m? ?l? 0 ?h? ?m? 1 ?l? ?m? 0 ?m? ?h? 0 0 1 ?m? ?l? 1 ?h? ?m? 1 ?l? ?m? 0 ?m? ?h? 1 1/2 duty dynamic 0 0 ?m? ?l? 0 *note: ?h? = v dd ; ?m? = v lc1 ; ?l? = v lc2 .
FEDL9472-02 lapis semiconductor ml9472 11/18 seg1-seg60 lc d segmnet driving signals are outputfrom these pins and they should be connected to the segment side of the lcd panel. ?h? level: v dd , ?l? level: v lc2 in the static display mode, the nth bit data of the data latch (a) corresponds to the segn. the data of the data latch (b) is invalid. a signal out of phase with the com_out signal is output to the segment outputs when the display is turned on, while a signal in phase with it is output when the display is turned off. in the 1/2 duty dynamic mode, the output of the segn corresponds to the nth bit data of the data latch (a) when com_a is in select mode and corresponds to the nth bit data of the data latch (b) when com_b is in select mode. when the display is turned on, a signal out of phase with the common signal corresponding to the data is output, while a signal in phase with the common signal is output when the display is turned off.
FEDL9472-02 lapis semiconductor ml9472 12/18 application circuits 1) single ml9472 operation in the static display mode 2) single ml9472 operation in the 1/2 duty dynamic display mode
FEDL9472-02 lapis semiconductor ml9472 13/18 3) cascade connections for ml9472s in the static display mode 4) cascade connections for ml9472s in the 1/2 duty dynamic display mode
FEDL9472-02 lapis semiconductor ml9472 14/18 5) output-expander
FEDL9472-02 lapis semiconductor ml9472 15/18 reference characteristics fcom ? r0,c0 fosc ? vdd,c0 fcom--r0,c0 1 10 100 1000 56 68 82 100 120 150 180 220 r0(k : ) fcom(hz) 0.001uf 0.0022uf 0.0047uf 0.01uf 0.022uf 0.047uf spec_min(25hz) spec_max(150hz) condition:d/s=?l? ext/int=?l? vdd=5v 25qc r1=10r0 theoretical value: fcom=1/8fosc fosc--vdd,c0 385 387 389 391 393 395 2 3 4 5 6 vdd(v) fosc (hz) 0.01uf condition 25qc c0=0.01uf r1=10r0 r1=1m :
FEDL9472-02 lapis semiconductor ml9472 16/18 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to he at in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ( unit: mm )
FEDL9472-02 lapis semiconductor ml9472 17/18 revision history page document no. date previous edition current edition description fedl9472-01 july. 2, 2007 ? ? final edition 1 2 2 block diagram 6 6 power dissipation 794mw 650mw 7 7 segment output impedance condition common output impedance condition 9 9 power-on/off timing 10 10 segn truth table 14 14 output-expander FEDL9472-02 feb. 1,2008 ? 15 reference characteristics
FEDL9472-02 lapis semiconductor ml9472 18/18 notice no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing lapis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the info rmation specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the pr escribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2008 - 2011 lapis semiconductor co., ltd.

▲Up To Search▲

Price & Availability of FEDL9472-02

	To Download FEDL9472-02 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .