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| 70313hk/61913hkim 20090907-s00001 no.a1535-1/24 semiconductor components industries, llc, 2013 july, 2013 http://onsemi.com v er.1.03 lc87f0a08a overview the lc87f0a08a is an 8-bit microcontr oller that, centered around a cpu running at a minimum bus cycle time of 12ns, integrates on a single chip a number of hardware feat ures such as 8k-byte flash rom, 256-byte ram, an on-chip debugger, a sophisticated 16-bit timer/counter, a 16-bit timer/counter, a 16-bit timer with a prescaler, a base timer serving as a realtime clock, an as ynchronous/synchronous si o interface, a 12-b it 8-channel ad converter with 12-/8-bit resolution selector, a 20 ? amplifier, constant-voltage detect interr upt, a comparator, a system clock frequency divider, an internal reset circuit, and a 16-source 9-vector interrupt feature. features ? flash rom ?? 8192 ?? 8 bits ?? capable of on-board programming with a wide range of supply voltage 2.7 to 5.5v ?? block-erasable in 128-byte units ?? writes data in 2-byte units ? ram ?? 256 ? 9 bits ? package form ?? qfp36 (7 ? 7): lead-free and halogen-free type orderin g numbe r : ena1535a cmos lsi 8-bit microcontroller 8k-byte flash rom / 256-byte ram / 36-pin ordering information see detailed ordering and shipping informa tion on page 24 of this data sheet. * this product is licensed from silicon storage technology, inc. (usa). 0.1 1.7max 0.3 0.65 (0.9) (1.5) qfp36(7x7) 19 10 18 19 27 28 36 9.0 0.5 7.0 9.0 7.0 0.15
lc87f0a08a no.a1535-2/24 ? minimum bus cycle time ?? 125ns (8mhz at v dd =2.5v to 5.5v) ?? 250ns (4mhz at v dd =2.5v to 5.5v) note: the bus cycle time here refers to the rom read speed. ? minimum instruction cycle time (tcyc) ?? 375ns (8mhz v dd =2.5v to 5.5v) ? 750ns (4mhz v dd =2.5v to 5.5v) ? ports ? normal withstand voltage i/o ports whose i/o direction specifiable in 1-bit units: 28 (p0n, p1n, p2n, p30 to p32, p70) ?? oscillation/input dedicated ports: 2 (cf1/xt1, cf2/xt2) ?? external reset pins: 1 ( res ) ?? power supply pins: 4 (v ss 1, av ss , v dd 1, v dd 2) ?? reference voltage outputs: 1 (vref) ? timers ?? timer 0: 16-bit timer/counter with a capture register. mode 0: 8-bit timer with an 8-bit programmab le prescaler (with an 8-bit capture register) ? 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programma ble prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ?? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescaler (with t oggle outputs) + 8-bit timer/counter with an 8- bit prescaler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler ? 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (lower-order 8 bits may be used as pwm outputs) ?? timer a: 16-bit timer mode 0: 8-bit timer with an 8-bit programmable prescaler ? 2 channels mode 1: 16-bit timer with an 8-bit programmable prescaler ?? base timer 1) the input clock is selectable from the subclock (32. 768khz crystal oscillation), low-speed rc oscillator clock, system clock, and timer 0 prescaler output. (release of the x'tal hold mode is enabled when the s ubclock or low-speed rc oscillator clock is selected.) 2) provided with an 8-bit programmable prescaler. 3) interrupts programmable in 5 different time schemes. ? sio ?? sio1: 8-bit asynchronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? ad converter ?? ad converter input port with a 20 ? operational amplifier (1 channel) ?? ad converter input ports (8 channels) 12/8 bits ad converter resolution selectable ? constant voltage detection interrupt (cvd) function 1) detects v dd voltage fluctuations and generates an interrupt request. 2) the cvd detection level can be selected from 12 levels (2.6v, 2.8v, 3.0v, 3.2v, 3.4v, 3.6v, 3.8v, 4.0v, 4.2v, 4.4v, 4.6v, and 4.8v) through a register. lc87f0a08a no.a1535-3/24 ? comparator comparator input pin (1 channel) comparator output pin (1 channel) comparator output set high when (comparator input level) < 1.22v comparator output set low when (comparator input level) > 1.22v ? clock output function ?? generates clocks with a clock rate of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source oscillation clock that is selected as the system clock. ? watchdog timer ?? generates an internal reset on an overflow occurring in the timer running on the low-speed rc oscillator clock (approx. 30khz) or subclock. ?? operating mode at standby is selectable from 3 modes (continue counting/suspend operation/suspend counting with the count value retained) ? interrupts ?? 16 sources, 9 vectors 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than th e current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address is given priority. no. vector address level interrupt source 1 00003h x or l int0/cvd 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4/tal 4 0001bh h or l int3/bt 5 00023h h or l t0h/tah 6 0002bh h or l t1l/t1h 7 00033h h or l 8 0003bh h or l sio1 9 00043h h or l adc 10 0004bh h or l p0 ?? priority levels x > h > l ?? when interrupts of the same level occur at the same time, an interrupt with a smaller vector address is given priority. ? subroutine stack levels: up to 128levels (the stack is allocated in ram.) ? high-speed multiplication/division instructions ?? 16 bits ? 8 bits (5 tcyc execution time) ?? 24 bits ? 16 bits (12 tcyc execution time) ?? 16 bits ? 8 bits (8 tcyc execution time) ?? 24 bits ? 16 bits (12 tcyc execution time) ? oscillation circuits ?? internal oscillation circuits 1) low-speed rc oscillation circuit: for system clock (approx.30khz) 2) medium-speed rc oscillation circuit: for system clock (1mhz) 3) hi-speed rc oscillation circuit: for system clock (8mhz) ? ? system clock divider function ?? can run on low consumption current. ?? minimum instruction cycle select able from 375ns, 750ns, 1.5 ? s, 3.0 ? s, 6.0 ? s, 12.0 ? s, 24.0 ? s, 48.0 ? s, and 96.0 ? s (at 8mhz main clock) lc87f0a08a no.a1535-4/24 ? internal reset circuit ?? power-on reset (por) function 1) por reset is generated only at power-on time. 2) the por release level can be selected from 8 levels (1.67v, 1.97v, 2.07v, 2.37v, 2.57v, 2.87v, 3.86v, and 4.35v) through option configuration. ?? low-voltage detection reset (lvd) function 1) lvd and por functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) the use/disuse of the lvd function and the low voltage threshold level can be selected from 7 levels (1.91v, 2.01v, 2.31v, 2.51v, 2.81v, 3.79v and 4.28v). through option configuration. ? standby function ?? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are three ways of resetting the halt mode. (1) setting the reset pin to the low level (2) having the watchdog timer or lvd function generate a reset (3) having an interrupt generated ?? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the cf, rc and crystal oscillators automatically stop operation. note: the low-speed rc oscillator is controlled directly by the watchdog timer; its oscillation in the standby mode is also controlled by the watchdog timer. 2) there are five ways of resetting the hold mode: (1) setting the reset pin to the lower level (2) having the watchdog timer or lvd function generate a reset (3) having an interrupt source established at one of the int0, int1, int2 and int4 pins * int0 and int1 can be used in the level sense mode only. (4) having an interrupt source established at port 0. (5) having an interrupt source established in the cvd circuit ?? x'tal hold mode: suspends instruction execution and the opera tion of the peripheral circu its except the base timer. (when x?tal oscillation or low-speed rc oscillation is selected). 1) the cf, low-speed, and medium-speed rc oscillators automatically stop operation. note: the low-speed rc oscillator is controlled directly by the watchdog timer; its oscillation in the standby mode is also controlled by the watchdog timer. note: if the base timer is run with low-speed rc oscillation selected as the base timer input clock source and the x?tal hold mode is entered, the lo w-speed rc oscillator retains the state that is established when the x?tal hold mode is entered. 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are six ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) having the watchdog timer or lvd function generate a reset (3) having an interrupt source established at one of the int0, int1, int2, and int4 pins * int0 and int1 can be used in the level sense mode only. (4) having an interrupt source established at port 0 (5) having an interrupt source established in the base timer circuit (6) having an interrupt source established in the cvd circuit ? on-chip debugger function ?? supports software debugging with the ic mounted on the target board. ?? provides 1 channel of on-chip debugger pin. dbgp0 (p0) ? data security function ?? protects the program data stored in flash memory from unauthorized read or copy. note: this data security function does not necessarily provide absolute data security. lc87f0a08a no.a1535-5/24 ? development tools ? on-chip debugger: tcb87 type b + lc87f0a08a or tcb87 type c (3-wire in terface cable) + lc87f0a08a ? programming board package programming board qfp36(7 ? 7) w87f0aq ? flash rom programmer vendor model supported version device flash support group, inc. (fsg) single af9709/af9709b/af9709c (including ando electric co., ltd. models) rev .02. xx or later lc87f0a08a gang af9723/af9723b(main body) (including ando electric co., ltd. models) - - af9833(unit) (including ando electric co., ltd. models) - - flash support group, inc. + our company (note 1) onboard single/gang af9101/af9103(main body) (fsg) (note 2) lc87f0a08a sib87(interface driver) (our company model) our company single/gang skk/skk type b (sanyo fws) application version 1.16 or later chip data version 2.13 or later lc87f0a08a onboard single/gang skk-dbg type b (sanyo fws) note1: pc-less standalone onboard programming is possible using the fsg onboard programmer (af9101/af9103) and the serial interface driver (sib87 ) provided by our company in pair. note2: dedicated programming device and program are required depending on the programming conditions. contact our company or fsg if you have any questions or difficulties regarding this matter. package dimensions unit : mm (typ) 3162c 0.1 1.7max 0.3 0.65 (0.9) (1.5) sanyo : qfp36(7x7) 19 10 18 19 27 28 36 9.0 0.5 7.0 9.0 7.0 0.15 lc87f0a08a no.a1535-6/24 pin assignment qfp36 (7 ? 7) ?lead-free and halogen-free type? qfp36 name qfp36 name 1 p27 19 av ss 2 p70/int0/t0lcp 20 vref 3 res 21 p00/an0 4 v ss 1 22 p01/an1 5 cf1/xt1 23 p02/an2/cpim 6 cf2/xt2 24 p03/an3 7 v dd 1 25 p04/an4 8 p10/so1 26 p05/cko/dbgp00 9 p11/si1/sb1 27 p06/dbgp01 10 p12/sck1 28 p07/dbgp02 11 p13/int4/t1in 29 v dd 2 12 p14/int4/t1in 30 p20 13 p15/int3/t0in/an5 31 p21 14 p16/t1pwml/int2/t0in/cpout 32 p22 15 p17/t1pwmh/buz/int1/t0hcp 33 p23 16 p30/an6 34 p24 17 p31/an7 35 p25 18 p32/an8 36 p26 p06/dbgp01 p05/cko/dbgp00 p04/an4 p03/an3 p02/an2/cpim p01/apip p00/apim vref av ss p27 p70/int0/t0lcp/an9 res v ss 1 cf1/xt1 cf2/xt2 v dd 1 p10/so1 p11/si1/sb1 1 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 p07/dbgp02 v dd 2 p20 p21 p22 p23 p24 p25 p26 18 17 16 15 14 13 12 11 10 p32/an8 p31/an7 p30/an6 p17/t1pwmh/buz/int1/t0hcp p16/t1pwml/int2/t0in/cpout p15/int3/t0in/an5 p14/int4/t1in p13/int4/t1in p12/sck1 28 29 30 31 32 33 34 35 36 lc87f0a08a to p view lc87f0a08a no.a1535-7/24 system block diagram interrupt control standby control ir pla flash rom pc bus interface port 0 port 1 timer 0 timer 1 port 2 adc int0-int4 (int3 with noise filter) acc b register c register psw rar ram stack pointer alu timer a reset circuit (lvd/por) wdt (low-speed rc) reset control res on-chip debugger 20x amplifier (1 channel) vref + - sio 1 base timer comparator port 3 port 7 clock generator medium- speed rc high-spee d rc low-spee d rc cf/xt cvd lc87f0a08a no.a1535-8/24 pin description pin name i/o description option v ss 1 - - power supply pin no v dd 1 - + power supply pin no v dd 2 - + power supply pin no av ss - - power supply pin no vref o reference voltage output no port 0 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units. ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p00 (an0), p01 (an1): ad converter input port with 20x operational amplifier p02: ad converter input port (a n2)/comparator input (cpim) p03: ad converter input port (an3) p04: ad converter input port (an4) p05: system clock output/on-chip debugger pin (dbgp00) p06: on-chip debugger pin (dbgp01) p07: on-chip debugger pin (dbgp02) yes p00 to p07 port 1 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units. ? pull-up resistors can be turned on and off in 1-bit units. ? current controllable in 1-bit units. 5ma (default), 10ma, 15ma, no current control ? pin functions p10: sio1 data output p11: sio1 data in put/bus input/output p12: sio1 clock input/output p13, p14: int4 input/hold release input/timer 1 event input/timer 0l capture input/ timer 0h capture input p15: int3 input(with noise filter)/timer 0 event input/timer 0h capture input/ ad converter input port (an5) p16: timer 1 pwml output/int2 input/hold release input/timer 0 event input/ timer 0l capture input/comparator output (cpout) p17: timer 1 pwmh output/beeper output/int1 inpu t/hold release input/timer 0h capture input interrupt acknowledge type p10, p11 options not available p12 to p17 options available p10 to p17 rising falling rising & falling h level l level int1 int2 int3 int4 enable enable enable enable enable enable enable enable disable enable enable enable enable disable disable disable enable disable disable disable port 2 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units. ? pull-up resistors can be turned on and off in 1-bit units. ? current controllable in 1-bit units. 5ma (default), 10ma, 15ma, no current control yes port 3 i/o ? 3-bit i/o port ? i/o specifiable in 1-bit units. ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p30: ad converter input port (an6) p31: ad converter input port (an7) p32: ad converter input port (an8) yes continued on next page. lc87f0a08a no.a1535-9/24 continued from preceding page. pin name i/o description option port 7 i/o ? 1-bit i/o port ? i/o specifiable ? pull-up resistors can be turned on and off. ? pin functions p70 : int0 input/hold release input/timer 0l capture input/ad converter input port (an9) interrupt acknowledge type no p70 rising falling rising & falling h level l level int0 enable enable disable enable enable res i/o external reset input/internal reset output pin no cf1/xt1 i ? ceramic oscillator/32.768khz crystal oscillator input pin ? pin functions general-purpose input port no cf2/xt2 i/o ? ceramic oscillator/32.768khz crystal oscillator output pin ? pin functions general-purpose input port no port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor p00 to p07 1 bit 1 cmos programmable 2 nch-open drain programmable p10 to p11 - no cmos programmable p12 to p177 1 bit 1 cmos programmable 2 nch-open drain programmable p20 to p27 1 bit 1 cmos programmable 2 nch-open drain programmable p30 to p32 1 bit 1 cmos programmable 2 nch-open drain programmable p70 - no nch-open drain programmable lc87f0a08a no.a1535-10/24 absolute maximum ratings at ta = 25 ? c, v ss 1 = v ss 2 =0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit maximum supply voltage v dd max v dd 1=v dd 2 -0.3 +6.5 v input voltage v i cf1, cf2 -0.3 v dd +0.3 input/output voltage v io ports 0, 1, 2 ports 3, 7 -0.3 v dd +0.3 high level output current peak output current ioph(1) ports 0, 3 cmos output type selected per 1 applicable pin -10 ma ioph(2) ports 1, 2 cmos output type selected per 1 applicable pin -20 average output current (note 1-1) iomh(1) ports 0, 3 cmos output type selected per 1 applicable pin -7.5 iomh(2) ports 1, 2 cmos output type selected per 1 applicable pin -15 total output current ? ioah(1) ports 0, 1, 3 tota l current of all applicable pins -30 ? ioah(2) port 2 total cu rrent of all applicable pins -30 ? ioah(3) ports 0, 1, 2, 3 to tal current of all applicable pins -50 low level output current peak output current iopl(1) ports 0, 3 per 1 applicable pin 20 iopl(2) ports 1, 2 per 1 applicable pin 20 iopl(3) port 7 per 1 applicable pin 10 average output current (note 1-1) ioml(1) ports 0, 3 per 1 applicable pin 15 ioml(2) ports 1, 2 per 1 applicable pin 15 ioml(3) port 7 per 1 applicable pin 7.5 total output current ? ioal(1) ports 0, 1, 2, 3, 7 total current of all applicable pins 80 allowable power dissipation pd max (1) qfp36 ta=-40 to +85 ? c package alone mw pd max (2) ta=-40 to +85 ? c mounted on thermal resistance test board (note 1-2) operating ambient temperature topr -40 +85 ? c storage ambient temperature tstg -55 +125 note 1-1: the average output current is an average of current values measured over 100ms intervals. note 1-2: thermal resistance test board used conforms to semi (size: 76.1114.31.6tmm, glass epoxy board). lc87f0a08a no.a1535-11/24 allowable operating conditions at ta = -40 ? c to +85 ? c, v ss 1 = v ss 2 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit operating supply voltage (note 2-1) v dd (1) v dd 1=v dd 2 0.367 ? s ? tcyc ? 200 ? s 2.5 5.5 v v dd (2) 0.735 ? s ? tcyc ? 200 ? s 2.5 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2 ram and register contents sustained in hold mode 2.0 high level input voltage v ih (1) ports 0, 1, 2, 3 p70 2.5 to 5.5 0.3v dd +0.7 v dd v ih (4) cf1, res 2.5 to 5.5 0.75v dd v dd low level input voltage v il (1) ports 1, 2, 3 p70 4.0 to 5.5 v ss 0.1v dd +0.4 2.5 to 4.0 v ss 0.2v dd v il (4) cf1, res 2.5 to 5.5 v ss 0.25v dd instruction cycle time (note 2-1) tcyc (note 2-2) 2.7 to 5.5 0.245 200 ? s 2.5 to 5.5 0.367 200 2.5 to 5.5 0.735 200 external system clock frequency fexcf cf1 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty=50 ? 5% 2.7 to 5.5 0.1 12 mhz 2.5 to 5.5 0.1 8 oscillation frequency range (note 2-3) fmcf(1) cf1, cf2 8mhz ceramic oscillation see fig. 1. 2.5 to 5.5 8 mhz fmcf(2) cf1, cf2 4mhz ceramic oscillation see fig. 1. 2.5 to 5.5 4 fmmrc 1/2 of high-speed rc oscillation frequency (rcctd=0) (note 2-4) 2.5 to 5.5 7.44 8.0 8.56 fmrc internal medium-speed rc oscillation 2.5 to 5.5 0.5 1.0 2.0 fmsrc internal low-speed rc oscillation 2.5 to 5.5 15 30 60 khz fsx?tal xt1, xt2 32.768khz crystal oscillation see fig. 2. 2.5 to 5.5 32.768 note 2-1: v dd must be held greater than or equal to 2.7v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see tables 1 and 2 for the oscillation constants. note 2-4: an oscillation stabilization time of 100 ? s or longer must be provided be fore switching the system clock source after the state of the high-speed rc oscillati on circuit is switched from ?oscillation stopped? to ?oscillation enabled? . lc87f0a08a no.a1535-12/24 electrical characteristics at ta = -40 ? c to +85 ? c, v ss 1 = v ss 2 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high level input current i ih (1) ports 0, 1, 2, 3 port 7, res output disabled pull-up resistor off v in =v dd (including output tr?s off leakage current) 2.5 to 5.5 1 ? a i ih (2) cf1 v in =v dd 2.5 to 5.5 15 low level input current i il (1) ports 0, 1, 2, 3 port 7, res output disabled pull-up resistor off v in =v ss (including output tr?s off leakage current) 2.5 to 5.5 -1 i il (2) cf1 v in =v ss 2.5 to 5.5 -15 high level output voltage v oh (1) ports 0, 3 i oh =-1ma 4.5 to 5.5 v dd -1 v v oh (2) i oh =-0.2ma 2.5 to 5.5 v dd -0.4 v oh (3) ports 1, 2 i oh =-6ma 4.5 to 5.5 v dd -1 v oh (4) i oh =-1.0ma 2.5 to 5.5 v dd -0.4 low level output voltage v ol (1) ports 0, 1, 2, 3 i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.0ma 2.5 to 5.5 0.4 v ol (3) p70 i ol =8ma 4.5 to 5.5 1.5 v ol (4) i ol =1.0ma 2.5 to 5.5 0.4 constant current operation enabled pin voltage vocc ports 1, 2 2.5 to 5.5 1 v dd -1.0 v constant current port current (5ma setting) iled(1) ports 1, 2 per 1 applicable pin only on time v o =1.0 to (v dd -1.0) 2.7 to 5.5 4 5 6 ma iled(2) 2.5 to 2.7 3 5 6 constant current port current (10ma setting) iled(3) 2.7 to 5.5 8 10 12 iled(4) 2.5 to 2.7 6 10 12 constant current port current (15ma setting) iled(5) 2.7 to 5.5 led(1)+led(3) iled(6) 2.5 to 2.7 led(2)+led(4) pull-up resistance rpu(1) ports 0, 1, 2, 3 port 7 v oh =0.9v dd 4.5 to 5.5 15 35 80 k ? rpu(2) 2.5 to 4.5 18 50 230 hysteresis voltage vhys(1) ports 0, 1, 2, 3 p70 res 2.5 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than that under test v in =v ss f=1mhz ta=25 ? c 2.5 to 5.5 10 pf lc87f0a08a no.a1535-13/24 sio1 serial i/o char acteristics (note 4-1) parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(1) sck1(p12) ? see fig. 5. 2.5 to 5.5 2 tcyc low level pulse width tsckl(1) 1 high level pulse width tsckh(1) 1 output clock frequency tsck(2) sck1(p12) ? cmos output type selected ? see fig. 5. 2.5 to 5.5 2 low level pulse width tsckl(2) 1/2 tsck high level pulse width tsckh(2) 1/2 serial input data setup time tsdi(1) si1(p11), sb1(p11) ? specified with respect to rising edge of sioclk. ? see fig. 5. 2.5 to 5.5 0.05 ? s data hold time thdi(1) 0.05 serial output output delay time tddo(1) so1(p10), sb1(p11) ? specified with respect to falling edge of sioclk ? specified as the time up to the beginning of output change in open drain output mode. ? see fig. 5. 2.5 to 5.5 (1/3)tcyc +0.08 note 4-1: these specifications are theoretical values. margins must be allowed according to the actual operating conditions. pulse input conditions at ta = -40 ? c to +85 ? c, v ss 1 = v ss 2 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high/low level pulse width tpih(1) tpil(1) int0(p70), int1(p71), int2(p16), int4(p13, p14) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.5 to 5.5 1 tcyc tpih(2) tpil(2) int3(p15) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.5 to 5.5 2 tpih(3) tpil(3) int3(p15) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.5 to 5.5 64 tpih(4) tpil(4) int3(p15) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.5 to 5.5 256 tpil(5) res ? resetting is enabled. 2.5 to 5.5 200 ? s lc87f0a08a no.a1535-14/24 ad converter characteristics at v ss 1 = av ss = 0v <12bits ad converter mode/ta = -40 ? c to +85 ? c > parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an2(p02) an3(p03) an4(p04) an5(p15) an6(p30) an7(p31) an8(p32) an9(p70) (note 6-3) 3.0 to 5.5 12 bit absolute accuracy et (note 6-1) 3.0 to 5.5 ? 16 lsb conversion time tcad ? see conversion time calculation method. (note 6-2) 4.0 to 5.5 32 115 ? s 3.0 to 5.5 64 115 analog input voltage range vain 3.0 to 5.5 v ss vref v analog port input current iainh vain=v dd 3.0 to 5.5 1 ? a iainl vain=v ss 3.0 to 5.5 -1 <8bits ad converter mode/ta = -40 ? c to +85 ? c > parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an2(p02) an3(p03) an4(p04) an5(p15) an6(p30) an7(p31) an8(p32) an9(p70) (note 6-3) 3.0 to 5.5 8 bit absolute accuracy et (note 6-1) 3.0 to 5.5 ? 1.5 lsb conversion time tcad ? see ?conversion time calculation method?. (note 6-2) 4.0 to 5.5 20 90 ? s 3.0 to 5.5 40 90 analog input voltage range vain 3.0 to 5.5 v ss vref v analog port input current iainh vain=v dd 3.0 to 5.5 1 ? a iainl vain=v ss 3.0 to 5.5 -1 lc87f0a08a no.a1535-15/24 reference voltage generator ci rcuit (vref) characteristics at ta = -40 ? c to +85 ? c, v ss 1 = av ss = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit vref voltage accuracy vrefvo vref (note 7-2) ? ta=-40 to +85 ? c 2.5 to 4.0 v dd -0.1 v dd v 4.0 to 5.5 3.92 4.00 4.08 ? ta=-40 to +60 ? c 4.5 to 5.5 3.96 4.04 vref output current vrefio ? ta=-40 to +85 ? c 2.5 to 5.5 v ss 1ma operation stabilization time (note 7-1) tvrefw 2.5 to 5.5 10 ? s note 7-1: refers to the interval between the time vronz is set to 0 and the time operation gets stabilized. note 7-2: an external 4.7 ? f capacitor must be connected to the vref pin to stabilize the vref voltage. 20x amplifier characteristics at ta = -40 ? c to +85 ? c, v ss 1 = av ss = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit amplifier gain apgain see fig. 7. p00/apim p01/apip ? ta=-40 to +85 ? c ? vref=4.0v ? p01=0v, p00 ? 0v or p00=0v, p01 ? 0v 5.0 20 operation stabilization time (note 8-1) tapw 1.0 ? s amplifier input voltage full scale (note 8-1) vapful 0.16 0.19 v amplifier input voltage range vapim p00/apim p01/apip=0v -vapful 0 vapip p01/apip p00/apim=0v 0 vapful amplifier input port input current iapinl p00/apim p00/apim=v ss -0.2v -1 ? a iapinh p01/apip p01/apip=v dd 1 note 8-1: refers to the interval between the time apon is set to 1 and the time operation gets stabilized. comparator characteristics at ta = -40 ? c to +85 ? c, v ss 1 = av ss = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit comparator threshold voltage (note 9-1) vcmvt p02/cpim 2.5 to 5.5 1.12 1.22 1.32 v common mode input voltage range vcmin 2.5 to 5.5 v ss v dd -1.5 v offset voltage voff ? within common mode input voltage range 2.5 to 5.5 10 30 mv response time trt ? within common mode input voltage range ? input amplitude=100mv ? overdrive=50mv 2.5 to 5.5 200 600 ns operation stabilization time (note 9-2) tcmw 2.5 to 5.5 1.0 ? s note 9-1: comparator output=high le vel when (p02/cpim voltage) < vcmvt comparator output=low level when (p02/cpim voltage) > (vcmvt +voff) note 9-2: refers to the interval between the time cponz is set to 0 and the time operation gets stabilized. lc87f0a08a no.a1535-16/24 power-on reset (por) characteristics at ta = -40 ? c to +85 ? c, v ss 1 = av ss = 0v parameter symbol pin / remarks conditions specification option selected voltage min typ max unit por release voltage porrl option selected (note 10-1) 1.67v 1.55 1.67 1.79 v 1.97v 1.85 1.97 2.09 2.07v 1.95 2.07 2.19 2.37v 2.25 2.37 2.49 2.57v 2.45 2.57 2.69 2.87v 2.75 2.87 2.99 3.86v 3.73 3.86 3.99 4.35v 4.21 4.35 4.49 detection voltage unpredictable area pouks see fig. 8. (note 10-2) 0.7 0.95 power supply rise time poris power startup time from v dd =0v to 1.6v 100 ms note 10-1: the por release voltage can be selected from 8 le vels when the low-voltage detection feature is deselected. note 10-2: there is an unpred ictable area before the transistor starts to turn on. low-voltage detection (lvd) reset characteristics at ta = -40 ? c to +85 ? c, v ss 1 = av ss = 0v parameter symbol pin/remarks conditions specification option selected voltage min typ max unit lvd reset voltage (note 11-2) lvdet option selected see fig. 9. (note 11-1) (note 11-3) 1.91v 1.81 1.91 2.01 v 2.01v 1.91 2.01 2.11 2.31v 2.21 2.31 2.41 2.51v 2.41 2.51 2.61 2.81v 2.71 2.81 2.91 3.79v 3.69 3.79 3.89 4.28v 4.18 4.28 4.38 lvd voltage hysteresis lvhys 1.91v 55 mv 2.01v 55 2.31v 55 2.51v 55 2.81v 60 3.79v 65 4.28v 65 detection voltage unpredictable area lvuks see fig. 9. (note 11-4) 0.7 0.95 v minimum low voltage detection width (response sensitivity) tlvdw lvdet-0.5v see fig. 10. 0.2 ms note 11-1: the lvd reset voltage can be selected from 7 le vels when the low-voltage detection feature is selected. note 11-2: the hysteresis voltage is not included in the lvd reset voltage specification value. note 11-3: there are cases when the lvd reset voltage specification value is exceeded when a greater change in the output level or large current is applied to the port. note 11-4: there is an unpr edictable area before the transistor starts to turn on. lc87f0a08a no.a1535-17/24 constant voltage detection (c vd) interrupt characteristics at ta = -40 to +85 ? c, v ss 1 = av ss = 0v parameter symbol pin/remarks conditions specification register selected voltage min typ max unit cvd detection voltage (note 12-2) cvdet register selected (note 12-1) (note 12-3) 2.6v 2.5 2.6 2.7 v 2.8v 2.7 2.8 2.9 3.0v 2.9 3.0 3.1 3.2v 3.1 3.2 3.4 3.4v 3.3 3.4 3.6 3.6v 3.5 3.6 3.8 3.8v 3.7 3.8 4.0 4.0v 3.9 4.0 4.2 4.2v 4.1 4.2 4.4 4.4v 4.3 4.4 4.6 4.6v 4.5 4.6 4.8 4.8v 4.7 4.8 5.0 cvd detection voltage hysteresis cvhys 2.6v 50 mv 2.8v 50 3.0v 50 3.2v 50 3.4v 50 3.6v 50 3.8v 50 4.0v 50 4.2v 50 4.4v 50 4.6v 50 4.8v 55 detection voltage unpredictable area cvuks (note 12-4) 0.7 0.95 v minimum cvd detection width (response sensitivity) tcvdw cvdet-0.5v 0.8 ms operation stabilization time (note 12-5) tcvdon v dd =2.5 to 5.5v 100 ? s note 12-1: the cvd detection voltage can be selected from 16 levels. note 12-2: the hysteresis voltage is not included in the cvd detection voltage specification value. note 12-3: there are cases wh en the cvd detection voltage specification valu e is exceeded when a greater change in the output level or large current is applied to the port. note 12-4: there is an unpredictable period before the cvd-related transistor starts to turn on. note 12-5: refers to the interval between the time cvdrun is set to 1 and the time operation gets stabilized. lc87f0a08a no.a1535-18/24 consumption current characteristics at ta = -40 ? c to +85 ? c, v ss 1 = v ss 2 = 0v parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit normal mode consumption current (note 13-1) (note 13-2) iddop(1) v dd 1 =v dd 2 ? fmcf=8mhz ceramic oscillation mode ? system clock set to 8mhz mode ? internal low-/medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/1 4.5 to 5.5 5.5 11.3 ma 2.5 to 4.5 3.4 9.0 iddop(2) ? fmcf=4mhz ceramic oscillation mode ? system clock set to 4mhz mode ? internal low-/medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/1 4.5 to 5.5 2.8 6.8 2.5 to 4.5 2.1 5.4 iddop(3) ? fsx?tal=32.768khz crystal oscillation mode ? internal low-speed rc oscillation stopped ? system clock set to internal medium-speed rc oscillation mode ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/2 4.5 to 5.5 0.6 1.9 2.5 to 4.5 0.3 1.4 iddop(4) ? fsx?tal=32.768khz crystal oscillation mode ? internal low-/medium-speed rc oscillation stopped ? system clock set to internal high-speed rc oscillation mode ? frequency division ratio set to 1/1 4.5 to 5.5 5.0 9.9 2.5 to 4.5 3.5 8.6 iddop(5) ? external oscillation fsx?tal/fmcf stopped ? system clock set to internal low-speed rc oscillation mode ? internal medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/1 4.5 to 5.5 21.3 89.4 ? a 2.5 to 4.5 13.6 64.8 iddop(6) ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz mode ? internal low-/medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/2 4.5 to 5.5 22.8 101.5 2.5 to 4.5 10.9 70.0 halt mode consumption current (note 13-1) (note 13-2) iddhalt(1) v dd 1 =v dd 2 halt mode ? fmcf=8mhz ceramic oscillation mode ? system clock set to 8mhz mode ? internal low-/medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/1 4.5 to 5.5 2.0 3.2 ma 2.5 to 4.5 1.0 2.3 iddhalt(2) halt mode ? fmcf=4mhz ceramic oscillation mode ? system clock set to 4mhz mode ? internal low-/medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/1 4.5 to 5.5 1.3 2.2 2.5 to 4.5 0.6 1.5 iddhalt(3) halt mode ? fsx?tal=32.768khz crystal oscillation mode ? internal low-speed rc oscillation stopped ? system clock set to internal medium-speed rc oscillation mode ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/2 4.5 to 5.5 0.3 1.2 2.5 to 4.5 0.2 0.8 note 13-1: the consumption current value includes none of the currents that flow into the output transistors and internal pull-up resistors. note 13-2: unless otherwise specified, the consumption current for the lvd circuit is not included. continued on next page. lc87f0a08a no.a1535-19/24 continued from preceding page. parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit halt mode consumption current (note 13-1) (note 13-2) iddhalt(4) v dd 1 =v dd 2 halt mode ? fsx?tal=32.768khz crystal oscillation mode ? internal low-/medium-speed rc oscillation stopped ? system clock set to internal high-speed rc oscillation mode ? frequency division ratio set to 1/1 4.5 to 5.5 1.6 2.2 2.5 to 4.5 1.1 1.8 iddhalt(5) halt mode ? external oscillation fsx?tal/fmcf stopped ? system clock set to internal low-speed rc oscillation mode ? internal medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/1 4.5 to 5.5 5.6 43 ? a 2.5 to 4.5 3.3 30.4 iddhalt(6) halt mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz mode ? internal low-/medium-speed rc oscillation stopped ? internal high-speed rc oscillation stopped ? frequency division ratio set to 1/2 4.5 to 5.5 12.0 69.8 2.5 to 4.5 4.4 44.7 hold mode consumption current (note 13-1) (note 13-2) iddhold(1) v dd 1 =v dd 2 hold mode 4.5 to 5.5 0.024 41.0 ? a 2.5 to 4.5 0.010 27.2 iddhold(2) hold mode ? lvd option selected 4.5 to 5.5 2.9 30.2 2.5 to 4.5 2.3 22.3 timer hold mode consumption current (note 13-1) (note 13-2) iddhold(3) v dd 1 =v dd 2 timer hold mode ? fsx?tal=32.768khz crystal oscillation mode 4.5 to 5.5 9.9 63.2 2.5 to 4.5 3.2 39.6 iddhold(4) timer hold mode ? fmsrc=30khz internal low-speed rc oscillation mode 4.5 to 5.5 2.1 31.6 2.5 to 4.5 1.2 8.4 iddhold(5) timer hold mode ? fmsrc=30khz internal low-speed rc oscillation mode cvd active mode 4.5 to 5.5 29.3 110.2 2.5 to 4.5 20.1 86.3 note 13-1: the consumption current value includes none of the currents that flow into the output transistors and internal pull-up resistors. note 13-2: unless otherwise specified, the consumption current for the lvd circuit is not included. f-rom programming characteristics at ta = +10 ? c to +55 ? c, v ss 1 = av ss = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? excluding power dissipation in the microcontroller block 2.7 to 5.5 5 10 ma programming time tfw(1) ? erase mode 2.7 to 5.5 20 30 ms tfw(2) ? programming mode 40 60 ? s lc87f0a08a no.a1535-20/24 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator ? murata manufacturing co., ltd. nominal frequency type oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rf [ ? ] rd [ ? ] typ [ms] max [ms] 4mhz smd cstcr4m00g53-r0 (10) ( 10) open 3.3k 2.5 to 5.5 0.03 c1 and c2 integrated type 8mhz smd cstce8m00g52-r0 (10) ( 10) open 1.5k 2.5 to 5.5 0.02 characteristics of a sample subs ystem clock oscillation circuit given below are the characteristics of a sample subsyste m clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cloc k oscillator circuit that uses a crystal oscillator ? epson toyocom nominal frequency type oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rf [ ? ] rd [ ? ] typ [ms] max [ms] 32.768khz smd mc-306 7 7 open 330k 2.5 to 5.5 0.85 cl value applied: 7pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized in the following cases (see figure 3): ? till the oscillation gets stabilized after the instruction for starting the subclock oscillation circuit is executed ? till the oscillation gets stabilized after the hold mode is released. note: the components that are involved in oscillation should be placed as close to the ic and to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf/xt oscillator circuit figure 2 ac timing measurement point 0.5v dd rf rd cf1/xt1 cf2/xt2 c2 cf/x?tal c1 lc87f0a08a no.a1535-21/24 reset time and oscillation stabilization time hold release signal and oscillation stabilization time note: when an external oscillation circuit is selected. figure 3 oscillation stabilization time power supply res internal medium speed rc oscillation cf1, cf2 operating mode reset time unpredictable reset instruction execution v dd operating v dd lower limit 0v tmscf/tmsx?tal internal medium speed rc oscillation or internal low speed rc oscillation cf1, cf2 (note) hold reset signal hold release signal absent tmscf/tmsx?tal hold halt hold release signal valid state lc87f0a08a no.a1535-22/24 figure 4 sample reset circuit figure 5 serial i/o waveform figure 6 pulse input timing signal waveform note: the external circuit for reset may vary depending on the usage of por and lvd. see ?reset function? in the user's manual. di0 di7 di2 di3 di4 di5 di6 do0 do7 do2 do3 do4 do5 do6 di1 do1 sioclk: datain: dataout: dataout : datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tpil tpih c res v dd r res res lc87f0a08a no.a1535-23/24 figure 7 20 ? amplifier characteristics (a) when p01/apip is 0v, p00/apim ? 0v. (b) when p00/apim is 0v, p01/apip ? 0v. figure 8 example of por only (lvd deselected) mode waveforms (at reset pin with r res pull-up resistor only) ? the por function generates a reset only when the power voltage goes up from the v ss level. ? no stable reset will be generated if power is turned on again when the power level does not go down to the v ss level as shown in (a). if such a case is an ticipated, use the lvd function together with the por function or implement an external reset circuit as shown below. ? a reset is generated only when the power level goes down to the v ss level as shown in (b) and power is turned on again after this condition continues for 100 ? s or longer. por release voltage ( p o rrl ) v dd res reset unknown area ( pouks ) (a) (b) reset period reset period 100 ? lc87f0a08a no.a1535-24/24 figure 9 example of por + lvd mode waveforms (at reset pin with r res pull-up resistor only) ? resets are generated both when power is tu rned on and when the power level lowers. ? a hysteresis width (lvhys) is provided to prevent the repetitions of reset releas e and entry cycles near the detection level. figure 10 minimum low voltage detection width (example of voltage sag/fluctuation waveform) ordering information device package shipping (qty / packing) lc87f0a08au-eb-tlm-h qfp36(7x7) (pb-free / halogen free) 1000 / tape & reel LC87F0A08AUEB-NH qfp36(7x7) (pb-free / halogen free) 1000 / tape & reel v dd res lvd hysteresis width (lvhys) reset unknown area ( lvuks ) reset period reset period reset period lvd release voltage (lvdet+lvhys) lvd reset voltage (lvdet) v dd lvd detect voltage tlvdw v ss lvd release voltage lvdet-0.5v on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner. ps |
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