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december 2013 docid025623 rev 2 1/22 AN4417 application note spc564axx/spc56elxx devices exception handling and single/double bit error introduction this document provides an overview of spc564axx/spc56elxx exception handling with main focus on different kinds of exception that the application code may face during the runtime like single and double bit errors in memories, mpu protection violation, aips access protection violation and others. it starts with the simple overview of machine check interrupt highlighting important things from application perspective. to get detailed view and to implement low level machine check interrupt handler, it is necessary to use z4 core user manual which describes all the details about the core exception and interrupts. the following part describes the reason of the exception, how to find it and what possibilities exist to remove the fault. www.st.com
contents AN4417 2/22 docid025623 rev 2 contents 1 z4 core exception overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 machine check interrupt (ivor1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.1 machine check registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 machine check handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 low level handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.1 start phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.2 final phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.3 modification of the mcsrr0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 user handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 spc564axx/spc56elxx exception cases . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 flash 2b ecc error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.1 cause of the exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.2 machine check exception status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.3 flash 2b ecc error detection by ecsm . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1.4 ecsm_esr.fnce implementation note for spc564a70 device only . 14 3.1.5 ecsm_esr implementation for spc56elx device only . . . . . . . . . . . . 14 3.1.6 flash 2b ecc error detection by flash controller . . . . . . . . . . . . . . . . . 14 3.1.7 flash_x.mcr.err implementation note for spc564a80 device only . 15 3.1.8 user exception handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.9 error solving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 appendix a comparison of microcontroller behavior during ecc error . . . . . 17 appendix b reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 b.1 acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
docid025623 rev 2 3/22 AN4417 list of tables 3 list of tables table 1. machine check interrupt causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. machine check register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. machine check causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4. spc564axx/spc56elxx exception causes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. flash 2b ecc - machine check exception status in core registers. . . . . . . . . . . . . . . . . . . 13 table 6. flash 2b ecc ? ecsm registers related to ecc error detection . . . . . . . . . . . . . . . . . . . . 13 table 7. flash 2b ecc ? flash controller registers related to ecc error detection. . . . . . . . . . . . . . 15 table 8. summary of reactions to single/double bit error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 9. acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
list of figures AN4417 4/22 docid025623 rev 2 list of figures figure 1. machine check exception flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. modification of mcsrr0 register content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3. machine check exception user handler flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. flash 2b ecc error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
docid025623 rev 2 5/22 AN4417 z4 core exception overview 21 1 z4 core exception overview z4 core used on spc564axx/spc56elxx devices contains many exception sources and sixteen interrupts to service them. multiple exception sources can be mapped to one interrupt handler where few supportive status registers provide flags to find the cause of the exception in the handler. detailed list of the exception causes and their mapping to interrupt handlers is found in the z4 core reference manual (see section appendix b: reference documents ). this chapter gives an overview of machine check interrupt that is utilized for several important fault states of spc564axx/spc56elxx devices. 1.1 machine check interrupt (ivor1) machine check interrupt is a handler that services multiple fault events that may occur during runtime code execution. this interrupt is used to handle various faults generated by peripherals in the spc564axx/spc56elxx devices, like mpu protection fault, 2b ecc error in the flash or ram memory etc. the reason is that most of the faults are signaled back as external bus error situation during the cpu-submodule bus transaction. 1.1.1 machine check registers z4 core implements few machine check status registers that are updated upon the exception event with some constraints stated in the z4 core reference manual (see section appendix b: reference documents ). these registers are used to find the source of the exception and based on, it is decided how to solve it. table 1. machine check interrupt causes interrupt type exception conditions machine check -nmi -isi, itlb, error on first instruction fetch for an exception handler -parity error signaled on cache access -external bus error
z4 core exception overview AN4417 6/22 docid025623 rev 2 machine check syndrome register (mcsr) this register is the first register to check additional information about the cause of the exception. there are three groups of machine check causes. machine check address register (mcar) mcar register contains target address reporting the fault condition. it is updated only for asynchronous machine check group when mcsr.mav bit is cleared and it is valid only if mcsr.mav status flag is set. otherwise the mcar register cannot be used in the fault analysis. it is important to clear mcsr.mav bit after reading mcar register value to enable capture of the address, in case of new asynchronous machine check fault. machine check mcsrr0 register this register is updated by the hw in the beginning of the machine check interrupt. it stores the address of the instruction that causes the error condition. table 2. machine check register register content mcsr (syndrome register) register indicates the source of machine check, this condition gives the possibility to differentiate between them mcar (address capture) register contains some sort of machine check conditions, the address for which the asynchronous type of the machine check exception was raised. address valid only when mcsr.mav bit was ?0? before the exception, otherwise mcar register is not updated. mcsrr0 (save/restore register) address of the instruction that caused the exception. once the exception is finished (mcrfi instruction), program starts execution with the same instruction, that was the cause of the exception. table 3. machine check causes machine check cause brief description error report machine check ( i f, l d , s t, g ) these exceptions are directly associated with the current instruction execution stream. they are not masked with msr me bit. it means that the exception is always taken whenever the condition occurs. they differentiate among instruction fetch, data store and load. non-maskable interrupt (nmi) not msr me gated exception occurs when nmi signaling is enabled and nmi pin is driven low. asynchronous machine check (bus_ireer, bus_drerr, bus_wrerr) exceptions reported by the subsystem, usually as bus error termination, back to the core. they are enabled by msr me bit and are cumulative. this machine check whether the exception group triggers capture of the corresponding address to the mcar register and if mcsr mav bit is cleared. if mcsr mav was previously set, then the mcar register is not affected.
docid025623 rev 2 7/22 AN4417 z4 core exception overview 21 it is used in the end of the machine check when mcrfi instruction is executed to fill the instruction pointer. the result is that code restarts the same instruction that was cause of the error, if additional modification of the mcsrr0 register is not explicitly done.
machine check handler AN4417 8/22 docid025623 rev 2 2 machine check handler machine check handler usually splits into two parts: ? low level handler ? user handler 2.1 low level handler low level handler is responsible for first and last part of the exception execution. it is usually written in assembly language as it needs to execute proper instruction sequence before it can pass the code execution to higher level routine and accesses special purpose core registers. the middle of the interrupt service routine belongs to the user handler where analysis of the root cause of the exception and fault removal is done. once the user handler finishes, code execution is given back to the low level driver to finish the interrupt and return back to the interrupt process. figure 1. machine check exception flow 0dfklqhfkhfn h[fhswlrq ([fhswlrqkdqgohu vwduwxs 6wrulqjdoovwdwxv lqirupdwlrqqhhghg 8vhukdqgohu 5hvwrulqjwkh lqwhuuxswhgfrqwh[w 5hwxuqlqjiurp lqwhuuxsw +:xsgdwhv 0&6650&655 ,qwhuuxswhgsurfhvv frqwlqxhv 6wdqgdugh[fhswlrq surfhvvlqj suhsduhlqiriruxvhu kdqgohu suhsduhiruilqlvklqj wkhlqwhuuxsw 0&655 xsgdwhli qhhghg /rzohyho kdqgohu /rzohyho kdqgohu ("1(3*
docid025623 rev 2 9/22 AN4417 machine check handler 21 2.1.1 start phase in the first step the hardware (core) carries out checks, when the machine occurs exception. the hardware stores content of the msr register and address of the current instruction pointer if it is possible (precise exception), low level driver immediately starts processing.the machine executes several steps like check status register saving, context of the interrupted process saving and others. this part stores some additional information as they are used by higher layer user handler to analyze the root cause of the exception later. in the z4 core user manual documentation is described a detailed description of the machine check resources, their meaning and proper handling in case of interrupt. low level handler follows rules and recommendation described in the user manual (see section appendix b: reference documents ). 2.1.2 final phase here the handler should restore the saved context of the interrupted process and return with the mcrfi instruction. before mcrfi instruction is executed, which fills instruction pointer with mcsrr0 content and msr register with mcsrr1 content, mcsrr0 modification might be needed. there are two cases which determine if the manipulation is needed or not. this information is useful in the user handler to pass down to the low level driver. 1. user handler finds the cause of the machine check exception and fix it in a way, that the program can re-execute the same instruction that caused the machine check exception. 2. user is able to find the cause of the exception, but the problem remains and re- executing the same instruction lead to the machine check exception again => modification of the mcsrr0 is needed. 2.1.3 modification of the mcsrr0 register in case that the cause of the exception cannot be removed, mcsrr0 register value is modified in a way that it takes the address of the following instruction. this prevents re- execution of the faulty instruction and retriggering the machine check exception. modification has to consider vle instruction coding in case the interrupted process is implemented in vle coding and increment the value accordingly of the length of the faulty instruction pointed by the current mcsrr0 register content, see figure 2 .
machine check handler AN4417 10/22 docid025623 rev 2 figure 2. modification of mcsrr0 register content 2.2 user handler here the root cause analysis is done. such analysis requires supportive information from ? low level driver (mcar, mcsr etc.) ? peripherals status registers for further elaboration based on the results of analysis and the corrective actions done, user handler should pass the information about the return type back to the low level driver; indication if mcsrr0 content is to be modified or not before mcrfi instruction. lqvwuxfwlrq 5hdg frqwhqwridgguhvv jlyhqe\0&655 uhj lqvwuxfwlrq %lw 0&655 0&655 lqvwuxfwlrq %lw 0&655 0&655 ? ? ? ? elw lqvwuxfwlrq elw lqvwuxfwlr q ("1(3*
docid025623 rev 2 11/22 AN4417 machine check handler 21 figure 3. machine check exception user handler flow exvbhuurubwhuplqdwlrq /rzohyhogulyhu 6xeprgxohfkhfn 0&655 xsgdwhqhhghg <hv 3urjudpzloofrqwlqxhrqqh[wlqvwuxfwlrq iroorzlqjwkhidlolqjrqhwrdyrlgidxow uhwuljjhulqfdvhwkhidxowuhpdlqv 8sgdwh0&655 1r pfuil 3urjudpzloofrqwlqxhiurpwkhvdph lqvwuxfwlrqwkdwfdxvhgwkhh[fhswlrq ehfdxvhidxowzdvvroyhg )dxowsurfhvvlqj dqgil[lisrvvleoh 5hwxuqiurppdfkl qh $ffhvvw\shfkhfn ,)'5': 0hpru\udqjh fkhfn0$9 &ohdu0&650$9 elwdiwhuuhdglqj 0&$5ydoxh )odvk&rgh )odvk'dwd 5$0 3hulskhudoduhdv ,qvwuxfwlrqihwfk 'dwduhdgzulwh 038 )odvk 8vhu+dqgohu /rzohyhogulyhusurylghv lqirupdwlrqwrwkhxvhu kdqgohu 8vhukdqgohusdvvhv lqirupdwlrqderxwwkh uhtxhvwhguhwxuq ("1(3*
spc564axx/spc56elxx exception cases AN4417 12/22 docid025623 rev 2 3 spc564axx/spc56elxx exception cases this chapter lists most common exception cases that application software can experience while running code on spc564axx/spc56elxx devices. in general all protection access exceptions and 2b ecc exception lead to the same machine check exception because of external bus error termination. in such cases further analysis relies on memory area check. 3.1 flash 2b ecc error 3.1.1 cause of the exception platform flash memory controller (pflashc) terminates bus transaction between cpu and pflashc controller in case the flash memory array signals 2b ecc problem during read access. this leads to machine check exception because of bus_error termination. table 4. spc564axx/spc56elxx exception causes exception cause error signaling exception description flash 2b ecc error external bus error machine check two or multiple bit error in the flash memory leads to the machine check exception when faulty area is read, instruction fetch or data read.
docid025623 rev 2 13/22 AN4417 spc564axx/spc56elxx exception cases 21 figure 4. flash 2b ecc error 3.1.2 machine check exception status 3.1.3 flash 2b ecc error detection by ecsm flash controller provides detection ability of ecc errors detection. &ruhb[ &urvvedu 3)/$6+& )/$6+$uud\ 5hdgdffhvv ,qvwuxfwlrqihwfkru'dwd uhdg e(&&huuru irxqg ([whuqdoexv huuruwhuplqdwlrq 5hdggdwdiurp)odvk duud\ ("1(3* table 5. flash 2b ecc - machine check exception status in core registers register description mcsrr0 address of the instruction that caused the exception. in case of ecc error in the data flash area, register modification is needed. mcsr type of operation is highlighted here, instruction fetch, data load or data write. mcar target address that was accessed, but finished with 2b ecc error. this address can be used for further analysis. table 6. flash 2b ecc ? ecsm registers related to ecc error detection register description ecsm_esr the ecsm_esr signals the last, properly enabled (in ecsm_ecr) memory event to be detected. ram and flash single bit errors, as well as dual bit errors, are signaled by separated status bits. ecsm_esr.r1bc a reportable single-bit platform ram correction has been detected. ecsm_esr.rnce a reportable non-correctable platform ram error (2b ecc) has been detected.
spc564axx/spc56elxx exception cases AN4417 14/22 docid025623 rev 2 maintaining of ecsm_esr register to be performed properly! for more details see section appendix b: reference documents . 3.1.4 ecsm_esr.fnce implementation note for spc564a70 device only flash controller always reads one complete prefetch buffer line (128-bit) from flash array. ecsm_esr.fnce bit detects ecc error separately for double word a (bit 0..63) and double word b (bit 64..127) in spc564a70 device, and it can cause an unexpected behavior. following is an example to demonstrate it: assuming that an ecc error is present in upper word and lower word is accessed by core. then the ecc error is detected during complete 128-bit line reading and core machine check exception is invoked, but ecsm_esr.fnce bit is not set in this case. if machine check exception handler tests the ecsm_esr.fnce bit only in our case, then it may unexpectedly assume that no ecc issue occurred. note: there is a possibility to check flash_a.mcr.eer bit instead of the ecsm_esr.fnce. the implementation depends on the application needs. for more details see section appendix a: comparison of microcontroller behavior during ecc error . 3.1.5 ecsm_esr implementation for spc56elx device only spc56elx devices have been designed with functional safety in mind. in case the reporting of dual bit errors is enabled in the ecsm, the device reacts in one of the safest way, i.e. a critical fault is triggered by th e fccu. the outcome of this critical fault is a functional reset of the device without any exception triggered to the core. rational for this severe reaction is that since the dual bit error cannot be corrected, software is not able to recover it. then safest reaction is assumed to be a reset. nevertheless this reset reaction prevents working correctly most of flash eeprom emulation drivers. an ecc error is a standard error situation during read in flash area used for data eeprom emulation. this situation is handled by the driver accordingly. in case of the dual bit error, reporting is disabled in the ecms and then a core exception is invoked instead of reset. core exception handler gives possibility to the flash eeprom emulation driver to react accordingly. 3.1.6 flash 2b ecc error detection by flash controller flash controller provides detection ability of ecc errors detection. ecsm_esr.f1bc a reportable single-bit platform flash correction has been detected. ecsm_esr.fnce a reportable non-correctable platform flash error (2b ecc) has been detected. table 6. flash 2b ecc ? ecsm registers related to ecc error detection (continued) register description
docid025623 rev 2 15/22 AN4417 spc564axx/spc56elxx exception cases 21 for more details see section appendix b: reference documents . 3.1.7 flash_x.mcr.err implementation note for spc564a80 device only spc564a80 contains two different flash modules. each of them contains its own flash_x.mcr.eer bit. addressing of particular flash modules depends on accessed address from flash address range. for more details see section appendix b: reference documents l. flash controller always reads one complete prefetch buffer line (128-bit) from flash array. flash_x.mcr.eer bit is always set, if ecc error is detected in any of double word a (bit 0..63) or double word b (bit 64..127). in contrast, core machine check exception is invoked only if the accessed one double word contains ecc error in spc564a80 device, and it can cause an unexpected behavior. following is an example to demonstrate it: assuming that an ecc error is present in upper word and lower word is accessed by core. the ecc error is detected during complete 128 bit line reading and core machine check exception is not invoked, but flash_x.mcr.eer bit is set in this case (and it is not cleared automatically). let us assume, that machine check exception is invoked later on caused by another reason (e.g. due to memory protection by mpu). if the machine check exception handler tests the flash_x.mcr.eer bit only, then it may unexpectedly assume that flash ecc error has occurred instead. however the machine check exception handler routine may handle this situation by cross-checking the data coming from flash ar and mcar. note: there is also a possibility to check ecsm_esr.fnce bit instead of the flash_x.mcr.eer registers. the implementation depends on the application needs. for more details see section appendix a: comparison of microcontroller behavior during ecc error . table 7. flash 2b ecc ? flash controller registers related to ecc error detection register description flash_x.mcr.eer (flash.mcr.err for spc56elxx devices) eer provides information on previous reads. if a double bit detection occurred, the eer bit is set to a 1.this bit must then be cleared, or a reset must occur before this bit returns to a 0 state. flash_x.ar (flash.adr for spc56elxx devices) the addr field provides the first failing address in the event of ecc event error (mcr[eer] set), single bit correction (mcr[sbc] set), as well as providing the address of a failure that may have occurred in a state machine operation (mcr[peg] cleared). note: flash controller always reads one complete prefetch buffer line (128-bit) from flash array. the first failing address stored in the ar register could be anywhere inside the flash prefetch line address range and can differ from the address originally accessed. x x = a for spc564a70 device x = a and/or b for spc564a74, spc564a80 devices, because flash address range is covered by two flash modules flash_a and flash_b.
spc564axx/spc56elxx exception cases AN4417 16/22 docid025623 rev 2 3.1.8 user exception handler handler has to analyze the following: ? type of access, instruction fetch, data read, and data write. only instruction fetch or data read access are expected in case of 2b ecc flash error. ? memory range memory access must be within area belonging to the flash memory. user has to know which part belongs to the code flash and which part belongs to the data flash memory. 3.1.9 error solving flash 2b ecc error can be solved only with erase of the flash sector containing the cell with 2b ecc error. it is usually not done in the exception handler itself, because it takes significant amount of time. the decision what to do in case of 2b ecc error is application specific, whether if to go to degraded mode or to continue, the case of eeprom emulation, and to solve the issue later in the application. if the decision is to continue, user handler has to request modification of the mcsrr0 register to continue the program flow with next instruction. otherwise program would be stuck in the reading of the fault flash address invoking machine checks.
docid025623 rev 2 17/22 AN4417 comparison of microcontroller behavior during ecc error 21 appendix a comparison of microcontroller behavior during ecc error table 8 is a summary of the behavior of different 90nm microcontrollers in case of either single or double bit error in the flash. to understand the table, the user should keep in mind that flash is accessed in word line of 128-bit. each time a master would like to access (read / code fetch) a location, which belongs to a certain word line, the whole word line is read out of the flash. the word line consists of two double-words a and b. each one double-word contains its own ecc. even there is always read complete word line, behavior of microcontroller can differ regarding which double-word is addressed and which one contains an ecc error. one concrete word line starting at address 0x00030000 is chosen as an example. the first 2 columns of the table represent the address location which can be accessed and can be affected by single/double bit error. each row represents a combination of access and an ecc error: ? the marked cells in the first 2 columns are affected by an ecc error. ? cells with the text ?accessed by master? are actually accessed by one of the crossbar master. ? in addition, few cells are marked which highlights some differences in term of behavior. the other columns contain reaction of selected registers, - separately for each microcontroller.
comparison of microcontroller behavior during ecc error AN4417 18/22 docid025623 rev 2 table 8. summary of reactions to single/double bit error flash line (128bit) e.g. address = 0x30000 means addr.range: 0x30000..0x3000f spc564a70 spc564axx spc563m spc56el family spc560p family double word a e.g. addr. range: 0x30000.. 0x30007 double word b e.g. addr. range: 0x30008.. 0x3000f flash mcr eer flash ar ecsm esr fnce ivor1 exception / flash mcr eer flash ar ecsm esr fnce ivor1 exception / flash mcr eer flash ar ecsm esr fnce ivor1 exception / flash mcr eer flash ar ecsm esr fnce bus error / flash mcr eer flash ar ecsm esr fnce bus error / reset accessed by master 0 no change 0no 0 no change 0no 0 no change 0no 0 no change 0no 0 no change 0no accessed by master 0 no change 0no 0 no change 0no 0 no change 0no 0 no change 0no 0 no change 0no accessed by master 1 0x30000 0 yes 1 0x30000 0 no 1 0x30000 1 yes 1 0x30000 0 no 1 0x30000 1 yes accessed by master 1 0x30000 1 yes 1 0x30000 1 yes 1 0x30000 1 yes 1 0x30000 1 ye s 1 0x30000 1 yes accessed by master 1 0x30008 1 yes 1 0x30008 1 yes 1 0x30008 1 yes 1 0x30008 1 ye s 1 0x30008 1 yes accessed by master 1 0x30008 0 yes 1 0x30008 0 no 1 0x30008 1 yes 1 0x30008 0 no 1 0x30008 1 yes
AN4417 comparison of microcontroller behavior during ecc error docid025623 rev 2 19/22 note: marking in the first 2 columns of the table represents the address locations which are affected by an ecc error. accessed by the master means address location accessed (read or write or core instruction fetch) by crossbar (xbar) master. microcontroller core is only one of the xbar masters. accessed by master 1 0x30000 1 yes 1 0x30000 1 yes 1 0x30000 1 yes 1 0x30000 1 ye s 1 0x30000 1 yes accessed by master 1 0x30000 1 yes 1 0x30000 1 yes 1 0x30000 1 yes 1 0x30000 1 ye s 1 0x30000 1 yes table 8. summary of reactions to single/double bit error (continued) flash line (128bit) e.g. address = 0x30000 means addr.range: 0x30000..0x3000f spc564a70 spc564axx spc563m spc56el family spc560p family double word a e.g. addr. range: 0x30000.. 0x30007 double word b e.g. addr. range: 0x30008.. 0x3000f flash mcr eer flash ar ecsm esr fnce ivor1 exception / flash mcr eer flash ar ecsm esr fnce ivor1 exception / flash mcr eer flash ar ecsm esr fnce ivor1 exception / flash mcr eer flash ar ecsm esr fnce bus error / flash mcr eer flash ar ecsm esr fnce bus error / reset
reference documents AN4417 20/22 docid025623 rev 2 appendix b reference documents ? z4d core reference manual ? spc56el60 32-bit mcu family built on the embedded power architecture ? (rm0032, doc id 15265) ? spc56xl70xx 32-bit mcu family built on the embedded power architecture ? (rm0042, doc id 023986) ? spc564a74xx, spc564a80xx 32-bit mcu family built on the embedded power architecture ? (rm0029, doc id 15177) ? spc564a70b4, spc564a70l7 32-bit mcu family built on the embedded power architecture ? (rm0068, doc id 18132) b.1 acronyms table 9. acronyms acronym name ecc error correction code edc error detection code 2b ecc double bit error (it is only detected by the ecc/edc hardware) 1b ecc single bit error (it?s detected and correct by the ecc/edc hardware. nmi non maskable interrupt
docid025623 rev 2 21/22 AN4417 revision history 21 revision history table 10. revision history date revision changes 12-dec-2013 1 initial release 19-dec-2013 2 modified table 8 .
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