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asix electronics corporation ver. 0.7 4f, no.8, hsin ann rd., science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http:// www.asix.com.tw AX81190 pci/cardbus/pcmcia bus wlan mac 802.11b pci/cardbus/pcmcia bus wlan mac controller document no.: AX81190-07 / v0.7 / mar. 15 ?03 features ? single chip multiple bus wlan mac controller ? ieee 802.11b wireless lan (wlan) compatible ? compliant with 802.11b protocol such as dcf, pcf, wep, power management, etc. ? embedded two 8k * 16 bit srams for tx and rx packet buffers ? compliant with pci bus standard ver 2.1(slave mode)/pcmcia bus standard. ? support pci 16-bit accsee for registers and 32-bit accsee for data ? support both 1/2/5.5/11 mbps data rate ? support both full-duplex (test) or half-duplex operation ? provides an industrial standard interface to interface with baseband processer and if/rf chips. ? support 256 bytes eeprom (used for saving configuration information and address id) ? support automatic loading of mac id and adapter configuration from eeprom on power-on initialization ? 128-pin tqfp low profile package ? 33/44mhz, 2.5vcore/3.3v io operation with 5v tolerance *ieee is a registered trademark of the institute of electrical and electronic engineers, inc. *all other trademarks and registered trademark are the property of their respective holder. product description the AX81190 is a high performance multiple bus wlan mac controller. the AX81190 cont ains a 16 bit pcmcia interfaces (32-bit pci/card bus) to host cpu and compliant with pc mcia bus standard ver 2.2. the AX81190 implements 1mbps, 2mbps, 5.5mbps and 11mbps wlan function based on dsss (direct sequence spread spectrum) of ieee802.11 /ieee802.11b wlan standard. the ax 81190 supports an industrial standard(such as intersil /rfmd/ralink) interface for ba seband processer and if/rf chips to simplify the design. system block diagram always contact asix for possible updates before starting a design. this data sheet contains new produc ts information. asix electronics re serves the rights to modify product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product. mac -- AX81190 ralink 2430 or bb -- rfmd r3000 or intersil 3861/63 if rf pa pci/cardbus pcmcia
asix electronics corporation 2 AX81190 pci/cardbus/pcmcia bus wlan mac contents 1.0 introduction ...........................................................................................................6 1.1 g eneral d escription ............................................................................................................6 1.2 AX81190 b lock d iagram .................................................................................................6 1.3 AX81190 p in c onnection d iagram .......................................................................7 1.3.1 ax88119 pin connection di agram for pcmcia bus mode ..............................7 1.3.2 AX81190 pin connection diagram for pci/cardbus mode ...............................8 2.0 signal description ...................................................................................9 2.1 pcmcia b us i nterface s ignals g roup ...........................................................9 2.2 pci/cardbus b us i nterface s ignals g roup .......................................10 2.3 eeprom s ignals g roup ..................................................................................................11 2.4 s erial p ort i nterface s ignals g roup ............................................................11 2.5 b aseband p rocesser c ontroller interface signals group 11 2.6 p ower c ontrol i nterface s ignals g roup ................................................12 2.7 s ynthesizer control signal i nterface pins group ........................12 2.8 m iscellaneous pins group ............................................................................................12 3.0 registers operation .........................................................................14 3.1 pci c onfiguration r egister ......................................................................................14 3.1.1 device vendor register -- offset 00h .................................................................................14 3.1.2 command register ? offset 04h ...........................................................................................14 3.1.3 status register ? offset 06h .....................................................................................................14 3.1.4 revision id register ? offset 08h ........................................................................................14 3.1.5 class code register ? offset 09h ..........................................................................................15 3.1.6 base io address register ? offset 10h ..............................................................................15 3.1.7 base memory address register ? offset 14h .................................................................15 3.1.8 cis pointer ? offset 28h ...........................................................................................................15 3.1.9 subsystem id ? 2ch ...................................................................................................................15 3.1.10 interrupt register ? 3ch ........................................................................................................15 3.2 pcmcia c onfiguration r egister .......................................................................16 3.2.1 cor register ? 0800h ...............................................................................................................16 3.2.2 ccr register ? 0802h ..............................................................................................................16 3.2.3 io base (lsb) ? 0804h .............................................................................................................16 3.2.4 io base (msb) ? 0806h ............................................................................................................16 3.3 io port ............................................................................................................................... ...................17 3.3.1 csr index port base ................................................................................................17
asix electronics corporation 3 AX81190 pci/cardbus/pcmcia bus wlan mac 3.3.2 csr data port base + 2 .............................................................................................17 3.3.3 tx data access control port base + 4 .............................................................17 3.3.4 tx data buffer port base + 6 .............................................................................17 3.3.5 rx data access control port base + 8 .............................................................17 3.3.6 rx data buffer port base + ah ...........................................................................17 3.3.7 soft reset port base + eh .............................................................................................17 3.3.8 interrupt status port base + 10h ...........................................................................17 3.3.9 interrupt mask port base + 12h ...........................................................................18 3.3.10 rx page status port base + 14h ........................................................................18 3.3.11 tx page status port1 base + 16h .....................................................................18 3.3.12 tx page status port2 base + 18h .....................................................................19 3.3.13 bbp_index port base + 1ah ............................................................................19 3.3.14 bbp_data out port base + 1ch .........................................................................19 3.3.15 bbp_data in port base + 1eh .............................................................................19 3.3.16 synthesizer control port base + 20h .............................................................19 3.3.17 synthesizer data port0 base + 22h .................................................................19 3.3.18 synthesizer data port1 base + 24h .................................................................19 3.3.19 ee_data port base + 26h ..................................................................................20 3.3.20 ee_cmd/addr port base + 28h ......................................................................20 3.3.21 ee_status_type port base + 2ah .....................................................................20 3.4 mac c onfiguration s tatus r egisters .........................................................21 3.4.1 csr1 ? mac physical address0 (padr[15:0]) .......................................................21 3.4.2 csr2 ? mac physical address1 (padr[31:16]) ....................................................21 3.4.3 csr3 ? mac physical address2 (padr[47:32]) ....................................................21 3.4.4 csr4 ? bssid matching register0, bssid[15:0] ..................................................21 3.4.5 csr5 ? bssid matching register1, bssid[31:16] ...............................................21 3.4.6 csr6 ? bssid matching register2, bssid[47:32] ...............................................21 3.4.7 csr7 ~ csr9 are reserved. .................................................................................................21 3.4.10 csr10 ? multicast filter pattern1 ...................................................................................21 3.4.11 csr11 ? multicast filter pattern2 ...................................................................................21 3.4.12 csr12 ? multicast filter pattern3 ...................................................................................21 3.4.13 csr13 ? multicast filter pattern4 ...................................................................................21 3.4.12 csr14 ~ csr15 are reserved. .......................................................................................22 3.4.16 csr16 ? clock pattern ..........................................................................................................22 3.4.17 csr17 ? wait md_rdy duration ......................................................................................22 3.4.18 csr18 ? short interframe space timing register ,sifs ....................................22 3.4.19 csr19 ? distributed interframe space timing register, difs/pifs .........22 3.4.20 csr20 ~ csr 21 ? reserved. ............................................................................................22 3.4.22 csr22 ? slottime register (slot) .............................................................................22 3.4.23 csr23 ? backoff timing ........................................................................................................22 3.4.24 csr24 ? rf3000 modulation duration (testing) ..................................................22 3.4.25 csr25 ? power testing and misc ...................................................................................22
asix electronics corporation 4 AX81190 pci/cardbus/pcmcia bus wlan mac 3.4.26 csr26 ? txvgc adjust register (support rf3000 only) .................................23 3.4.27 csr27 ? tx beacon/pr obe response enable register ..........................................23 3.4.28 csr28 ? tbtt compensation register ......................................................................23 3.4.29 csr29 ? rx filtering register ...........................................................................................23 3.4.30 csr30 ? tx power ramp-up control register1 ...................................................24 3.4.31 csr31 ? tx power ramp-up control register2 ...................................................24 3.4.32 csr32 ? tx power ramp control register3 ..........................................................24 3.4.33 csr33 ? tx power ramp control register4 ..........................................................24 3.4.34 csr34 ? tx power ramp control register5 ..........................................................24 3.4.35 csr35 ? beaconperiod (bp) .............................................................................................24 3.4.36 csr36 ? tx retry counter ...................................................................................................24 3.4.37 csr37 ? mac feature register .........................................................................................24 3.4.38 csr38 is reserved ...................................................................................................................25 3.4.39 csr39 ? transmit page control register ....................................................................25 3.4.40 csr40 ? tx rate control register. .................................................................................25 3.4.41 csr41 ? response time-out register ..............................................................................26 3.4.42 csr42 ? rssi-sq location register ...............................................................................26 3.4.43 csr43 ? tsf compensate register .................................................................................26 3.4.44 csr44 ? calibration adjust register .............................................................................26 3.4.45 csr45 ? bbp plcp service/signal fie ld location register ( for intersil 3861/3863) ............................................................................................................................... ....................26 3.4.46 csr46 ? bbp plcp length field location register (for intersil 3861/3863) ............................................................................................................................... ....................26 3.4.47 csr47 is reserved ...................................................................................................................27 3.4.48 csr48 ? software reset duration ....................................................................................27 3.4.49 csr49 ? cfp duration register .......................................................................................27 3.4.50 csr50 ? atim duration register ....................................................................................27 3.4.51 csr51 ? 802.11 protocol status .......................................................................................27 3.4.52 csr52 ? mac mode status .................................................................................................27 3.4.53 csr53 ? bbp mode .................................................................................................................27 3.4.54 csr54 ? spi chip address ...................................................................................................28 3.4.55 csr55 ~ csr59 reserved . ..................................................................................................28 3.4.60 csr60 crc32 counter ..........................................................................................................28 3.4.61 csr61 is reserved. ...................................................................................................................28 3.4.62 csr62 ? nav timer .................................................................................................................28 3.4.63 csr63 ? tsf timer register0 (tsfr[15:0]) ............................................................28 3.4.64 csr64 ? tsf timer register1 (tsfr[31:16]) ..........................................................28 3.4.65 csr65 ? tsf timer register2 (tsfr[47:32]) ..........................................................28 3.4.66 csr66 ? tsf timer register3 (tsfr[63:48]) ..........................................................28 3.4.67 csr67 ~ csr69 reserved. ..................................................................................................28 3.4.70 csr70 ? not my unicast frame counter .......................................................................28 3.4.71 csr71 ? broadcast and multicast counter ................................................................29
asix electronics corporation 5 AX81190 pci/cardbus/pcmcia bus wlan mac 3.4.72 csr72 ? rssi-sq value ........................................................................................................29 3.4.73 csr73 ? outbuf/inbuf current page pointer ............................................................29 3.4.74 csr74: tx power ramp-down control register1 ...............................................29 3.4.75 csr75: tx power ramp-down control register2 ...............................................29 3.4.76 csr76: tx power ramp-down control register3 ...............................................29 3.4.77 csr77: tx power ramp-down control register4 ...............................................29 3.4.78 csr78: rx_pe de-asserted duration ...........................................................................29 3.4.79 csr79: min size of rx packet ..........................................................................................30 3.4.80 csr80: gpio status control ..............................................................................................30 3.4.81 csr81: gpio data port ........................................................................................................30 3.4.82 csr82: wep control ................................................................................................................30 3.4.83 wep key matrix (csr83 ~ csr110, 16 bit registers) ...............................................30 4.0 pcmcia device access functions ....................31 4.1 a ttribute m emory access functions . ...........................................................31 4.2 i/o access functions . ..........................................................................................................31 5.0 electrical specification and timings ............................................................................................................................... ..................32 5.1 a bsolute m aximum r atings ......................................................................................32 5.2 g eneral o peration c onditions .............................................................................32 5.3 dc c haracteristics .............................................................................................................32 5.4 a.c. t iming c haracteristics .....................................................................................33 5.4.1 clock ............................................................................................................................... ...............33 5.4.2 pcmcia reset timing .............................................................................................................33 5.4.3 pcmcia attribute memory read timing .....................................................................34 5.4.4 pcmcia attribute memory write timing ....................................................................35 5.4.5 pcmcia i/o read timing .....................................................................................................36 5.4.6 pcmcia i/o write timing ....................................................................................................37 5.4.7 synthesizer timings ....................................................................................................................38 5.4.8 serial port timings ....................................................................................................................39 5.4.9 tx path waveforms ....................................................................................................................40 5.4.10 rx path waveforms ................................................................................................................41 6.0 package information ....................................................................42 appendix a: application note 1 ........................................43 a.1 e xternal eeprom format .......................................................................................43
asix electronics corporation 6 AX81190 pci/cardbus/pcmcia bus wlan mac 1.0 introduction 1.1 general description the AX81190 wireless lan controller is a high performance pcmcia/pci bus wlan controller. the AX81190 contains a 16 bit pcmcia (32 bit pci) in terfaces to host cpu. the AX81190 implement 1mbps, 2mbps, 5.5mbps and 11mbps wlan function based on ieee802.11 /ieee802.11b wlan standard. the AX81190 supports indudtrial standard mac to baseband controller interface to simplify the design. the AX81190 is built in two 8k*16 bit sram for tx and rx packet buffer to reduce system cost and size. AX81190 is also implemented wep (hardwared) func tion, supports 64/128 bit key to reduce computing load of cpu. AX81190 use 128-pin tqfp low profile package, 33/44m hz operation frequency, 2.5v core/3.3v cmos process with 5v i/o tolerance. 1.2 AX81190 block diagram two 8k*16 sram mac engine s-eeprom loader if registers buffer management and fifo power controller serial i/f host interface eecs eeclk eedi eedo gpio pa_pe . . . bbp i/f rf i/f ctrl bus ad[31:0]
asix electronics corporation 7 AX81190 pci/cardbus/pcmcia bus wlan mac 1.3 AX81190 pin connection diagram the AX81190 is housed in the 128-pin plastic quad flat pack fig - 1 AX81190 pin connection diagram shows the AX81190 pin assignment. 1.3.1 ax88119 pin connection diagram for pcmcia bus mode fig - 1 AX81190 pin connection diagram for pcmcia bus mode vss1 ireq# 10 vss1 eepm_dis txd a15 eecs vss1 gpio2 gpio0 spi_do 120 90 101 d8 81 51 62 86 a13 115 36 100 29 23 14 cca rf_pe 70 vdd2 gpio3 led1 40 d3 pe2 116 vss1 bbpmode0 d7 vss2 d12 105 2 55 11 21 reg# eecl k vdd2 synclk 106 13 led2 33 le_if# 99 cs# 117 d11 43 73 41 127 71 vdd1 sclk 6 vdd2 d15 hrst d1 AX81190 a3 78 92 md_rdy rstphy# we# 25 bbpmode1 a1 vss2 60 93 102 104 111 gpio4 125 31 95 a14 vdd2 16 66 97 80 4 118 89 109 61 3 ( pcmcia ) txclk 67 nc vss1 82 49 12 vdd2 wait# a5 34 d6 32 hbusmode 27 56 d0 108 oe# mt0 a8 103 syndata cbse l rx_pe iois16# 91 69 pa_pe 85 a4 a0 vdd1 a2 44 57 48 vdd2 75 64 126 eed o mt1 113 79 rxclk 84 vss2 110 128 119 vdd1 rxd nc d14 vdd1 114 83 53 98 26 vdd1 vdd2 30 19 63 tx_rdy eed i vdd1 sd vss2 65 vss1 a11 vss1 15 112 a6 vdd1 38 tx_pe 68 vss1 77 d13 vss2 d9 45 24 20 22 50 le_rf# 47 nc vdd1 8 124 39 88 121 59 d2 rw# vss2 vss1 cal_en vss2 vss1 37 tr_sw# 76 gpio1 52 iord# 94 42 iowr# 96 7 vdd2 35 a7 107 87 d5 vdd1 46 a12 122 d4 ce1# tr_sw 18 vss2 nc 74 17 1 9 a9 d10 54 pe1 hclk gpio5 72 a10 28 58 123 nc 5
asix electronics corporation 8 AX81190 pci/cardbus/pcmcia bus wlan mac 1.3.2 AX81190 pin connection diagram for pci/cardbus mode fig - 2 AX81190 pin connection diagram for pci/cardbus ad0 59 121 rf_pe rstphy# 109 98 vdd1 perr# vss1 74 99 50 eecl k 26 ad12 9 par 93 gpio3 vss2 ad30 vdd1 ad5 86 ad7 ad2 stop# nc 120 ad14 vss2 sd AX81190 34 6 mt0 rx_pe cs# 76 84 44 29 32 vss1 rxclk 15 ad9 111 78 21 83 123 68 ad20 ad19 70 rw# 91 vss1 100 7 105 vss2 128 pa_pe 107 irdy# eecs bbpmode0 75 46 16 19 cxbe0 # 39 tr_sw# 106 syndata cbse l vdd1 ad15 8 127 31 ad21 tx_rdy pe1 73 vss1 67 63 gpio5 vss1 90 vdd1 3 22 47 18 ad11 ad28 125 13 ad17 79 81 ( pci ) 115 ad26 hbusmode 57 2 17 ad29 vdd2 112 20 117 ad16 ad6 1 95 ad8 49 55 27 ad22 le_if# 116 102 60 hrst# le_rf# eepm_dis 69 trdy# 66 35 23 vdd2 ad1 10 mt1 77 vdd2 synclk 124 vdd1 cca ad31 48 txclk 89 126 gpio2 cxbe1 # 103 43 devsel# vss1 vdd1 ad13 11 vss1 28 37 53 62 vss2 gpio4 ad25 36 114 14 eed i ad18 52 87 cxbe2# 108 30 96 cal_en 113 tx_pe frame# vdd2 65 58 gpio1 intr# vss2 txd ad23 rxd 92 41 45 ad4 vss2 122 spi_do vss2 82 85 119 38 hclk 88 pe2 vdd2 42 64 110 cxbe3# 101 ad10 5 vdd1 led2 94 ad24 80 12 vss1 vss1 vdd2 71 vss2 25 eed o vss1 vdd2 md_rdy tr_sw 72 54 24 idsel sclk 51 104 vdd2 bbpmode1 vdd1 97 gpio0 56 led1 61 40 vdd1 ad27 33 4 ad3 118
asix electronics corporation 9 AX81190 pci/cardbus/pcmcia bus wlan mac 2.0 signal description the following terms describe the AX81190 pin-out: all pin names with the ?#? suffix are asserted low. the following abbreviations are used in following tables. i input pu internal pull up o output pd internal pull down i/o input/output p power pin od open drain 2.1 pcmcia bus interface signals group signal type pin no. description hclk i 28 reference clock. 33mhz or 44mhz. hrst i 26 reset signal. active high for pcmcia. a[15:0] i 61,62,33,34, 36,37,39,40, 44,45,46,47, 49,50,52,53 system address : signals a[15:0] are address bus input lines which enable direct address of up to 64k memory and i/o spaces on card. d[15:0] i/o 68,69,70,73, 74,76,77,78, 81,83,84,85, 86,88,89,91 system data bus : signals d[15:0] constitute the bi-directional data bus. ireq# o 24 interrupt request : ireq# is asserted to indicate the host system that the pc card device require s host software service. wait# o 64 wait : this signal is set low to insert wait states during remote dma transfer. reg# i 42 attribute memory and i/o sp ace select : when the reg# signal is asserted, access is limited to attri bute memory and to the i/o space. iord# i 55 i/o read : the host asserts iord# to read data from AX81190 i/o space. iowr# i 41 i/o write : the host asserts iowr# to write data into AX81190 i/o space. oe# i 32 output enable : the oe# line is used to gate memory read data from memory on pc card we# i 30 write enable : the we# signal is used for strobing memory write data into the memory on pc card. iois16# o 56 i/o is 16 bit port : the iois16# is asserted when the address at the socket corresponds to an i/o address to which the card responds, and the i/o port addressed is capable of 16-bit access. ce1# i 80 card enable : the ce1# enables even numbered address bytes. pcmcia bus interface signals group
asix electronics corporation 10 AX81190 pci/cardbus/pcmcia bus wlan mac 2.2 pci/cardbus bus interface signals group signal type pin no. description hclk i 28 the clock provides the timing for the AX81190 related pci bus transactions. all the bus signals are sampled on the rising edge of hclk. the max frequency is 33mhz. hrst# i 26 resets the AX81190 to its initial st ate. this signal must be asserted for at least 10 active pci clock cycles. when is the reset state, all pci output pins are put into tri-state and all pci o/d signals are floated. frame# i/o 56 the frame# signal is driven by the master to indicate the beginning and duration of an access. frame# asserts to indicate the beginning of a bus transaction. while frame# is asserted, data transfers continue. when frame# deasserts the next data phase is the final data phase transaction. irdy# i/o 58 initiator ready indicates the bus master r ability to complete the current data phase of the transaction. a data phase is completed on any rising edge of the clock when both irdy# and target ready trdy# ar e asserted. wait cycles are inserted until both irdy# and trdy# are asserted together. trdy# i/o 59 target ready indicates the target ability to complete the current data p hase of the transaction. a data phase is completed on any clock when b oth trdy# and irdy# are asserted. wait cycles are inserted until both irdy# and trdy# are asserted together. devsel# i/o 61 device select is asserted by the AX81190 of the current bus access hit to AX81190 stop# i/o 62 stop indicator indicates that the current target is requesting the bus master to stop the current transaction. par i/o 65 parity is an even parity bit for the ad[31:0] ad and cxbe[3:0]#. during address and data phases, parity is calculated on all the ad[31:0] and cxbe[3:0]# lines whet her or not any of these lines carry meaningful information. idsel i 42 initialization devise select asserts to indicate that the host is issuing a configuration cycle to the AX81190. for cardbus application, this pin always is pulled high with vdd1. ad[31:0] i/o 30,32,33,34, 36,37,39,40, 44,45,46,47, 49,50,52,53, 68,69,70,73, 74,76,77,78, 81,83,84,85, 86,88,89,91 address and data bits are multiplexed on the same pins. during the address phase, the ad[31:0] contain a physical address (32 bits). during, data phases, ad[31:0] contain 32 bits of data. cxbe[3:0]# i/o 41,55,66,80 bus command and byte enable are multiplexed on the same pci pins. during the address phase of the transaction, cxbe[3:0]# provide the bus command. during the data phase, cxbe[3:0]# provide the byte enable. the byte enable determines which byte lines carry valid data., cxbe0# applies to byte 0, and cxbe3# applies to byte 3. perr# i/o 63 parity error asserts when a data parity error is detected. when a parity error is detected, the AX81190 asserts perr#. this pin must be pulled up with vdd2 by an external resistor.
asix electronics corporation 11 AX81190 pci/cardbus/pcmcia bus wlan mac intr# o/d 24 interrupt request asserts when one of the appropriate bits of interrupt status register sets and causes an interrupt, provided that the corresponding mask bit in interrupt mask register is not asserted. interrupt request deasserts by writing an ?1? into the appropriate interrupt status register bit. this pin must be pulled up with vdd2 by an external resistor. pci/cardbus bus interface signals group 2.3 eeprom signals group signal type pin no. description eecs o 96 eeprom chip select : eeprom chip select signal. eeclk o 94 eeprom clock : signal connected to eeprom clock pin. eedi o 93 eeprom data in : signal connected to eeprom data input pin. eedo i/pd 92 eeprom data out : signal connected to eeprom data output pin. eeprom bus interface signals group 2.4 serial port interface signals group signal type pin no. description sclk o 9 sclk is the clock for sd serial bus. the data on sd is latched in rising edge. sd i/o/pd 10 sd is serial bi-directional data bus, which is used to transfer address and data to/from bbp internal register for intersil type bbp. this signal is input only for rfmd type bbp. spi_do o 12 spi_do is serial data output only bus, which is used to transfer address and data to rfmd type bbp. rw# o 7 to control the direction when mac reads or writes data on sd bus. a high level indicates a read cycle a nd low level indicates a write cycle. cs# o 8 mac selects bbp to be as target. serial port interface signals group 2.5 baseband processer controller interface signals group signal type pin no. description txd o 1 mac transmits data to bbp. the data is valid in rising edge of txclk. txclk i 2 the clock from bbp is to be valid txd. tx_rdy i 111 bbp indicates the valid data phase. tx_pe o 117 to control the transmitted phase. cca i 113 mac will monitor this signal to determine whether it can transmit data or not. rxd i 4 rxd is an input from bbp. the data is sent serially with lsb first and the data is frame aligned with rx_rdy.
asix electronics corporation 12 AX81190 pci/cardbus/pcmcia bus wlan mac rxclk i 5 this is the bit clock input from bbp. this clock is used to transfer header information and payload data through the rxd serial bus. rxclk becomes active after sfd ha s been detected. data (rxd) should be samples on rising edge. md_rdy i 114 bbp indicates header data and data packet are ready to be transferred. rx_pe o 115 mac enables bbp to qualify receive stage. baseband processer interface signals group 2.6 power control interface signals group signal type pin no. description cal_en o 125 calibration mode enable. tr_sw# o 120 transmit & receive switch control. active low. tr_sw o 119 transmit & receive switch control. active high. pa_pe o 122 power amplifier control pin,. active high. rf_pe o 121 power enable pin to rf and if components. pe1 o 13 power enable1 for i/q modulation/demodulation pe2 o 15 power enable2 for i/q modulation /demodulation power control interface signals group 2.7 synthesizer control signal interface pins group signal type pin no. description syndata o 128 serial data for front-end chip synthesizer. synclk o 127 serial clock for front-end chip synthesizer. le_if# o 123 load (latch) enable to if synthesizer. mac selects if as target for serial access. le_rf# o 124 load (latch) enable rf synthesizer. mac selects rf as target for serial access channel activity status interface pins group 2.8 miscellaneous pins group signal type pin no. description rstphy# o 14 mac will reset bbp when it monitors the system-reset occurred. due to power management issue, mac will drive bbp into stand- b y mode by rstphy# signal driven low for intersil-like bbp or high for rfmd-like bbp. hbusmode i/pu 106 pull high with vdd2 for pci/cardbus operation pull low with vss2 for pcmcia operation. cbsel i/pd 71 pull high for cradbus operation. in cardbus mode, both hbusmode and cbsel are also pulled high. bbpmode[1:0] i/pu 108,109 bbp interface selection. 2?b00: for intersil-like interface. 2?b01: for rfmd-like interface. 2?b10: reserved 2?b11: for ralink bbp.
asix electronics corporation 13 AX81190 pci/cardbus/pcmcia bus wlan mac led1 o 17 indicates in transmitted state. led2 o 19 indicates in received state. eepm_dis i/pd 97 reserved, pull down with vss2 for normal operation. mt[1:0] i/pd 99,100 memory test, pull down with vss2 (2?b00) for normal operation. gpio[5:0] i/o/pd 21,22,102, 103,104,105 general pins are cotrolled by software. vdd1 p 11,16,25,38, 54,72,79,110, 126 power supply: +2.5v dc. vdd2 p 20,31,48,60, 82,87,98,116 power supply: +3.3v dc. vss1 p 3,18,27,35,51 ,57,67,90,107 ,112 ground pin for +2.5v. vss2 p 6,23,29,43,75 ,95,101,118 ground pin for +3.3v. miscellaneous pins group
asix electronics corporation 14 AX81190 pci/cardbus/pcmcia bus wlan mac 3.0 registers operation r read only rc read to clear w write only wc write ?one? to clear wo write ?one? only 3.1 pci configuration register 3.1.1 device vendor register -- offset 00h field r/w default description 31:16 r 1190h indicate the device id in pci system. 15:0 r 125bh asix vendor id. 3.1.2 command register ? offset 04h field r/w default description 15-10 r 6?b000000 reserved. 9 r 0 fast back-to-back transactions. always 0 , this function is not supported. 8 r 0 serr_ enable function. always 0 , this function is not supported. 7 r 0 address/data step function. always 0 , this function is not supported. 6 r/w 0 parity error response functi on. if set high, interface will response parity error message via perr_. if th is bit is 0, interface will ignore parity error. default:0 5 r 0 vga snooping. always 0, not supported. 4 r 0 memory write and invalid command. always 0 , interface will not generate this command. 3 r 0 special cycle response. always 0 , interface ignores all special cycle. 2 r 0 bus master control. interf ace does not support master function. 1 r/w 0 memory space response enable. 0 r/w 0 i/o space control. if it is set to ?0?, interface does not response io access, otherwise interface will response io access. 3.1.3 status register ? offset 06h field r/w default description 15 r/wc 0 perr_ detected. set to ?1 whenev er parity error is detected, write ?1? to clear. 14 r 0 serr_ detected. 13 r 0 receive master abort. 12 r 0 receive target abort. 11 r 0 target abort. 10:9 r 0 timing. 8 r 0 perr_ reported. 7 r 0 fast back-to-back capability, always 0. 6 r 0 user define features. always 0. 5 r 0 66mhz capability. always 0, interface is not supported 66 mhz. 4 r 0 capability bit. always 0. 3:0 r 4?b0000 reserved. always 4?b0000 3.1.4 revision id register ? offset 08h
asix electronics corporation 15 AX81190 pci/cardbus/pcmcia bus wlan mac bit r/w default description 7:0 r 00h current revision, the value is 01h now. 3.1.5 class code register ? offset 09h bit r/w default description 23:0 r 020000h ethernet network controller. 3.1.6 base io address register ? offset 10h bit r/w default description 31:16 r 0 reserved 15:7 r/w 0 to be mapped in 64k in space 6:1 r 0 reserved. 0 r 1 io space indicator. 3.1.7 base memory address register ? offset 14h bit r/w default description 31:8 r/w 0 to 4g memory space. 7:0 r 0 reserved. 3.1.8 cis pointer ? offset 28h 3.1.9 subsystem id ? 2ch bit r/w default description 31:16 r/w 1190h download from eeprom when power on. 15:0 r/w 125bh download from eeprom when power on. 3.1.10 interrupt register ? 3ch bit r/w default description 15:8 r 01h interrupt pin assigned. the value is always 01h. 7:0 r/w ffh interrupt line routing information. default value is ffh.
asix electronics corporation 16 AX81190 pci/cardbus/pcmcia bus wlan mac 3.2 pcmcia configuration register in pcmcia application, there are four registers, 800h, 802h, 804, and 806h located in attribute memory. 3.2.1 cor register ? 0800h field r/w default description 7 r/w 0 soft reset enable. set to ?1? to reset mac core. mac will reset this bit if it finished reset operation. this function is replaced with base_e register. 6 r 0 reserved 5:0 r/w 0 configure index, set to non-zero?s bit to enable io transfer. 3.2.2 ccr register ? 0802h field r/w default description 7:6 r 0 reseerved 5 r 0 iois8 indicator. mac always respons es 16-bit access except the memory access. 4: r 0 reserved. 3.2.3 io base (lsb) ? 0804h field r/w default description 7:0 r/w 0 for io base address pointer (lsb) 3.2.4 io base (msb) ? 0806h field r/w default description 7:0 r/w 0 for io base address pointer (msb)
asix electronics corporation 17 AX81190 pci/cardbus/pcmcia bus wlan mac 3.3 io port 3.3.1 csr index port base field r/w default description 15-8 r 0 reserved 7-0 r/w 0 selects the csr location of mac to be accessed. 3.3.2 csr data port base + 2 field r/w default description 15-0 r/w 0 16-bit data port for mac c ontrol and status register accesses. 3.3.3 tx data access control port base + 4 field r/w default description 15 r/w 0 enable for data burst. driver can set this bit to ?1?. hardware will automatically increase address when driver accesses tx data buffer port. 14:12 r/w 0 3?b111: for beacon in formation to be transmitted 3?b110: for probe response frame to be transmitted others : for general data to be transm itted. AX81190 support 6 pages for general data using. 11:0 r/w 0 address for internal tx memory access. (byte access) 3.3.4 tx data buffer port base + 6 field r/w default description 15-0 r/w 0 16-bit port for mac in ternal tx data buffer access 3.3.5 rx data access control port base + 8 field r/w default description 15 r/w 0 burst enable for access rx buffer. 14:11 r/w 0 rx buffer page pointer. there are 10 pa ges available and valid range is from 0 to 9. 10:0 r/w 0 address for internal rx buffer access. (word access) 3.3.6 rx data buffer port base + ah field r/w default description 15-0 r/w 0 16-bit port for mac internal rx data buffer access 3.3.7 soft reset port base + eh field r/w default description 15:2 r/w 0 reserved 1 r/w 0 if set to ?1?, mac will reset bbp. this bit will be reset when it was finished operation. 0 r/w 0 if set to ?1?, mac will reset internal core. when mac finished reset itself, it will reset this bit to ?0?. the reset only affect ed buffer management and protocol control unit. 3.3.8 interrupt status port base + 10h field r/w default description 15:11 r 0 reserved 10 r/wc 0 tx packet length error. 9 r 0 reserved 8 r/wc 0 tbtt time-out indication.
asix electronics corporation 18 AX81190 pci/cardbus/pcmcia bus wlan mac 7 r/wc 0 rx data indicator. when mac has r eceived data from another station and these are been stored in internal buffer. this bit will be set to 1 while data is completed in buffer. mac will interrupt host to check the status. 6 r/wc 0 tx data complete indicator. when mac has successfully sended out data and it obtains a ack returned or no needs ack, this bit will be set to high. driver can approach this bit to determine the status. 5 r/wc 0 tx fail. when mac issues a transmit frame and finds no response corresponding frame. 4 r/wc 0 tx beacon finish. 3 r/wc 0 protocol change event. this bit indicates there is a protocol changed. 2 r/wc 0 atim window end. 1 r/wc 0 soft reset complete. 0 r/wc 0 rx buffer full indication. 3.3.9 interrupt mask port base + 12h field r/w default description 15:11 r 0 reserved 10 r/w 0 set ?1? to enable corresponding event that generates interrupt. 9 r 0 reserved 8 r/w 0 set ?1? to enable corresponding event that generates interrupt. 7 r/w 0 set ?1? to enable corresponding event that generates interrupt. 6 r/w 0 set ?1? to enable corresponding event that generates interrupt. 5 r/w 0 set ?1? to enable corresponding event that generates interrupt. 4 r/w 0 set ?1? to enable corresponding event that generates interrupt. 3 r/w 0 set ?1? to enable corresponding event that generates interrupt. 2 r/w 0 set ?1?to enable corresponding event that generates interrupt. 1 r/w 0 set ?1?to enable corresponding event that generates interrupt. 0 r/w 0 set ?1?to enable corresponding event that generates interrupt. 3.3.10 rx page status port base + 14h field r/w default description 15:10 r 0 reserved 9 r/wc 0 this bit indicates that there is a packet stored in page9 of rx buffer. 8 r/wc 0 this bit indicates that there is a packet stored in page8 of rx buffer. 7 r/wc 0 this bit indicates that there is a packet stored in page7 of rx buffer. 6 r/wc 0 this bit indicates that there is a packet stored in page6 of rx buffer. 5 r/wc 0 this bit indicates that there is a packet stored in page5 of rx buffer. 4 r/wc 0 this bit indicates that there is a packet stored in page4 of rx buffer. 3 r/wc 0 this bit indicates that there is a packet stored in page3 of rx buffer. 2 r/wc 0 this bit indicates that there is a packet stored in page2 of rx buffer. 1 r/wc 0 this bit indicates that there is a packet stored in page1 of rx buffer. 0 r/wc 0 this bit indicates that there is a packet stored in page0 of rx buffer. 3.3.11 tx page status port1 base + 16h field r/w default description 15 r/wo 0 beacon packet indicator. if set to ?1? means data occupied the beacon buffer. driver set this bit to ?1? and AX81190 will reset it if it transmits out the beacon packet. 14:6 r 0 reserved. 5 r/wo 0 if set to ?1? means data occupied the page5 of tx buffer. driver set this bit to ?1? and AX81190 will reset it if it tr ansmits out the packet. 4 r/wo 0 if set to ?1? means data occupied the page4 of tx buffer. driver set this bit to ?1? and AX81190 will reset it if it tr ansmits out the packet. 3 r/wo 0 if set to ?1? means data occupied the page3 of tx buffer. driver set this bit to ?1? and AX81190 will reset it if it tr ansmits out the packet.
asix electronics corporation 19 AX81190 pci/cardbus/pcmcia bus wlan mac 2 r/wo 0 if set to ?1? means data occupied the page2 of tx buffer. driver set this bit to ?1? and AX81190 will reset it if it tr ansmits out the packet. 1 r/wo 0 if set to ?1? means data occupied the page1 of tx buffer. driver set this bit to ?1? and AX81190 will reset it if it tr ansmits out the packet. 0 r/wo 0 if set to ?1? means data occupied the page0 of tx buffer. driver set this bit to ?1? and AX81190 will reset it if it tr ansmits out the packet. 3.3.12 tx page status port2 base + 18h field r/w default description 15:6 r 0 reserved 5 rc 0 if set to ?1? means page5 fail in transmittance. 4 rc 0 if set to ?1? means page4 fail in transmittance. 3 rc 0 if set to ?1? means page3 fail in transmittance. 2 rc 0 if set to ?1? means page2 fail in transmittance. 1 rc 0 if set to ?1? means page1 fail in transmittance. 0 rc 0 if set to ?1? means page0 fail in transmittance. 3.3.13 bbp_index port base + 1ah field r/w default description 15 r/w 0 write bbp register enable bit. bbp controlling flag (open bit). if set to 1 , any access to bbp_data port register will generate serial write cycle between bbp and mac. when mac completes the access, it will reset this bit to 0. 14 r/w 0 read bbp register enable bit. if this bit is set to 1, mac will generate serial read cycle to bbp. default is 0. when mac comple tes the access, it will re set this bit to 0. 13:8 r/w 0 reserved 7:0 r/w 0 bbp internal register?s index. 3.3.14 bbp_data out port base + 1ch field r/w default description 15:8 r 0 reserved 7:0 r/w 0 contained the data will be out to bbp. 3.3.15 bbp_data in port base + 1eh field r/w default description 15:8 r 0 reserved 7:0 r/w 0 store the data read from bbp internal registers. 3.3.16 synthesizer control port base + 20h field r/w default description 15:9 r 0 reserved 8 r/w 0 start program pll phase 7 r/w 0 if pll latch enable. self-rese t if it finished programming if chip. 6 r/w 0 rf pll latch enable. self-rese t if it finished. programming rf chip. 5:0 r/w 14h contain bit-length to program pll of synthesizer. max value is 32. 3.3.17 synthesizer data port0 base + 22h field r/w default description 15:0 r/w 0 the register contains lower 16 bits data that want to program to pll of synthesizer. 3.3.18 synthesizer data port1 base + 24h field r/w default description 15:0 r/w 0 the re g ister contains hi g her 4 to 16 bits data that want to p ro g ram to pll of
asix electronics corporation 20 AX81190 pci/cardbus/pcmcia bus wlan mac synthesizer. 3.3.19 ee_data port base + 26h field r/w default description 15:0 r/w 0 16 bit data port for serial eeprom access. 3.3.20 ee_cmd/addr port base + 28h field r/w default description 15:13 r/w 0 command type. 3?b110 : read 3?b111 : erase 3?b101 : write 3?b100: erase/write enable 12 r/w 0 set to ?1? to enable write eeprom, it will be reset if mac finished the write operation. 11 r/w 0 set to ?1? to enable read eeprom, it will be reset if mac finished the read operation. driver can read base_26 port to get the data. 10 r/w 0 set to ?1? to indicate mac to verify the write operation. 9:8 r 0 reserved 7:0 r/w 0 address for serial eeprom access. ( only support 16 bit data access ) 93c56 : use a7 ~ a0, but a7 always is?0? 3.3.21 ee_status_type port base + 2ah field type default description 15:9 r 0 reserved 8 r 0 if set to ?1? means mac is currently loading data from eeprom. 5:4 r 2?b01 serial eeprom configuration indicator. 2?b01 : 93c56 supported. 3 r 0 reserved. 2:0 r 3?b001 serial eeprom clock rate indicator. 3?b001 : 1mhz..
asix electronics corporation 21 AX81190 pci/cardbus/pcmcia bus wlan mac 3.4 mac configuration status registers 3.4.1 csr1 ? mac physical address0 (padr[15:0]) field r/w default description 15:0 r 0 physical address register. when power-on, mac loads data from external eeprom and update this register once. 3.4.2 csr2 ? mac physical address1 (padr[31:16]) field r/w default description 15:0 r 0 physical address register. when power-on, mac loads data from external eeprom and update this register once. 3.4.3 csr3 ? mac physical address2 (padr[47:32]) field r/w default description 15:0 r 0 physical address register. when power-on, mac loads data from external eeprom and update this register once. 3.4.4 csr4 ? bssid matching register0, bssid[15:0] field r/w default description 15:0 r/w 0 this 16-lsb of the 48-bit address3 matching pattern. 3.4.5 csr5 ? bssid matching register1, bssid[31:16] field r/w default description 15:0 r/w 0 this 16-csb of the 48-bit address3 matching pattern. 3.4.6 csr6 ? bssid matching register2, bssid[47:32] field r/w default description 15:0 r/w 0 this 16-msb of the 48-bit address3 matching pattern. 3.4.7 csr7 ~ csr9 are reserved. 3.4.10 csr10 ? multicast filter pattern1 field r/w default description 15:0 r/w 0 this field defines the filtering pattern for multicast frame note: when m_csr29 bit6 is enabled, this register will be referred. 3.4.11 csr11 ? multicast filter pattern2 field r/w default description 15:0 r/w 0 this field defines the filtering pattern for multicast frame note: when m_csr29 bit6 is enabled, this register will be referred. 3.4.12 csr12 ? multicast filter pattern3 field r/w default description 15:0 r/w 0 this field defines the filtering pattern for multicast frame note: when m_csr29 bit6 is enabled, this register will be referred. 3.4.13 csr13 ? multicast filter pattern4 field r/w default description 15:0 r/w 0 this field defines the filtering pattern for multicast frame
asix electronics corporation 22 AX81190 pci/cardbus/pcmcia bus wlan mac note: when m_csr29 bit6 is enabled, this register will be referred. note: multicast filter matrix csr10[7:0] 7 6 5 4 3 2 1 0 csr10[15:8] 15 14 13 12 11 10 9 8 csr11[7:0] 23 22 21 20 19 18 17 16 csr11[15:8] 31 30 29 28 27 26 25 24 csr12[7:0] 39 38 37 36 35 34 33 32 csr12[15:8] 47 46 45 44 43 42 41 40 csr13[7:0] 55 54 53 52 51 50 49 48 csr13[15:8] 63 62 61 60 59 58 57 56 3.4.12 csr14 ~ csr15 are reserved. 3.4.16 csr16 ? clock pattern field r/w default description 15:12 r 0 reserved. 11:8 r/w fh rts-cts max duration 7:0 r/w 10h set to 10h if use 33mhz host clock. set to 16h if use 44mhz host clock. 3.4.17 csr17 ? wait md_rdy duration field r/w default description 7:0 r/w 14h the duration mac waited for the md_rdy, if there is plcp field is found. . 3.4.18 csr18 ? short interframe space timing register ,sifs field r/w default description 15:0 r/w 0ah this field defines th e timing slice of short interfame space timing. the timing unit is 1us. 3.4.19 csr19 ? distributed interframe space timing register, difs/pifs field r/w default description 15:0 r/w 20h this field defines the timing slice of difs space timing. the timing unit is 1us. 3.4.20 csr20 ~ csr 21 ? reserved. 3.4.22 csr22 ? slottime register (slot) field r/w default description 15:0 r/w 14h the slot time register is written to by some proper values by the driver. it determines the unit of the backoff time. the unit of the register value is in s. 3.4.23 csr23 ? backoff timing field r/w default description 15:0 r 0 to show the backoff timing of mac. 3.4.24 csr24 ? rf3000 modulation duration (testing) field r/w default description 15:0 r/w 4000h available when rf3000 bbp is used. 3.4.25 csr25 ? power testing and misc field r/w default description
asix electronics corporation 23 AX81190 pci/cardbus/pcmcia bus wlan mac 15 r/w 0 1: tx power enable. 0: none 14 r/w 0 tx power pattern. 13 r/w 0 1: tx power toggle enable. 0: none 12 r/w 0 reserved 11 r/w 0 1: enable software control 0: none 10 r/w 0 reserved 9 r/w 0 reserved 8 r/w 0 software control syndata 7 r/w 0 software control synclk 6 r/w 0 software control le_rf# 5 r/w 0 software control rf_pe 4 r/w 0 software control pe2. 3 r/w 0 software control pe1 2 r/w 0 software control pa_pe 1 r/w 0 software control rx_pe 0 r/w 0 software control tx_pe 3.4.26 csr26 ? txvgc adjust register (support rf3000 only) field r/w default description 7 r/w 0 0: long preamble 1: short preamble 6:1 r/w 25h gain setting for transmission. 0 r/w 0 scrambler indication. 0 : enable 1: disable 3.4.27 csr27 ? tx beacon/probe response enable register field r/w default description 7:2 r 0 reserved. 1 r/w 0 1: enable mac to grab data from beacon buffer and transmit the data. the data is especially for probe response frame used and max length can not exceed 512 byte. 0 r/w 0 1: enable mac to grab data from beacon buffer and transmit the data. mac will reset this bit if it finished the transmittance. the max length can not exceed 512 byte. 3.4.28 csr28 ? tbtt compensation register field r/w default description 15:10 r 0 reserved 9:0 r/w 0 this 10- b it register, which is used to compensate the calculation delay of tbtt generation circuit. it can also be used to compensate the driver?s processing delay to generate a beacon frame. the unit of the value is in s. 3.4.29 csr29 ? rx filtering register field rw default description 15:11 r/w 0 reserved 10 r/w 0 multicast algorithm selection. 0: select xor 1: select crc32. 9 r/w 0 1: enable rx length filtering. 8 r/w 0 1: force rx enable. (always enable rx_pe to be high)
asix electronics corporation 24 AX81190 pci/cardbus/pcmcia bus wlan mac 7 r/w 0 enable broadcast reception. if set to 0, all broadcast frames will be dropped. 6 r/w 0 enable multicast filtering. if set to 1, only the multicasts whose address1 field matches the matching criteria will be passed to the driver. the default is 0. 5 r/w 0 enable multicast reception. if set to 1, multicast frames will be received, and no logical address matching will be performed. 4 r/w 0 reserved 3 r/w 0 crc32 check enabled. if set to 1, the crc32 fields with will be verified. 2 r/w 0 control frame enable. if set to 1, a ll control frames received will be passed to the driver. 1 r/w 0 promiscuous mode enabled. if set to 1, all data/mgmt frames will be passed to the driver. 0 r/w 0 rx enable. this bit defi nes whenever mac can receive da ta. driver must set this bit to ?1? to enable receive mode. 3.4.30 csr30 ? tx power ramp-up control register1 field rw default description 15:0 r/w 0ah this field defines the tx_pe lagged time when rx_pe was driven low. 3.4.31 csr31 ? tx power ramp-up control register2 bit rw default description 15:0 r/w 14h this field defines pe2 lagged time when rx_pe was driven low. 3.4.32 csr32 ? tx power ramp control register3 bit r/w default description 15:0 r/w 1bh this field defines the pa_pe lagged time when rx_pe was driven low. 3.4.33 csr33 ? tx power ramp control register4 bit r/w default description 15:0 r/w 46h this field defines the tr_sw lagged time when rx_pe was driven low. 3.4.34 csr34 ? tx power ramp control register5 bit r/w default description 15:0 r/w bdh this field defines the duration before rx_pe asserted. the start point is based on last bit to be transmitted. 3.4.35 csr35 ? beaconperiod (bp) field r/w default description 15:0 r/w 0200h this 16 bit register, which is used to uniquely define the ta rget beacon transmission time (tbtt). the unit of the value is kus. 3.4.36 csr36 ? tx retry counter field rw default description 7:0 r/w 10h tx retry counter. this register defines the retry number. mac will assert a packet, if there is no relative frame returned. 3.4.37 csr37 ? mac feature register field r/w default description 15 r/w 0 the duration field of rts frame is from data or information header. 1: from data. 0: from information header. 14 r/w 0 1: enable nav mechanism for channel status.
asix electronics corporation 25 AX81190 pci/cardbus/pcmcia bus wlan mac 13 r/w 1 1: disable to set intersil 3861 cr31 register 0: mac will set the inters il 3861 before transmittance. 12 r/w 0 pe2 polarity. 11 r/w 0 1 : to reset tsf timer, mac will clear this bit when the reset is finished. 10 r/w 0 1:tx stop normal page. driver set this bit to stop the transmittance. 9 r/w 0 1:tx stop urgent page. driver set this bit to stop the transmittance. 8 r/w 1 inbuf overflow protect. 1: protect when inbuf is full. data will not be written to inbuf. 0: no protect. data will be written to inbuf , regardless of inbuf whether it is full or not. 7 r/w 0 backoff procedure disable. when set to 1, backoff procedur e will ignore. mac will be prepared to request medium immediately whenever it has data to be sent. 6 r/w 0 cca enable. 5 r/w 0 cca polarity for channel available. (rfmd) 4 r/w 0 to indicate mac employs 3-wire or 4-wire approach to program bbp. 0: 3-wire, use cs#, sclk and sd signals. 1: 4-wire, use cs#, sclk, sd and rw# signals. 3 r/w 0 1: latch sq enable. 0: nothing 2 r/w 0 1: latch rssi enable. 0: nothing 1 r/w 1 pe1 polarity. 0: active low 1: active high. 0 r/w 0 rf_pe (radio-pd) polarity. 0: active low 1: active high 3.4.38 csr38 is reserved 3.4.39 csr39 ? transmit page control register field r/w default description 7 r/w 0 if this bit is set, it claims this trans action has the priority; otherwise, it is a normal transmittance. 6:3 r/w 0 reserved 2:0 r/w 0 driver set this field to claim which the page data will be transmitted. 2?b000: page0 to be transmitted. 2?b001: page1 to be transmitted. 2?b010: page2 to be transmitted. 2?b011: page3 to be transmitted. 2?b100: page4 to be transmitted. 2?b101: page5 to be transmitted. 3.4.40 csr40 ? tx rate control register. field r/w default description 15 r 0 reserved 14:12 r/w 3?b000 rts speed control 3?b000: auto 3?b001: 1m 3?b010: 2m 3?b011: 5.5m 3?b100: 11m others: reserved 11 r 0 reserved 10:8 r/w 3?b000 ack/cts speed control
asix electronics corporation 26 AX81190 pci/cardbus/pcmcia bus wlan mac 3?b000: auto 3?b001: 1m 3?b010: 2m 3?b011: 5.5m 3?b100: 11m others: reserved 7:5 r 0 reversed. 4 0 tx/rx filter cmf weight. 0 = u.s. 1=japan. 3 r/w 0 select preamble mode 0= normal, long preamble 1= short preamble and header mode. 2:0 r 0 reserved bit7 ~ bit0 is only for intersil 3861/3863. 3.4.41 csr41 ? response time-out register field r/w default description 15:0 r/w 0145h mac will count the time when it desi res cts/ack returned. the time unit is us. 3.4.42 csr42 ? rssi-sq location register field r/w default description 15:8 r/w 72h sq location in bbp 7:0 r/w 7ch rssi location in bbp. for 3861 set to 727ch for r3000 set to xx03h. 3.4.43 csr43 ? tsf compensate register field r/w default description 15 r/w 0 this bit defines how many us need to compensate the tsf timer when mac transmitted beacon frame. 0: mac will add bit[14:0] value to tsf timer. 1: mac will deduct bit[14:0] value from tsf timer and inserted the final value to frame body of beacon. 14:0 r/w 0 compensate value for tsf. this unit is us. 3.4.44 csr44 ? calibration adjust register field r/w default description 15 r/w 0 calibration enable. if set, mac will drive cal_en pin. driver set this bit to 1 to enable calibration mode. if mac finished calibration, it will reset it to 0. 14 r/w 0 set to ?1? to enable cal_en until it?s cleared. 13:0 r/w 64h this field defines how many us of calibration mode driven by mac when bit15 is set to ?1? 3.4.45 csr45 ? bbp plcp service/signal field location register ( for intersil 3861/3863) field r/w default description 15:8 r/w 0ch this field defines the index of bbp tx service field register. 7:0 r/w 0ah this field defines the index of bbp tx signal field register. 3.4.46 csr46 ? bbp plcp length field location register (for intersil 3861/3863)
asix electronics corporation 27 AX81190 pci/cardbus/pcmcia bus wlan mac field r/w default description 15:8 r/w 10h this field defines the index of bbp tx length field, low, register. 7:0 r/w 0eh this field defines the index of bbp tx length field, high, register. 3.4.47 csr47 is reserved 3.4.48 csr48 ? software reset duration field r/w default description 15:0 r/w 200h this register defines the dura tion of mac generates the reset signal. 3.4.49 csr49 ? cfp duration register field r/w default description 15:0 r/w 0 cfp duration is set by driver. the time unit is k s. 3.4.50 csr50 ? atim duration register field r/w default description 15:0 r/w 0 atim duration is set by driver. the time unit is k s.. 3.4.51 csr51 ? 802.11 protocol status field r/w default description 7:2 r 0 reserved 1 r/w 0 1: atim start 0: nothing driver set this bit to claim the beginning of atim, hardware will reset it and generate interrupt when the atim is expired. 0 r/w 0 1: pcf status 0: dcf status driver set this bit to indicate mac behavi or. mac will reset from pcf to dcf, if it recognizes cf_end packet. 3.4.52 csr52 ? mac mode status field r/w default description 7 r/w 0 this bit indicates mac to response cf_ack when mac is as ap in pcf. 0: none 1: enable 6 r/w 0 1: driver issue beacon enable. driver also needs to set m_csr27 bit0 to assert a beacon transmittance. 5 r/w 0 1: hardware auto generate beacon enable. 4 r/w 0 1: enable hardware automatically parse beacon frame. 3 r/w 0 1: enable atim window counter begin to down count. 2 r/w 0 1: enable cfp counter begin to down count 1 r/w 0 1: ap mode 0 r/w 0 1: ibss mode 3.4.53 csr53 ? bbp mode field r/w default description 7:2 r 0 reserved 1:0 r 0 00 : support intersil 3861/3863 bbp 01: support rfmd rf3000 bbp 10: reserved. 11: for ralink 2430 bbp
asix electronics corporation 28 AX81190 pci/cardbus/pcmcia bus wlan mac 3.4.54 csr54 ? spi chip address field r/w default description 15:8 r/w 0 reserved 7:0 r/w 40h chip address for rf3000. employ bit7 ~ bit1, bit0 is r/w control support rfmd r3000 spi interface 3.4.55 csr55 ~ csr59 reserved . 3.4.60 csr60 crc32 counter field r/w default description 15:0 r 0 this counter defi nes the number of crc32. 3.4.61 csr61 is reserved. 3.4.62 csr62 ? nav timer field r/w default description 15:0 r 0 this timer is updated by rts, cts and data from arrive at the station. rts, cts and data frames include a field that i ndicates the expected length of the rts-cts-data-ack exchange. the mac used this value to update nav timer. if any portion of rts-cts-data-ack exchange is missing, then a mac timer will timeout and the nav is reset to zero. the time unit is us. 3.4.63 csr63 ? tsf timer register0 (tsfr[15:0]) field r/w default description 15:0 r 0 local timer. mac will adopt the timer information in beacon or in probe response (from ap). if mac?s tsf timer is different from the timestamp in received beacon, mac would set tsf timer when it received. 3.4.64 csr64 ? tsf timer register1 (tsfr[31:16]) field r/w default description 15:0 r 0 local timer. mac will adopt the timer information in beacon or in probe response (from ap). if mac?s tsf timer is different from the timestamp in received beacon, mac would set tsf timer when it received. 3.4.65 csr65 ? tsf timer register2 (tsfr[47:32]) field r/w default description 15:0 r 0 local timer. mac will adopt the timer information in beacon or in probe response (from ap). if mac?s tsf timer is different from the timestamp in received beacon, mac will set tsf timer as it received. 3.4.66 csr66 ? tsf timer register3 (tsfr[63:48]) field r/w default description 15:0 r 0 local timer. mac will adopt the timer information in beacon or in probe response (from ap). if mac?s tsf timer is different from the timestamp in received beacon, mac will set tsf timer as it received. 3.4.67 csr67 ~ csr69 reserved. 3.4.70 csr70 ? not my unicast frame counter field r/w default description 15:0 r 0 the counter is creased b y 1 when mac receives a data or mana g ement frame that does
asix electronics corporation 29 AX81190 pci/cardbus/pcmcia bus wlan mac not hit to me. (not included control frame) 3.4.71 csr71 ? broadcast and multicast counter field r/w default description 15:0 r 0 the counter is creased by 1 when m ac receives a broadcast or multicast (not my) frame. 3.4.72 csr72 ? rssi-sq value field r/w default description 15:8 r/w 0 sq value from bbp, if m_csr37 bit3 is set to ?1? 7:0 r/w 0 this field defines the rssi value from bbp when m_csr37 bit2 is set to ?1?. its range is from 0 to 255 db. 3.4.73 csr73 ? outbuf/inbuf current page pointer field r/w default description 15 r 0 current transmission. 14 r 0 driver starts tx. (data is not yet transmitted by mac) 13 r 0 priority queue status. 1: queue is not empty. 0: queue is empty. 12 r 0 normal queue status. 1: queue is not empty. 0: queue is empty. 11:10 r 0 reserved 9:8 r 0 outbuf current page pointer. 7:3 r 0 reserved 2:0 r/w 0 point to the next page that is written to inbuf . 3.4.74 csr74: tx power ramp-down control register1 bit r/w default description 15:0 r/w 5ah this field defines the duration before tr_sw released. the start point is based on last bit to be transmitted. it is about 4.04 us. 3.4.75 csr75: tx power ramp-down control register2 bit r/w default description 15:0 r/w 8ah this field defines the duration before pa_pe released. the start point is based on last bit to be transmitted. it is about 6.2us. 3.4.76 csr76: tx power ramp-down control register3 bit r/w default description 15:0 r/w e0h this field defines the duration before pe2 released. the start point is based on last bit to be transmitted. it is about 6.5 we. 3.4.77 csr77: tx power ramp-down control register4 bit r/w default description 15:0 r/w f0h this field defines the duration before tx_pe released. the start point is based on last bit to be transmitted. it is about 6.92us. 3.4.78 csr78: rx_pe de-asserted duration bit r/w default description
asix electronics corporation 30 AX81190 pci/cardbus/pcmcia bus wlan mac 15:0 r/w 5bh this field defines rx_pe de-asserted duration in rx state ending. in rx state, rx_pe will be high until th e receive finished. if there is no any data to be transmitted, the rx_p e will be de-asserted about 4.1 us then asserted. the duration is about 3.9 ~ 4.2 us. 3.4.79 csr79: min size of rx packet bit r/w default description 15:0 r/w 15 this register defines the min packet size of rx 3.4.80 csr80: gpio status control bit r/w default description 7:6 r 2?b00 reserved 5 r/w 1 0: enable goip5 as output 4 r/w 1 0: enable goip4 as output 3 r/w 1 0: enable goip3 as output 2 r/w 1 0: enable goip2 as output 1 r/w 1 0: enable goip1 as output 0 r/w 1 0: enable goip0 as output 3.4.81 csr81: gpio data port bit r/w default description 15:14 r 2?b00 reserved 13:8 r/w 5?h0 the data will to be output from gpio[5:0], if the respective bit is set. 7:6 r 2?b00 reserved 5:0 r 5?h0 indicate the status from gpio[5:0] pin. 3.4.82 csr82: wep control bit r/w default description 7:3 r 0 reserved 2 r/w 0 0: 64 bit wep key 1: 128 bit wep key 1 r/w 0 1: enable rx wep(decryption) 0 r/w 0 1: enable tx wep(encryption) 3.4.83 wep key matrix (csr83 ~ csr110, 16 bit registers) 128 bit 64 bit key id0 csr83 csr84 csr85 csr86 cs87 csr88 csr89[7:0] key id1 csr90 csr91 csr92 csr93 csr94 csr95 csr96[7:0] key id2 csr97 csr98 csr99 csr100 csr101 csr102 csr103[7:0] key id3 csr104 csr105 csr106 csr107 csr108 csr109 csr110[7:0] note: in 64-bit mode, csr85, csr92, csr99, csr106 only used bit7 ~ b0
asix electronics corporation 31 AX81190 pci/cardbus/pcmcia bus wlan mac 4.0 pcmcia device access functions the AX81190, as a pcmcia i/o device, needs support both attribute memory access function and i/o access function. the access methods are described as the following sections. 4.1 attribute memory access functions. attribute memory read function function mode reg# ce2# ce1# sa0 oe# we# d[15:8] d[7:0] standby mode x h h x x x high-z high-z byte access (8 bits) l l h h l l l h l l h h high-z high-z even-byte not valid word access (16 bits) l l l x l h not valid even-byte odd byte only access l l h x l h not valid high-z attribute memory write function function mode reg# ce2# ce1# sa0 oe# we# sd[15:8] sd[7:0] standby mode x h h x x x x x byte access (8 bits) l l h h l l l h h h l l x x even-byte x word access (16 bits) l l l x h l x even-byte odd byte only access l l h x h l x x 4.2 i/o access functions. i/o read function function mode reg# ce2# ce1# sa0 oe# we# d[15:8] d[7:0] standby mode x h h x x x high-z high-z byte access (8 bits) l l h h l l l h l l h h high-z high-z even-byte odd-byte word access (16 bits) l l l l l h odd-byte even-byte i/o inhibit h x x x l h high-z high-z odd byte only access l l h x l h odd-byte high-z i/o write function function mode reg# ce2# ce1# sa0 iord# iowr# d[15:8] d[7:0] standby mode x h h x x x x x byte access (8 bits) l l h h l l l h h h l l x x even-byte odd-byte word access (16 bits) l l l l h l odd-byte even-byte i/o inhibit h x x x h l x x odd byte only access l l h x h l odd-byte x
asix electronics corporation 32 AX81190 pci/cardbus/pcmcia bus wlan mac 5.0 electrical specification and timings 5.1 absolute maximum ratings description min max units operating temperature -40 +125 c storage temperature -65 +150 c supply voltage -0.3 +4.6 v input voltage -0.3 5.5 v output voltage -0.3 4.6 v note : stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for exte nded period, adversely affect device life and reliability. note : the power supply voltages must always fulfill hvdd >= lvdd inequality. 5.2 general operation conditions description min tpy max units operating temperature 0 25 +75 c supply voltage vdd1 +2.25 +2.5 +2.75 v supply voltage vdd2 +3.00 +3.30 +3.60 v 5.3 dc characteristics (vdd2=3.3v, vss2=0v, ta=0 c to 75 c) description sym min tpy max units low input voltage vil -0.3 0.8 v high input voltage vih 2 5.5 v low output voltage vol - 0.4 v high output voltage voh 2.4 - v input leakage current iil -1 +1 ua output leakage current iol -1 +1 ua description sym min tpy max units power consumption spt3v tbd ma
asix electronics corporation 33 AX81190 pci/cardbus/pcmcia bus wlan mac 5.4 a.c. timing characteristics 5.4.1 clock hclk tr tf tlow symbol description min typ. max units tcyc cycle time 22 30 ns thigh clk high time 10 15 20 ns tlow clk low time 10 15 20 ns tr/tf clk slew rate 1 - 4 ns note: for pci/cardbus , the clock rate is recommended 33mhz 5.4.2 pcmcia reset timing hclk hrst symbol description min typ. max units trst reset pulse width 100 - - hclk pci reset timing hclk hrst# symbol description min typ. max units trst reset pulse width 10 - - pci clk tcyc thigh
asix electronics corporation 34 AX81190 pci/cardbus/pcmcia bus wlan mac 5.4.3 pcmcia attribute memory read timing tcr ta(a) th(a) sa[13:0], reg# ta(ce) tv(a) tsu(ce) ce# tsu(a) ta(oe) th(ce) oe# tv(wt-oe) tw(wt) tdis(ce) wait# ten(oe) tv(wt) tdis(oe) sd[15:0] data valid symbol description min typ. max units tcr read cycle time 300 - - ns ta(a) address access time - - 120 ns ta(ce) card enable access time - - 100 ns ta(oe) output enable access time - - 100 ns tdis(oe) output disable time from oe# 0.5 - - ns ten(oe) output enable time from oe# - - 100 ns tv(a) data valid from address change 0 - - ns tsu(a) address setup time 30 - - ns th(a) address hold time 20 - - ns tsu(ce) card enable setup time 0 - - ns th(ce) card enable hold time 20 - - ns tv(wt-oe) wait# valid from oe# - - 10 ns tw(wt) wait# pulse width - - 200 ns tv(wt) data setup for wait# released 100 - - ns
asix electronics corporation 35 AX81190 pci/cardbus/pcmcia bus wlan mac 5.4.4 pcmcia attribute memory write timing tcw sa[13:0], reg# tsu(ce-weh) ce# tsu(ce) tsu(a-weh) th(ce) oe# tsu(a) tw(we) trec(we) we# tv(wt-we) tv(wt) tw(wt) th(oe-we) wait# tsu(oe-we) tsu(d-weh) th(d) sd[15:0](din) data input establish tdis(we) ten(oe) tdis(oe) ten(we) sd[15:0](dout) symbol description min typ. max units tcw write cycle time 250 - - ns tw(we) write pulse width 150 - - ns tsu(a) address setup time 30 - - ns tsu(a-weh) address setup time for we# 180 - - ns tsu(ce-weh) card enable setup time for we# 180 - - ns tsu(d-weh) data setup time for we# 80 - - ns th(d) data hold time 30 - - ns trec(we) write recover time 30 - - ns tdis(we) output disable time from we# - - 5 ns tdis(oe) output disable time from oe# - - 5 ns ten(we) output enable time from we# 5 - - ns ten(oe) output enable time from oe# 5 - - ns tsu(oe-we) output enable setup time from oe# 10 - - ns th(oe-we) output enable hold time from oe# 10 - - ns tsu(ce) card enable setup time 0 - - ns th(ce) card enable hold time 20 - - ns tv(wt-we) wait# valid from we# - - 15 ns tw(wt) wait# pulse width - - 200 ns tv(wt) we# high from wait# released 0 - - ns
asix electronics corporation 36 AX81190 pci/cardbus/pcmcia bus wlan mac 5.4.5 pcmcia i/o read timing sa[13:0] tha tsureg threg reg# tsuce thce ce# tw iord# tsua tdrinpack inpack# tdfinpack tdriois16 iois16# tdfiois16 td tdr(wt) wait# tdfwt tw(wt) th sd[15:0] data valid symbol description min typ. max units td data delay after iord# - - 50 ns th data hold following iord# 0.5 - - ns tw iord# width time 165 - - ns tsua address setup before iord# 70 - - ns tha address hold before iord# 20 - - ns tsuce ce# setup before iord# 5 - - ns thce ce# hold before iord# 20 - - ns tsureg reg# setup before iord# 5 - - ns threg reg# hold before iord# 0 - - ns tdfinpack inpack# delay falling from iord# 0 - 10 ns tdrinpack inpack# delay rising from iord# - - 10 ns tdfiois16 iois16# delay falling from address* - - 10 ns tdriois16 iois16# delay rising from address* - - 0 ns tdfwt wait# delay falling from iord# - - 5 ns tdr(wt) data delay from wait# rising - - 0 us tw(wt) wait# width time - - 100 ns * note : the address includes reg# and ce1# signal
asix electronics corporation 37 AX81190 pci/cardbus/pcmcia bus wlan mac 5.4.6 pcmcia i/o write timing sa[13:0] tha tsureg threg reg# tsuce thce ce# tw iowr# tsua tdriois16 iois16# tdfiois16 tdriowr wait# tdfwt tw(wt) th tsu sd[15:0] data symbol description min typ. max units tsu data setup before iowr# 60 - - ns th data hold following iowr# 30 - - ns tw iowr# width time 165 - - ns tsua address setup before iowr# 70 - - ns tha address hold before iowr# 20 - - ns tsuce ce# setup before iowr# 5 - - ns thce ce# hold before iowr# 20 - - ns tsureg reg# setup before iowr# 5 - - ns threg reg# hold before iowr# 0 - - ns tdfiois16 iois16# delay falling from address* - - 10 ns tdriois16 iois16# delay rising from address* - - 0 ns tdfwt wait# delay falling from iowr# - - ** ns tw(wt) wait# width time - - ** ns tdriowr iowr# high from wait# high 0 - - us *note : the address includes reg# and ce1# signal ** note : there is no wait state while i/o write operation
asix electronics corporation 38 AX81190 pci/cardbus/pcmcia bus wlan mac 5.4.7 synthesizer timings tch tcl tclk synclk le_if# le_rf# trs tfh tfh syndata d[n] d[n-1] d[n-2] d[2] d[1] d[0 ] symbol description min typ. max units ttclk cycle time - 90 - ns tch high time 14 - 26 ns tch low time 14 - 26 ns trs clock rising edge to data valid setup time 6 - - ns tfh clock falling edge to data output hold time 5 - - ns tth data output hold time 5 - - ns
asix electronics corporation 39 AX81190 pci/cardbus/pcmcia bus wlan mac 5.4.8 serial port timings tclk tch tcl sclk cs# rw# (read) trs tfh tfh sd a[7] a[6] ? a[0] d[7] d[6] d[0] (read) rw# (write) trs tfh tfh sd a[7] a[6] ? a[0] d[7] d[6] d[0] (write) spi_do
asix electronics corporation 40 AX81190 pci/cardbus/pcmcia bus wlan mac 5.4.9 tx path waveforms txdata txclk t tx_rdy tx_rdy tx_pe2 figure. tx path
asix electronics corporation 41 AX81190 pci/cardbus/pcmcia bus wlan mac 5.4.10 rx path waveforms rxdata rxclk t surx_rdy rx_rdy rx_pe2 t drx_pe2 t hrx_rdy t wrx_pe2 t ccaf figure. rx path
asix electronics corporation 42 AX81190 pci/cardbus/pcmcia bus wlan mac 6.0 package information b e d hd e he pin 1 a2 a1 l l1 a milimeter symbol min. nom max a1 0.1 a2 1.3 1.4 1.5 a 1.7 b 0.155 0.16 0.26 d 13.90 14.00 14.10 e 13.90 14.00 14.10 e 0.40 hd 15.60 16.00 16.40 he 15.60 16.00 16.40 l 0.30 0.50 0.70 l1 1.00 0 10
asix electronics corporation 43 AX81190 pci/cardbus/pcmcia bus wlan mac appendix a: application note 1 a.1 external eeprom format external eeprom format: addr description 0 cis pointer (x) 1 physical addr[15:0] 2 physical addr[31:16] 3 physical addr[47:32] 4 subsystem id[15:0] 5 subsystem id[31:16] 6 ~ 10 reserved 11 ~ x for driver used x cis area x + 1 cis area max addr index is 127 (93c56 ? 16 bit)

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