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asix electronics corporation first released date : july/31/2000 2f, no.13, industry east rd. ii, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-579-9500 fax: 886-3-579-9558 http:// www.asix.com.tw ax88796 l 3-in-1 local bus fast ethernet controller 10/100base 3-in-1 local cpu bus fast ethernet controller with embedded sram document no.: ax796-19 / v1.9 / aug, 19, 03 features ? highly integrated with embedded 10/100mbps mac, phy and transceiver ? embedded 8k * 16 bit sram ? compliant with ieee 802.3/802.3u 100base-tx/fx specification ? ne2000 register level compatible instruction ? single chip local cpu bus 10/100mbps fast ethernet mac controller ? support both 8 bit and 16 bit local cpu interfaces include mcs-51 series, 80186 series and mc68k series cpu ? support both 10mbps and 100mbps data rate ? support both full-duplex or half-duplex operation ? provides an extra mii port for supporting other media. for example, home lan application ? support eeprom interface to store mac address ? external and internal loop-back capability ? support standard print port for printer server application ? support upto 3/1 general purpose in/out pins ? 128-pin lqfp low profile package ? low power consumption, typical under 100ma ? 0.25 micron low power cmos process. 25mhz operation, pure 3.3v operation with 5v i/o tolerance. *ieee is a registered tradem ark of the institute of electrical and electroni c engineers, inc. *all other trademarks and registered trademark are the property of their respective holders. product description the ax88796 fast ethernet controller is a high performance and highly integrated local cpu bus ethernet controller with embedded 10/100mbps phy/transceiver and 8k*16 bit sram. the ax88796 supports both 8 bit and 16 bit local cpu interfaces include mcs-51 series , 80186 series, mc68k series cpu and isa bus. the ax88796 implements both 10mbps and 100mbps ethernet function based on ieee802.3 / ieee802.3u lan standard. the ax88796 also provides an extra ieee802.3u compliant media-i ndependent interface (mii) to support ot her media applica tions. using mii interface, home lan phy type media can be supported. as well as, the chip also provides optiona l standard print port ( parallel port inte rface ), can be used for printer server device or treat as simple general i/o port. the chip al so support upto 3/1 additional ge neral purpose in/out pins system block diagram always contact asix for possible updates before starting a design. this data sheet contains new products information. asix electr onics reserves the rights to m odify product sp ecification withou t notice. no liability is assumed as a result of the us e of this product. no rights under any pa tent accompany the sale of the product. 8051 cpu latch ax88796 with 10/100 mbps phy/txrx ad bus addr l addr h ctl bus rj45 optional home lan phy rj11 optional print port or general i/o ports
asix electronics corporation 2 ax88796 l 3-in-1 local bus fast ethernet controller contents 1.0 introduction............................................................................................................... .......................................5 1.1 g eneral d escription : .............................................................................................................................. .............5 1.2 ax88796 b lock d iagram : .............................................................................................................................. ......5 1.3 a ax88796 p in c onnection d iagram ...................................................................................................................6 1.3 b ax88796 p in c onnection d iagram with spp p ort o ption ............................................................................7 1.3.1 ax88796 pin connection di agram for isa bus mode .......................................................................... ...........8 1.3.2 ax88796 pin connection diagram for 80x86 mode ............................................................................ ............9 1.3.3 ax88796 pin connection diagram for mc68k mode ............................................................................ .......10 1.3.4 ax88796 pin connection diagram for mcs-51 mode........................................................................... ........11 2.0 signal description......................................................................................................... ...............................12 2.1 l ocal cpu b us i nterface s ignals g roup .......................................................................................................12 2.2 10/100m bps t wisted -p air i nterface pins group ..............................................................................................13 2.3 b uilt - in phy led indicator pins group ..........................................................................................................13 2.4 eeprom s ignals g roup ............................................................................................................................... ......14 2.5 mii interface signals group (o ptional ) ..........................................................................................................14 2.6 s tandard p rinter p ort (spp) i nterface pins group (o ptional ) ..................................................................15 2.7 g eneral p urpose i/o pins group ................................................................................................15 2.8 m iscellaneous pins group ............................................................................................................................... ..16 2.9 p ower on configuration setup signals cross reference table .......................17 3.0 memory and i/o mapping ..................................................................................................... .......................18 3.1 eeprom m emory m apping ............................................................................................................................... .18 3.2 i/o m apping ............................................................................................................................... ...........................18 3.3 sram m emory m apping ............................................................................................................................... ......18 4.0 basic operation ........................................................................................................... ..................................19 4.1 r eceiver f iltering ............................................................................................................................... ...............19 4.1.1 unicast address match filter ............................................................................................. ............................19 4.1.2 multicast addr ess match filter........................................................................................... ............................19 4.1.3 broadcast address match filter ........................................................................................... ..........................20 4.1.4 aggregate address filter w ith receive confi guration setup................................................................ ..........20 4.2 b uffer m anagement o peration ........................................................................................................................22 4.2.1 packet reception ......................................................................................................... ....................................22 4.2.2 packet transmision ....................................................................................................... ..................................25 4.2.3 filling packet to transmit bu ffer (host fill data to memory) ............................................................. ............27 4.2.4 removing packets from the ri ng (host read data from memory).............................................................. .....28 4.2.5 other useful operations .................................................................................................. ...............................31 5.0 registers operation........................................................................................................ ............................32 5.1 mac c ore r egisters ............................................................................................................................... ...........32 5.1.1 command register (cr) offset 00h (read/write) ........................................................................... .............34 5.1.2 interrupt status register (isr) offs et 07h (read/write) ................................................................. ..............34 5.1.3 interrupt mask register (imr) offset 0fh (write)........................................................................ .................35 5.1.4 data configuration register (dcr) offset 0eh (write) .................................................................... ...........35 5.1.5 transmit configuration regist er (tcr) offset 0dh (write) ................................................................ .........35 5.1.6 transmit status register (tsr) offset 04h (read) ........................................................................ ................36 5.1.7 receive configuration (r cr) offset 0ch (write) .......................................................................... ...............36 5.1.8 receive status register (rsr) offset 0ch (read) ......................................................................... ................36 5.1.9 inter-frame gap (ifg) offset 16h (read/write) ........................................................................... .................37 5.1.10 inter-frame gap segment 1(ifg s1) offset 12h (read/write)............................................................... .......37 5.1.11 inter-frame gap segment 2(ifg s2) offset 13h (read/write)............................................................... .......37 5.1.12 mii/eeprom management register (memr) offset 14h (read/write).....................................................37 5.1.13 test register (tr) offset 15h (write).................................................................................. ........................37 5.1.14 test register (tr) offset 15h (read) ................................................................................... .......................38 5.1.15 general purpose input regist er (gpi) offset 17h (read) ................................................................. .........38
asix electronics corporation 3 ax88796 l 3-in-1 local bus fast ethernet controller 5.1.16 gpo and control (gpoc) offset 17h (write) .............................................................................. ..............38 5.1.17 spp data port register (spp_ dpr) offset 18h (read/write) ............................................................... ....39 5.1.18 spp status port register (spp_spr) offset 19h (read) ................................................................... .........39 5.1.19 spp command port register (spp_ cpr) offset 1a h (read/write)...........................................................3 9 5.2 t he e mbedded phy r egisters ...........................................................................................................................40 5.2.1 mr0 -- control regi ster bit de scriptions................................................................................. ......................41 5.2.2 mr1 -- status regi ster bit de scriptions .................................................................................. .......................42 5.2.3 mr2, mr3 -- identification regi sters (1 and 2) b it descriptions.......................................................... .........43 5.2.4 mr4 ? autonegotiation advertisem ent registers b it descriptions........................................................... ......43 5.2.5 mr5 ? autonegotiation link partner ability (base page) register bit descriptions.....................................43 5.2.6 mr5 ?autonegotiation link partner(lp)ability register (n ext page)bit descriptions.................................44 5.2.7 mr6 ? autonegotiation expansi on register bit descriptions ................................................................ ........44 5.2.8 mr7 ?next page transmit register bit descriptions ........................................................................ .............45 5.2.9 mr16 ? pcs control re gister bit de scriptions ............................................................................. ................45 5.2.10 mr17 ?autonegotiation regi ster a bit de scriptions....................................................................... .............46 5.2.11 mr18 ?autonegotiation regi ster b bit de scriptions....................................................................... .............46 5.2.12 mr20 ?user defined re gister bit de scriptions ............................................................................ ...............46 5.2.13 mr21 ?rxer counter regi ster bit de scriptions ............................................................................ .............47 5.2.14 mr28 ?device-specific register 1 (status register) bit descri ptions ..................................................... ....47 5.2.15 mr29 ?device-specific register 2 (100mbps control) bit descri ptions ..................................................... 48 5.2.16 mr30 ?device-specific register 3 (10mbps control) bit descri ptions ...................................................... .49 5.2.17 mr31 ?device-specific register 4 (quick status) b it descriptions ........................................................ .....50 6.0 cpu i/o read and write functions.......................................................................................... .............51 6.1 isa bus type access functions . .........................................................................................................................51 6.2 80186 cpu bus type access functions ..............................................................................................................51 6.3 mc68k cpu bus type access functions ...........................................................................................................52 6.4 mcs-51 cpu bus type access functions . .........................................................................................................52 6.5 cpu a ccess mii s tation m anagement functions ..........................................................................................53 7.0 electrical specification and timings ...................................................................................... .....54 7.1 a bsolute m aximum r atings ..............................................................................................................................5 4 7.2 g eneral o peration c onditions ........................................................................................................................54 7.3 dc c haracteristics ............................................................................................................................... .............54 7.4 a.c. t iming c haracteristics .............................................................................................................................55 7.4.1 xtal / clock ............................................................................................................. ..................................55 7.4.2 reset timing............................................................................................................. .......................................55 7.4.3 isa bus access timing.................................................................................................... ................................57 7.4.4 80186 type i/o access timing............................................................................................. ...........................58 7.4.5 68k type i/ o access timing ............................................................................................... ............................59 7.4.6 8051 bus access timing................................................................................................... ...............................60 7.4.7 mii timing ............................................................................................................... .......................................61 8.0 package information ........................................................................................................ .........................62 appendix a: application note 1................................................................................................ ...................63 a.1 u sing c rystal 25mh z ......................................................................................................................63 a.2 u sing o scillator 25mh z ...............................................................................................................63 appendix b: power consum ption refere nce data ..........................................................................64 errata of ax88796.............................................................................................................. ....................................65 demonstration circuit (a) : ax88796 with isa bus + homepna 1m8 phy.................................66
asix electronics corporation 4 ax88796 l 3-in-1 local bus fast ethernet controller figures f ig - 1 ax88796 b lock d iagram ............................................................................................................................... ....5 f ig - 2 ax88796 p in c onnection d iagram ...................................................................................................................6 f ig - 3 ax88796 p in c onnection d iagram with spp p ort o ption ............................................................................7 f ig - 4 ax88796 p in c onnection d iagram for isa b us m ode ...................................................................................8 f ig - 5 ax88796 p in c onnection d iagram for 80 x 86 m ode ......................................................................................9 f ig - 6 ax88796 p in c onnection d iagram for mc68k m ode .................................................................................10 f ig - 7 ax88796 p in c onnection d iagram for mcs-51 m ode .................................................................................11 f ig - 8 r eceive b uffer r ing ............................................................................................................................... ...........22 f ig - 9 r eceive b uffer r ing a t i nitialization ...........................................................................................................23 tables t ab - 1 l ocal cpu bus interface signals group ......................................................................................................12 t ab - 2 10/100m bps t wisted -p air i nterfaces pins group .........................................................................................13 t ab - 3 b uilt - in phy led indicator pins group .......................................................................................................13 t ab - 4 eeprom bus interface signals group ..........................................................................................................14 t ab - 5 mii interface signals group ..........................................................................................................................14 t ab - 6 s tandard p rinter p ort i nterface pins group ..............................................................................................15 t ab - 7 g eneral p urposes i/o pins group ...................................................................................................................15 t ab - 8 m iscellaneous pins group ..............................................................................................................................1 7 t ab - 9 p ower on c onfiguration s etup t able ..........................................................................................................17 t ab - 10 i/o a ddress m apping ............................................................................................................................... .......18 t ab - 11 l ocal m emory m apping ............................................................................................................................... .18 t ab - 12 p age 0 of mac c ore r egisters m apping ....................................................................................................32 t ab - 13 p age 1 of mac c ore r egisters m apping ....................................................................................................33 t ab - 14 t he e mbedded phy r egisters ......................................................................................................................40 t ab - 15 mii m anagement f rame f ormat .................................................................................................................53 t ab - 16 mii m anagement f rames - field d escription .............................................................................................53
asix electronics corporation 5 ax88796 l 3-in-1 local bus fast ethernet controller 1.0 introduction 1.1 general description: the ax88796 provides industrial standard ne2000 registers level compatible instruction set. various drivers are easy acquired, maintenance and usage. no much additional effort to be paid. software is easily port to various embedded systems with no pain and tears the ax88796 fast ethernet controller is a high performance and highly integrated local cpu bus ethernet controller with embedded 10/100mbps phy/transceiver and 8k*16 bit sram. the ax88796 supports both 8 bit and 16 bit local cpu interfaces include mcs-51 series , 80186 series, mc68k series cpu and isa bus. the ax88796 implements both 10mbps and 100mbps ethernet function based on ieee802.3 / ieee802.3u lan standard. the ax88796 also provides an extra ieee802.3u compliant media-i ndependent interface (mii) to support ot her media applica tions. using mii interface, home lan phy type media can be supported. as well as, the chip also provides optiona l standard print port ( parallel port inte rface ), can be used for printer server device or treat as simple general i/o port. the chip al so support upto 3/1 additional ge neral purpose in/out pins the main difference between ax88796 and ax88195 are : 1) embedded packet buffer memo ry 2) built-in 10/100mbps phy/transceiver 3) replace memory i/f with phy/transceiver i/f. 4) can celing sax address decoding. 5) fix interrupt status can?t always clean up problem of ax88195. 6) add upto 3/1 general purpose in/out pins. ax88796 use 128-pin lqfp low profile package, 25mhz operation, and single 3.3v operation with 5v i/o tolerance. the ultra low power consumption is an outstanding feature and enlarges the application field. it is suitable for some power consumption sensitive product like small size embedded pr oducts, pda (personal digital assistant) and palm size computer ?etc. 1.2 ax88796 block diagram: fig - 1 ax88796 block diagram mac core & phy+ tranceiver 8k* 16 sram and memory arbiter remote dma fifos ne2000 re g isters host interface sta seeprom i/f sd [ 15:0 ] sa [ 9:0 ] ctl bus mii i/f eecs eeck eedi eedo tpi , tpo spp / gpio print port or general i/o smdc smdio
asix electronics corporation 6 ax88796 l 3-in-1 local bus fast ethernet controller 1.3a ax88796 pin connection diagram the ax88796 is housed in the 128-pin plastic light quad flat pack. fig - 2 shows the ax88796 pin connection diagram. fig - 2 ax88796 pin connection diagram ax88796 local cpu bus 10/100base mac controller i_act vdd sa[1] vss vss lclk/xtalin vdd vss vss vdd vdd vss vss tpin tpip vsso tpon tpop vsso vdda rext100 rext10 i_link i_speed gpi[0]/link sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset xtalout eedi eedo eeck eecs nc vdd vdd vss vss vssa vssa rdy/dtack irq /cs /iocs16 aen/psen /iord /iowr /lds /uds clko25m io_base[2] io_base[1] io_base[0] cpu[1] cpu[0] test1 mdc mdio tx_en tx_clk rxd[3] rxd[2] rxd[1] rxd[0] rx_clk crs col rx_dv txd[0] txd[1] txd[2] txd[3] gpi[1]/dpx gpi[2]/spd rextbs 123 118 122 78 70 64 54 41 32 24 12 8 117 75 57 42 26 31 21 107 105 66 65 63 60 25 16 13 3 7 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 68 58 56 55 45 23 53 116 113 59 36 34 1 124 108 28 22 9 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 40 37 50 18 14 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 vdda vsspd vddpd vddm vssm vssa vdda vssa vssa vss vdda vss vdd vdd vss test2 iddq bist i_op vsso vddo vssm zvreg /bhe nc nc nc gpo[0] nc nc nc nc r/w /irq
asix electronics corporation 7 ax88796 l 3-in-1 local bus fast ethernet controller 1.3b ax88796 pin connection diagram with spp port option fig - 3 ax88796 pin connection di agram with spp port option ax88796 local cpu bus 10/100base mac controller i_act vdd sa[1] vss vss lclk/xtalin vdd vss vss vdd vdd vss vss tpin tpip vsso tpon tpop vsso vdda rext100 rext10 i_link i_speed pd0 slct pe /ack busy /strb /atfd /init /slin sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset xtalout eedi eedo eeck eecs nc vdd vdd vss vss vssa vssa rdy/dtack irq /cs /iocs16 aen/psen /iord /iowr /lds /uds clko25m io_base[2] io_base[1] io_base[0] cpu[1] cpu[0] test1 pd1 pd2 pd3 pd4 pd5 pd6 pd7 mdc mdio rextbs 123 118 122 78 70 64 54 41 32 24 12 8 117 75 57 42 26 31 21 107 105 66 65 63 60 25 16 13 3 7 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 68 58 56 55 45 23 53 116 113 59 36 34 1 124 108 28 22 9 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 40 37 50 18 14 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 vdda vsspd vddpd vddm vssm vssa vdda vssa vssa vss vdda vss vdd vdd vss test2 iddq bist i_op vsso vddo vssm zvreg /err /bhe nc nc nc gpo[0] nc nc nc nc r/w /irq (with spp port)
asix electronics corporation 8 ax88796 l 3-in-1 local bus fast ethernet controller 1.3.1 ax88796 pin connection diagram for isa bus mode fig - 4 ax88796 pin connection diagram for isa bus mode ax88796 i_act vdd sa[1] vss vss lclk/xtalin vdd vss vss vdd vdd vss vss tpin tpip vsso tpon tpop vsso vdda rext100 rext10 i_link i_speed gpi[0]/link sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset xtalout eedi eedo eeck eecs nc vdd vdd vss vss vssa vssa rdy irq /cs /iocs16 aen /iord /iowr clko25m io_base[2] io_base[1] io_base[0] cpu[1] cpu[0] test1 mdc mdio tx_en tx_clk rxd[3] rxd[2] rxd[1] rxd[0] rx_clk crs col rx_dv txd[0] txd[1] txd[2] txd[3] gpi[1]/dpx gpi[2]/spd rextbs 123 118 122 78 70 64 54 41 32 24 12 8 117 75 57 42 26 31 21 107 105 66 65 63 60 25 16 13 3 7 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 68 58 56 55 45 23 53 116 113 59 36 34 1 124 108 28 22 9 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 40 37 50 18 14 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 vdda vsspd vddpd vddm vssm vssa vdda vssa vssa vss vdda vss vdd vdd vss test2 iddq bist i_op vsso vddo vssm zvreg /bhe nc nc nc gpo[0] nc nc nc nc local cpu bus 10/100base-tx mac controller (for isa bus i/f)
asix electronics corporation 9 ax88796 l 3-in-1 local bus fast ethernet controller 1.3.2 ax88796 pin connection diagram for 80x86 mode fig - 5 ax88796 pin connection diagram for 80x86 mode i_act vdd sa[1] vss vss lclk/xtalin vdd vss vss vdd vdd vss vss tpin tpip vsso tpon tpop vsso vdda rext100 rext10 i_link i_speed gpi[0]/link sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset xtalout eedi eedo eeck eecs nc vdd vdd vss vss vssa vssa rdy irq /cs nc /iord /iowr clko25m io_base[2] io_base[1] io_base[0] cpu[1] cpu[0] test1 mdc mdio tx_en tx_clk rxd[3] rxd[2] rxd[1] rxd[0] rx_clk crs col rx_dv txd[0] txd[1] txd[2] txd[3] gpi[1]/dpx gpi[2]/spd rextbs 123 118 122 78 70 64 54 41 32 24 12 8 117 75 57 42 26 31 21 107 105 66 65 63 60 25 16 13 3 7 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 68 58 56 55 45 23 53 116 113 59 36 34 1 124 108 28 22 9 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 40 37 50 18 14 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 vdda vsspd vddpd vddm vssm vssa vdda vssa vssa vss vdda vss vdd vdd vss test2 iddq bist i_op vsso vddo vssm zvreg /bhe nc nc nc gpo[0] nc nc nc nc ax88796 local cpu bus 10/100base-tx mac controller (for x86 interface) nc
asix electronics corporation 10 ax88796 l 3-in-1 local bus fast ethernet controller 1.3.3 ax88796 pin connection diagram for mc68k mode fig - 6 ax88796 pin connection diagram for mc68k mode i_act vdd sa[1] vss vss lclk/xtalin vdd vss vss vdd vdd vss vss tpin tpip vsso tpon tpop vsso vdda rext100 rext10 i_link i_speed gpi[0]/link sd[0] sd[1] sd[2] sd[3] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset xtalout eedi eedo eeck eecs nc vdd vdd vss vss vssa vssa /dtack /irq /cs nc r/w /lds /uds clko25m io_base[2] io_base[1] io_base[0] cpu[1] cpu[0] test1 mdc mdio tx_en tx_clk rxd[3] rxd[2] rxd[1] rxd[0] rx_clk crs col rx_dv txd[0] txd[1] txd[2] txd[3] gpi[1]/dpx gpi[2]/spd rextbs 123 118 122 78 70 64 54 41 32 24 12 8 117 75 57 42 26 31 21 107 105 66 65 63 60 25 16 13 3 7 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 68 58 56 55 45 23 53 116 113 59 36 34 1 124 108 28 22 9 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 40 37 50 18 14 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 vdda vsspd vddpd vddm vssm vssa vdda vssa vssa vss vdda vss vdd vdd vss test2 iddq bist i_op vsso vddo vssm zvreg nc nc nc gpo[0] nc nc nc nc ax88796 local cpu bus 10/100base-tx mac controller (for 68k interface) nc nc
asix electronics corporation 11 ax88796 l 3-in-1 local bus fast ethernet controller 1.3.4 ax88796 pin connection diagram for mcs-51 mode fig - 7 ax88796 pin connection diagram for mcs-51 mode i_act vdd sa[1] vss vss lclk/xtalin vdd vss vss vdd vdd vss vss tpin tpip vsso tpon tpop vsso vdda rext100 rext10 i_link i_speed gpi[0]/link sd[0] sd[1] sd[2] sd[3] sa[0] sa[3] sa[2] sa[5] sa[4] sa[6] sa[7] sa[9] sa[8] sd[15] sd[14] sd[13] sd[12] sd[11] sd[10] sd[9] sd[8] sd[6] sd[4] sd[5] sd[7] reset xtalout eedi eedo eeck eecs nc vdd vdd vss vss vssa vssa /irq /cs /psen /iord /iowr clko25m io_base[2] io_base[1] io_base[0] cpu[1] cpu[0] test1 mdc mdio tx_en tx_clk rxd[3] rxd[2] rxd[1] rxd[0] rx_clk crs col rx_dv txd[0] txd[1] txd[2] txd[3] gpi[1]/dpx gpi[2]/spd rextbs 123 118 122 78 70 64 54 41 32 24 12 8 117 75 57 42 26 31 21 107 105 66 65 63 60 25 16 13 3 7 128 115 112 61 33 111 43 19 15 4 109 106 77 62 11 6 71 49 17 68 58 56 55 45 23 53 116 113 59 36 34 1 124 108 28 22 9 126 119 110 121 79 74 80 72 46 29 52 10 67 44 39 27 51 5 127 125 120 114 73 69 38 48 76 47 35 30 20 2 40 37 50 18 14 103 104 82 91 81 86 93 94 84 87 95 96 90 88 92 85 89 83 98 97 99 100 102 101 vdda vsspd vddpd vddm vssm vssa vdda vssa vssa vss vdda vss vdd vdd vss test2 iddq bist i_op vsso vddo vssm zvreg nc nc nc gpo[0] nc nc nc nc ax88796 local cpu bus 10/100base-tx mac controller (for 8051 interface) nc nc nc
asix electronics corporation 12 ax88796 l 3-in-1 local bus fast ethernet controller 2.0 signal description the following terms describe the ax88796 pin-out: all pin names with the ?/? suffix are asserted low. the following abbreviations are used in following tables. i input pu pull up o output pd pull down i/o input/output p power pin od open drain 2.1 local cpu bus interface signals group signal type pin no. description sa[9:1], sa[0]/lds i 15, 12 ? 4 system address : signals sa[9:0] are address bus input lines, which lower i/o spaces on chip. sa[0] al so means lower data strobe (/lds) active low signal in 68k application mode. /bhe or /uds i/pu 22 bus high enable or upper data strobe : bus high enable is active low signal in some 16-bit application mode, which enable high bus (sd[15:8]) active. the signal also name as upper data strobe (/uds) for 68k application mode. sd[15:0] i/o/pd 23 ? 26, 29 ? 33, 35 ? 39, 41 ? 42 system data bus : signals sd[15:0] constitute the bi-directional data bus. ireq/ireq o 16 interrupt request : when isa bus or 80186 cpu mode is select. ireq is asserted high to indicate th e host system that the chip requires host software service. when mc68k or mcs-51 cpu mode is select. /ireq is asserted low to indicate the host system that the chip requires host software service. rdy/dtack od 2 ready : this signal is set low to insert wait states during remote dma transfer. /dtack : when motorola cpu type is selected, the pin is active low inform cpu that data is accepted. /cs i/pu 128 chip select when the /cs signal is assert ed, the chip is selected. /iord i/pu 19 i/o read :the host asserts /iord to read data from ax88796 i/o space. when motorola cpu type is select , the pin is useless. /iowr or r/w i/pu 18 i/o write :the host asserts /iowr to write data into ax88796 i/o space. when motorola cpu type is select, the pin is active high for read operation at the same time. /ocs16 od 123 i/o is 16 bit port : the /iois16 is asserted when the address at the range corresponds to an i/o addre ss to which the chip responds, and the i/o port addressed is capable of 16-bit access. aen or /psen i/pd 1 address enable : the signal is asserted when the address bus is available for dma cycle. when negated (low), ax88796 an i/o slave device may respond to addresses and i/o command. psen : this signal is active low for 8051 program access. for i/o device, ax88796, this signal is ac tive high to access the chip. this signal is for 8051 bus application only. tab - 1 local cpu bus interface signals group
asix electronics corporation 13 ax88796 l 3-in-1 local bus fast ethernet controller 2.2 10/100mbps twisted-pair interface pins group signal type pin no. description tpi+ i 70 received data. positive diffe rential received 125m baud mlt3 or 10m baud manchester data from magnetic. tpi- i 71 received data. negative diffe rential received 125m baud mlt3 or 10m baud manchester data from magnetic. tpo+ o 88 transmit data. positive diffe rential transmit 125m baud mlt3 or 10m baud manchester data to magnetic. tpo- o 87 transmit data. negative differential transmit 125m baud mlt3 or 10m baud manchester data to magnetic. rext10 i 84 current setting 10mbits/s. an ex ternal resistor 20k ohm is placed from this signal to ground to set the 10mbits/s tp driver transmit output level. rext100 i 83 current setting 100mbits/s. an external resistor 2.49k ohm is placed from this signal to ground to set the 100mbits/s tp driver transmit output level. rextbs i 74 external bias resistor. band gap reference for the receive channel. connect this signal to a 24.9k ohm +/- 1 percent resistor to ground. the parasitic load capacitance should be less than 15 pf. tab - 2 10/100mbps twisted-pa ir interfaces pins group 2.3 built-in phy led indicator pins group signal type pin no. description i_act or i_full/col o 62 active status : when i_op is logic 1. if there is activity, transmit or receive, on the line occurred, the output will be driven low for 0.67 sec and then driven high at least 0.67 sec. full-duplex/collision status. when i_op is logic 0. if this signal is low, it indicates full-duplex link established, and if it is high, then the link is in half-duplex mode. wh en in half-duplex and collision occurrence, the output will be driven low for 0.67 sec and driven high at least 0.67 sec. (curre nt sink capacity is 6ma) i_speed o 61 speed status : if this signal is low, it indicates 100mbps, and if it is high, then the speed is 10mbps. (current sink capacity is 6ma) i_link or i_lk/act o 60 link status : when i_op is logic 1. if this signal is low, it indicates link, and if it is high, then the link is fail. link status/active : when i_op is logic 0. if this signal is low, it indicates link, and if it is high, then the link is fail. when in link status and line activity occurrence, the output will be driven low for 0.67 sec and driven high at least 0.67 sec. (current sink capacity is 6ma) tab - 3 built-in phy led indicator pins group
asix electronics corporation 14 ax88796 l 3-in-1 local bus fast ethernet controller 2.4 eeprom signals group signal type pin no. description eecs o 51 eeprom chip select : eeprom chip select signal. eeck o/pd 50 eeprom clock : signal connected to eeprom clock pin. eedi o 49 eeprom data in : signal connected to eeprom data input pin. eedo i/pu 48 eeprom data out : signal connected to eeprom data output pin. tab - 4 eeprom bus interface signals group 2.5 mii interface signals group(optional) signal type pin no. description rxd[3:0] i/pu 98 ? 95 receive data : rxd[3:0] is driven by the phy synchronously with respect to rx_clk. crs i/pd 100 carrier sense : asynchronous signal crs is asserted by the phy when either the transmit or receive medium is non-idle. rx_dv i/pd 102 receive data valid : rx_ dv is driven by the phy synchronously with respect to rx_clk. asserted high when valid data is present on rxd [3:0]. rx_er (omit) no support receive error : rx _er ,is driven by phy and synchronous to rx_clk, is asserted for one or more rx_clk periods to indicate to the port that an error has detected. rx_clk i/pu 99 receive clock : rx_clk is a continuous clock that provides the timing reference for the transfer of the rx_dv,rxd[3:0] and rx_er signals from the phy to the mii port of the repeater. col i/pd 101 collision : this signal is driv en by phy when collision is detected. tx_en o 108 transmit enable : tx_en is tr ansition synchronously with respect to the rising edge of tx_clk. tx_en indicates that the port is presenting nibbles on txd [3:0] for transmission. txd[3:0] o 112 ? 109 transmit data : txd[3:0] is transition sy nchronously with respect to the rising edge of tx_clk. fo r each tx_clk period in which tx_en is asserted, txd[3:0] ar e accepted for transmission by the phy. tx_clk i/pu 107 transmit clock : tx_clk is a continuous clock from phy. it p rovides the timing reference for the transfer of the tx_en and txd[3:0] signals from the mii port to the phy. mdc o/pu 67 station management data clock : the timing reference for mdio. all data transfers on mdio are synchronized to the rising edge of this clock. the signal output reflects mdc register value. about mdc register, please refer to mii/eeprom management register bit 0. mdc clock frequency is a 2.5mhz maximum accourding to ieee 802.3u mii specification. acturely, many phys are designed to accept higher frequency than 2.5mhz. mdio i/o/pu 66 station management data input/output :serial data input/output transfers from/to the phys . the tr ansfer protocol has to meet the ieee 802.3u mii specification. for more information, please refer to section 6.5 cpu access mii station management functions. tab - 5 mii interface signals group
asix electronics corporation 15 ax88796 l 3-in-1 local bus fast ethernet controller 2.6 standard printer port (spp) interface pins group (optional) signal type pin no. description pd[7:5] pd[4:0] i/o/pd i/o/pu 102 ? 100 99 - 95 parallel data :the bi-directional parallel data bus is used to transfer information between cpu and peri pherals. default serve as input, using /doe bit of register offset x1ah to set the direction. busy i/pu 108 busy : this is a status input from the printer, high indicating that the printer is not ready to receive new data. /ack i/pu 107 acknowledge : a low active input from the printer indicating that it has received the data and is ready to accept new data. pe i/pu 106 paper empty : a status input from the printer, high indicating that the printer is out of paper. slct i/pu 103 slect: this high active input from the printer indicating that it has power on. /err i/pu 113 error : a low active input from the printer indicating that there is an error condition at the printer. /slctin o 112 slect in: this active low output selects the printer. /init o 111 init: this signal is used to initiate the pr inter when low. /atfd o 110 auto feed :this output goes low to cause the printer to automatically feed one line after each line is printed. /strb o 109 strobe : a low active pulse on this output is used to strobe the print data into the printer. tab - 6 standard printer port interface pins group 2.7 general purpose i/o pins group signal name type pin no. description gpi[2]/spd i/pu 113 read register offset 17h bit 6 value reflects this input value. gpi[1]/dpx i/pu 106 when mii port is selected. read register offset 17h bit 5 value reflects this input value. when spp port is selected. the pin is defined as pe. gpi[0]/link i/pu 103 when mii port is selected. read register offset 17h bit 4 value reflects this input value. when spp port is selected. the pin is defined as slct. gpo[0] o 120 default ?1?. the pin reflects write register offset 17h bit 0 inverted value. tab - 7 general purposes i/o pins group
asix electronics corporation 16 ax88796 l 3-in-1 local bus fast ethernet controller 2.8 miscellaneous pins group signal type pin no. description lclk/xtalin i 79 cmos local clock : a 25mhz clock, +/- 100 ppm, 40%-60% duty cycle. the signal not supports 5 volts tolerance. crystal oscillator input : a 25mhz crystal, +/- 30 ppm can be connected across xtalin and xtalout. xtalout o 80 crystal oscillator output : a 25mhz crystal, +/- 30 ppm can be connected across xtalin and xtal out. if a single-ended external clock (lclk) is connected to xtalin, the crystal output pin should be left floating. clko25m o 44 clock output : this clock is source from lclk/xtalin. reset i/pu 3 reset : reset is active high then place ax88796 into reset mode immediately. during the falling edge the ax88796 loads the power on setting data. cpu[1:0] i/pu 59, 58 cpu type selection: cpu[1] cpu[0] cpu type 0 0 isa bus 0 1 80186 1 0 mc68k 1 1 mcs-51 (805x) io_base[2:1] io_base[0] i/pu i/pd 119, 118, 117 i/o base address selection: io_base[2] io_base[1] io_base[0] io_base 0 0 0 300h 0 0 1 320h 0 1 0 340h 0 1 1 360h 1 0 0 380h 1 0 1 3a0h 1 1 0 200h(default) 1 1 1 220h i_op i/pu 116 led indicator option : selection of led display mode. i_op = 0: i_lk/act, i_speed and i_full/col led display mode. i_op = 1: i_link, i_speed and i_act led display mode. (default) test[2:1] i/pd 47, 65 test pins : active high these pins are just for test mode setting purpose only. must be pull down or keep no connection when normal operation. iddq i 46 for test only. must be pulled down at normal operation. bist i/pd 45 for test only. must be pulled down or keep no connection when normal operation. zvreg o 92 this sets the common mode voltage for 10base-t and 100base-tx modes. it should be connected to the center tap of the transmit side of the transformer nc n/a 17, 20, 21, 64, 122, 124, 125 no connection : for manufacturing test only. vdd p 13, 27, 40, 53, 57, 104, 114, 126 power supply : +3.3v dc. vss p 14, 28, 34, 43, 52, 54, 63, 94, 105,115, 127 power supply : +0v dc or ground power. vdda p 56, 69, 73, 82 power supply for analog circuit: +3.3v dc.
asix electronics corporation 17 ax88796 l 3-in-1 local bus fast ethernet controller vssa p 55, 68, 72, 75, 85, power supply for analog circu it: +0v dc or ground power. vddm p 76 powers the analog block around the transmit/receive area. this should be connected to vdda: +3.3v dc. vssm p 77, 93 powers the analog block ar ound the transmit/receive area. this should be connected to vssa: +0v dc or ground power. vddpd p 78 the phase detector (or pll) power. this should be isolated with other power: +3.3v dc. vsspd p 81 the phase detector (or pll) pow er. this should be isolated with other power: +0v dc or ground. vddo p 91 power supply for transceiver output driver: +3.3v dc. vsso p 86, 89, 90 power supply for transceiver output driver: +0v dc or ground. tab - 8 miscellaneous pins group 2.9 power on configuration setup si gnals cross reference table signal name share with description /spp_set mdc standard pr inter port selection: /spp_set = 0 : standard printer port or gpio is selected /spp_set = 1 : mii port is selected (default) ppd_set eeck ppd_set = 0 : internal phy in normal mode. (default) ppd_set = 1 : internal phy in power down mode. tab - 9 power on configuration setup table
asix electronics corporation 18 ax88796 l 3-in-1 local bus fast ethernet controller 3.0 memory and i/o mapping there are three memories or i/o mapping used in ax88796. 1. eeprom memory mapping 2. i/o mapping 3. local memory mapping 3.1 eeprom memory mapping user can define by them and can access via i/o address offset 14h mii/eeprom registers. the contants of eeprom will not be loading to any registers automaticlly. 3.2 i/o mapping system i/o offset function 0000h 001fh mac core register tab - 10 i/o address mapping 3.3 sram memory mapping offset function 0000h 3fffh reserved 4000h 7fff ne2000 compatable mode 8k x 16 sram buffer 8000h ffffh reserved tab - 11 local memory mapping
asix electronics corporation 19 ax88796 l 3-in-1 local bus fast ethernet controller 4.0 basic operation 4.1 receiver filtering the address filtering logic compares the destination address fi eld (first 6 bytes of the recei ved packet) to the physical address registers stored in the address register array. if any one of the six bytes does not match the pre-programmed physical address, the protocol control logic rejects the packet. this is for unicast address filtering. all multicast destination addresses are filtered using a hashing algorithm. (see following description.) if the multicast address indexes a bit that has been set in th e filter bit array of the multicast address regist er array the packet is accepted, otherwise it is rejected by the protocol control logic. each destination address is also checked for a ll 1's which is the reserved broadcast address. 4.1.1 unicast address match filter the physical address registers are used to compare the destination address of incoming packets for rejecting or accepting packets. comparisons are performed on a byte wide basis. the bit assignment shown below relates the sequence in par0-par5 to the bit sequen ce of the received packet. d7 d6 d5 d4 d3 d2 d1 d0 par0 da7 da6 da5 da4 da3 da2 da1 da0 par1 da15 da14 da13 da12 da11 da10 da9 da8 par2 da23 da22 da21 da20 da19 da18 da17 da16 par3 da31 da30 da29 da28 da27 da26 da25 da24 par4 da39 da38 da37 da36 da35 da34 da33 da32 par5 da47 da46 da45 da44 da43 da42 da41 da40 note: the bit sequence of the received p acket is da0, da1, ? da7, da8 ?. 4.1.2 multicast address match filter the multicast address registers provide filtering of multicast addresses hashed by the crc logic. all destination addresses are fed through the 32 bits crc ge neration logic and as the last bit of the destination address enters the crc, the 6 most significant bits of the crc generator are latched. these 6 bits are then decoded by a 1 of 64 decode to index a unique filter bit (fb0-63) in the multicast address registers. if the filter bit selected is set, the multicast packet is accepted. the system designer would use a program to determin e which filter bits to set in the multicast registers. all multicast filter bits that correspond to mu lticast address registers accepted by the node are then set to one. to accept all multicast packets all of the re gisters are set to all ones. d7 d6 d5 d4 d3 d2 d1 d0 mar0 fb7 fb6 fb5 fb 4 fb3 fb2 fb1 fb0 mar1 fb15 fb14 fb13 fb12 fb11 fb10 fb9 fb8 mar2 fb23 fb22 fb21 fb20 fb19 fb18 fb17 fb16 mar3 fb31 fb30 fb29 fb28 fb27 fb26 fb25 fb24 mar4 fb39 fb38 fb37 fb36 fb35 fb34 fb33 fb32 mar5 fb47 fb46 fb45 fb44 fb43 fb42 fb41 fb40 mar6 fb55 fb54 fb53 fb52 fb51 fb50 fb49 fb48 mar7 fb63 fb62 fb61 fb60 fb59 fb58 fb57 fb56
asix electronics corporation 20 ax88796 l 3-in-1 local bus fast ethernet controller if address y is found to hash to the value 32 (20h), then fb 32 in mar2 should be initialized to ``1''. this will cause the ax88796 to accept any multicast pack et with the address y. although the hashing algorithm doe s not guarantee perfect filtering of multicast address, it will perfectly filter up to 64 logical address filteres if these addresses are chosen to map into unique locations in the multicast filter. note: the first bit of received packet sequen ce is 1?s stands by multicast address. 4.1.3 broadcast address match filter the broadcast check logic compar es the destination address field (first 6 bytes of the received packet) to all 1?s, that is the values are ?ff ff ff ff ff ff ff? in hex format. if any bit of the six bytes does not equal to 1?s, the protocol control logic rejects the packet. 4.1.4 aggregate address filter with receive configuration setup the final address filter decision depands on the destina tion address types, identified by the above 3 address match filters, and the setup of parameters of receive configuration register. definitions of address match filter result are as following: signal value description phy =1 unicast address match =0 unicast address not match mul =1 multicast address match =0 multicast address not match bro =1 brocast address match =0 brocast address not match agg =1 aggregate address match =0 aggregate address not match the meaning of ab, am and pro signals, please refer to ? receive configur ation register? 32-bit crc generator latch 1 of 64 bit decoder filter bit array x=31 to x=26 clock selected bit 0 = reject, 1= accept
asix electronics corporation 21 ax88796 l 3-in-1 local bus fast ethernet controller aggregate address filter function will be: agg bro ab /bro /mul pro /bro mul am phy and logic and logic and logic or logic
asix electronics corporation 22 ax88796 l 3-in-1 local bus fast ethernet controller 4.2 buffer management operation there are four buffer memory access types used in ax88796. 1. packet reception (write data to memory from mac) 2. packet transmision (read data from memory to mac) 3. filling packets to transmit buffer (host fill data to memory) 4. removing packets from the receive buffer ring (host read data from memory) the type 1 and 2 operations act as local dma. type 1 does local dma write operation and type 2 does local dma read operation. the type 3 and 4 operations act as remote dma. type 3 does remote dma write operation and type 4 does remote dma read operation. 4.2.1 packet reception the local dma receive channel uses a buffer ring struct ure comprised of a series of contiguous fixed length 256 byte (128 word) buffers for storage of received p ackets. the location of the receive buffer ring is programmed in two registers, a page start and a page stop register. ethernet packets consist of minimum packet size (64 bytes) to maximum packet size (1522 bytes), the 256 byte buffer length provides a good compromise between short packets and longer packets to most efficiently use memory. in addition these buffers provide memory resources for storage of back-t o-back packets in loaded networks. the assignment of buffers for storing packets is controlled by bu ffer management logic in the ax88796. the buffer management logic provides three basic functions: linki ng receive buffers for long packets, recovery of buffers when a packet is rejected, and recirculation of buffer pages that have been read by the host. at initialization, a portion of the 16k byte (or 8k word) address space is reserved for the receiver buffer ring. two eight bit registers, the page start address re gister (pstart) and the page stop address register (pstop) define the physical boundaries of where the buffers reside. the ax88796 treats the list of buffers as a logical ring; whenever the dma a ddress reaches the page stop address, the dma is reset to the page start address. buffer #1 buffer #2 buffer #3 ? ? ? ? buffer #n physical memory map l ogic receive buffer ring fig - 8 receive buffer ring 4000h 8000h page start page stop 1 2 3 4 ? n-2 n-1 n
asix electronics corporation 23 ax88796 l 3-in-1 local bus fast ethernet controller initialization of the buffer ring two static registers and two working registers contro l the operation of the buffer ring. these are the page start register, page stop register (both described prev iously), the current page register and the boundary pointer register. the current page register points to th e first buffer used to store a packet and is used to restore the dma for writing status to the buffer ring or for restoring the dma address in the event of a runt packet, a crc, or frame alignment error. the boundary re gister points to the first packet in the ring not yet read by the host. if the local dma address ever r eaches the boundary, reception is aborted. the boundary pointer is also used to initialize th e remote dma for removing a packet a nd is advanced when a packet is removed. a simple analogy to remember the function of these registers is that the current page register acts as a write pointer and the boundary pointer acts as a read pointer. buffer #1 buffer #2 buffer #3 ? ? ? ? buffer #n physical memory map l ogic receive buffer ring fig - 9 receive buffer ring at initialization beginning of reception when the first packet begins arriving the ax88796 and begi ns storing the packet at the location pointed to by the current page register. an offset of 4 bytes is reserve d in this first buffer to allow room for storing receive status corresponding to this packet. linking receive buffer pages if the length of the packet exhausts the first 256 byt es buffer, the dma performs a forward link to the next buffer to store the remainder of the packet. for a maxima l length packet the buffer logic will link six buffers to store the entire packet. buffers cannot be skipped when linking, a packet will always be stored in contiguous buffers. before the next buffer can be linked, the buffer management logic performs two comparisons. the first comparison tests for equality between the dma addr ess of the next buffer and the contents of the page stop register. if the buffer address equals the page stop register, the buffer management logic will restore the dma to the first buffer in the receive buffer ring valu e programmed in the page start address register. the second comparison test for equality between the dma addr ess of the next buffer address and the contents of the boundary pointer register. if the two values are e qual the reception is aborted. the boundary pointer register can be used to protect against overwriting an y area in the receive buffer ring that has not yet been read. when linking buffers, buffer management will ne ver cross this pointer, effectively avoiding any overwrites. if the buffer address does not match either th e boundary pointer or page stop address, the link to the next buffer is performed. 4000h 8000h page start page stop 1 2 3 4 ? n-2 n-1 n boundary page current page
asix electronics corporation 24 ax88796 l 3-in-1 local bus fast ethernet controller linking buffers before the dma can enter the next contiguous 256 byt es buffer, the address is checked for equality to pstop and to the boundary pointer. if neither are reached , the dma is allowed to use the next buffer. buffer ring overflow if the buffer ring has been filled and the dma reach es the boundary pointer address, reception of the incoming packet will be aborted by the ax88796. thus, th e packets previously received and still contained in the ring will not be destroyed. in a heavily loaded network environment the local dma may be disabled, preventing the ax88796 from buffering packets from the network. to guarantee this will not happen, a software reset must be issued during all receive bu ffer ring over flows (indicated by the ovw bit in the interrupt status register). the following procedur e is required to recover from a receiver buffer ring overflow. if this routine is not adhered to, the ax88796 ma y act in an unpredictable manner. it should also be noted that it is not permissible to service an overflow in terrupt by continuing to empty packets from the receive buffer without implementing the prescribed overflow routine. note: it is necessary to define a variable in the driver, which will be called ``resend''. 1. read and store the value of the txp bit in the ax88796's command register. 2. issue the stop command to the ax88796. this is accomplished be setting the stp bit in the ax88796's command register. writing 21h to the command register will stop the ax88796. 3. wait for at least 1.5 ms. since the ax88796 will complete any transmission or reception that is in progress, it is necessary to time out for the maximum possible dura tion of an ethernet transmission or reception. by waiting 1.5 ms this is achieved with some guard ba nd added. previously, it was recommended that the rst bit of the interrupt status register be polled to insure that the pending transmission or reception is completed. this bit is not a reliable indi cator and subsequently should be ignored. 4. clear the ax88796's remote byte count registers (rbcr0 and rbcr1). 5. read the stored value of the txp bit from step 1, above . if this value is a 0, set the ``resend'' variable to a 0 and jump to step 6. if this value is a 1, read the ax88796's interrupt status register. if either the packet transmitted bit (ptx) or transmit error bit (txe) is set to a 1, set the ``resend'' variable to a 0 and jump to step 6. if neither of these bits is set, place a 1 in th e ``resend'' variable and jump to step 6. this step determines if there was a transmission in progress when the stop command was issued in step 2. if there was a transmission in progress, the ax88796's isr is read to determine whether or not the packet was recognized by the ax88796. if neither the ptx nor txe bit was set, then the packet will essentially be lost and retransmitted only after a time-out takes place in the upper level software. by determining that the packet was lost at the driver level, a transmit command can be reissued to the ax88796 once the overflow routine is completed (as in step 11). also, it is po ssible for the ax88796 to defer indefinitely, when it is stopped on a busy network. step 5 also alleviates this problem. step 5 is essential and should not be omitted from the overflow routine, in order for the ax88796 to operate correctly. 6. place the ax88796 in mode 1 loopback. this can be accomplished by setting bits d2 and d1, of the transmit configuration register to ``0,1''. 7. issue the start command to the ax88796. this can be accomplished by writing 22h to the command register. this is necessary to activate the ax88796's remote dma channel. 8. remove one or more packets from the receive bufferring. 9. reset the overwrite warning (ovw, overflow) bit in the interrupt status register. 10. take the ax88796 out of loopback. this is done by writing the transmit configuration register with the value it contains during normal operation. (bits d2 and d1 should both be programmed to 0.) 11. if the ``resend'' variable is set to a 1, reset the ``resend'' variable a nd reissue the transmit command. this is done by writing a value of 26h to the command regist er. if the ``resend'' variable is 0, nothing needs to bedone. end of packet operations
asix electronics corporation 25 ax88796 l 3-in-1 local bus fast ethernet controller at the end of the packet the ax88796 determines whether th e received packet is to be accepted or rejected. it either branches to a routine to store the buffer header or to another routin e that recovers the buffers used to store the packet. successful reception if the packet is successfully received as shown, the dma is restored to the first buffer used to store the packet (pointed to by the current page register). the dma then stores the receive status, a pointer to where the next packet will be stored and the number of received bytes. note that the remaining bytes in the last buffer are discarded and reception of the next packet begins on the next empty 256 byte buffer boundary. the current page register is then initialized to the next available buffer in the buffer ring. (the location of the next buffer had been previously calculated and temporarily stored in an internal scratchpad register.) buffer recovery for rejected packets if the packet is a runt packet or contains crc or frame alignment errors, it is rejected. the buffer management logic resets the dma back to the first buffer page used to store the packet (pointed to by cpr), recovering all buffers that had been used to store the rejected packet. this operation will not be performed if the ax88796 is programmed to accept either runt packet s or packets with crc or frame alignment errors. the received crc is always stored in buffer memory af ter the last byte of received data for the packet. error recovery if the packet is rejected as shown, the dma is restored by the ax88796 by reprogramming the dma starting address pointed to by the current page register. 4.2.2 packet transmision the local dma read is also used during transmission of a packet. three registers control the dma transfer during transmission, a transmit page start address register (tpsr) and the transmit byte count registers (tbcr0,1). when the ax88796 receives a command to tran smit the packet pointed to by these registers, buffer memory data will be moved into the fifo as required during transmission. the ax88796 controller will generate and append the pr eamble, synch and crc fields. transmit packet assembly the ax88796 requires a contiguous assembled packet with the format shown. the transmit byte count includes the destination address, source address, lengt h field and data. it does not include preamble and crc. when transmitting data smaller than 46 bytes, the packet must be padded to a minimum size of 64 bytes. the programmer is responsible for adding and stripping pad bytes. the packets are placed in the buffer ram by the system. system programs the ax88796 core's remote dma to move the data from the data port to the ram handshaking with system transfers loading the i/o data port. the data transfer must be 16 bits (1 word) when in 16-bit mode, and 8 bits when the ax88796 controller is set in 8-bit mode. the data width is selected by setting the wts bit in the data configuration register and setting the cpu[1:0] pins for isa, 80186 or mc68k mode.
asix electronics corporation 26 ax88796 l 3-in-1 local bus fast ethernet controller destination address 6 bytes source address 6 bytes length / type 2 bytes data (pad if < 46 bytes) 46 bytes min. general transmit packet format transmission prior to transmission, the tpsr (transmit page star t register) and tbcr0, tbcr1 (transmit byte count registers) must be initialized. to initiate transmission of the packet the txp bit in the command register is set. the transmit status register (tsr) is cleared and the ax88796 begins to prefetch transmit data from memory. if the interpacket gap (ipg) has timed out the ax88796 will begin transmission. conditions required to begin transmission in order to transmit a packet, the following three conditions must be met: 1. the interpacket gap timer has timed out 2. at least one byte has entered the fifo. (this i ndicates that the burst transfer has been started) 3. if a collision had been detected then before tran smission the packet backoff time must have timed out. collision recovery during transmission, the buffer management logic monito rs the transmit circuitry to determine if a collision has occurred. if a collision is detected, the buffer ma nagement logic will reset the fifo and restore the transmit dma pointers for retransmission of the packet . the col bit will be set in the tsr and the ncr (number of collisions register) will be incremented. if 15 retransmissions each result in a collision the transmission will be aborted and the abt bit in the tsr will be set. transmit packet assembly format the following diagrams describe the format for how p ackets must be assembled prior to transmission for different byte ordering schemes. the various formats ar e selected in the data configuration register and setting the cpu[1:0] pins for isa, 80186, mc68k or mcs-51 mode. d15 d8 d7 d0 destination address 1 destination address 0 destination address 3 destination address 2 destination address 5 destination address 4 source address 1 source address 0 source address 3 source address 2 source address 5 source address 4 type / length 1 type / length 0 data 1 data 0 ? ? bos = 0, wts = 1 in data configuration register. this format is used with isa or 80186 mode.
asix electronics corporation 27 ax88796 l 3-in-1 local bus fast ethernet controller d15 d8 d7 d0 destination address 0 destination address 1 destination address 2 destination address 3 destination address 4 destination address 5 source address 0 source address 1 source address 2 source address 3 source address 4 source address 5 type / length 0 type / length 1 data 0 data 1 ? ? bos = 1, wts = 1 in data configuration register. this format is used with mc68k mode. d7 d0 destination address 0 (da0) destination address 1 (da1) destination address 2 (da2) destination address 3 (da3) destination address 4 (da4) destination address 5 (da5) source address 0 (sa0) source address 1 (sa1) source address 2 (sa2) source address 3 (sa3) source address 4 (sa4) source address 5 (sa5) type / length 0 type / length 1 data 0 data 1 ? bos = 0, wts = 0 in data configuration register. this format is used with isa, 80186 or mcs-51 mode. note: all examples above will result in a transmission of a packet in order of da0 (destination address 0), da1, da2, da3 . . . in byte. bits within each byte will be transmitted least significant bit first. 4.2.3 filling packet to transmit buffer (host fill data to memory) the remote dma channel is used to both assemble packet s for transmission, and to remove received packets from the receive buffer ring. it may also be used as a general purpose slave dma channel for moving blocks of data or commands between host memory and local buffer memory. there are two modes of operation, remote write and remote read packet. two register pairs are used to control the remote dma, a remote start address (rsar0, rsar1) and a remote byte count (rbcr0, rbcr1) register pair. the start address register pair points to the beginning of the block to be moved while the byte count register pair is used to indicate the number of bytes to be transferred. full handshake logic is provided to move data between lo cal buffer memory (embedded memory) and a bidirectional i/o port. remote write
asix electronics corporation 28 ax88796 l 3-in-1 local bus fast ethernet controller a remote write transfer is used to move a block of data from the host into local buffer memory. the remote dma will read data from the i/o port and sequentially wr ite it to local buffer memory beginning at the remote start address. the dma address will be incremented and the byte counter will be decremented after each transfer. the dma is terminated when the remote byte count register reaches a count of zero. 4.2.4 removing packets from the ring (host read data from memory) remote read a remote read transfer is used to move a block of data from local buffer memory to the host. the remote dma will sequentially read data from the local buffer memory, beginning at the remote start address, and write data to the i/o port. the dma address will be in cremented and the byte counter will be decremented after each transfer. the dma is terminated when the remote byte count register reaches zero. packets are removed from the ring using the remote dm a or an external device. when using the remote dma. the boundary pointer can also be moved ma nually by programming the boundary register. care should be taken to keep the boundary pointer at l east one buffer behind the current page pointer. the following is a suggested method for maintaining the receive buffer ring pointers. 1. at initialization, set up a software variable (next_pkt) to indicate where the next packet will be read. at the beginning of each remote read dma operation, the va lue of next_pkt will be loaded into rsar0 and rsar1. 2. when initializing the ax88796 set: bnry = pstart cpr = pstart + 1 next_pkt = pstart + 1 3. after a packet is dmaed from the receive buffer ring, the next page pointer (second byte in ax88796 receive packet buffer header) is used to update bnry and next_pkt. next_pkt = next page pointer bnry = next page pointer - 1 if bnry < pstart then bnry = pstop ? 1 note the size of the receive buffer ring is reduced by one 256-byte buffer; this will not, however, impede the operation of the ax88796. the advantage of this scheme is that it easily differentiates between buffer full and buffer empty: it is full if bnry = cpr; empty when bnry = cpr-1. storage format for received packets the following diagrams describe the format for how r eceived packets are placed into memory by the local dma channel. these modes are sel ected in the data configuration register and setting the cpu[1:0] pins for isa, 80186, mc68k or mcs-51 mode. d15 d8 d7 d0
asix electronics corporation 29 ax88796 l 3-in-1 local bus fast ethernet controller next packet pointer receive status receive byte count 1 receive byte count 0 destination address 1 destination address 0 destination address 3 destination address 2 destination address 5 destination address 4 source address 1 source address 0 source address 3 source address 2 source address 5 source address 4 type / length 1 type / length 0 data 1 data 0 ? ? bos = 0, wts = 1 in data configuration register. this format is used with isa or 80186 mode. d15 d8 d7 d0 receive status next packet pointer receive byte count 0 receive byte count 1 destination address 0 destination address 1 destination address 2 destination address 3 destination address 4 destination address 5 source address 0 source address 1 source address 2 source address 3 source address 4 source address 5 type / length 0 type / length 1 data 0 data 1 ? ? bos = 1, wts = 1 in data configuration register. this format is used with mc68k mode. d7 d0 receive status next packet pointer
asix electronics corporation 30 ax88796 l 3-in-1 local bus fast ethernet controller receive byte count 0 receive byte count 1 destination address 0 destination address 1 destination address 2 destination address 3 destination address 4 destination address 5 source address 0 source address 1 source address 2 source address 3 source address 4 source address 5 type / length 0 type / length 1 data 0 data 1 ? bos = 0, wts = 0 in data configuration register. this format is used with isa, 80186 or mcs-51 mode.
asix electronics corporation 31 ax88796 l 3-in-1 local bus fast ethernet controller 4.2.5 other useful operations memory diagnostics memory diagnostics can be achieved by remote write /read dma operations. the following is a suggested step for memory test and assume the ax88796 has been well initilized. 1. issue the stop command to the ax88796. this is accomplished be setting the stp bit in the ax88796's command register. writing 21h to the command register will stop the ax88796. 2. wait for at least 1.5 ms. since the ax88796 will comple te any reception that is in progress, it is necessary to time out for the maximum possible duration of an ethernet reception. this action prevents buffer memory from written data through local dma write. 3. write data pattern to mut (memory unde r test) by remote dma write operation. 4. read data pattern from mut (memory unde r test) by remote dma read operation. 5. compare the read data pattern with original write data pattern and check if it is equal. 6. repeat step 3 to step 5 with various data pattern. loopback diagnostics 1. issue the stop command to the ax88796. this is accomplished be setting the stp bit in the ax88796's command register. writing 21h to the command register will stop the ax88796. 2. wait for at least 1.5 ms. since the ax88796 will comple te any reception that is in progress, it is necessary to time out for the maximum possible duration of an ethernet reception. this action prevents buffer memory from written data through local dma write. 3. place the ax88796 in mode 1 loopback. (mac internal loopback) this can be accomplished by setting bits d2 and d1, of the transmit configuration register to ``0,1''. 4. issue the start command to the ax88796. this can be accomplished by writing 22h to the command register. this is necessary to activate the ax88796's remote dma channel. 5. write data that want to transmit to tr ansmit buffer by remote dma write operation. 6. issue the txp command to the ax88796. this can be accomplished by writing 26h to the command register. 7. read data current receive buffer by remote dma read operation. 8. compare the received data with original transmit data and check if it is equal. 9. repeat step 5 to step 8 for more packets test.
asix electronics corporation 32 ax88796 l 3-in-1 local bus fast ethernet controller 5.0 registers operation 5.1 mac core registers all registers of mac core are 8-bit wide and mapped into pages which are selected by ps (page select) in the command register. page 0 (ps1=0,ps0=0) offset read write 00h command register ( cr ) command register ( cr ) 01h page start register ( pstart ) page start register ( pstart ) 02h page stop register ( pstop ) page stop register ( pstop ) 03h boundary pointer ( bnry ) boundary pointer ( bnry ) 04h transmit status register ( tsr ) transmit page start address ( tpsr ) 05h number of collisions register ( ncr ) transmit byte count register 0 ( tbcr0 ) 06h current page register ( cpr ) transmit byte count register 1 ( tbcr1 ) 07h interrupt status register ( isr ) interrupt status register ( isr ) 08h current remote dma address 0 ( crda0 ) remote start address register 0 ( rsar0 ) 09h current remote dma address 1 ( crda1 ) remote start address register 1 ( rsar1 ) 0ah reserved remote byte count 0 ( rbcr0 ) 0bh reserved remote byte count 1 ( rbcr1 ) 0ch receive status register ( rsr ) receive configura tion register ( rcr ) 0dh reserved transmit configuration register ( tcr ) 0eh reserved data configuration register ( dcr ) 0fh reserved interrupt mask register ( imr ) 10h, 11h data port data port 12h ifgs1 ifgs1 13h ifgs2 ifgs2 14h mii/eeprom access mii/eeprom access 15h test register test register 16h inter-frame gap (ifg) inter-frame gap (ifg) 17h gpi gpoc 18h - 1ah standard printer port ( spp) standard printer port (spp) 1bh - 1eh reserved reserved 1fh reset reserved tab - 12 page 0 of mac core registers mapping
asix electronics corporation 33 ax88796 l 3-in-1 local bus fast ethernet controller page 1 (ps1=0,ps0=1) offset read write 00h command register ( cr ) command register ( cr ) 01h physical address register 0 ( para0 ) physical address register 0 ( par0 ) 02h physical address register 1 ( para1 ) physical address register 1 ( par1 ) 03h physical address register 2 ( para2 ) physical address register 2 ( par2 ) 04h physical address register 3 ( para3 ) physical address register 3 ( par3 ) 05h physical address register 4 ( para4 ) physical address register 4 ( par4 ) 06h physical address register 5 ( para5 ) physical address register 5 ( par5 ) 07h current page register ( cpr ) current page register ( cpr ) 08h multicast address register 0 ( mar0 ) multicast address register 0 ( mar0 ) 09h multicast address register 1 ( mar1 ) multicast address register 1 ( mar1 ) 0ah multicast address register 2 ( mar2 ) multicast address register 2 ( mar2 ) 0bh multicast address register 3 ( mar3 ) multicast address register 3 ( mar3 ) 0ch multicast address register 4 ( mar4 ) multicast address register 4 ( mar4 ) 0dh multicast address register 5 ( mar5 ) multicast address register 5 ( mar5 ) 0eh multicast address register 6 ( mar6 ) multicast address register 6 ( mar6 ) 0fh multicast address register 7 ( mar7 ) multicast address register 7 ( mar7 ) 10h, 11h data port data port 12h inter-frame gap segment 1 ifgs1 inter-frame gap segment 1 ifgs1 13h inter-frame gap segment 2 ifgs2 inter-frame gap segment 2 ifgs2 14h mii/eeprom access mii/eeprom access 15h test register test register 16h inter-frame gap (ifg) inter-frame gap (ifg) 17h gpi gpoc 18h - 1ah standard printer port ( spp) standard printer port (spp) 1bh - 1eh reserved reserved 1fh reset reserved tab - 13 page 1 of mac core registers mapping
asix electronics corporation 34 ax88796 l 3-in-1 local bus fast ethernet controller 5.1.1 command register (cr) offset 00h (read/write) field name description 7:6 ps1,ps0 ps1,ps0 : page select the two bits selects which regi ster page is to be accessed. ps1 ps0 0 0 page 0 0 1 page 1 5:3 rd2,rd1 ,rd0 rd2,rd1,rd0 : remote dma command these three encoded bits control operation of the remote dma channel. rd2 could be set to abort any remote dma command in process. rd2 is reset by ax88796 when a remote dma has been completed. the remote byte count should be cleared when a remote dma has been aborted. the remote start address is not restored to the starting address if the remote dma is aborted. rd2 rd1 rd0 0 0 0 not allowed 0 0 1 remote read 0 1 0 remote write 0 1 1 not allowed 1 x x abort / complete remote dma 2 txp txp : transmit packet this bit could be set to initiate transmission of a packet 1 start start : this bit is used to active ax88796 operation. 0 stop stop : stop ax88796 this bit is used to stop the ax88796 operation. 5.1.2 interrupt status register (isr) offset 07h (read/write) field name description 7 rst reset status : set when ax88796 enters reset state and cleared when a start command is issued to the cr. writing to this bit is no effect. 6 rdc remote dma complete set when remote dma operation has been completed 5 cnt counter overflow set when msb of one or more of the tally counters has been set. 4 ovw overwrite : set when receive buffer ring storage resources have been exhausted. 3 txe transmit error set when packet transmitted with one or more of the following errors excessive collisions fifo underrun 2 rxe receive error indicates that a packet was received w ith one or more of the following errors crc error frame alignment error fifo overrun missed packet 1 ptx packet transmitted indicates packet transmitted with no error 0 prx packet received indicates packet received with no error.
asix electronics corporation 35 ax88796 l 3-in-1 local bus fast ethernet controller 5.1.3 interrupt mask register (imr) offset 0fh (write) field name description 7 - reserved 6 rdce dma complete interrupt enable. default ?low? disabled. 5 cnte counter overflow interrupt enable. default ?low? disabled. 4 ovwe overwrite interrupt enable. default ?low? disabled. 3 txee transmit error interrupt enable. default ?low? disabled. 2 rxee receive error interrupt en able. default ?low? disabled. 1 ptxe packet transmitted interrupt enable. default ?low? disabled. 0 prxe packet received interrupt enable. default ?low? disabled. 5.1.4 data configuration register (dcr) offset 0eh (write) field name description 7 rdcr remote dma always completed 6:2 - reserved 1 - reserved 0 wts word transfer select 0 : selects byte-wide dma transfers. 1 : selects word-wide dma transfers. 5.1.5 transmit configuration register (tcr) offset 0dh (write) field name description 7 fdu full duplex : this bit indicates the current media mode is full duplex or not. 0 : half duplex 1 : full duplex 6 pd pad disable 0 : pad will be added when packet length less than 60. 1 : pad will not be added when packet length less than 60. 5 rlo retry of late collision 0 : don?t retransmit packet when late collision happens. 1 : retransmit packet when late collision happens. 4:3 - reserved 2:1 lb1,lb0 encoded loop-back control these encoded configuration bits set the type of loop-back that is to be performed. lb1 lb0 mode 0 0 0 normal operation mode 1 0 1 internal ax88796 loop-back mode 2 1 0 phycevisor loop-back 0 crc inhibit crc 0 : crc appended by transmitter. 1 : crc inhibited by transmitter.
asix electronics corporation 36 ax88796 l 3-in-1 local bus fast ethernet controller 5.1.6 transmit status register (tsr) offset 04h (read) field name description 7 owc out of window collision 6:4 - reserved 3 abt transmit aborted indicates the ax88796 aborted transmi ssion because of excessive collision. 2 col transmit collided indicates that the transmission collided at least once with another station on the network. 1 - reserved 0 ptx packet transmitted indicates transmission without error. 5.1.7 receive configuration (rcr) offset 0ch (write) field name description 7 - reserved 6 intt interrupt trigger mode for isa and 80186 modes 0 : low active 1 : high active (default) interrupt trigger mode for mcs-51 and mc68k modes 0 : high active 1 : low active (default) 5 mon monitor mode 0 : normal operation 1 : monitor mode, the input packet w ill be checked on node address and crc but not buffered into memory. 4 pro pro : promiscuous mode enable the receiver to accept all p ackets with a physical address. 3 am am : accept multicast enable the receiver to accept p ackets with a multicast address. that multicast address must pass the hashing array. 2 ab ab : accept broadcast enable the receiver to accept broadcast packet. 1 ar ar : accept runt enable the receiver to accept runt packet. 0 sep sep : save error packet enable the receiver to accept a nd save packets with error. 5.1.8 receive status register (rsr) offset 0ch (read) field name description 7 - reserved 6 dis receiver disabled 5 phy multicast address received. 4 mpa missed packet 3 fo fifo overrun 2 fae frame alignment error. 1 cr crc error. 0 prx packet received intact
asix electronics corporation 37 ax88796 l 3-in-1 local bus fast ethernet controller 5.1.9 inter-frame gap (ifg) offset 16h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap. default value 15h. 5.1.10 inter-frame gap segment 1(if gs1) offset 12h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap segment 1. default value 0ch. 5.1.11 inter-frame gap segment 2(if gs2) offset 13h (read/write) field name description 7 - reserved 6:0 ifg inter-frame gap segment 2. default value 12h. 5.1.12 mii/eeprom management register (memr) offset 14h (read/write) field name description 7 eeclk eeclk: eeprom clock 6 eeo eeo : (read only) eeprom data out value. that reflects pin-48 eedo value. 5 eei eei eeprom data in. that output to pin-49 eedi as eeprom data input value. 4 eecs eecs eeprom chip select 3 mdo mdo mii data out. the value reflects to pin-66 mdio when mdir=0. 2 mdi mdi: (read only) mii data in. that reflects pin-66 mdio value. 1 mdir mii sta mdio signal direction mii read control bit, asserts this bit let mdio signal as the in p ut signal. deassert this bit let mdio as output signal. 0 mdc mdc mii clock. this value reflects to pin-67 mdc. 5.1.13 test register (tr) offset 15h (write) field name description 7:5 - reserved 4 tf16t test for collision, default value is logic 0 (user always keep the default value unchanged) 3 tpe test pin enable, default value is logic 0 (user always keep the default value unchanged) 2:0 ifg select test pins output, default value is logic 0 (user always keep the default value unchanged)
asix electronics corporation 38 ax88796 l 3-in-1 local bus fast ethernet controller 5.1.14 test register (tr) offset 15h (read) field name description 7:4 - reserved 3 rst_tx b 100base-tx in reset : this signal indicates that 100base-tx logic of internal phy is in reset. 2 rst_10b 10base-t in reset : this signal indicates that 10base-t logic of internal phy is in reset. 1 rst_b reset busy : this signal indicates that internal phy is in reset. 0 autod autonegotiation done : this signal goes high whenever internal phy autonegotiation has completed. it will go low if autonegotiation has to restart. 5.1.15 general purpose input register (gpi) offset 17h (read) field name description 7 - reserved 6 gpi2 this register reflects gpi[2] input value. may connect to external phy speed status. 5 gpi1 this register reflects gpi[1] input value. may connect to external phy duplex status. 4 gpi0 this register reflects gpi[0] input value. may connect to external phy link status. 3 - reserved 2 i_spd this register reflects internal phy speed status value. logic one means 100mbps 1 i_dpx this register reflects internal phy duplex status value. logic one means full duplex. 0 i_link this register reflects internal phy link status value. logic one means link ok. 5.1.16 gpo and control (gpoc) offset 17h (write) field name description 7 - reserved 6 ppdset internal phy power down setting: default ?0?, internal phy is in normal operation mode write ppdset to ?1? force internal phy into power down mode 5 mpset media set by program : the signal is valid only when mpsel is set to high. when mpset is logic 0 , in ternal phy is selected. when mpset is logic 1 , exte rnal mii phy is selected. 4 mpsel media priority select : mpsel i_link gpi0 media selected 0 1 0 internal phy 0 1 1 internal phy 0 0 0 external mii phy 0 0 1 internal phy 1 x x depend on mpset bit 3:1 - reserved 0 /gpo0 default ?0?. the register reflects to gpo[0] pin with inverted value.
asix electronics corporation 39 ax88796 l 3-in-1 local bus fast ethernet controller 5.1.17 spp data port register (spp_ dpr) offset 18h (read/write) field name description 7:0 dp printer data port. default is in input mode . write /doe of spp_cpr register to logic ?0? to enable print data output to printer as bi-directional mode. 5.1.18 spp status port register (spp_spr) offset 19h (read) field name description 7 /busy reading a ?0? indicates that the printer is not ready to receive new data. the register reflects the inverted value of busy pin. 6 /ack reading a ?0? indicates that the printer ha s received the data and is ready to accept new data. the register reflects the value of /ack pin. 5 pe reading a ?1? indicates that the printer is out of paper. the register reflects the value of pe pin. 4 slct reading a ?1? indicates that the printer has power on. the register reflects the value of slct pin. 3 /err reading a ?0? indicates that there is an error condition at the printer. the register reflects the value of /err pin. 2:0 - reserved 5.1.19 spp command port register (spp_ cpr) offset 1ah (read/write) field name description 7:6 - reserved 5 /doe setting to ?0? enables print data output to printer. default sets to ?1?. 4 irqen irq enable : printer port interrupt is not supported . 3 slctin setting to ?1? selects the printer. /slin pin reflects the inverted value of this signal. 2 /init setting to ?0? initiates the printer /init pin reflects the value of this signal. 1 atfd setting to ?1? causes the pr inter to automatically feed one line after each line is printed. /atfd pin reflects the inverted value of this signal. 0 strb setting a low-high-low pulse on this register is used to strobe the print data into the printer. /strb pin reflects the inverted value of this signal.
asix electronics corporation 40 ax88796 l 3-in-1 local bus fast ethernet controller 5.2 the embedded phy registers the mii management 16-bit register set implemented is as follows. and the following sub-section will describes each field of the registers. the format for th e ?field? descriptions is as follows: the first number is the register number, the second number is the bit position in the register and the name of the instantiated pad is in capital letters. the format for the ?type? descriptions is as follows: r = read, w = write, lh = latch high, na = not applicable. address name description default(hex code) 0 mr0 control 3000h 1 mr1 status 7849h 2 mr2 phy identifier 1 0180h 3 mr3 phy identifier 2 bb10h 4 mr4 autonegotiation advertisement 01e1h 5 mr5 autonegotiation li nk partner ability 0000 6 mr6 autonegotiation expansion 0000 7 mr7 next page transmit 0000 8 - 15 mr8 -15 (reserved) - 16 mr16 pcs control register 0000 17 mr17 autonegotiation (read register a) 0000 18 mr18 autonegotiation (read register b) 0000 19 mr19 analog test register - 20 mr20 user-defined register - 21 mr21 rxer counter 0000 22 - 24 mr22 -24 analog test registers - 25 - 27 mr25 -27 analog test (tuner) registers - 28 mr28 device specific 1 - 29 mr29 device specific 2 2080 30 mr30 device specific 3 0000 31 mr31 quick status register - tab - 14 the embedded phy registers
asix electronics corporation 41 ax88796 l 3-in-1 local bus fast ethernet controller 5.2.1 mr0 -- control register bit descriptions field type description 0.15 (sw_reset) r/w reset. setting this bit to a 1 will reset the phy. all registers will be set to their default state. this bit is self-clearing. the default is 0. 0.14 (loopback) r/w loopback. when this bit is set to 1, no da ta transmission will take place on the media. any receive data will be ignored. the loopback signal path will contain all circuitry up to, but not including, the pmd. the default value is a 0. 0.13(speed100) r/w speed selection. the value of this bit reflects the current speed of operation (1 = 100mbits/s; 0 = 10mbits/s). this bit will only affect operating speed when the autonegotiation enable bit (register 0, bit 12) is disabled (0). this b it is ignored when autonegotiation is enabled (register 0, bit 12). this bit is anded with the speed_pin signal. 0.12 (nway_ena) r/w autonegotiation enable. the autonegotiation process will be enabled by set-ting this bit to a 1. the default state is a 1. 0.11 (pwrdn) r/w powerdown. the phy may be placed in a low- p ower state by setting this bit to a 1, both the 10mbits/s transcei ver and the 100mbits/s transceiver will b e powered down. while in the power down state, the phy will respond to management transactions. the default state is a 0. 0.10 (isolate) r/w isolate. when this bit is set to a 1, th e mii outputs will be brought to the high-impedance state. the default state is a 0. 0.9 (redonway) r/w restart autonegotiation. n ormally, the autonegotiation process is started at powerup. the process may be restarted by setting this bit to a 1. the default state is a 0. the nwaydone bit (regi ster 1, bit 5) is reset when this bit goes to a 1. this bit is self-cleared when autonegotiation restarts. 0.8 (full_dup) r/w duplex mode. this bit reflects the mode of operation (1 = full duplex; 0 = half duplex). this bit is ignored when the autonegotiation enable bit (register 0, bit 12) is enabled. the default state is a 0. this bit is ored with the f_dup pin. 0.7 (coltst) r/w collision test. when this bit is set to a 1, the phy will assert the mcol signal in response to mtx_en. 0.6:0 (reserved) na reserved. all bits will read 0.
asix electronics corporation 42 ax88796 l 3-in-1 local bus fast ethernet controller 5.2.2 mr1 -- status register bit descriptions field type description 1.15 (t4able) r 100base-t4 ability. this bit will always be a 0. 0: not able. 1: able. 1.14 (txfuldup) r 100base-tx full-duplex ability. this bit will always be a 1. 0: not able. 1: able. 1.13 (txhafdup) r 100base-tx half-duplex ability. this bit will always be a 1. 0: not able. 1: able. 1.12 (enfuldup) r 10base-t full-duplex ability. this bit will always be a 1. 0: not able. 1: able. 1.11 (enhafdup) r 10base-t half-duplex ability. this bit will always be a 1. 0: not able. 1: able. 1.10:7 (reserved) r reserved. all bits will read as a 0. 1.6 (no_pa_ok) r suppress preamble. when this bit is set to a 1, it indicates that the phy accepts management frames with the preamble suppressed. 1.5 (nwaydone) r autonegotiation complete. when this bit is a 1, it indicates the autonegotiation process has been completed. the contents of registers mr4, mr5, mr6, and mr7 are now valid. the default value is a 0. this bit is reset when autonegotiation is started. 1.4 (rem_flt) r remote fault. when this bit is a 1, it indicates a remote fault has been detected. this bit will remain set until cleared by reading the register. the default is a 0. 1.3 (nwayable) r autonegotiation ability. when this bit is a 1, it indicates the ability to perform autonegotiation. the value of this bit is always a 1. 1.2 (lstat_ok) r link status. when this bit is a 1, it indicates a valid link has been established. this bit has a latching function: a link failure will cause the bit to clear and stay cleared until it has b een read via the management interface. 1.1 (jabber) r jabber detect. this bit will be a 1 whenever a jabber condition is detected. it will remain set until it is read, and the jabber condition no longer exists. 1.0 (ext_able) r extended capability. this bit indicates that the phy supports the extended register set (mr2 and beyond) . it will always read a 1.
asix electronics corporation 43 ax88796 l 3-in-1 local bus fast ethernet controller 5.2.3 mr2, mr3 -- identification registers (1 and 2) bit descriptions field type description 2.15:0 (oui[3:18]) r organizationally unique identifier. the third through the twenty-fourth b it of the oui assigned to the phy ma nufacturer by the ieee are to be placed in bits. 2.15:0 and 3.15:10. this value is programmable. 3.15:10 (oui[19:24]) r organizationally unique identifier. the remaining 6 bits of the oui. the value for bits 24:19 is programmable. 3.9:4 (model[5:0]) r model number. 6-bit model number of the device. the model number is programmable. 3.3:0 (version[3:0]) r revision number. the value of the present revision number. the version number is programmable. 5.2.4 mr4 ? autonegotiation advertisement registers bit descriptions field type description 4.15 (next_page) r/w next page. the next page function is activated by setting this bit to a 1. this will allow the exchange of additional data. data is carried by optional next pages of information. 4.14 (ack) r/w acknowledge. this bit is the acknowledge bit from the link code word. 4.13 (rem_fault) r/w remote fault. when set to 1, the phy indicates to the link partner a remote fault condition. 4.12:10 (pause) r/w pause. when set to a 1, it indicates that the phy wishes to exchange flow control information with its link partner. 4.9 (100baset4) r/w 100base-t4. this bit should always be set to 0. 4.8 (100baset_fd) r/w 100base-tx full duplex. if written to 1, autonegotiation will advertise that the phy is capable of 100base-tx full-duplex operation. 4.7 (100basetx) r/w 100base-tx. if written to 1, autonegotiation will advertise that the phy is capable of 100base-tx operation. 4.6 (10baset_fd) r/w 10base-t full duplex. if written to 1, autonegotiation will advertise that the phy is capable of 10base-t full-duplex operation. 4.5 (10baset) r/w 10base-t. if written to 1, autonegotiation will advertise that the phy is capable of 10base-t operation. 4.4:0 (select) r/w selector field . reset with the value 00001 for ieee 802.3. 5.2.5 mr5 ? autonegotiation link pa rtner ability (base page) register bit descriptions field type description 5.15 (lp_next_page) r link partner next page. when this bit is set to 1, it indicates that the link partner wishes to engage in next page exchange. 5.14 (lp_ack) r link partner acknowledge. when this bit is set to 1, it indicates that the link partner has successfully receive d at least three consecutive and consistent flp bursts. 5.13 (lp_rem_fault) r remote fault. when this bit is set to 1, it indicates that the link partner has a fault. 5.12:5 (lp_tech_ability) r technology ability field. this field contains the technology ability of the link partner. these bits are similar to the bits defined for the mr4 register (see table 16). 5.4:0 (lp_select) r selector field. this field contains the type of message sent by the link p artner. for ieee 802.3 compliant link partners, this field should read 00001.
asix electronics corporation 44 ax88796 l 3-in-1 local bus fast ethernet controller 5.2.6 mr5 ?autonegotiation link partn er(lp)ability register (next page)bit descriptions field type description 5.15 (lp_next_page) r next page . when this bit is set to logic 0, it indicates that this is the last page to be transmitted. logic 1 indicates that additional pages will follow. 5.14 (lp_ack) r acknowledge. when this bit is set to a logic 1, it indicates that the link partner has successfully received its partner?s link code word. 5.13 (lp__mes_page) r message page. this bit is used by the next _page function to differentiate a message page (logic 1) from an unformatted page (logic 0). 5.12 (lp_ack2) r acknowledge 2. this bit is used by the next_page function to indicate that a device has the ability to comply with the message (logic 1) or not (logic 0). 5.11 (lp_toggle) r toggle . this bit is used by the arbitration function to ensure synchronization with the link partner during next page exchange. logic 0 indicates that the p revious value of the transmitted link code word was logic 1. logic 1 indicates that the previous value of the transmitted link code word was logic 0. 5.10:0 (mcf) r message/unformatted code field . with these 11 b its, there are 2048 p ossible messages. message code field definitions are described in annex 28c of the ieee 802.3u standard. 5.2.7 mr6 ? autonegotiation expansion register bit descriptions field type description 6.15:5 (reserved) r reserved . 6.4 (par_det_fault) r/lh parallel detection fault. when this bit is set to 1, it indicates that a fault has been detected in the parallel detection function. this fault is due to more than one technology detec ting concurrent link cond itions. this bit can only be cleared by reading this register. 6.3 (lp_next_page_ab le) r link partner next page able. when this bit is set to 1, it indicates that the link partner supports the next page function. 6.2 (next_page_able) r next page able. this bit is set to 1, indicating that this device supports the next_page function. 6.1 (page_rec) r/lh page received . when this bit is set to 1, it indicates that a next_page has been received. 6.0 (lp_nway_able) r link partner autonegotiation capable. when this bit is set to 1, it indicates that the link partner is autonegotiation capable.
asix electronics corporation 45 ax88796 l 3-in-1 local bus fast ethernet controller 5.2.8 mr7 ?next page transmit register bit descriptions field type description 7.15 (next_page) r/w next page. this bit indicates whether or not this is the last next page to be transmitted. when this bit is 0, it indicates that this is the last page. when this bit is 1, it indicates there is an additional next page. 7.14 (ack) r acknowledge. this bit is the acknowledge bit from the link code word. 7.13 (message) r/w message page. this bit is used to differentiate a message page from an unformatted page. when this bit is 0, it indicates an unformatted page. when this bit is 1, it indicates a formatted page. 7.12 (ack2) r/w acknowledge 2. this bit is used by the next page function to indicate that a device has the ability to comply with the message. it is set as follows: when this bit is 0, it indicates the device cannot comply with the message. when this bit is 1, it indicates the device will comply with the message. 7.11 (toggle) r toggle. this bit is used by the arbitration function to ensure synchronization with the link partner during next page exchange. this bit will always take the opposite value of the toggle bit in the previously exchanged link code word: if the bit is logic 0, the previous value of the transmitted link code word was logic 1. if the bit is a 1, the previous value of the transmitted link code word was a 0. the initial value of the t oggle bit in the first next page transmitted is the inverse of the value of bit 11 in the base link code word, and may assume a value of 1 or 0. 7.10:0 (mcf) r/w message/unformatted code field. with these 11 bits, there are 2048 p ossible messages. message code field definitions are described in annex 28c of the ieee 802.3u standard. 5.2.9 mr16 ? pcs control register bit descriptions field type description 16.15 (locked) r locked. locked pin from descrambler block. 16.14-12 (unused) r unused. will always be read back as 0. 16.11-4 (testbits) r/w generic test bits. these bits have no effect on the pcs block. they are for external use only. a 0 should be written to these bits. 16.3 (loopback) r/w loopback configure. when this bit is high, the entire loopback is p erformed in the pcs macro. when this bit is low, only the collision pin is disabled in loopback. 16.2 (scan) r/w scan test mode . 16.1 (force loopback) r/w force loopback. force a loopback without forcing idle on the transmit side or disabling the collision pin. 16.0 (speedup counters) r/w speedup counters. reduce link monitor counter to 10 us from 620 us. (same as fasttest = 1.)
asix electronics corporation 46 ax88796 l 3-in-1 local bus fast ethernet controller 5.2.10 mr17 ?autonegotiation register a bit descriptions field type description 17.15-13 r reserved. always 0. 17.12 r next page wait. 17.11 r wait link_fail_inhibit_wait _timer (link status check). 17.10 r wait autoneg_wait_timer (link status check). 17.9 r wait break_link_timer (transmit disable). 17.8 r parallel detection fault. 17.7 r autonegotiation enable. 17.6 r flp link good check. 17.5 r complete acknowledge. 17.4 r acknowledge detect. 17.3 r flp link good. 17.2 r link status check. 17.1 r ability detect. 17.0 r transmit disable. 5.2.11 mr18 ?autonegotiation register b bit descriptions field type description 18.15 r receiving flps . any of flp capture, clock, data_0, or data_1 (flp rcv). 18.14 r flp pass (flp rcv). 18.13 r link pulse count (flp rcv). 18.12 r link pulse detect (flp rcv). 18.11 r test pass (nlp rcv). 18.10 r test fail count (nlp rcv). 18.9 r test fail extend (nlp rcv). 18.8 r wait max timer ack (nlp rcv). 18.7 r detect freeze (nlp rcv). 18.6 r test fail (nlp rcv). 18.5 r transmit count ack (flp xmit). 18.4 r transmit data bit (flp xmit). 18.3 r transmit clock bit (flp xmit). 18.2 r transmit ability (flp xmit). 18.1 r transmit remaining acknowledge (flp xmit). 18.0 r idle (flp xmit). 5.2.12 mr20 ?user defined register bit descriptions field type description 20.[15:0] r/w the data written into this user-defined register appears on the reg20_out[15:0] bus.
asix electronics corporation 47 ax88796 l 3-in-1 local bus fast ethernet controller 5.2.13 mr21 ?rxer counter register bit descriptions field type description 21.0 w this bit, when 0 puts this register in 16- b it counter mode. when 1, it puts this register in 8-bit counter mode. this bit is reset to a 0 and cannot be read. 21.15:0 r when in 16-bit counter mode, these maintain a count of rxers. it is reset on a read operation. 21.7:0 r when in 8- b it counter mode, these maintain a count of rxers. it is reset on a read operation 21.11:8 r when in 8- b it mode, these contain a count of false carrier events (802.3 section 27.3.1.5.1). it is reset on a read operation. 21.15:12 r when in 8- b it mode, these contain a count of disconnect events (link unstable 6, 802.3 section 27.3.1.5.1). it is reset on a read operation. 5.2.14 mr28 ?device-specific register 1 (status register) bit descriptions field type description 28.15:9 (unused) r unused. read as 0. 28.8 (bad_frm) r/lh bad frame. if this bit is a 1, it indicates a packet has been received without an sfd. this bit is only valid in 10mbits/s mode. this bit is latching high and will only clear after it has been read or the device has been reset. 28.7 (code) r/lh code violation. when this bit is a 1, it indicates a manchester code violation has occurred. the error code will be output on the mrxd lines. refer to table 1 for a detailed description of the mrxd pin error codes. this bit is only valid in 10mbits/s mode. this bit is latching high and will only clear after it has been read or the device has been reset. 28.6 (aps) r autopolarity status. when register 30, bit 3 is set and this bit is a 1, it indicates the phy has detected and corrected a polarity reversal on the twisted pair. if the apf_en bit (register 30, bit 3) is set, the reversal will be corrected inside the phy. this bit is not valid in 100mbits/s operation. 28.5 (discon) r/lh disconnect. if this bit is a 1, it indicates a disconnect. this bit will latch high until read. this bit is only valid in 100mbits/s mode. 28.4 (unlocked) r/lh unlocked. indicates that the tx scrambler lost lock. this bit will latch high until read. this bit is only valid in 100mbits/s mode. 28.3 (rxerr_st) r/lh rx error status. indicates a false carrier. this bit will latch high until read. this bit is only valid in 100mbits/s mode. 28.2 (frc_jam) r/lh force jam. this bit will latch high until read. this bit is only valid in 100mbits/s mode. 28.1 (lnk100up) r link up 100. this bit, when set to a 1, indicates a 100mbits/s transceiver is up and operational. 28.0 (lnk10up) r link up 10. this bit, when set to a 1, indicates a 10mbits/s transceiver is up and operational.
asix electronics corporation 48 ax88796 l 3-in-1 local bus fast ethernet controller 5.2.15 mr29 ?device-specific register 2 (100mbps control) bit descriptions field type description 29.15 (localrst) r/w management reset. this is the local management reset bit. writing logic 1 to this bit will cause the lower 16 registers and registers 28 and 29 to be reset to their default values. this bit is self-clearing. 29.14 (rst1) r/w generic reset 1. this register is used for manufacture test only. 29.13 (rst2) r/w generic reset 2. this register is used for manufacture test only. 29.12 (100_off) r/w 100mbits/s transmitter off. when this bit is set to 0, it forces tpi low and tpin- high. this bit defaults to 1. 29.11 (led_blink) r/w led blinking. this register, when 1, enables led blinking. this is ored with led_blink_en. default is 0. 29.10 (crs_sel) r/w carrier sense select. mcrs will be asserted on receive only when this bit is set to a 1. if this bit is set to logi c 0, mcrs will by asserted on receive or transmit. this bit is ored with the crs_sel pin. 29.9 (link_err) r/w link error indication. when this bit is a 1, a link error code will be reported on mrxd[3:0] of the phy when mrx_er is asserted on the mii. the specific error codes are listed in the mrxd pin description. if it is 0, it will disable this function. 29.8 (pkt_err) r/w packet error indication enable. when this bit is a 1, a packet error code, which indicates that the scrambler is not locked, will be reported on mrxd[3:0] of the phy when mrx_er is asserted on the mii. when this bit is 0, it will disable this function. 29.7 (pulse_str) r/w pulse stretching. when this bit is set to 1, the cs, xs, and rs output signals will be stretched between approximately 42 ms - 84 ms. if this bit is 0, it will disable this feature. default state is 0. 29.6 (edb) r/w encoder/decoder bypass. when this bit is set to 1, the 4b/5b-encoder and 5b/4b-decoder function will be disabled. this bit is ored with the edbt pin. 29.5 (sab) r/w symbol aligner bypass. when this bit is set to 1, the aligner function will be disabled. 29.4 (sdb) r/w scrambler/descrambler bypass. when this bit is set to 1, the scrambling/ descrambling functions will be disabled. this bit is ored with the sdbt pin. 29.3 (carin_en) r/w carrier integrity enable. when this bit is set to a 1, carrier integrity is enabled. this bit is ored with the carin_en pin. 29.2 (jam_col) r/w jam enable. when this bit is a 1, it enable s jam associated with carrier integrity to be ored with mcolmcrs. 29.1 (fef-en) r/w far-end fault enable . this bit is used to enable the far-end fault detection and transmission capability. this capability may only be used if autonegotiation is disabled. this capability is to be used only with media which does not support autonegotiation. setting this bit to 1 enables far-end fault detection, and logic 0 will disable the function. default state is 0. 29.0 (fx) r/w fiber-optic mode. when this bit is a 1, the phy is in fiber-optic mode. this bit is ored with fx_mode.
asix electronics corporation 49 ax88796 l 3-in-1 local bus fast ethernet controller 5.2.16 mr30 ?device-specific register 3 (10mbps control) bit descriptions field type description 30.15 (test10tx) r/w when high and 10base-t is powered up, a continuous 10 mhz signal (1111) will be transmitted. this is only meant for testing. default 0. 30.14 (rxpllen) r/w when high, all 10base-t logi c will be powered up when the link is up. otherwise, portions of the logic will be powered down when no data is being received to conserve power. default is 0. 30.13 (jab_dis) r/w jabber disable. when this bit is 1, disables the jabber function of the 10base-t receive. default is 0. 30.12:7 (unused) r/w unused. read as 0. 30.6 (litf_enh) r/w enhanced link integrity test function. when high, function is enabled. this is ored with the litf_enh input. default is 0. 30.5 (hbt_en) r/w heartbeat enable. when this bit is a 1, the heartbeat function will be enabled. valid in 10mbits/s mode only. 30.4 (ell_en) r/w extended line length enable. when this bit is a 1, the receive squelch levels are reduced from a nominal 435 mv to 350 mv, allowing reception of signals with a lower amplitude. valid in 10mbits/s mode only. 30.3 (apf_en) r/w autopolarity function disable. when this bit is a 0 and the phy is in 10 mbits/s mode, the autopolarity functi on will determine if the tp link is wired with a polarity reversal. if there is a polarity reversal, the phy will assert the aps bit (register 28, bit 6) and correct the polarity reversal. if this bit is a 1 and the device is in 10 mbits/s mode, the reversal will not be corrected. 30.2 (reserved) r/w reserved . 30.1 (serial _sel) r/w serial select. when this bit is set to a 1, 10mbits/s serial mode will be selected. when the phy is in 100mbits /s mode, this bit will be ignored. 30.0 (ena_no_lp) r/w no link pulse mode. setting this bit to a 1 will allow 10mbits/s operation with link pulses disabled. if the phy is configured for 100mbits/s operation, setting this bit will not affect operation.
asix electronics corporation 50 ax88796 l 3-in-1 local bus fast ethernet controller 5.2.17 mr31 ?device-specific register 4 (quick status) bit descriptions field type description 31.15 (error) r receiver error. when this bit is a 1, it indicates that a receive error has been detected. this bit is valid in 100mbits /s only. this bit will remain set until cleared by reading the register. default is a 0. 31.14 (rxerr_st)/(link_st at_change) r false carrier. when bit [31.7] is set to 0 and this bit is a 1, it indicates that the carrier detect state machine has found a false carrier. this bit is valid in 100mbits/s only. this bit will remain set until cleared by reading the register. default is 0. link status change. when bit [31.7] is set to a 1, this bit is redefined to become the link_stat_change bit and goes high whenever there is a change in link status (bit [31.11] changes state) 31.13 (rem_flt) r remote fault. when this bit is a 1, it indicates a remote fault has been detected. this bit will remain set until cleared by reading the register. default is a 0. 31.12 (unlocked)/(jabbe r) r unlocked/jabber. if this bit is set when opera ting in 100mbits/s mode, it indicates that the tx descrambler has lost lock. if this bit is set when operating in 10mbits/s mode, it indicates a jabber condition has been detected. this bit will remain set until cleared by reading the register. 31.11 (lstat_ok) r link status. when this bit is a 1, it indicates a valid link has been established. this bit has a latching low function: a link failure will cause the bit to clear and stay cleared until it has been read via the management interface. 31.10 (pause) r link partner pause. when this bit is set to a 1, it indicates that the lu3x54ftl wishes to exchange flow control information. 31.9 (speed100) r link speed. when this bit is set to a 1, it indicates that the link has negotiated to 100mbits/s. when this bit is a 0, it i ndicates that the link is operating at 10mbits/s. 31.8 (full_dup) r duplex mode. when this bit is set to a 1, it indicates that the link has negotiated to full-duplex mode. when this bit is a 0, it indicates that the link has negotiated to half-duplex mode. 31.7 (int_conf) r/w interrupt configuration. when this bit is set to a 0, it defines bit [31.14] to be the rxerr_st bit and the interr upt pin (mask_stat_int) goes high whenever any of bits [31.15:12] go high, or bit [31.11] goes low. when this bit is set high, it redefines bit [31.14] to become the link_stat_change bit, and the interrupt pin (mask_stat_int) goes high only when the link status changes (bit [31.14] goes high). this bit defaults to 0. 31.6 (int_mask) r/w interrupt mask. when set high, no interrupt is generated by this channel under any condition. when set low, interrupts are generated according to bit [31.7]. 31.5:3 (low_auto__state) r lowest autonegotiation state. these 3 bits report the state of the lowest autonegotiation state reached since the last register read, in the priority order defined below: 000: autonegotiation enable. 001: transmit disables or ability detects. 010: link status check. 011: acknowledge detects. 100: complete acknowledges. 101: flp link good check. 110: next page wait. 111: flp link good. 31.2:0 (hi_auto_state) r highest autonegotiation state. these 3 bits report the state of the highest autonegotiation state reached since the last register read, as defined above for bit [31.5:3].
asix electronics corporation 51 ax88796 l 3-in-1 local bus fast ethernet controller 6.0 cpu i/o read and write functions 6.1 isa bus type access functions. isa bus i/o read function function mode /cs /bhe a0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x x x high-z high-z byte access l l h h l h l l h h not valid not valid even-byte odd-byte word access l l l l h odd-byte even-byte isa bus i/o write function function mode /cs /bhe a0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x x x x x byte access l l h h l h h h l l x x even-byte odd-byte word access l l l h l odd-byte even-byte 6.2 80186 cpu bus type access functions. 80186 cpu bus i/o read function function mode /cs /bhe a0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x x x high-z high-z byte access l l h l l h l l h h not valid odd-byte even-byte not valid word access l l l l h odd-byte even-byte 80186 cpu bus i/o write function function mode /cs /bhe a0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x x x x x byte access l l h l l h h h l l x odd-byte even-byte x word access l l l h l odd-byte even-byte
asix electronics corporation 52 ax88796 l 3-in-1 local bus fast ethernet controller 6.3 mc68k cpu bus type access functions. 68k bus i/o read function function mode /cs /uds /lds r/w sd[15:8] sd[7:0] standby mode h x x x high-z high-z byte access l l h l l h h h not valid even-byte odd-byte not valid word access l l l h even-byte odd-byte 68k bus i/o write function function mode /cs /uds /lds r/w sd[15:8] sd[7:0] standby mode h x x x x x byte access l l h l l h l l x even-byte odd-byte x word access l l l l even-byte odd-byte 6.4 mcs-51 cpu bus type access functions. 8051 bus i/o read function function mode /cs /psen sa0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x l x x x x x x high-z high-z high-z high-z byte access l l h h l h l l h h not valid not valid even-byte odd-byte 8051 bus i/o write function function mode /cs /psen sa0 /iord /iowr sd[15:8] sd[7:0] standby mode h x x l x x x x x x x x x x byte access l l h h l h h h l l x x even-byte odd-byte
asix electronics corporation 53 ax88796 l 3-in-1 local bus fast ethernet controller 6.5 cpu access mii station management functions. basic operation the primary function of station management is to trans fer control and status information about the phy to a management entity. this function is accomplished by t he mdc clock input from mac entity, which has a maximum frequency of 12.5 mhz (for internal phy only, as to external phy please refer to the relevant specification), along with the mdio signal. the internal phy address is fixed to 10h and the equivalent circuit is shown as below: a specific set of registers and their contents (described in tab - 16 mii management frames- field description ) defines the nature of the information transferred acro ss the mdio interface. frames transmitted on the mii management interface will have t he frame structure shown in tab - 15 mii management frame format . the order of bit transmission is from left to right. note t hat reading and writing the m anagement register must be completed without interruption. read/write (r/w) pre st op phyad regad ta data idle r 1. . .1 01 10 aaaaa rrrrr z0 dddddddddddddddd z w 1. . .1 01 01 aaaaa rrrrr 10 dddddddddddddddd z tab - 15 mii management frame format field descriptions pre preamble . the phy will accept frames with no preamble. this is indicated by a 1 in register 1, bit 6. st start of frame. the start of frame is indicated by a 01 pattern. op operation code . the operation code for a read transacti on is 10. the operation code for a write transaction is a 01. phyadd phy address . the phy address is 5 bits, allowing for 32 unique addresses. the first phy address bit transmitted and received is the msb of the a ddress. a station management entity that is attached to multiple phy entities must have prio r knowledge of the appropriate phy address for each entity. regad register address. the register address is 5 bits, allowing fo r 32 unique registers within each phy. the first register address bit transmitted a nd received is the msb of the address. ta turnaround . the turnaround time is a 2-bit time spacing between the register address field, and the data field of a frame, to avoid drive contention on mdio during a read transaction. during a write to the phy, these bits is driven to 10 by the station. during a read, the mdio is not driven during the first bit time and is driven to a 0 by the phy during the second bit time. data data . the data field is 16 bits. the first bit transm itted and received will be bit 15 of the register being addressed. idle idle condition. the idle condition on mdio is a high-impedan ce state. all three state drivers will be disabled and the phy?s pull-up resistor will pull the mdio line to logic 1. tab - 16 mii management frames- field description 0 y (mux) 1 s (internal phy) mdc mdio-out mdio-in if (phy_id==10h) then s=1 else s=0 pin67 mdc pin66 mdio from register offset 14h mdc mdo mdi mdi r
asix electronics corporation 54 ax88796 l 3-in-1 local bus fast ethernet controller 7.0 electrical specification and timings 7.1 absolute maximum ratings description sym min max units operating temperature ta 0 +85 c storage temperature ts -55 +150 c supply voltage vdd -0.3 +4.6 v input voltage vin -0.3 5.5* v output voltage vout -0.3 vdd+0.5 v lead temperature (soldering 10 seconds maximum) tl -55 +220 c note : stress above those listed under absolute maximum rati ngs may cause permanent damage to the device. exposure to absolute maximum ratings conditions for extended period, adversely affect device life and reliability. note: * all digital input signals can sustain 5 volts input voltage except pin-79 lclk/xtalin 7.2 general operation conditions description sym min tpy max units operating temperature ta 0 25 +75 c supply voltage vdd +3.14 +3.30 +3.46 v 7.3 dc characteristics (vdd=3.0v to 3.6v, vss=0v, ta=0 c to 75 c) description sym min tpy max units low input voltage vil - 0.8 v high input voltage vih 1.9 - v low output voltage vol - 0.4 v high output voltage voh vdd-0.4 - v input leakage current iil -1 +1 ua output leakage current iol -1 +1 ua description sym min tpy max units power consumption (3.3v) spt3v 94 120 ma
asix electronics corporation 55 ax88796 l 3-in-1 local bus fast ethernet controller 7.4 a.c. timing characteristics 7.4.1 xtal / clock lclk/xtalin tr tf tlow clko tod symbol description min typ. max units tcyc cycle time 40 ns thigh clk high time 16 20 24 ns tlow clk low time 16 20 24 ns tr/tf clk slew rate 1 - 4 ns tod lclk/xtalin to clko out delay 10 7.4.2 reset timing lclk/xtalin reset /reset symbol description min typ. max units trst reset pulse width 100 - - lclk note : some chips may need long power down for successful phy auto negotiation root of cause: the phy inside of ax88796 has a special request due to the semiconductor?s process. namely, it needs a very long power down for successful auto negotiation for some chips. we made a test in lab and found it would be no problem if the phy's initial time kept for 2 sec for all chips . if the power down is less then this number, some of the phy's auto negotiation will not be complete and there will be potential to cause the link fail. if the auto negotiation time is not long enough, uncertain numbers of chip may not work properly. countermeasure: tcyc thigh
asix electronics corporation 56 ax88796 l 3-in-1 local bus fast ethernet controller following actions will fix the problem of long auto negotiation. 1. set the phy register mr0 with 0x800h (1000,0000,0000) -- bit 11 of mr0 to '1' (power down mode). 2. wait for 2.5 sec 3. set the phy register mr0 with 0x1200h(0001,0010,0000,0000) -- bit 12,9 of mr0 to '1' (auto negotiation enable and restart auto negotiation)
asix electronics corporation 57 ax88796 l 3-in-1 local bus fast ethernet controller 7.4.3 isa bus access timing tsu(aen) th(aen) aen tsu(a) th(a) /bhe sa[9:0],/cs tv(cs16-a) tdis(cs16-a) /iocs16 ten(rd) /iowr,/iord tv(rdy) tdis(rdy) rdy tdis(rd) read data sd[15:0](dout) data valid tsu(wr) th(wr) write data sd[15:0](din) data input establish symbol description min typ. max units tsu(a) address setup time 0 - - ns th(a) address hold time 5 - - ns tsu(aen) aen setup time 0 - - ns th(aen) aen hold time 5 - - ns tv(cs16-a) /iocs16 valid from address change - - 20 ns tdis(cs16-a) /iocs16 disable from address change - - 6 ns tv(rdy) rdy valid from sa[9:0]=310 valid - - 20 ns tdis(rdy) rdy disable from /iord or /iowr 0 - - ns ten(rd) output enable time from /iord - - 20 ns tdis(rd) output disable time from /iord 0.5 - 4 ns tsu(wr) data setup time 5 - - ns th(wr) data hold time 5 - - ns tio(ds) i/o cycle width time 160 ns note: tio(ds) is for data port only (register 10 and 11) tio(ds)
asix electronics corporation 58 ax88796 l 3-in-1 local bus fast ethernet controller 7.4.4 80186 type i/o access timing tsu(a) th(a) /bhe sa[9:0],/cs tw(rw) /iowr,/iord tv(rdy) tdis(rdy) rdy ten(rd) tdis(rd) read data sd[15:0](dout) data valid tsu(wr) th(wr) write data sd[15:0](din) data input establish symbol description min typ. max units tsu(a) address setup time 0 - - ns th(a) address hold time 5 - - ns tv(rdy) rdy valid from /iord or /iowr - - 20 ns tdis(rdy) rdy disable from sa[9:0]=310 valid 0 - - ns ten(rd) output enable time from /iord - - 20 ns tdis(rd) output disable time from /iord 0.5 - 4 ns tsu(wr) data setup time 5 - - ns th(wr) data hold time 5 - - ns tw(rw) /iord or /iowr width time 50 ns tio(ds) i/o cycle width time 160 ns note: tio(ds) is for data port only (register 10 and 11) tio(ds)
asix electronics corporation 59 ax88796 l 3-in-1 local bus fast ethernet controller 7.4.5 68k type i/o access timing tsu(a) th(a) sa[9:1],/cs tv(ds-wr) tw(ds) tdis(wr-ds) /uds,/lds (read) r/w ten(ds) (write) r/w tv(dtack) tdis(dtack) /dtack tdis(ds) (read data) sd[15:0](dout) data valid tsu(ds) th(ds) (write data) sd[15:0](din) data input establish symbol description min typ. max units tsu(a) address setup time 0 - - ns th(a) address hold time 5 - - ns tv(ds-wr) /uds or /lds valid from /w 0 - - ns tdis(wr-ds) /w disable from /uds or /lds 5 - - ns tv(dtack) dack valid from /uds or /lds - - 20 ns tdis(dtack) dack disable from /uds or /lds 0 - - ns ten(ds) output enable time from /uds or /lds - - 20 ns tdis(ds) output disable time from /uds or /lds 0.5 - 4 ns tsu(ds) data setup time 5 - - ns th(ds) data hold time 5 - - ns tio(ds) i/o cycle width time 160 ns tw(ds) /uds or /lds width time 50 ns note: tio(ds) is for data port only (register 10 and 11) tio(ds)
asix electronics corporation 60 ax88796 l 3-in-1 local bus fast ethernet controller 7.4.6 8051 bus access timing /psen tsu(psen) th(psen) tsu(a) th(a) sa[9:0],cs ten(rd) /iowr,/iord tw(rw) tv(rdy) tdis(rdy) (for reference) rdy tdis(rd) read data sd[7:0](dout) data valid tsu(wr) th(wr) write data sd[7:0](din) data input establish symbol description min typ. max units tsu(a) address setup time 0 - - ns th(a) address hold time 5 - - ns tsu(psen) /psen setup time 0 - - ns th(psen) /psen hold time 5 - - ns ten(rd) output enable time from /iord - - 20 ns tdis(rd) output disable time from /iord 0.5 - 4 ns tsu(wr) data setup time 5 - - ns th(wr) data hold time 5 - - ns tio(ds) i/o cycle width time 160 ns note: tio(ds) is for data port only (register 10 and 11) tio(ds)
asix electronics corporation 61 ax88796 l 3-in-1 local bus fast ethernet controller 7.4.7 mii timing ttclk ttch ttcl txclk ttv tth txd<3:0> txen trclk trch trcl rxclk trs trh rxd<3:0> rxdv trs1 rxer symbol description min typ. max units ttclk cycle time(100mbps) - 40 - ns ttclk cycle time(10mbps) - 400 - ns ttch high time(100mbps) 14 - 26 ns ttch high time(10mbps) 140 - 260 ns trch low time(100mbps) 14 - 26 ns trch low time(10mbps) 140 - 260 ns ttv clock to data valid - - 20 ns tth data output hold time 5 - - ns trclk cycle time(100mbps) - 40 - ns trclk cycle time(10mbps) - 400 - ns trch high time(100mbps) 14 - 26 ns trch high time(10mbps) 140 - 260 ns trcl low time(100mbps) 14 - 26 ns trcl low time(10mbps) 140 - 260 ns trs data setup time 6 - - ns trh data hold time 10 - - ns trs1 rxer data setup time 10 - - ns
asix electronics corporation 62 ax88796 l 3-in-1 local bus fast ethernet controller 8.0 package information b e d hd e he pin 1 a2 a1 l l1 a milimeter symbol min. nom max a1 0.05 0.1 0.15 a2 1.35 1.40 1.45 a 1.6 b 0.17 0.22 0.27 d 13.90 14.00 14.10 e 19.90 20.00 20.10 e 0.5 hd 15.60 16.00 16.40 he 21.00 22.00 23.00 l 0.45 0.60 0.75 l1 1.00 0 7
asix electronics corporation 63 ax88796 l 3-in-1 local bus fast ethernet controller appendix a: application note 1 a.1 using crystal 25mhz ax88796 clko25m 25mhz xtalin xtalout 25mhz crystal 33pf 33pf note : the capacitors (33pf) may be various depend on the specification of crystal. while designing, please refer to the suggest circuit provided by crystal supplier. a.2 using oscillator 25mhz ax88796 clko 25m 25mhz xtalin xtalout nc 3.3v power osc 25mhz
asix electronics corporation 64 ax88796 l 3-in-1 local bus fast ethernet controller appendix b: power consumption reference data the following reference data of power consumption are measured base on prime application, that is ax88796 + eeprom, at 3.3v/25 c room temperature. item test conditions typical value units 1 power save mode ( power down regi ster bit set to ?1? asserted) 0 ma 2 idel without link 22 ma 3 idel with 10m link 30 ma 4 idel with 100m link 91 ma 5 full traffic with 10mbps at half-duplex mode 48 ? 80 ma 6 full traffic with 10mbps at full-duplex mode 48 ? 80 ma 7 full traffic with 100mbps at half-duplex mode 88 ? 94 ma 8 full traffic with 100mbps at full-duplex mode 88 ? 94 ma 9 power save mode ( power down register bit set to ?1? asserted) no led drive 0 ma 10 idel without link, no led drive 22 ma 11 idel with 10m link, no led drive 25 ma 12 idel with 100m link, no led drive 84 ma 13 full traffic with 10mbps at half-duplex mode, no led drive 46 ? 66 ma 14 full traffic with 10mbps at full-duplex mode, no led drive 46 ? 66 ma 15 full traffic with 100mbps at half-duplex mode, no led drive 83 ma 16 full traffic with 100mbps at full-duplex mode, no led drive 83 ma
asix electronics corporation 65 ax88796 l 3-in-1 local bus fast ethernet controller errata of ax88796 1. mii station management functions has some defference from previous target specification. description: the target specification is using station management can access both internal phy registers and external phy registers when the phy address is matched as describe in section 5.5. anyway, this version can only access the current selected phy?s registers. how do you know which is the selected media or phy? please refer to section 4.1.16 gpo and control (gpoc) register. solution: the defect will not affect single media application that is using embedded phy. when using mii interface connects to external media (for example homepna) to come out with combo solution. care must be taken, be sure which media is the current selected when you access phy registers. 2. ax88796 can?t support 68k cpu with byte mode solution: please using word mode for high performance. mc68008 has only 8-bit bus, so ax88796 can?t support this cpu. 3. when ax88796 transmit a packet and the pack et is collided for 16 times. the packet will be reported as as ptx bit asserted rather than txe asserted. solution: packet collided 16 times and aborted is normal way, even that is rare happen in live network, in very heavy traffic. while the upper protocol layer will handle the situation and cover the packet loss.
asix electronics corporation 66 ax88796 l 3-in-1 local bus fast ethernet controller demonstration circuit (a) : ax88796 with isa bus + homepna 1m8 phy sa6 iois16# c26 0.1u sd7 sa9 irq11 5v + c54 47u/16v dip 100mil & smd 1206 + c60 47u/16v dip 100mil & smd1206 gnd aen ax88796 10base-t/100base-tx & 1m homepna application with ns83851 phyceiver. (reference only)(isa mode) sa0 + c52 47u/16v dip 100mil & smd 1206 gnd sd1 c53 0.1u sd5 sd15 sd9 irq7 irq sd10 gnd gnd 5v reset gnd 5v sa4 sa3 irq12 iowr# irq5 reset sd4 iowr# sd[8..15] sd6 irq7 sd[0..15] irq iowr# u1 ams1117 sot-223 1 2 3 4 adj/gnd out in out irq3 c59 0.1u sd[0..7]] sa[0..9] sd3 iord# jp2 is setting irq sa[0..9] gnd c55 0.1u rdy irq12 sa8 iois16# sa2 3.3v c18 0.1u sd[0..15] sd2 aen iord# bhe# 3.3v jp2 10pin jump 1 3 5 7 9 2 4 6 8 10 rdy iois16# sa7 sa[0..9] sa1 sd8 5v bhe# + c17 47u/16v dip 100mil & smd 1206 sd13 3.3v irq5 + c23 47u/16v dip 100mil & smd 1206 irq3 sa5 irq rdy sd11 bhe# sd0 sd14 aen gnd isa1 isa 16bit isa slot a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 b26 b27 b28 b29 b30 b31 d1 d2 d3 d4 d5 d6 d7 d8 d9 d11 d12 d13 d14 d15 d16 d17 d18 d10 iochk# d<7> d<6> d<5> d<4> d<3> d<2> d<1> d<0> chrdy aen sa<19> sa<18> sa<17> sa<16> sa<15> sa<14> sa<13> sa<12> sa<11> sa<10 sa<9> sa<8> sa<7> sa<6> sa<5> sa<4> sa<3> sa<2> sa<1> sa<0> sbhe# la<23> la<22> la<21> la<20> la<19> la<18> la<17> mrdc# mw tc # d<8> d<9> d<10> d<11> d<12> d<13> d<14> d<15> gnd resdrv +5v irq<9> -5v drq<2> -12v nows# +12v gnd smwtc# smrdc lowc# lorc# dak<3># drq<3> dak<1># drq<1> refrsh# bclk irq<7> irq<6> irq<5> irq<4> irq<3> dak<2># t/ c bale +5v osc gnd m16# io16# irq<10> irq<11> irq<12> irq<13> irq<14> dak<0># drq<0> drq<5> dak<6># drq<6> dak<7># drq<7> +5v master16# gnd dak<5># iord# 3.3v sd12 irq11 reset 796ns3a.sch 2.0 isa bus asix electronic corporation a4 14 thursday , april 19, 2001 tit le size document number rev date: sheet of
asix electronics corporation 67 ax88796 l 3-in-1 local bus fast ethernet controller 796ns3a1.sch 2.0 ax88796 a3 24 thursday, april 19, 2001 asix electronics corporation title size document number rev date: sheet of sd11 sd2 sd5 txd3 eedi iois16# sa2 txen pclk sd8 sd6 iowr# sd10 clko25 sd14 sa5 xout xin mdio sd0 sa4 reset txd0 sa8 3.3v cpu0 eecs sa1 mdc sa0 sa7 sd15 sa9 ireq rdy sa3 iord# sd1 sd3 bhe# txck eedo sd7 aen sd9 sd4 sd12 cpu1 sd13 sa6 gnd xin xout rxd0 rxd3 rxd1 rxdv txck crs txen col txd0 txd3 pclk mdc rxck txd1 rxd2 mdio txd2 rxer 3.3v gnd eedi eecs eesk eedo tpip tpin tpon tpop gpi0 txd1 txd2 bhe# irq iowr# reset rdy aen iord# iois16# cs# ledop 3.3v iddq rextbs rext10 rext100 tpip full tpop tpon tpin zvreg zvreg 3.3va 3.3v 3.3vp 3.3v 3.3v 3.3vo eesk txd0 rxd3 rxd0 txd1 txck rxd1 gpi1 gnd crs rxd2 gpi2 txd3 col txd2 rxck txen gpi0 rxdv 3.3v 3.3vd gnd gnd 3.3vd gnd link speed 3.3v rxck rxdv rxd0 rxd1 col crs rxd3 rxd2 xin 3.3v gpi1 gpi2 y1 25mhz r3 10k l2 f.b. smd 1206 c12 0.1u r7 330 r8 330 + c13 4.7uf/16v smd 1206 + c8 4.7uf/16v smd 1206 c4 0.001u + c3 4.7uf/16v smd 1206 r9 330 jp1 6pin jump 1 2 3 4 5 6 c10 0.1u p1 db-25f 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 c19 0.1u l1 f.b. smd 1206 c5 0.01u + c1 4.7uf/16v smd 1206 + c2 4.7uf/16v smd 1206 c20 0.01u c27 0.01u c35 0.001u + c36 4.7uf/16v smd 1206 d1 led d2 led d3 led r52 2m r26 10k u2 93c56r 1 2 3 4 5 6 7 8 cs sk di do gnd nc nc vcc l3 f.b. smd 1206 c31 0.01u c34 0.01u c7 0.01u c33 0.01u c6 0.01u r49 10k r48 10k c9 0.01u c32 0.01u u3 ax88796 lqfp 1 2 3 4 5 6 7 8 9 10 11 12 15 13 14 16 18 19 22 23 24 25 27 28 26 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 123 126 127 128 aen /psen rdy /dtack reset sa0 /lds sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 vdd vss irq /irq /iowr r/w /iord /bhe /uds sd15 sd14 sd13 vdd vss sd12 sd11 sd10 sd9 sd8 sd7 vss sd6 sd5 sd4 sd3 sd2 vdd sd1 sd0 vss clko25m bist iddq test2 eedo eedi ppd_set eeck eecs vss vdd vss vssa vdda vdd cpu0 cpu1 link_led link/act_led speedled act_led full/col_led vss test1 mdio /spp_set mdc vssa vdda tpip tpin vssa vdda rextbs vssa vddm vssm vddpd lclk/xtalin xtalout vsspd vdda rext100 rext10 vssa vsso tpon tpop vsso vsso vddo zvreg vssm vss pd0 rxd0 pd1 rxd1 pd2 rxd2 pd3 rxd3 pd4 rx_clk pd5 crs pd6 col pd7 rx_dv slct gpi0/link vdd vss pe gpi1/dpx /ack tx_clk busy tx_en /strb txd0 /atfd txd1 /init txd2 /slctin txd3 /err gpi2/spd vdd vss led_op io_base0 io_base1 io_base2 gpo0 /iois16 vdd vss /cs + c43 4.7uf/16v smd 1206 r23 24.9k 1% r46 10k c14 0.1u r20 20 r21 20k 1% r22 2.49k 1% r27 10k c29 0.1u r5 0 c28 33p c37 0.1u c21 0.01u c22 0.01u c25 0.01u c30 33p c42 0.01u u4 25mhz osc 8 4 5 vcc gnd out c24 0.1u r1 10k r6 10k l5 f.b. smd 1206 r2 10k r25 10k + c11 4.7uf/16v smd 1206 sd[0..15] iois16# reset bhe# gnd iord# irq aen iowr# rdy 3.3v sa[0..9] txen txd3 rxck rxer txd1 txck rxd3 crs mdc rxd2 txd0 txd2 col rxd0 rxdv mdio rxd1 pclk tpip tpin tpon tpop zvreg link led speed led full led pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 strob# atfd# err init# slin# ack busy pe slct off 220h 320h isa bus off off iobase1 on 8051 340h on cpu0 380h iobase0 300h mode mc68k on cpu1 off iobase2 360h io base 80186 on 200h 3a0h *3 cpu type select on on on off off off off off off off off off off off off on on on on on on on on on default *5 iobase select *4 pin 116 i_op = 0 : lnk/act & full/col led display be used. pin 116 i_op = 1 : lnk & act led display be used. *2 pin 50 ppd_set = 0 : internal phy in normal mode.(default) pin 50 ppd_set = 1 : internal phy in power down mode.(match up cis) *1 pin 67 spp_set# = 0 : select printer interface. pin 67 spp_set# = 1 : select mii interface.(default) *1 *2 *3 *4 *5 *6 use crystal or oscillator. *3 *5 *5
asix electronics corporation 68 ax88796 l 3-in-1 local bus fast ethernet controller c49 0.1u r12 20 txd 3 3.3v ti p txen actled c16 0.1u rxdv c48 0.01u led4 3.3va2 3.3v rxck ring txen rxer txd 1 gnd actled c40 0.1u crs txd 0 gnd txd 1 md i o reset txd 1 crs txd 3 + c39 4.7uf/16v smd 1206 rxd3 r37 4.7k r11 4.7k rxd3 gnd col rxd0 q1 2sc2412k ring col d6 led md c txd 0 led5 3.3v c41 0.01u txd 2 rxd3 txc k md c reset r13 4.7k d5 led r16 330 set phy address to 00001. rxclk rxd0 spdled crs r19 4.7k rxd1 ring txc k txen colled 3.3v tip pwrled d4 led colled 3.3v r15 4.7k r29 2k rxd1 pwrled txc lk r18 4.7k ti p reset# c15 0.01u txd 2 u5 dp83851c tqf p 36 35 34 33 32 31 23 24 25 26 27 28 37 38 21 22 45 46 19 29 39 5 11 20 7 8 4 17 18 16 15 44 14 42 43 48 30 40 41 47 3 6 10 1 2 9 12 13 txd 3 txd 2 txd 1 txd 0/ txd tx_en tx_c lk rxd3/phyad0 rxd2/cmddis# rxd1/hi_power_en# rxd0/rxd/low_speed_en# rx_dv/gpsi_sel# rx_clk col/mdio_int_en# crs/pin_intrp_en# md i o md c x1 x2 io_vdd1 io_vdd2 core_vdd ana_vdd2 ana_vdd3 io_gnd1 ti p ring rbias led_col/phyad2 led_act/phy ad1 led_speed/phy ad3 led_power/phyad4 reset# reserved reserved reserved ana_vdd1 io_gnd2 core_gnd core_sub(0v) ana_gnd1 ana_gnd2 ana_gnd3 ana_gnd4 sub_gnd1 sub_gnd2 sub_gnd3 reserved reserved rxck spdled reset# rxdv rxd2 reset 3.3v r14 330 rxd2 rxd3 pclk gnd txd 3 796ns3a2.sch 2.0 dp83851c a4 34 thursday , april 19, 2001 asix electronics corporation tit le size document number rev date: sheet of 3.3v 3.3va1 r33 9.31k 1% c44 0.1u col 3.3v rxdv md i o rxd2 rxer pclk gnd c46 0.01u pclk r17 4.7k r10 330 rbias md c txd 2 r28 20 r30 2k l4 f.b. smd 1206 txc k 3.3v led6 l6 f.b. smd 1206 rxd1 rxd0 c38 0.01u rxck gnd txd 0 md i o c50 0.1u
asix electronics corporation 69 ax88796 l 3-in-1 local bus fast ethernet controller 796ns3a3.sch 2.0 rj45 & rj11 asix electronic co. a4 44 wednesday, may 22, 2002 title size document number rev date: sheet of gnd_ch gnd_ch tpon tpop gnd tpip tpin 3.3v tip ring c45 0.1u r31 49.9 r32 49.9 c62 0.1u r41 75 j3 rj45n 1 2 3 6 4 5 7 8 c51 1000pf/2kv smd 1206 r40 75 + c47 4.7uf/16v smd 1206 r34 0 t1 hr002 1 2 3 10 9 + - gnd tip ring r36 49.9 r38 0 r35 49.9 c57 0.1u r42 49.9 r43 49.9 j1 rj11-s 1 2 3 4 5 6 nc a1 tip ring a2 nc j2 rj11-s 1 2 3 4 5 6 nc a1 tip ring a2 nc c56 0.001u c58 0.001u t2 16st8515 16 14 15 1 3 2 10 12 11 7 5 6 td+ ct td- rd+ ct rd- tx+ ct tx- rx+ ct rx- r39 75 r44 75 c61 0.01u gnd tpon tpop zvreg tpip tpin tip ring 3.3v *7 1ct : 1ct *8 receive 1ct : 1ct transmit 1ct : 1ct
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asix electronics corporation 71 ax88796 l 3-in-1 local bus fast ethernet controller 4f, no.8, hsin ann rd., science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-5799500 fax: 886-3-5799558 email: support@asix.com.tw web: http://www.asix.com.tw revision date comment v. 1.7 24/01/02 1 remove tally counter at mac register list 2 modify rdy timing diagram in isa and 186 mode 3 remove bos bit in dcr register 4 include led current sink value v.1.8 18/06/02 schematic change for hi-vol tage cap, change from 0.01u to 1000pf v.1.9 2003/8/19 1. add tio (ds) timing information to all modes

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