1. general description the 74axp1g97 is a configurable multiple function gate wit h schmitt-trigger inputs. the device can be configured as any of the fo llowing logic functions mux, and, or, nand, nor, inverter and buffer. all inputs can be connected directly to v cc or gnd. this device ensures very low static and dynamic power consumption across the entire v cc range from 0.7 v to 2.75 v. this device is fully specif ied for partial power down applications using i off . the i off circuitry disables the output, preven ting the potentially damaging backflow current through the device when it is powered down. 2. features and benefits ? wide supply voltage range from 0.7 v to 2.75 v ? high noise immunity ? complies with jedec standard: ? jesd8-12a.01 (wide range: 0.8 v to 1.3 v) ? jesd8-12a.01 (normal range: 1.1 v to 1.3 v) ? jesd8-11a.01 (1.4 v to 1.6 v) ? jesd8-7a (1.65 v to 1.95 v) ? jesd8-5a.01 (2.3 v to 2.7 v) ? esd protection: ? hbm ansi/esda/jedec js-001 class 2 exceeds 2 kv ? cdm jesd22-c101e exceeds 1000 v ? low static power consumption; i cc = 0.6 ? a (85 ? c maximum) ? latch-up performance exceeds 100 ma per jesd 78 class ii ? inputs accept voltages up to 2.75 v ? low noise overshoot and undershoot < 10 % of v cc ? i off circuitry provides partial power-down mode operation ? multiple package options ? specified from ? 40 ? cto+85 ? c 74axp1g97 low-power configurable multiple function gate rev. 1 ? 25 june 2013 preliminary data sheet
74axp1g97 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. preliminary data sheet rev. 1 ? 25 june 2013 2 of 17 nxp semiconductors 74axp1g97 low-power configurable multiple function gate 3. ordering information 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram table 1. ordering information type number package temperature range name description version 74AXP1G97GM ? 40 ? c to +85 ? c xson6 plastic extremely thin sm all outline package; no leads; 6 terminals; body 1 ? 1.45 ? 0.5 mm sot886 74axp1g97gn ? 40 ? c to +85 ? c xson6 extremely thin small outline package; no leads; 6 terminals; body 0.9 ? 1.0 ? 0.35 mm sot1115 74axp1g97gs ? 40 ? c to +85 ? c xson6 extremely thin small outline package; no leads; 6 terminals; body 1.0 ? 1.0 ? 0.35 mm sot1202 table 2. marking type number marking code [1] 74AXP1G97GM rv 74axp1g97gn rv 74axp1g97gs rv fig 1. logic symbol 001aad998 a y 4 b c 3 1 6
74axp1g97 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. preliminary data sheet rev. 1 ? 25 june 2013 3 of 17 nxp semiconductors 74axp1g97 low-power configurable multiple function gate 6. pinning information 6.1 pinning 6.2 pin description 7. functional description [1] h = high voltage level; l = low voltage level. fig 2. pin configuration sot886 fig 3. pin configuration sot1115 and sot1202 $ ; 3 * * 1 ' d d d % $ 9 & |