1. general description the 74lv74-q100 is a dual positive edge trigge red, d-type flip-flop. it has individual data (nd) inputs, clock (n cp) inputs, set (nsd ) and (nrd ) inputs, and complementary nq and nq outputs. the set and reset are asynchronous active lo w inputs that operate independently of the clock input. information on the data input is transferred to the nq output on the low-to-high transition of the clock pulse. the nd inputs must be stable one set-up time prior to the low-to-hig h clock transition, for predictable operation. schmitt-trigger action in the clock input makes the circuit highly tole rant to slower clock rise and fall times. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? wide supply voltage range from 1.0 v to 5.5 v ? optimized for low voltage applications: 1.0 v to 3.6 v ? direct interface with ttl levels (2.7 v to 3.6 v) ? esd protection: ? mil-std-833, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) 3. ordering information 74lv74-q100 dual d-type flip-flop with set and reset; positive-edge trigger rev. 1 ? 23 september 2013 product data sheet table 1. ordering information type number package temperature range name description version 74LV74D-Q100 ? 40 ? c to +125 ? c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74lv74pw-q100 ? 40 ? c to +125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1
74lv74_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 23 september 2013 2 of 17 nxp semiconductors 74lv74-q100 dual d-type flip-flop with set and reset; positive-edge trigger 4. functional diagram fig 1. logic symbol fig 2. iec logic symbol q 1q sd rd 2q 1d 2d 1cp 2cp 5 9 2 12 3 11 1q 2q 6 8 q ff 1rd 2rd 113 1sd 2sd 410 d cp aaa-008836 aaa-008837 4 3 2 1 10 9 8 5 s c1 1d r s c2 2d r 6 11 12 13 fig 3. functional diagram q 1q sd rd sd rd 1d 1sd 1cp 5 2 4 3 1 10 1q 6 q ff1 q 2q 9 2q 8 q ff2 2rd 13 1rd 2sd d cp 2d 2cp 12 11 d cp aaa-008838
74lv74_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 23 september 2013 3 of 17 nxp semiconductors 74lv74-q100 dual d-type flip-flop with set and reset; positive-edge trigger fig 4. logic diagram (one flip-flop) aaa-008839 d rd c c sd cp c c c c q c c c q c
74lv74_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 23 september 2013 4 of 17 nxp semiconductors 74lv74-q100 dual d-type flip-flop with set and reset; positive-edge trigger 5. pinning information 5.1 pinning 5.2 pin description fig 5. pin configuration (so16 and tssop16) 6 ' / 9 4 5 ' 9 & |