View EVAL-ADAU1452MINIZ_8354951.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

si gmadsp digital audio processor data sheet adau1452/adau1451/adau1450 features qualified for automotive applications fully programmable audio dsp for enhanced sound processing features sigmastudio, a proprietary graphical programming tool for the development of custom signal flows up to 29 4.912 mhz , 32 - bit s igmadsp core at 1 .2 v up to 6144 simd instructions per sample at 48 khz up to 40 k words of parameter/ data ram up to 800 ms digital audio delay pool at 48 khz audio i/o and routing 4 serial input ports, 4 serial output ports 48- channel , 32 - bit digital i/o up to a sample rat e of 192 khz flexible configuration for tdm, i 2 s, left and right justified formats , and pcm up to 8 stereo asrcs from 1:8 up to 7.75:1 ratio and 139 db dnr stereo s/pdif input and output (not on the adau1450 ) four pdm microphone input channels multichannel , byte addressable tdm serial port s clock oscillator for generating master clock from crystal integer pll and flexible clock generators integrated die temperature sensor i 2 c and spi control interfaces ( both slave and master) stand alone operation self boot from serial eeprom 6 - channel, 10 - bit sar auxiliary control adc 14 m ulti purpose pins for digital controls and o utputs on - chip regulator for generating 1. 2 v from 3.3 v supply 72- lead , 10 mm 10 mm lfcsp package with 5.3 mm exposed pad temperature range: ? 40c to +105c applications automotive audio processing head units navigation systems rear seat entertainment systems dsp amplifiers (sound system amplifiers) commercial and professional audio processing functional block dia gram adau1452/ adau1451 s/pdif transmitter s/pdif receiver 8 2-channel asynchronous sample rate converters input clock domains (4) output clock domains (4) clock oscillator gpio/ aux adc pll i 2 c/spi slave xtalin/mclk xtalout spi/i 2 c* bclk_in3 to bclk_in0/ lrclk_in3 to lrclk_in0 (input clock pairs) selfboot spdifin spdifout clkout sdata_in3 to sdata_in0 (48-channel digital audio inputs) sdata_out3 to sdata_out0 (48-channel digital audio outputs) regulator adau1452/ adau1451 pllfilt mp13 to mp0 auxadc5 to auxadc0 bclk_out3 to bclk_out0 lrclk_out3 to lrclk_out0 (output clock pairs) temperature sensor thd_p vdrive thd_m i 2 c/spi master spi/i 2 c* digital mic input serial data input ports (4) serial data output ports (4) dejitter and clock generator *spi/i 2 c includes the following pin functions: ss_m, mosi_m, scl_m, sclk_m, sda_m, miso_m, miso, sda, sclk, scl, mosi, addr1, ss, and addr0 pins. input audio routing matrix output audio routing matrix 1 1486-001 294.912mhz 2 programmable audio processing core ram, rom, watchdog, memory parity check figure 1. rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change witho ut notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106 , u.s.a. tel: 781.329.4700 ? 2013 C 2014 analog devices, inc. all rights reserved. technical support www.a nalog.com
adau1452/adau1451/adau1450 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram adau1452/adau1451 ................. 1 revision history ............................................................................... 3 gene ral description ......................................................................... 4 differences between the adau1452 , adau1451 , and adau1450 ..................................................................................... 4 functional block diagram adau1450 ...................................... 5 specifications ..................................................................................... 6 electrical characteristics ............................................................. 8 timing specifications .................................................................. 9 absolute maximum ratings .......................................................... 17 thermal characteristics ............................................................ 17 maximum power diss ipation ................................................... 17 esd caution ................................................................................ 17 pin configuration and function descriptions ........................... 18 theory of operation ...................................................................... 22 system block diagram ............................................................... 22 overview ...................................................................................... 22 initialization ................................................................................ 24 master clock, pll, and clock generators .............................. 27 power supplies, voltage regulator, and hardware reset ...... 32 temperature sensor diode ........................................................ 33 slave control ports ..................................................................... 34 master control port s .................................................................. 40 self boot ....................................................................................... 41 audio signal routing ................................................................. 43 serial data input/outp ut ........................................................... 53 flexible tdm interface .............................................................. 64 asynchronous sample rate converters .................................. 69 s/pdif interface ......................................................................... 70 digital pdm microphone interface ......................................... 72 multipurpose pins ...................................................................... 73 auxiliary adc ............................................................................ 76 sigmadsp core .......................................................................... 76 software features ....................................................................... 80 pin drive strength, slew rate, and pull configuration ........ 81 global ram and control register map ...................................... 83 random access memory .......................................................... 83 control registers ........................................................................ 84 control register details ................................................................ 94 pll configur ation registers .................................................... 94 clock generator registers ........................................................ 98 power reduction registers ..................................................... 102 audio signal routing registers .............................................. 105 serial port configuration registers ....................................... 111 flexible tdm interface registers ........................................... 114 dsp core control registers .................................................... 118 debug and reliability registers .............................................. 123 dsp program execution registers ......................................... 131 multipurpose pin configuration registers .......................... 135 asrc status and control registers ....................................... 140 auxiliary adc registers ......................................................... 143 s/pdif interface registers ...................................................... 144 hardware inte rfacing registers .............................................. 157 soft reset register .................................................................... 175 applications information ............................................................ 176 pcb design considerations ................................................... 176 typical applications block diagram ..................................... 177 example pcb layout ............................................................... 178 pcb manufacturing guidelines ............................................. 179 outline dimensions ..................................................................... 180 ordering guide ........................................................................ 180 automotive products ............................................................... 180 rev. c | page 2 of 180
data sheet adau1452/adau1451/adau1450 revision history 7/14 rev. b to rev. c change s to scl_m/sclk_m/mp2 pin description, table 23 ............................................................................................. 19 change to pll lock register section .......................................... 96 changes to ordering guide .........................................................180 5/ 14 rev. a to rev. b reorganized layout ........................................................... universal added adau1452 and adau1451 ................................. universal changes to features section ............................................................ 1 moved revision history section ..................................................... 3 changes to general description section ....................................... 4 added d ifferences b etween the adau1452 , ada u1451 , and adau1450 section and table 1, renumbered sequentially ....... 4 added functional block diagram adau1450 section and figure 2, renumbered sequentially ................................................ 5 changes to table 2 ............................................................................ 6 changes to table 3 ............................................................................ 7 changes to table 6 ............................................................................ 9 changes to maximum power dissipation s ection, table 19, and table 20 ..................................................................................... 17 added table 21 and table 22 ......................................................... 17 changes to figure 12 and table 23 ............................................... 18 changes to overview section ........................................................ 22 change to clocking overview section and power up sequence section ............................................................................. 24 changes to setting the master clock and pll mode sec tion .. 27 changes to example pll settings section and table 25 ........... 28 changed pll loop filter section to pll filter section ............ 29 changes to pll filter section , figure 17 caption, and table 26 ............................................................................................. 29 changes to clock generators section .......................................... 30 changes to master clock outpu t section ................................... 31 changes to i 2 c slave port section ................................................. 35 changes to audio signal routing section ................................... 43 changes to serial audio inputs to dsp core section ................ 44 changes to asynchronous sample rate converter input routing section ............................................................................... 49 change to serial input ports section ............................................ 6 1 changes to asynchronous sample rate converters section .... 68 changes to s/pdif i nterface section and s/pdif receiver section .............................................................................................. 69 changes to auxiliary output mode section ............................... 70 change to d igital pdm m icrophone interface section ............ 71 changes to sigmadsp core sectio n ............................................. 76 changes to soft reset function section ...................................... 81 changes to r andom a ccess m emory section ............................. 83 added table 62 and table 63 ......................................................... 83 changes to table 84 ...................................................................... 109 changed pll loop filter section to pll filter section .......... 176 change to eos/esd protection section .................................... 177 change to pc b manufacturing guidelines section ................. 179 changes to ordering guide ......................................................... 1 80 1/14 rev. 0 to rev. a changed s/pdif transceiver and receiver maximum audio sample rate from 192 khz to 96 khz table 9 and table 10 ....... 9 10/ 1 3 rev ision 0 : initial version rev. c | page 3 of 180
adau1452/adau1451/adau1450 data sheet general desc ription the adau1452 / adau1451 / adau1450 are automot i ve qualified audio pro cessor s that far exceed the digital signal processing capabilities of earlier sigmadsp? devices. the restructured hardware architecture is optimized for efficient audio processing. the a udio processing algorithms are realized in sample - by - sample and block - by - block paradigms that can both be executed simul - taneously in a signal processing flow created using the graphical programming tool, sigmastudio? . the restructured digital signal processor ( dsp ) core architecture enables some types of audio processing al gorithms to be executed using significantly fewer instructions than were required on previous sigmadsp generations, leading to vastly improved code efficiency. the 1.2 v, 32 - bit dsp core can run at frequencies of up to 294.912 mhz and execute up to 6144 in structions per sample at the standard sample rate of 48 khz. however, in addition to industry standard rates , a wide range of sample rates are available. the integer pll and flexible clock generator hardware can generate up to 15 audio sample rates simulta neously. these clock generators, along with the on board asynchronous sample rate converters (asrcs) and a flex ible hardware audi o routing matrix, make the adau1452 / adau1451 / adau1450 ideal audio hub s that greatly simplif y the design of complex multirate audio systems. the adau1452 / adau1451 / adau1450 interface with a wide range of adcs, dacs, digital audio dev ices, amplifiers, and control circuitr y, due to their highly configurable serial ports, s/pdif interfaces (on the adau1452 and adau1451 ) , and multipurpose input/output pins. they can also directly interface with pdm ou tput mems microphones , thanks to integrated decimation filters specifically designed for that purpose. independent slave and master i 2 c/spi control ports allow the adau1452 / adau1451 / adau1450 not only to be programmed and configured by an external master device, but also to act as master s that can program and configure extern al slave devices directly. this flexibility , combined with self boot functionality, enables the design of standalone systems that do not require any external input to operate. the power efficient dsp core execute s full programs while consuming only a few h undred milliwatts (mw) of power and can run at a maximum program load while consuming less than a watt, even in worst case temperatures exceeding 100c. this relatively low power consumption and small footprint make the adau1452 / adau1451 / adau1450 ideal replacement s for large , general - purpose dsps that consume more power at t he same processing load. differences between the adau1452 , adau1451 , and adau1450 the three variants of this device are differentiated by memory, dsp core frequency, availability of s/pdif interfaces, and asrc configuration. a detailed summary of the differences is listed in table 1 . because the adau1450 does not contain an s/pdif receiver or transmitter, the spdifin and spdifout pins are nonfunctional. also, the settings of any registers related to the s/pdif input or output in the adau1450 do not have any effect on the operation of the device. l i kewise, b ecause the adau1450 does not contain asrcs, t he settings of any registers related to the asrcs in the adau1450 do not have any effect on the operation of the device. table 1 . product selection table device number data memory (kwords) program memory (kwords) dsp core frequency s/pdif input and output asrc configuration adau1452 40 8 294.912 mhz available 16 channels (8 rates 2 channels per rate) adau1451 16 8 294.912 mhz available 16 channels (8 rates 2 channels per rate) adau1450 8 8 147.456 mhz no t available no asrcs included rev. c | page 4 of 180
data sheet adau1452/adau1451/adau1450 functional block dia gram adau1450 input clock domains (4) output clock domains (4) clock oscillator gpio/ aux adc pll i 2 c/spi slave xtalin/mclk xtalout spi/i 2 c* bclk_in3 to bclk_in0/ lrclk_in3 to lrclk_in0 (input clock pairs) selfboot clkout sdata_in3 to sdata_in0 (48-channel digital audio inputs) sdata_out3 to sdata_out0 (48-channel digital audio outputs) regulator adau1450 pllfilt mp13 to mp0 auxadc5 to auxadc0 bclk_out3 to bclk_out0 lrclk_out3 to lrclk_out0 (output clock pairs) temperature sensor thd_p vdrive thd_m i 2 c/spi master spi/i 2 c* digital mic input serial data input ports (4) serial data output ports (4) dejitter and clock generator *spi/i 2 c includes the following pin functions: ss_m, mosi_m, scl_m, sclk_m, sda_m, miso_m, miso, sda, sclk, scl, mosi, addr1, ss, and addr0 pins. input audio routing matrix output audio routing matrix 1 1486-101 147.456mhz programmable audio processing core ram, rom, watchdog, memory parity check figure 2. rev. c | page 5 of 180
adau1452/adau1451/adau1450 data sheet specifications avdd = 3.3 v 10% , dvdd = 1.2 v 5% , pvdd = 3.3 v 10% , iovdd = 1.8 v ? 10% to 3.3 v + 10% , t a = 25c, mast er clock input = 12.288 mhz, core clock (f core ) = 294.912 mhz, i/o pins set to low drive setting, unless otherwise noted. table 2 . parameter min typ max unit test conditions/comments power supply voltage analog voltage (avdd) 2.97 3.3 3.63 v supply for analog circuitry, including auxiliary adc digital voltage (dvdd) 1.14 1.2 1.26 v supply for digital circuitry, including the dsp core, asrcs, and signal routing pll voltage (pvdd) 2. 97 3.3 3.63 v supply for phase - locked loop (pll) circuitry i/o supply voltage (iovdd) 1.71 3.3 3.63 v supply for input/output circuitry, including pads and level shifters supply current analog current (avdd) 1.5 1.73 2 ma idle state 0 5 40 a pow er applied, chip not programmed reset state 1.9 6.5 40 a power applied, reset held low pll current (pvdd) 9.5 10 13 ma 12.288 mhz mclk with default pll settings idle state 0 7.3 40 a power applied, pll not configured reset state 3. 9 8.5 40 a power applied, reset held low i/o current (iovdd) d e pen dent on the number of active serial ports, clock pins, and characteristics of external loads operation state 53 ma iovdd = 3.3 v ; all serial ports are clock maste rs 22 ma iovdd = 1.8 v ; all serial ports are clock masters power - down state 0.3 2.5 ma iovdd = 1.8 v ? 10% to 3.3 v + 10% digital current (dvdd) operation state , adau1452 maximum program 350 415 ma typical program 100 ma test program includes 16 - channel i/o, 10 - band eq per channel, all asrcs active minimal program 85 ma test prog ram includes 2 - channel i/o, 10 - band eq per channel operation state, adau1451 maximum program 350 415 ma typical program 100 ma test program includes 16 - channel i/o, 10 - band eq per channel, all asrcs active minimal program 85 ma test program includes 2 - channel i/o, 10 - band eq per channel operation state, adau1450 maximum program 125 250 ma f core = 147.456 mhz typical program 65 ma test program includes 16 - channel i/o, 10 - band e q per channel, f core = 147.456 mhz minimal program 55 ma test program includes 2 - channel i/o, 10 - band eq per channel, f core = 147.456 mhz idle state 20 95 ma power applied, dsp not enabled reset state 20 95 ma power applied, reset held low asynchronous sample rate converters dynamic range 139 db a - weighted, 20 hz to 20 khz i/o sample rate 6 192 khz i/o sample rate ratio 1:8 7.75:1 thd + n ? 120 db crystal oscillator transconductance 8.3 10.6 13.4 ms regulator dvdd voltage 1.14 1.2 v regulator maintains typical output voltage up to a maximum 800 ma load; iovdd = 1.8 v ? 10% to 3.3 v + 10% rev. c | page 6 of 180
data sheet adau1452/adau1451/adau1450 av dd = 3.3 v 10%, dvdd = 1.2 v 5 %, pvdd = 3.3 v 10%, iovdd = 1.8 v ? 10% to 3.3 v + 10% , t a = ? 40c t o + 1 05 c, ma ster clock input = 12.288 mhz, core clock ( f core ) = 294.912 mhz, i/o pins set to low drive setting, unless otherwise noted. table 3 . parameter min t yp max unit test conditions/comments power supply voltage analog voltage (avdd) 2.97 3.3 3.63 v supply for analog circuitry, including auxiliary adc digital voltage (dvdd) 1.14 1.2 1.26 v supply for digital circuitry, including the dsp core, asrcs, and signal routing pll voltage (pvdd) 2.97 3.3 3.63 v supply for pll circuitry iovdd voltage (iovdd) 1.71 3.3 3.63 v supply for input/output circuitry, including pads and level shifters supply current analog current (avdd) 1.44 1.72 2 ma idle state 0 6.3 40 a reset state 0.26 7.1 40 a pll current (pvdd) 6 10.9 15 ma 12.288 mhz master clock; default pll settings idle state 0 7.8 40 a power applied, pll not configured reset state 1.2 9.3 40 a power applied, reset held low i/o current (iovdd) depend ent on the number of active serial ports, clock pins, and characteristics of external loads operation state 47 ma iovdd = 3.3 v; all serial ports are clock masters 15 ma iovdd = 1.8 v; all serial ports are c lock masters power - down state 1.3 2.2 ma iovdd = 1.8 v ? 10% to 3.3 v + 10% digital current (dvdd) operation state , adau1452 maximum program 500 690 ma typical program 200 ma test program includes 16 - channel i /o, 10 - band eq per channel, all asrcs active minimal program 160 ma test program includes 2 - channel i/o, 10 - band eq per channe l operation state, adau1451 maximum program 500 690 ma typical program 200 ma test progr am includes 16 - channel i/o, 10 - band eq per channel, all asrcs active minimal program 160 ma test program includes 2 - channel i/o, 10 - band eq per channel operation state, adau1450 maximum program 270 635 ma f core = 147.456 mhz typical program 110 ma test program includes 16 - channel i/o, 10 - band eq per channel, f core = 147.456 mhz minimal pr ogram 90 ma test program includes 2 - channel i/o, 10 - band eq per channel, f core = 147.456 mhz idle state 315 635 ma reset state 315 635 ma asynchronous sample rate converters dynamic range 139 db a - weighted, 20 hz to 20 khz i/o sample ra te 6 192 khz i/o sample rate ratio 1:8 7.75:1 thd + n ?120 db crystal oscillator transconductance 8.1 10.6 14.6 ms regulator dvdd voltage 1.14 1.2 v regulator maintains typical output voltage up to a maximum 800 ma load; iovdd = 1.8 v ? 10% to 3.3 v + 10% rev. c | page 7 of 180
adau1452/adau1451/adau1450 data sheet electrical character istics digital i nput /o utput table parameter min typ max unit test conditions/comments digital input input voltage iovdd = 3.3 v high level (v ih ) 1 1.71 3.3 v low level (v il ) 1 0 1.71 v iovdd = 1.8 v high level (v ih ) 1 0.92 1.8 v low level (v il ) 1 0 0.89 v input leakage high level (i ih ) ?2 +2 a digital input pins with pull - up resistor 2 12 a digital input pins with pull - down resistor ?2 +2 a digital input pins with no pull resistor 0 8 a mclk 80 120 a spdifin low level (i il ) at 0 v ?12 ?2 a digital input pins with pul l - up resistor ?2 +2 a digital input pins with pull - down resistor ?2 +2 a digital input pins with no pull resistor ?8 0 a mclk ?120 ?77 a spdifin input capacitance (c i ) 2 pf guaranteed by design digital output output voltage iovdd = 3.3 v high level (v oh ) 3.09 3.3 v i oh = 1 ma low level (v ol ) 0 0.26 v i ol = 1 ma iovdd = 1.8 v high level (v oh ) 1.45 1.8 low level (v ol ) 0 0.33 digital output pins , output drive th e digital output p ins are driving low i mpedance pcb traces to a high impedance digital input buffer iovdd = 1.8 v drive strength setting lowest 1 ma t he digital output pins are not designed for static current draw ; do not use these pins to drive leds directly low 2 ma the di gital output pins are not designed for static current draw; do not use these pins to drive leds directly high 3 ma the digital output pins are not designed for static current draw; do not use these pins to drive leds directly highest 5 ma the digital output pins are not designed for static current draw; do not use these pins to drive leds directly iovdd = 3.3 v drive strength setting lowest 2 ma the digital output pins are not designed for static current draw; do not use these pins to drive leds directly low 5 ma the digital output pins are not designed for static current draw; do not use these pins to drive leds directly high 10 ma the digital output pins are not designed for static current draw; do not use these pins to drive l eds directly highest 15 ma the digital output pins are not designed for static current draw; do not use these pins to drive leds directly 1 digital input pins except spdifin , which is not a standard digital input . rev. c | page 8 of 180
data sheet adau1452/adau1451/adau1450 auxiliary adc t a = ?40c to +105c, dvdd = 1.2 v 5% , avdd = 3.3 v 10%, iovdd = 1.8 v ? 10% to 3.3 v + 10%, unless otherwise noted . table 5 . parameter min typ max unit resolution 10 bits full - scale analog input avdd v nonlinearity i ntegrated nonlinearity (inl) ?2 +2 lsb differential nonlinearity (dnl) ?2 +2 lsb gain error ?2 +2 lsb input impedance 200 k? sample rate f core /6144 hz timing specification s master clock input t a = ?40c to +105 c, dvdd = 1.2 v 5%, iovdd = 1. 8 v ? 10% to 3.3 v + 10%, unless otherwise noted. table 6 . parameter min max unit description master clock input (mclk) f mclk 2.375 36 mhz mclk frequency t mclk 27.8 421 ns mclk period t mclkd 25 75 % mclk duty cycle t mclkh 0.25 t mclk 0.75 t mclk ns mclk width high t mclkl 0.25 t mclk 0.75 t mclk ns mclk width low clkout jitter 12 106 ps cycle - to - cycle rms average core clock f core adau1452 and adau1451 152 294.912 mhz system (dsp core) clock frequency; pll feedback divider ranges from 64 to 108 adau1450 76 147.456 mhz system (dsp core) clock frequency; pll feedback divider ranges from 64 to 108 t core adau1452 and adau1451 3.39 ns system (dsp core) clock period adau1450 6.78 ns system (dsp core) clock period mclk t mclkh t mclkl t mclk 1 1486-003 figure 3. master clock input timing specifications rese t t a = ?40c to +105c, dvdd = 1.2 v 5%, iovdd = 1.8 v ? 10% to 3.3 v + 10% . table 7 . parameter min max unit description reset t wrst 10 ns reset pulse width low reset t wrst 1 1486-004 figure 4. re set timing specification rev. c | page 9 of 180
adau1452/adau1451/adau1450 data sheet serial ports t a = ?40c to +105c, dvdd = 1.2 v 5%, iovdd = 1.8 v ? 10% to 3.3 v + 10% , unless otherwise noted. bclk in table 8 refers to bclk_out3 to bclk_out0 and bclk_in3 to bclk_in0 . lrclk refers to lrclk_out3 to lrclk_out0 and lrclk_in3 to lrckl_in0. table 8 . parameter min max unit description serial port f lrclk 192 khz lrclk frequency t lrclk 5.21 s lrclk period f bclk 24.576 mhz bclk frequency, s ample rate ranging from 6 khz to 192 khz t bclk 40.7 ns bclk period t bil 10 ns bclk low pulse width, slave mode; bclk frequency = 24.576 mhz; bclk period = 40.6 ns t bih 14.5 ns bclk high pulse width, slave mode; bclk frequency = 24.576 mhz; bclk peri od = 40.6 ns t lis 20 ns lrclk setup to bclk_inx input rising edge, slave mode; lrclk frequency = 192 khz t lih 5 ns lrclk hold from bclk_inx input rising edge, slave mode; lrclk frequency = 192 khz t sis 5 ns sdata_inx setup to bclk_inx input rising e dge t sih 5 ns sdata_inx hold from bclk_inx input rising edge t ts 10 ns bclk_outx output falling edge to lrclk_outx output timing skew, slave t sods 35 ns sdata_outx delay in slave mode from bclk_outx output falling edge; serial outputs function in sla ve mode at all valid sample rates, provided that the external circuit design provides sufficient electrical signal integrity t sodm 10 ns sdata_outx delay in master mode from bclk_outx output falling edge t tm 5 ns bclk falling edge to lrclk timing skew, master lsb t bih t bclk t tm t lih msb msb ? 1 msb msb t lis t sis t sih t sih t sis t lrclk t sis t s i h t sis t sih t bil bclk_inx lrclk_inx sdata_inx left justified mode (serial_byte_x_0[4:3], (data_fmt) = 0b01) sdata_inx i 2 s mode (serial_byte_x_0[4:3], (data_fmt) = 0b00) sdata_inx right justified modes (serial_byte_x_0[4:3], (data_fmt) = 0b10 or serial_byte_x_0[4:3], (data_fmt) = 0b11) 1 1486-005 figure 5 . serial input port timing specifications bclk_outx lsb t bih t lrclk t bclk m s ? 1 m s b msb t s o d s t s o d m t ts t bil t s o d s t s o d m t sods t sodm lrclk_outx sdata_outx left justified mode (serial_byte_x_0 [4:3] (data_fmt) = 0b01) sdata_outx i 2 s mode (serial_byte_x_0 [4:3] (data_fmt) = 0b00) sdata_outx right justified modes (serial_byte_x_0 [4:3] (data_fmt) = 0b10 or serial_byte_x_0 [4:3] (data_fmt) = 0b11) msb b 1 1486-006 figure 6 . serial output port timing specifications rev. c | page 10 of 180
data sheet adau1452/adau1451/adau1450 multipurpose pins t a = ?40c to +105c, dvdd = 1.2 v 5% , iovdd = 1.8 v ? 10% to 3.3 v + 10% . table 9 . parameter min max unit description multipurpose pins (mpx) f mp 1 24.576 m hz mpx maximum switching rate when pin is configured as a general - pu rpose input or general - purpose output t mpil 1 10 t core 6144 t core s ec mpx pin input latency until high/low value is read by core; the duration in the max column is equal to the period of one audio samp le when the dsp is processing 6144 instructions per sample 1 guaranteed by design. s/pdif transmitter t a = ?40c to +105c, dvdd = 1.2 v 5% , iovdd = 1.8 v ? 10% to 3.3 v + 10% . table 10. parameter min max unit description s/pdif transmitter audio sample rate 18 96 khz audio sample rate of data output from s/pdif transmitter s/pdif receiver t a = ?40c to +105c, dvdd = 1.2 v 5%, iovdd = 1.8 v ? 10% to 3.3 v + 10% . table 11. parameter min max unit description s/pdif receiver audio sample rate 18 96 khz audio sample rate of data input to s/pdif receiver rev. c | page 11 of 180
adau1452/adau1451/adau1450 data sheet i 2 c interface slave t a = ?40c to +105c, dvdd = 1.2 v 5%, iovdd = 1.8 v ? 10% to 3.3 v + 10% , default drive strength (f scl ) = 400 khz. table 12. parameter min max unit description i 2 c slave port f scl 400 khz sc l clock frequency t sclh 0.6 s scl pulse width high t scll 1.3 s scl pulse width low t scs 0.6 s start and repeated start condition setup time t sch 0.6 s start condition hold time t ds 100 ns data setup time t dh 0.9 s data hold time t sclr 300 ns scl rise time t sclf 300 ns scl fall time t sdr 300 ns sda rise time t sdf 300 ns sda fall time t bft 1.3 s bus - free time between stop and start t susto 0.6 s stop condition setup time t sclh t sclr t scll sda scl t dh t sdr t sch t ds stop start t susto t sch t sdf t scs t sclf t bft 1 1486-007 figure 7. i 2 c slave port timin g specifications rev. c | page 12 of 180
data sheet adau1452/adau1451/adau1450 rev. c | page 13 of 180 i 2 c interfacemaster t a = ?40c to +105c, dvdd = 1.2 v 5%, iovdd = 1.8 v ? 10% to 3.3 v + 10%. table 13. parameter min max unit description i 2 c master port f scl 400 khz scl clock frequency t sclh 0.6 s scl pulse width high t scll 1.3 s scl pulse width low t scs 0.6 s start and repeated start condition setup time t sch 0.6 s start condition hold time t ds 100 ns data setup time t dh 0.9 s data hold time t sclr 300 ns scl rise time t sclf 300 ns scl fall time t sdr 300 ns sda rise time t sdf 300 ns sda fall time t bft 1.3 s bus-free time between stop and start t susto 0.6 s stop condition setup time sda_m scl_m t sclh t sclr t scll t dh t sdr t sch t ds stop start t susto t sch t sdf t scs t sclf t bft 11486-008 figure 8. i 2 c master port timing specifications
adau1452/adau1451/adau1450 data sheet spi interface sl ave t a = ?40c to +105c, dvdd = 1.2 v 5%, iovdd = 1.8 v ? 10% to 3.3 v + 10% . table 14. parameter min max unit description spi slave port f s clk write 22 mhz sclk write frequency f s clk read 22 mhz sclk read frequency t scl kpwl 6 ns sclk pulse width low, sclk = 22 mhz t sclkpwh 21 ns sclk pulse width high, sclk = 22 mhz t sss 1 ns ss setup to sclk rising edge t ssh 2 ns ss hold from sc lk rising edge t sspwh 10 ns ss pulse width high t sspwl 10 ns ss pulse width low; m i nimum low pulse width for ss when entering spi mode by toggling the ss pin three times t mosis 1 ns mosi setup to sclk rising edge t mosih 2 ns mosi hold from sclk rising edge t misod 3 9 ns miso valid output delay from sclk falling edge ss t sss t mosis t mosih t misod t sclkpwh t sclkpwl t ssh sclk miso mosi t sspwh 1 1486-009 figure 9 . spi slave port timing specifications rev. c | page 14 of 180
data sheet adau1452/adau1451/adau1450 spi interface master t a = ?40c to +105c, dvdd = 1.2 v 5% , iovdd = 1.8 v ? 10% to 3.3 v + 10% . table 15. parameter min max unit description spi master port tim ing requirements t sspidm 15 ns miso_m data input valid to sclk_m edge (data input setup time) t hspidm 5 ns sclk_m last sampling edge to data input not valid (data input hold time) switching characteristics t spiclkm 41.7 ns spi master clock c ycle period f sclk_m 24 mhz spi master clock frequency t spichm 17 ns sclk_m high period (f sclk_m = 24 mhz) t spiclm 17 ns sclk_m low period (f sclk_m = 24 mhz) t ddspidm 16.9 ns sclk_m edge to data out valid (data out delay time) (f sclk_m = 24 mhz) t h dspidm 21 ns sclk_m edge to data out not valid (data out hold time) (f sclk_m = 24 mhz) t sdscim 36 ns ss_m (spi device select) low to first sclk_m edge (f sclk_m = 24 mhz) t hdsm 95 ns last sclk_m edge to ss_m high (f sclk_m = 24 mhz) t spichm t sdscim t spiclm t spiclkm t hdsm t spiclm t spichm msb valid lsb valid msb valid lsb msb lsb msb t ddspidm t hspidm t sspidm lsb valid cphase = 1 cphase = 0 t hdspidm t hspidm t sspidm t hspidm t sspidm t ddspidm t hdspidm ss_m (output) sclk_m (cp = 0) (output) sclk_m (cp = 1) (output) mosi_m (output) miso_m (input) mosi_m (output) miso_m (input) 1 1486-010 figure 10 . spi master port timing specifications rev. c | page 15 of 180
adau1452/adau1451/adau1450 data sheet pdm inputs t a = ?40c to +105c, dvdd = 1.2 v 5% , iovdd = 1.8 v ? 10% to 3.3 v + 10% . pdm data is latched on both edges of the clock (see figure 11). table 16. parameter t min t max unit description timing requirements t setup 10 ns data setup time t hold 5 ns data hold time r l t hold t setup p d m _ c l k p d m _ da t r l 1 1486-0 1 1 figure 11 . pdm timing diagram rev. c | page 16 of 180
data sheet adau1452/adau1451/adau1450 absolute maximum rat ings table 17. parameter rating dvdd to ground 0 v to 1.4 v avdd to ground 0 v to 4.0 v iovdd to ground 0 v to 4.0 v pvdd to ground 0 v to 4.0 v digital inputs dgnd ? 0.3 v to iovdd + 0.3 v maximum ambient temperature range ?40 c to +105c maximum junction temperature 125 c storage temperature range ?65c to +150c soldering (10 sec) 300c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operati ng conditions for extended periods may affect product reliability . thermal characterist ics ja represents the junction - to - ambient thermal resistance; jc represents the junction - to - case thermal resistance. all charac - teristics are for a 4 - layer jedec board. the exposed pad has 49 vias that are arranged in a 7 7 grid. table 18 . thermal resistance package type ja jc unit 72- lead lfcsp 23.38 3.3 c/w maximum power dissip ation the characteristics listed in table 19 show the absolute worst case power dissipation for the adau1452 , adau1451 , and adau1450 . these tests were co nducted at an ambient tempera - ture of 105c, with a completely full dsp program that executes an endless loop of the most power i ntensive core calculations and with all power supplies at their maximum values. thus , the conditions described in table 19 are intended as a stress test only and are not representative of realistic device operation in a real - world application. in a system where the operating conditions and limits outlined in the specifications section of this document are not exceeded, and where the device is mounted to a printed circuit board ( pcb ) that follows the design recommendations in the pcb design considerations section of this document, the value s that are listed represent the total power consumption of the device . in actual applications, the power consumptio n of the device is far lower. table 20, table 21 , and table 22 show more realistic estimate s for power consumption in a typical use case. table 19 . worst case maximum power dissipation parameter value unit test conditions/ com ments avdd, dvdd, pvdd during adau1452 operation 960 mw ambient temperature = 105c, all supplies at maximum, full dsp program using most power intensive calculations; measure - ment does not include iovdd avdd, dvdd, pvdd during adau1451 operation 960 mw ambient temperature = 105c, all supplies at maximum, full dsp program using most power intensive calculations; measure - ment does not include iovdd avdd, dvdd, pvdd during adau1450 operation 960 mw ambient temperature = 105c, all supplies at maximum, full dsp program using most power intensive calcu lations; measure - ment does not include iovdd reset all supplies 570 mw ambient temperature = 105c, all supplies at maximum, reset mode enabled; measurement does not include iovdd table 20. adau1452 typical power dissipation estimates ambient temperature ( c ) full program (mw) typical (mw) 25 420 250 85 700 420 105 885 530 table 21. adau1451 typical power dissipation estimates ambient temperat ure ( c ) full program (mw) typical (mw) 25 420 250 85 700 420 105 885 530 table 22. adau1450 typical power dissipation estimates ambient temperature ( c ) full program (mw) typical (mw) 25 170 100 85 385 230 105 480 290 esd caution rev. c | page 17 of 180
adau1452/adau1451/adau1450 data sheet pin configuration an d function descripti ons dgnd dgnd dgnd dgnd dvdd sdata_out3 bclk_out3 lrclk_out3/mp9 sdata_out2 bclk_out2 lrclk_out2/mp8 mp7 mp6 sdata_out1 bclk_out1 lrclk_out1/mp5 sdata_out0 bclk_out0 lrclk_out0/mp4 iovdd dgnd 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 adau1452/ adau1451/ adau1450 top view dvdd sdata_in3 lrclk_in3/mp13 bclk_in3 sdata_in2 lrclk_in2/mp12 bclk_in2 thd_p thd_m sdata_in1 lrclk_in1/mp11 bclk_in1 sdata_in0 lrclk_in0/mp10 bclk_in0 iovdd dgnd iovdd vdrive spdifin spdifout agnd avdd auxadc0 auxadc1 auxadc2 auxadc3 auxadc4 auxadc5 pgnd pvdd pllfilt dgnd iovdd dvdd xtalin/mclk xtalout clkout reset dgnd ss_m/mp0 mosi_m/mp1 scl_m/sclk_m/mp2 sda_m/miso_m/mp3 miso/sda sclk/scl mosi/addr1 ss/addr0 selfboot dvdd dgnd 1 1486-002 notes 1. the exposed pad must be grounded by soldering it to a copper square of equivalent size on the pcb. identical copper squares must exist on all layers of the board, connected by vias, and they must be connected to a dedicated copper ground layer within the pcb. figure 12 . pin configuration table 23 . pin function descriptions pin no. mnemonic internal pull resistor description 1 dgnd none digital and i/o ground r eference. tie a ll dgnd, agnd, and pgnd pins directly together in a common gr ound plane. 2 iovdd none input/output supply, 1.8 v ? 10% to 3.3 v + 10% . bypass this pin w ith decoupling capacitors to p in 1 (dgnd). 3 vdrive none pnp bipolar junction transistor - base drive bias p in for the digital supply regulator . connect vdrive to the base of an external pnp pass transistor (std2805 is recommended). if an external supply is provided directly to dvdd, connect the vdrive pin to ground . 4 spdifin none input to the integrated sony/philips digital interface format receiver. disconnect this pin when not in use. this pin is internally biased to iovdd/2. this pin is nonfunctional on the adau1450 and should be left disconnected. 5 spdifout c onfigurable output from the integrated sony/philips digital interface format transmitter. disconnect this pin when not in use. this pin is internally biased to iovdd/2. this pin is nonfunctional on the adau1450 and should be left disconnected. 6 agnd none analog ground reference. tie all dgnd, agnd, and pgnd pins directly together in a common ground pla ne. 7 avdd none a nalog (auxiliary adc) supply. must be 3.3 v 10% . bypass this pin with decoupling capacitors to pin 6 (agnd). 8 auxadc0 none auxiliary adc input channel 0. this pin read s an analog input signal and use s its value in the dsp program. dis connect this pin when not in use. 9 auxadc1 none auxiliary adc input channel 1. this pin read s an analog input signal and use s its value in the dsp program. disconnect this pin when not in use. rev. c | page 18 of 180
data sheet adau1452/adau1451/adau1450 pin no. mnemonic internal pull resistor description 10 auxadc2 none auxiliary adc input channel 2. this pin read s an analog input signal and uses its value in the dsp program. disconnect this pin when not in use. 11 auxadc3 none auxiliary adc input channel 3. this pin reads an analog input signal and uses its value in the dsp program. disconnect this pin when not i n use. 12 auxadc4 none auxiliary adc input channel 4. this pin reads an analog input signal and uses its value in the dsp program. disconnect this pin when not in use. 13 auxadc5 none auxiliary adc input channel 5. this pin reads an analog input signal a nd uses its value in the dsp program. disconnect this pin when not in use. 14 pgnd none pll ground reference. tie a ll dgnd, agnd, and pgnd pins directly together in a common ground plane. 15 pvdd none pll s upply. must be 3.3 v 10%. bypass this pin wit h decoupling capacitor s to p in 14 (pgnd). 16 pllfilt none pll f ilter. the voltage on the pllfilt pin, which is internally generated, is typically between 1.65 v and 2.10 v. 17 dgnd none digital and i/o ground r eference. tie all dgnd, agnd, and pgnd pins d irectly together in a common ground plane. 18 iovdd none input/output supply, 1.8 v ? 10% to 3.3 v + 10%. bypass this pin to pin 17 (dgnd) w ith decoupling capacitors . 19 dgnd none digital and i/o ground r eference. tie all dgnd, agnd, and pgnd pins direct ly together in a common ground plane. 20 dvdd none digital s upply. must be 1.2 v 5% . this pin c an be supplied externally or by using the internal regulator and external pass transistor. b ypass this pin to pin 19 (dgnd) with decoupling capacitors . 21 xt alin/mclk none cr ystal oscillator input (xtalin) / master clock i nput to th e pll (mclk) . this pin can be supplied di rectly or generated by driving a crystal with the i nternal crystal oscillator via p in 22 (xtalout). if a crystal is used, refer to the circuit shown in figure 15. 22 xtalout none c r ystal oscillator output for driving an e xterna l c rystal. if a crystal is used, refer to the circuit shown in figure 15. disconnect t his pin when not in use. 23 clkout configurable master clock output. this pin drive s a master clock signal to other ics in the system. clkout can be configured to output a clock signal with a frequency of 1 , 2 , 4 , or 8 the frequency of the divided clo ck signal being input to the pll. disconnect this pin when not in use. 24 reset pull - down active low r e set i nput. a r eset is triggered on a high - to - low edge and exited on a low -to - high edge. a reset event sets all rams and registers to their default values. 25 dgnd none digital and i/o ground r eference . tie all dgnd, agnd, and pgnd pins directly together in a common ground plane. 26 ss_m/mp0 pull - up; nominally 250 k? ; can be disabled by a write to control register spi master/ slave select port (ss_m)/multi purpose, general - purpose input/output (mp0) . when in spi master mode, this pin acts as the slave select signal to sla ve devices on the spi bus. the pin m ust go low at the beginning of a master spi transaction and high at the end of a transaction. this pin has an internal pull -up resistor that is nominally 250 k ? . when the selfboot pin is held high and the reset pin has a transition from low to high , pin 26 sets the commu nications protocol for self boot operation. if this pin is left floating, the spi communications protocol is used for self boot operation. if this pin has a 10 k ? pull - down resistor to gnd, the i 2 c communi - cations protocol is used fo r self boot operation. when self boot operation is not used and this pin is not needed as a general - purpose input or output, leave it disconnected. 27 mosi_m/mp1 pull - up ; can be disabled by a write to control register spi master data output port (mosi_m)/ multi purpose, general - purpose input/output (mp1) . when in spi master mode, this pin sends data from the spi master port to slave devices on the spi bus. disconnect this pin when not in use. 28 scl_m/ sclk_m/ mp2 pull - up; can be disabled by a write to contr ol register i 2 c master serial clock port (scl_m)/spi master mode serial clock (sclk_m)/multipurpose, general - purpose input/output (mp2). when in i 2 c master mode, this pin functions as an open collector output and drives a serial clock to slave devices on t he i 2 c bus; use a 2.0 k ? pull - up resistor to iovdd on the line connected to this pin. when in spi master mode, this pin drives the clock signal to slave devices on the spi bus. disconnect this pin when not in use. 29 sda_m/ miso_m/ mp3 pull - up; can be disabled by a wr ite to control register i 2 c master port serial data (sda_m)/spi master mode data input (miso_m)/multipurpose, general - purpose input/output (mp3). when in i 2 c master mode, this pin functions as a bi - directional open collector data line between the i 2 c maste r port and slave devices on the i 2 c bus ; use a 2.0 k ? pull - up resistor to iovdd on the line connected to this pin. when in spi master mode, this pin receives data from slave devices on the spi bus. disconnect this pin when not in use. rev. c | page 19 of 180
adau1452/adau1451/adau1450 data sheet pin no. mnemonic internal pull resistor description 30 miso/sda pull - up; can be disabled by a write to control regist er spi slave data output port (miso)/i 2 c slave serial data port (sda). in spi slave mode, this pin outputs data to the master device on the spi bus. in i 2 c slave mode, this pin functions as a bi - directional open collector data line between the i 2 c slave po rt and the master device on the i 2 c bus; use a 2.0 k ? pull - up resistor to iovdd on the line connected to this pin. when this pin is not in use, connect it to iovdd with a 10.0 k ? pull - up resistor. 31 sclk/scl pull - up; can be disabled by a write to control register spi slave port serial clock (sclk)/ i 2 c slave port serial clock (scl). in spi slave mode, this pin receives the serial clock signal from the master device on the spi bus. in i 2 c slave mode, this pin receives the serial clock signal from the master device on the i 2 c bus; use a 2.0 k ? pull - up resistor to iovdd on the line connected to this pin . when this pin is not in use, connect it to iovdd with a 10.0 k ? pull - up resistor. 32 mosi/addr1 pull - up; can be disabled by a write to control register spi slave port data input (mosi)/i 2 c slave port ad dress msb (addr1). in spi slave mode, this pin receives a data signal from the master device on the spi bus. in i 2 c slave mode, this pin acts as an input and sets the chip address of the i 2 c slave port, in conjunction with pin 33 (ss/addr0). 33 ss/addr0 p ull - up, nominally 25 0 k ? ; can be disabled by a write to control register spi slave port slave select (ss)/ i 2 c slave port address lsb (addr0) . in spi slave mode, this pin receives the slave select signal from the master device on the spi bus. in i 2 c slave mode, this pin acts a s an input and sets the chip address of the i 2 c s lave port in conjunction with p in 32 (mosi/addr1). 34 selfboot pull -up self boot select. this pin a llo ws the device to perform a self boot, in which it loads its ram and register settings from an external e eprom. connecting pin 34 to logic high ( iovdd ) initiate s a self boot operation the next time there is a rising edge on p in 24 ( reset ). when this pin is connected to ground, no self boot operation is initiated. this pin can be connected t o iovdd or to grou nd either directly or pulled up or down with a 1.0 k ? or larger resistor. 35 dvdd none digital s upply. must be 1.2 v 5% . this pin c an be supplied externally or by using the internal regulator and external pass transistor. b ypass this p in to pin 36 (dgnd) with decoupling capacitors . 36 dgnd none digital and i/o ground reference. tie a ll dgnd, agnd, and p gnd pins directly together in a common ground plane. 37 dgnd none digital and i/o ground r eference. tie all dgnd, agnd, and p gnd pins directly together in a common ground plane. 38 iovdd none input/output supply, 1.8 v ? 10% to 3.3 v + 10%. b ypass this pin with decoupling capacitors to p in 37 (dgnd). 39 lrclk_out0/ mp4 configurable frame cloc k, serial output port 0 (lrclk_out0)/ multi purpose, general - purpose input/output (mp4) . this pin is bidirectional, with the dir ecti on depending on whether serial output port 0 is a master or slave. disconnect this pin when not in use. 40 bclk_out0 configurable bit clock, serial output port 0. this pin is bidirectional, with the direction depending on whether the serial output port 0 is a master or slave. disconnect this pin when not in use. 41 sdata_out0 configurable serial data output port 0 (channel 0 to channel 15). capable of 2 - channel, 4 - channel, 8 - channel, and 16 - channel modes. disconnect this pin when not in use. 42 lrclk_out 1/ mp5 configurable frame clock, serial output port 1 (lrclk_out1)/multi purpose, general - purpose input/output (mp5) . this pin is bidirectional, with the dir ection depending on whether serial output port 1 is a master or slave. disconnect this pin when not in use. 43 bclk_out1 configurable bit clock, serial output port 1. this pin is bidirectional, with the direction depending on whether output serial port 1 is a master or slave. disconnect this pin when not in use. 44 sdata_out1 configurable serial data o utput port 1 (channel 16 to channel 31). capable of 2 - channel, 4 - channel, 8 - channel, and 16 - channel modes. disconnect this pin when not in use. 45 mp6 configurable multi purpose, general - purpose input/output 6. disconnect this pin when not in use. 46 mp7 configurable multi purpose, general - purpose input/output 7. disconnect this pin when not in use. 47 lrclk_out2/ mp8 configurable frame clock, serial output port 2 (lrclk_out2)/multi purpose, general - purpose input/output (mp8) . this pin is bidirectional, wit h the dir ection depending on whether serial output port 2 is a master or slave. disconnect this pin when not in use. 48 bclk_out2 configurable bit clock, serial output port 2. this pin is bidirectional, with the dir ection depending on whether serial outpu t port 2 is a master or slave. disconnect this pin when not in use. 49 sdata_out2 configurable serial data output port 2 (channel 32 to channel 39). capable of 2 -ch annel, 4 - channel, 8 - channel, or f lexibl e tdm mode . disconnect this pin when not in use. 50 lrclk_out3/ mp9 configurable frame clock, serial output port 3 (lrclk_out3)/multi purpose, general - purpose input/output (mp9) . this pin is bidirectional, with the direction depending on whether serial output port 3 is a master or slave. disconnect this pin when not in use. rev. c | page 20 of 180
data sheet adau1452/adau1451/adau1450 pin no. mnemonic internal pull resistor description 51 bclk_out3 configurable bit clock, serial output port 3. this pin is bidirectional, with the direction depending on whether serial output port 3 is a master or slave. disconnect this pin when not in use. 52 sdata_out3 configurable ser ial data output port 3 (channel 40 to channel 47). cap able of 2 - channel, 4 - channel, 8 - channel, and flexible tdm modes. disconnect this pin when not in use . 53 dvdd none digital s upply. must be 1.2 v 5%. this pin c an be supplied externally or by using th e internal regulator and external pass transistor. bypass pin 53 w ith decoupling capacitors to p in 54 (dgnd). 54 dgnd none digital and i/o g round r eference. tie a ll dgnd, agnd, and p gnd pins directly together in a common ground plane. 55 dgnd none digita l and i/o ground r eference. tie all dgnd, agnd, and p gnd pins directly together in a common ground plane. 56 iovdd none input/output supply, 1.8 v ? 10% to 3.3 v + 10%. bypass this pin with decoupling capacitor s to p in 55 (dgnd). 57 bclk_in0 configurable bit clock, serial input port 0. this pin is bidirectional, with the direction depending on whether serial input port 0 is a master or slave. disconnect this pin when not in use. 58 lrclk_in0/ mp10 configurable frame clock, serial input port 0 (lrclk_in0) /multi purpose, general - purpose input/output (mp10) . this pin is bidirectional, with the direction depending on whether serial input port 0 is a master or slave. disconnect this pin when not in use. 59 sdata_in0 configurable serial data input port 0 (chann el 0 to channel 15). capable of 2 - channel, 4 - channel, 8 - channel, or 16 - channel mode . disconnect this pin when not in use. 60 bclk_in1 configurable bit clock, serial input port 1. this pin is bidirectional, with the direction depending on whether the seria l input port 1 is a master or slave. disconnect this pin when not in use. 61 lrclk_in1/ mp11 configurable f rame clock, serial input port 1 (lrclk_in1)/multi purpose, general - purpose input/output (mp11) . this pin is bidirectional, with the direction dependi ng on whether the serial input port 1 is a master or slave. disconnect this pin when not in use. 62 sdata_in1 configurable serial data input port 1 (c hannels 16 to channel 31). capable of 2 - channel, 4 - channel, 8 - channel, or 16 - channel mode . disconnect thi s pin when not in use. 63 thd_m none thermal diode negative ( ? ) i nput. connect t his pin to the d ? pin of an external te mperature sensor ic . disconnect this pin when not in use. 64 thd_p none thermal d i ode positive (+) i nput. connect this pin to the d+ pin of an external temperature sensor ic . disconnect this pin wh en not in use. 65 bclk_in2 configurable bit clock, serial input port 2. this pin is bidirectional, with the direction depending on whether the serial input port 2 is a master or slave. disconnect this pin when not in use. 66 lrclk_in2/ mp12 configurable frame clock, input serial port 2 (lrclk_in2)/multi purpose, general - purpose input/output (mp12) . this pin is bidirectional, with the direction depending on whether serial input port 2 is a master or slave. disconnect this pin when not in use. 67 sdata_in2 configurable serial data input port 2 (channel 32 to channel 39). capable of 2 - channel, 4 - channel, 8 - channel, or flexible tdm mode . disconnect this pin when not in use. 68 bclk_in3 configurable bit clock, input serial port 3. this pin is bidirectional, wi th the direction depending on whether input serial port 3 is a master or slave. disconnect this pin when not in use. 69 lrclk_in3/ mp13 configurable frame clock, serial input port 3 (lrclk_in3)/multi purpose, general - purpose input/output (mp13) . this pin i s bidirectional, with the direction depending on whether serial input port 3 is a master or slave. disconnect this pin when not in use. 70 sdata_in3 configurable serial data input port 3 (channel 40 to channel 47). capable of 2 - channel, 4 - channel, 8 - chann el, or flexible tdm mode . disconnect this pin when not in use. 71 dvdd none digital s upply. must be 1.2 v 5%. this pin c an be supplied externally or by using the internal regulator and external pass transistor. b ypass with decoupling capacitors to p in 7 2 (dgnd). 72 dgnd none digital and i/o ground r eference. tie all dgnd, agnd, and p gnd pins directly together in a common ground plane. ep exposed pad none the exposed pad must be grounded by soldering it to a copper square of equivalent size on the pcb. identical copper squares must exist on all layers of the board, connected by vias, and they must be connected to a dedicated copper ground layer within the pcb. for more detailed information, see figure 84 and figure 85. rev. c | page 21 of 180
adau1452/adau1451/adau1450 data sheet theory of o peration system block diagram pll loop filter crystal resonator control circuitry (push buttons, rotary encoders, potentiometers) self boot memory system host controller 1 the s/pdif receiver, the s/pdif transmitter, and the asynchronous sample r a te converters are not present on the adau1450. 2 the adau1450 has a 147.456mhz programmable audio processing core . (microcontroller, microprocessor) s/pdif optical receiver audio adcs mems microphones audio sources power supply temperature sensor controller digital audio sources s/pdif optical transmitter audio dacs audio sinks digital audio sinks lpf s/pdif transmitter 1 s/pdif receiver 1 8 2-channel asynchronous sample rate converters 1 input clock domains (4) output clock domains (4) clock oscillator gpio/ aux adc pll i 2 c/spi slave regulator adau1452/ adau1451/ adau1450 temperature sensor i 2 c/spi master digital mic input serial data input ports (4) serial data output ports (4) dejitter and clock generator input audio routing matrix output audio routing matrix 1 1486-013 294.912mhz 2 programmable audio processing core ram, rom, watchdog, memory parity check figure 13 . system block diagram with example connections to external components overview the adau1452 / adau1451 / adau1450 are enhanced audio process or s with 48 channels of input and output . they include options for the hardware routing of audio signals between the various inputs, outputs, sigma dsp core , and integrated sample rate converters . the sigmadsp core features full 32 - bit processing ( that is, 64 - bit processing in double p recision mode) with an 80 - bit arithmetic logic unit (alu). by using a quad ruple multiply accumulator (mac ) data path, the adau1452 / adau1451 can execute more than 1.2 billion mac operations per second, w hich allows for processing power that far exceeds the predecessors in the sigmadsp family of products. the powerful dsp core can process over 3000 double precision biquad filters or 24, 000 fir filter taps per sample at the standard 48 khz audio sampling ra te. the adau1450 features half the processing power of the adau1452 / adau1451 . other features, including synchronous parameter loadin g for ensuring filter stability and 100% code efficiency with the sigmastudio tools, reduce complexity in audio system development . the sigmastudio library of audio proce ssing algorithms allows system designers to compensate for real - world limitations of speakers, amplifiers, and listening envi ronments, through speaker equalization, multiband compression, limiting, and third party branded algorithms. the input audio routin g matrix and output audio routing matrix allow the user to multiplex inputs from multiple sources that are running at various sample rates to or from the sigmadsp core, and then to pass them on to the desired hardware outputs. this drastically reduces the complexity of signal routing and clocking issues in the audio system. the audio subsystem includes up to eight stereo asynchronous sample rate converters ( asrcs), depending on the device model; sony/philips digital interconnect f ormat (s/pdif) input and ou tput (available on the adau1452 / adau1451 ) ; and serial (i 2 s) and time division multiplexing (tdm) i/os. any of these inputs can be routed to the sigmadsp core or to any of the asrcs (except on the adau1450 , which does not have asrcs) . similarly, the output signals can be taken from the sigmadsp core, any of the asrc outputs, the serial inputs, the pdm microphones, or the s/pdif receiver. this routing scheme, which can be modified at any time using control registers, allows for maximum system flexibility without requiring hardware design changes. rev. c | page 22 of 180
data sheet adau1452/adau1451/adau1450 two se rial input ports and two serial output ports can operate as pairs in a special flexible tdm mode, allowing the user to independently assign byte specific locations to audio streams at varying bit depths. this mode ensures compatibility with codecs that use similar flexible tdm streams. the dsp core is optimized for audio processing, and it can process audio at sample rates of up to 192 khz. the program and para - meter/data rams can be loaded with a custom audio processing signal flow built with the sigmastud io graphical programming software from analog devices, inc. the values that are stored in the parameter ra m can control individual signal pro cessing blocks, such as iir and fir equalization filters, dynamics pro - cessors, audio delays, and mixer levels. a s oftware safeload feature allows for transparent parameter updates and prevents clicks on the output signals. reliability features , such as memory parity checking and a program counter watchdog , help ensure that the system can detect and recover from any er rors related to memory corruption. on the adau1452 / adau1451 , s/pdif signals can be routed through an asrc for processing in the dsp or can be sent directly to output on the multipurpose pins (mpx) for r ecovery of the embedded audio signal. other components of the embedded signal, including status and user bits, are not lost and can be output on the mp x pins as well. the user can als o independently program the non audio data that is embedded in the output signal of the s/pdif transmitter . the 14 mpx pins are available for providing a simple user interface without the need for an external microcontroller. these multipurpose pins are available to input external control signals and output flags or controls to other devices in the system. as inputs, the mp x pins can be connected to push buttons, switches, rotary encoders, or other external control circuitry to control the internal sign al processing program. when con figured as outputs, these pins can be used to d rive leds (with a buffer), output flags to a microcontroller, control other ics, or connect to other external circuitry in an application. in addition to the multipurpose pins, six dedicated input pins (auxadc5 to auxadc0) are connected to an auxiliary adc for use with analog controls such as potentiometers or system voltages. the sigmastudio software program s and control s the device through the control port. in addition to designing and tuning a signal flow, the software can configure all of the dsp regist ers in real time and download a new program and p arameter s into the external self boot eeprom. the easy to use sigmastudio graphical interface allows anyone with audio processing knowledge to easily design a dsp signal flow and port it to a target applicat ion without the need for writing line level code. at the same time, the software provides enough flexibility and programmability to allow an experienced dsp programmer to have in - depth control of the design. in sigmastudio, the user can add signal proces sing cells from the library by dragging and dropping cells, connect them together in a flow, compile the design, and load the program and parameter files into memory through the control port. the complicated tasks of linking, compiling, and downloading the project are all handled automatically by the software. signal processing algorithms that are available in the provided libraries include the following: ? single and double precision biquad filter ? mono and multichannel dynamics processors with peak or rms de tection ? mixer and splitter ? tone and noise generator ? fixed and variable gain ? loudness ? delay ? stereo enhancement ? dynamic bass boost ? noise and tone source ? level detector ? mp x pin control and conditioning ? fft and frequency domain processing algorithms analog dev ices continuously develops new processing algorithm s and provides proprietary and thir d party algorithms for applications such as matrix decoding, bass enhancement, and surround virtualizers. several power - saving mechanisms are available , including program mable pad strength for digital i/o pins and the ability to power down unused subsystems. f abricated on a single monolithic integrated circuit for operation over the ?40c to +105c temperature range , the device is housed in a 72- lead lfcsp package with an exposed pad to assist in heat dissipation. the device can be controlled in one of two operational modes, as follows: ? t he settings of the chip can be loaded and dynamically updated through the spi/i 2 c port. ? t he dsp can self boot from an external eeprom in a system with no microcontroller. the adau14 52wbcpz , adau1452wbcpz - rl , adau1451wbcpz , adau1451wbcpz - rl , adau1450wbcpz , and adau1450wbcpz - rl models are qualified for use in automotive applications. rev. c | page 23 of 180
adau1452/adau1451/adau1450 data sheet initialization power - up sequ ence the first step in the initialization seque nce is to power up the device. first, apply v oltage to the power pins. all power pins can be supplied simultaneously. if the power pins are not supplied simultaneously, then supply iovdd first because the inte rnal esd protection diodes are referenced to the iovdd voltage. avdd, dvdd, and pvdd can be supplied at the same time as iovdd or after, but they m ust not be supplied prior to iovdd. the order in which avdd, dvdd, and pvdd are supplied does not matter. whe n the internal regulator is not used and dvdd is directly supplied, no special sequence is required when providing the proper voltages to avdd, dvdd, and pvdd. when the internal regulator is used, dvdd is generated by the regulator , in combination with an external pass transistor , after av dd, iovdd, and pvdd are supplied. see the power supplies section for more information. each power supply domain has its own power - on reset (por ) circuits ( also known as power ok circuits) to ensure that the level shifters attached to each power domain can be initialized properly. avdd and pvdd must reach their nominal level before the auxiliary adc and pll can be used, respectively. however, the avdd and pvdd supplies have no role in the rest of the power - up sequence. after avdd power reaches its nominal threshold , the regulator become s active and begin s to charge up the dvdd supply. the dvdd also has a por circui t to ensure that the level shifters initialize during power - up. the p or signals are combined into three global level shifter resets that properly initialize the signal crossings between each separate power domain and dvdd. the digital circuits remain in reset until the iovdd to dvdd leve l shifter reset is released. at that point, the digital circuits exit reset. when a crystal is in use, the crystal oscillator circuit must provide a stable master clock to the xtalin/mclk pin by the time the pvdd supply reaches its nominal level. the xtalin/mclk pin is restricted from passin g into the pll circuitry until the dvdd por sig nal becomes active and the pvdd to dvdd level shifter is initialized. when all four por circuits si gnal that the power - on conditions are met, a reset synchronizer circuit release s the internal digital circuitr y from reset , provided the following conditions are met: ? a valid mclk signal is provided to the digital circuitry and the pll . ? the reset pin is high . when the internal digital circuitry becomes active, the dsp core run s eight lines of in itialization code stored in rom , requiring eight cycles of the mclk signal. for a 12.288 mhz mclk input, this process takes 650 ns . after the rom program completes its execution, the pll is ready to be configured using register writes to register 0xf000 (p ll_ctrl0), register 0xf001 (pll_ctrl1), register 0xf002 (pll_clk_src), and register 0xf003 (pll_enable) . when the pll is configured and enabled, the pll start s to lock to the incoming master clock signal. the absolute maximum pll lock time is 32 1024 = 3 2 , 768 clock cycles on the clock signal (after the input pre sc aler), which is fed to the input of the pll. in a standard 48 khz use case, the pll input clock frequency after the pre scaler is 3.072 mhz; therefore, the maximum pll lock time is 10.666 m s. typi cally, the pll lock s much faster than 10.666 ms. in most systems, the pll lock s within about 3.5 ms. the pll_lock register (a ddress 0xf004) can be pol led via the control port until bit 0 ( pll_lock ) goes high, signifying that the pll lock has completed succ essfully. while the pll is attempting to lock to the input clock, the i 2 c slave and spi slave control ports are inactive; therefore, no other registers are accessible over the control port. while the pll is attempting to lock, all a ttempts to write to the control port fail. rev. c | page 24 of 180
data sheet adau1452/adau1451/adau1450 figure 14 shows an example power - up sequence with all relevant signals labeled. if possible, apply the required voltage to all four power supply domains (iovdd, avdd, pvdd, and dvdd) simultane ously. if the power supplies are separate, iovdd , which is the reference for the esd protection diodes that are situated inside the input and output pins , must be applied first to avoid stressing these diodes . pvdd, avdd, and dvdd can then be supplied in a ny order (see the system initialization sequence section for more information) . note that the gray areas in this figure represent clock signals. ste p 1 2 3 4 5 6 7 8 9 10 1 1 12 iovdd pins pvdd pin avdd pin dvdd pins iovdd to dvdd level shifter enable (internal) pvdd to dvdd level shifter enable (internal) avdd to dvdd level shifter enable (internal) reset pin reset (internal) master power-on reset (internal) xtalin/mclk pin clock input to the pll pll output clock description starting conditions. all signals are low. if power supplies are se p ar a te, app l y vo lt age t o iovdd firs t . app l y master clock signa l t o x t alin/mclk, unless master clock is au t om a tical l y gener a ted using a c r ys t a l oscill a t or circui t . supp l y pvdd a t the same time, or after, iovdd. do not bring u p pvdd before iovdd. supp l y a vdd a t the same time, or after, iovdd. do not bring u p a vdd before iovdd. if dvdd is external l y supplied, supp l y it a t the same time as iovdd and pvdd, or after pvdd. do not bring it u p before iovdd or pvdd. after al l supplies reach their nomina l levels, the leve l shifters acti va te, allowing signals t o p ass internal l y between power domains. when the iovdd t o dvdd and pvdd t o dvdd leve l shifters become active, the master clock input signa l is p assed t o the pll. if the reset pin is not alread y high, pul l it high a t an y time. ( a t the beginning of a power sequence, the s ta te of the reset pin is don?t care.) the interna l reset signa l goes high when the following conditions are true: al l power supplies are v alid, and the reset pin is logic high. when the interna l reset goes high, the ds p core runs initializ a tion code, which requires eight cycles of the x t alin/mclk signal. a t 12.2888mhz, the process requires 650ns. the contro l port is now accessible. program the pl l using register writes. the pl l then locks, requiring a maximum of 10.666ms. after the pl l locks, other registers can be programmed, and the ds p can s t art running. 1 1486-018 figure 14 . power sequencing and por ti ming diagram for a system with separate power supplies rev. c | page 25 of 180
adau1452/adau1451/adau1450 data sheet system initialization sequence before the ic can process the audio in the dsp, the following initial ization sequence must be completed. 1. if possible, a pply the required voltage to all four power suppl y domains ( iovdd, avdd, pvdd, and dvdd) simultaneously . if simultaneous application is not possible, s upply iovdd first to prevent damage or reduced operating lifetime. if using the on - board regulator, avdd and pvdd can be supplied in any order, and dvdd i s then generated automatically. if not using the on - board regulator, avdd, pvdd, and dvdd can be supplied in any order following iovdd. 2. start providing a master clock signal to the xtalin/mclk pin, or, if using the crystal oscillator, let the crystal oscil lator start generating a master clock signal. the master clock signal must be valid when the dvdd supply stabilizes . 3. if the self boot pin is pulled high, a self boot sequence in i tiate s on the master contr ol port. wait until the self boot operation is comple te. 4. if spi slave control mode is desired, toggle the ss/addr0 pin three times. e nsure that e ach toggle last s at least the duration of one cycle of the master clock being input to the xtalin/ mclk pin . when the ss/addr0 line rises for the third time, the sla ve control port is then in spi mode. 5. execute the register and memory write sequence that is required to configure the device in the proper operating mode. table 24 contains an example series of register writes us ed to configure the system at startup . the contents of the data column may vary depending on the system configuration. the configuration that is listed in table 24 represents the default initialization sequence f or project files generated in sigmastudio. recommended program/parameter loading procedure when writing large amounts of data to the program or parameter ram in direct write mode (such as when downloading the initial contents of the rams from an external m emory), use the hibernate register (address 0xf400) to disable the processor core, thus preventing unpleasant noises from appearing at the audio output. when small amounts of data are transmitted during real - time operation of the dsp (such as when updating individual parameters), the software safeload mechanism can be used (see the software safeload section). table 24. example system initialization register write sequence 1 address data re gister / memory description n/a n/a n/a toggle ss/addr0 three times to enable spi slave mode, if necessary . 0xf890 0x00, 0x00 soft_reset enter soft reset . 0xf890 0x00, 0x01 soft_reset exit soft reset . 0xf000 0x00, 0x60 pll_ctrl0 set feedback divider to 9 6 (this is the default power - on setting) . 0xf001 0x00, 0x02 pll_ctrl1 set pll input clock divider to 4 . 0xf002 0x00, 0x01 pll_clk_src set clock source to pll clock . 0xf005 0x00, 0x05 mclk_out enable mclk output (12.288 mhz) . 0xf003 0x00, 0x01 pll_enabl e enable pll . n/a n/a n/a wait for pll lock (see the power - up sequence section) ; t he maximum pll lock time is 10.66 6 ms . 0xf050 0x4f, 0xff power_enable0 enable power for all major systems e xcept clock g enerator 3 (clock g enerator 3 is rarely used in most systems) . 0xf051 0x00, 0x00 power_enable1 disable power for subsystems like pdm mic rophone s, s/pdif, and the adc if they are not being used in the system . 0xc000 data generated by sigmastudio program ram d ata download the entire program ram contents using a block write (data provided by sigmastudio compiler) . 0x0000 data generated by sigmastudio dm0 ram d ata download data m emory dm0 using a block write (data provided by sigmastudio compiler) . 0x600 0 data gene rated by sigmastudio dm1 ram d ata download data m emory dm1 using a block write (data provided by sigmastudio compiler) ; t he start address of dm1 may vary , depending on the sigmastudio compilation . 0xf404 0x00, 0x00 start_address set program start address as defined by the sigmastudio compiler . 0xf401 0x00, 0x02 start_pulse set dsp core start pulse to internally generated pulse . n/a n/a n/a configure any other registers that require nondefault values . 0xf402 0x00, 0x00 start_core stop the core . 0xf402 0 x00, 0x01 start_core start the core . n/a n/a n/a wait 50 s for initialization program to execute . 1 n/a means not applicable. rev. c | page 26 of 180
data sheet adau1452/adau1451/adau1450 master clock, pll , and clock generato rs clocking overview to externally supply the master clock, c onnect the clock source directly to the xtalin/mclk pi n . alternatively, use the internal clock oscillator to drive an external crystal. using the oscillator the adau1452 / adau1451 / adau1450 can use an on - board oscillator to generate its master clock. however, to complete the oscillator circuit, an external crystal must be attached. the on - board oscillator is designed to work with a crystal that is tuned to resonate at a frequency of the nominal system clock divided by 24. for a normal system, where the nominal system clock is 294.912 mhz, this frequency is 12.288 mhz. the fundamental frequency of the crysta l can be up to 30 mhz . practically speak ing, in most systems the fundam ental frequency of the crystal should be in a range from 3.072 mhz to 24.576 mhz. for t he external crystal in the circuit , use an at - cut parallel resonance device operating at its funda mental frequency. do not use c eram ic resonators, because of their poor jitter performance. quartz crystals are ideal for audio applications. figure 15 shows the crystal oscillator circuit that is recommended for proper operation. 100 ? 22pf 22pf 12.288mhz xtalout xtalin/mclk 1 1486-019 figure 15 . crystal resonator circuit the 100 damping resistor on xtalout provides the oscillator with a voltage swing of approximately 3.1 v at the xtalin/ mclk pin. the optimal cry stal shunt capacitance is 7 p f. its optimal load capacitance, specified by the manufacturer, should be about 20 pf, although the circuit supports values of up to 25 pf. ensure that t he equivalent series resistance is as small as possible. calculate t he necessary values of the two loa d capacitors in the circuit from the crystal load capacitance , using the following equation: stray l c c2 c1 c2 c1 c u w here : c1 and c2 are the load capacitors . c st r ay is the stray capacitance in the circuit . c st r ay is usually assumed to be approximately 2 pf to 5 p f, but it varies depending on the pcb design. short trace lengths in the oscillator circuit decrease stray capaci - tance, thereby increasing the loop gain of the circuit and helping to avoid crystal start - up problems. therefore, place the crystal a s near to the xtalo ut pin as possible , and on the same side of the pcb. on the e va l - adau1452 m ini z evaluation board, the c1 and c2 load capacitors are 22 pf . do not use xtalo ut to directly drive the crystal signal to another ic. this signal is an analog sine wave with low drive capability and, therefore , is not appro priate to drive a n external dig ital input. a separate pin, clkout, is provided for this pur - pose. the clkout pin is set up using the mclk_out register (a ddress 0xf005). for a more detailed explanation of clkout, refer to the master clock output section or the register map description of the mclk_out register (see the clkout control register section) . if a clock signal is provided from elsewhere in the system directly to the xtalin/mclk pin, the crysta l resonator circuit is not necessary, and the xtalout pin can remain disconnected. setting the master clock and pll mode an integer pll is available to generate the core system clock from the master clock input signal. the pll generates the nominal 294.912 mhz core system clock to run the dsp core. as a result of the flexible clock generator circuitry , t his nominal core clock frequency can be used for a variety of audio sample rates . an integer prescaler takes the clock signal from the mclk pin and divides its frequency by 1, 2, 4, or 8 to meet the appropriate frequency range require ments for the pll itself. the nominal input frequency to the pll is 3.072 mhz. for systems with an 11.2896 mhz input master clock, the input to the pll is 2.8224 mhz. 1, 2, 4, or 8 xtalin/ mclk 294.912mhz system clock nominally 3.072mhz (default) 96 1 1486-020 figure 16 . pll functional block diagram the master clock input signal ranges in frequency from 2.375 mhz to 36 mhz. for systems that are intended to operate at a 48 khz, 96 khz, or 192 khz audio sample rate, the typical master clock input f requencies are 3.072 mhz, 6.144 mhz, 12.288 mhz, and 24.576 mhz. note that the flexibility of the pll allows for a large range of other clock frequencies, as well. the pll in the adau1452 and adau1451 h as a nominal (and maximum) output frequency of 294.912 mhz. the pll of the adau1450 outputs a freque ncy at half the rate of the pll of the adau1452 and adau1451 , with a nominal (and maximum) output frequency of 147.456 mhz. the pll is configured by setting register 0xf000 (pll_ctrl0), register 0xf001 (pll_ctrl1), and register 0xf002 (pll_clk_ src) . after these registers are modified, set register 0xf003, bit 0 (pll_enable) , forcing the pll to reset itself and attempt to relock to the incoming clock signal. typically, the pll locks within 3.5 ms. when t he pll locks to an input clock and creates a stable output clock, a lock flag is set in register 0xf004, bit 0 (pll_lock). rev. c | page 27 of 180
adau1452/adau1451/adau1450 data sheet example pll settings depending on the input clock frequency, there are several possible configurations for the pll. setting the pll t o generate the highest possible system clock, without exceeding the maximum, allows for the execution of more dsp program instructions for each audio frame. alternatively, setting the pll to generate a lower frequency system clock allows fewer instructions to be executed and also lowers overall power consumption of the device. table 25 shows several example mclk frequencies and the corresponding pll settings that allow for the highest number of program instructions to be executed f or each audio frame. the settings provide the highest possible system clock without exceeding the 294.912 mhz upper limit (or 147.456 mhz in the case of the adau1450 ). table 25 . optimal predivider and feedback divider settings for varying input mclk frequencies input mclk frequency (mhz) pre divider setting pll input clock (mhz) feedback divider setting adau1452 and adau1451 system clock (mhz) adau1450 system clock (mhz) 2.8224 1 2.8224 104 293.5296 146.7648 3 1 3 98 294 147 3.072 1 3.072 96 294.912 147.456 3.5 1 3.5 84 294 147 4 1 4 73 292 146 4.5 1 4.5 65 292.5 146.25 5 2 2.5 117 292.5 146.25 5.5 2 2.75 107 294.25 1 47.125 5.6448 2 2.8224 104 293.5296 146.7648 6 2 3 98 294 147 6.144 2 3.072 96 294.912 147.456 6.5 2 3.25 90 292.5 146.25 7 2 3.5 84 294 147 7.5 2 3.75 78 292.5 146.25 8 2 4 73 292 146 8.5 2 4.25 69 293.25 146.625 9 2 4.5 65 292.5 146.25 9.5 4 2. 375 124 294.5 147.25 10 4 2.5 117 292.5 146.25 10.5 4 2.625 112 294 147 11 4 2.75 107 294.25 147.125 11.2896 4 2.8224 104 293.5296 146.7648 11.5 4 2.875 102 293.25 146.625 12 4 3 98 294 147 12.288 4 3.072 96 294.912 147.456 12.5 4 3.125 94 293.75 1 46.875 13 4 3.25 90 292.5 146.25 13.5 4 3.375 87 293.625 146.8125 14 4 3.5 84 294 147 14.5 4 3.625 81 293.625 146.8125 15 4 3.75 78 292.5 146.25 15.5 4 3.875 76 294.5 147.25 16 4 4 73 292 146 16.5 4 4.125 71 292.875 146.4375 17 4 4.25 69 293.25 14 6.625 17.5 4 4.375 67 293.125 146.5625 18 4 4.5 65 292.5 146.25 18.5 8 2.3125 127 293.6875 146.84375 19 8 2.375 124 294.5 147.25 19.5 8 2.4375 120 292.5 146.25 20 8 2.5 117 292.5 146.25 20.5 8 2.5625 115 294.6875 147.34375 21 8 2.625 112 294 147 rev. c | page 28 of 180
data sheet adau1452/adau1451/adau1450 input mclk frequency (mhz) pre divider setting pll input clock (mhz) feedback divider setting adau1452 and adau1451 system clock (mhz) adau1450 system clock (mhz) 2 1.5 8 2.6875 109 292.9375 146.46875 22 8 2.75 107 294.25 147.125 22.5 8 2.8125 104 292.5 146.25 22.5792 8 2.8224 104 293.5296 146.7648 23 8 2.875 102 293.25 146.625 23.5 8 2.9375 100 293.75 146.875 24 8 3 98 294 147 24.5 8 3.0625 96 294 147 24.576 8 3.072 96 294.912 147.456 25 8 3.125 94 293.75 146.875 relationship between system clock and instruc tions p er sample the dsp core execute s only a limited number of instructions within the span of each audio sample. the number of instructions that can be executed is a function of the system c lock and the dsp core sample rate. the core sample rate is set by register 0 xf401 (start_pulse) , bits [4:0] ( start_pulse ) . the number of instructions that can be executed per sample is equal to the system clock frequ ency divided by the dsp core sample rate. however, the program ram size is 8192 words; therefore, in cases where the maximum instructions per sample exceeds 8192, subroutines and loops must be utilized to make use of all available instructions (see table 26) . pll filter an external pll filter is required to help the pll maintain stability and to limit the amount of ripple appearing on the phase detector output of the pll. for a nominal 3.072 mhz pll input and a 29 4.912 mhz system clock output (or 147.456 mhz in the case of the adau1450 ), the recommended filter c onfiguration is shown in figure 17 . this filter works for the full frequency range of the pll. 5.6nf 150pf 4.3k pllfilt pvdd 1 1486-021 figure 17 . pll filter because the center frequency and bandwidth of the loop filter is det ermined by the values of the included components, use high accuracy (low tolerance) components. components that are valued within 10% of the recommended component values and with a 15% or lower tolerance are suitable for use in the loop filter circuit. the voltage on the pllfilt pin, which is internally generated, is typically between 1.65 v and 2.10 v. table 26 . maximum instructions per sample , depending on system clock and dsp core sample rate system clock (mhz) dsp core sample rate (khz) maximum instructions p er sample 294.912 8 36, 864 1 294.912 12 24, 576 1 294.912 16 18, 432 1 294.912 24 12, 288 1 294.912 32 9216 1 294.912 48 6144 294.912 64 4608 294.912 96 3072 294.912 128 2304 294.912 192 1536 293.5296 11.025 26 , 624 1 293 .5296 22.05 13, 312 1 293.5296 44.1 6656 293.5296 88.2 3328 293.5296 176.4 1664 147.456 8 184320 147.456 12 122880 147.456 16 92160 147.456 24 61440 147.456 32 46080 147.456 48 3072 147.456 64 2304 147.456 96 1536 147.456 128 1152 147.456 192 768 146.7648 11.025 133120 146.7648 22.05 66560 146.7648 44.1 3328 146.7648 88.2 1664 146.7648 176.4 832 1 the instructions per sample in these cases exceed the program memory size of 819 2 words ; therefore, to utilize the full number of instructions, s ubroutines or branches are required in the sigmastudio program . rev. c | page 29 of 180
adau1452/adau1451/adau1450 data sheet clock generators three clock generators are available to generate audio clocks for the serial ports, dsp, asrcs, and oth er audio related functional blocks in the system. each clock generator can be configured to generate a base frequency and several fractions or multiples of that base frequency, creating a total of 15 clock domains available for use in the system. each of the 15 clock domains can create the appropriate lrclk (frame clock) and bclk (bit clock) signals for the serial ports. five bclk signals are generated at frequencies of 32 bclk/sample, 64 bc lk/sample, 128 bclk/sample, 256 bclk/ sample, and 512 bclk/sample to deal with tdm data. thus, with a single master clock input frequency, 15 different frame clock frequencies and 75 different bit clock frequencies can be generated for use in the system. the nominal output of each clock generator is determined by the following formula : output_frequency = ( inp ut_frequency n )/(1024 m ) w h e re: input_frequency is the pll output (nominally 294.912 mhz) . output_frequency is the frame clock output frequency. n and m are integers that are configured by writing to the clock generator configuration registers. these calculations are also accurate in the case of the adau1450 , even though the output rate of its pll is half of that of the adau1452 / adau1451 . in addition to the nominal output, four additional output signals are generated at double, quadruple, half, and a quarter of the frequency of the nominal output frequency. for clock generator 1 and clock generator 2, the integer numera - tor ( n ) and the integer denominator ( m ) are each nine bits long. for clock g enerator 3, n and m are each 16 bits long, allowing for a higher precision when generating arbitrary clock frequencies. figure 18 shows a basic block diagram of the pll and clock generators. each division operator symbolizes that the frequency of the clock is divided when passing through that block. each multiplication operator symbolizes that th e frequency of the clock is multiplied when passing through that block. figure 19 shows an example where the master clock input has a frequency of 12.288 mhz, and the default settings are used for the pll predivi der, feedback divider, and clock generator 1 and clock generator 2. the resulting system clock is 12.288 mhz 4 96 = 294.912 mhz the base output of clock generator 1 is 294.912 mhz 1024 1 6 = 48 khz the base output of clock generator 2 is 294.912 mhz 1024 1 9 = 32 khz in this example, clock generator 3 is configured with n = 49 and m = 320; therefore, the resulting base output of clock generator 3 is 294.912 mhz 1024 49 320 = 44.1 khz 4 (default) n = 1, m = 6 clkgen 1 n m 1024 4 (default) n = 1, m = 9 clkgen 2 n m 1024 4 clkgen 3 n m 1024 1, 2, 4, or 8 divider xtalin/ mclk system clock programmable typically 96 feedback divider 2 1 2 4 2 1 2 4 2 1 2 4 1 1486-022 figure 18 . pll and cloc k generators block diagram 192khz 96khz 48khz 24khz 12khz 128khz 64khz 32khz 16khz 8khz 176.4khz 88.2khz 44.1khz 22.05khz 11.025khz n = 1, m = 6 clkgen 1 n m 1024 n = 1, m = 9 n = 49, m = 320 clkgen 2 n m 1024 clkgen 3 n m 1024 divider 12.288mhz clock source 96 4 feedback divider 294.912mhz system clock (147.456mhz for adau1450) 1 1486-023 figure 19 . pll and audio clock generators with default settings and resulting clock frequencies labeled, xtalin/mclk = 12.288 mhz rev. c | page 30 of 180
data sheet adau1452/adau1451/adau1450 192khz 96khz 48khz 24khz 12khz 117.6khz 58.8khz 29.4khz 14.7khz 7.35khz 176.4khz 88.2khz 44.1khz 22.05khz 11.025khz n = 1, m = 6 clkgen 1 n m 1024 n = 1, m = 9 n = 80, m = 441 clkgen 2 n m 1024 clkgen 3 n m 1024 divider 11.2896mhz clock source 4 feedback divider 270.9504mhz system clock (135.4752mhz for adau1450) 1 1486-024 96 figure 20 . pll and audio clock generators wit h default settings and resulting clock frequencies labeled, xtalin/mclk = 11.2896 mhz figure 20 shows an example whe re the master clock input has a frequency of 11.2896 mhz , and the default se ttings are used for the pll predivider, feedback divider, and clock generator 1 and clock generator 2. the resulting system clock is 11.2896 mhz 4 96 = 270.9504 mhz the base output of clock generator 1 is 270.9504 mhz 1024 1 6 = 44.1 khz the base output of clock ge nerator 2 is 270.9504 mhz 1024 1 9 = 29.4 khz in this example, clock generator 3 is configured with n = 80 and m = 441; therefore, the resulting base output of clock generator 3 is 270.9504 mhz 1024 80 441 = 48 khz master clock output the maste r clock output pin (clkout) is useful in cases where a master clock must be fed to other ics in the system, such as audio codecs. the master clock output frequency is determined by the setting of the mclk_out register (address 0xf005). four frequencies are possible: 1, 2, 4, or 8 the frequency of the predivider output. ? the pre divider output 1 generates a 3.072 mhz output for a nominal system clock of 294.912 mhz. ? the predivider output 2 generates a 6.144 mhz output for a nominal system clock of 294 .912 mhz. ? the predivider output 4 generates a 12.288 mhz output for a nominal system clock of 294.912 mhz. ? the predivider output 8 generates a 24.576 mhz output for a nominal system clock of 294.912 mhz. clkgen 1 clkgen 2 clkgen 3 1, 2, 4, or 8 1, 2, 4, or 8 divider mclk system clock typically 96 feedback divider clkout 1 1486-025 figure 21 . clock outp ut generator the clkout pin can drive more than one external slave ic if the drive strength is sufficient to drive the traces and external receiver circuitry. the ability to drive external ics varies greatly, depending on the application and the charac teri stics of the pcb and the slave ics. the drive strength and slew rate of the clkout pin is configurable in the clkout_pin register (address 0xf7a3); thus, its performance can be tuned to match the specific application. the clkout pin is not designed to driv e long cables or other high impedance transmission lines. use the clkout pin only to drive signals to other integrated circuits on the same pcb. when changing the settings for the predivider, disable and then reenable the pll using register 0xf003 (pll_ena ble), allowing the frequency of the clkout signal to update. dejitter circuitry to account for jitter between ics in the system and to handle interfacing safely between internal and external clocks, de - jitter circuits are included to guarantee that jitter related clocking errors are avoided. the dejitter circuitry is automated and does not require interaction or control from the user. rev. c | page 31 of 180
adau1452/adau1451/adau1450 data sheet master clock, pll, and clock generators registers an overview of the registers related to the master clock, pll, and clock g enerators is listed in table 27 . for a more detailed description, see the pll configuration registers section and the clock g enerator registers section. table 27 . master clock, pll, and clock generator registers address register description 0xf000 pll_ctrl0 pll feedback divider 0xf001 pll_ctrl1 pll prescale divider 0xf002 pll_clk_src pll clock source 0xf003 pll_enable pll enable 0xf004 pll_lock pll lock 0xf005 mclk_out clkout control 0xf006 pll_watchdog analog pll watchdog control 0xf020 clk_gen1_m denominator (m) for clock generator 1 0xf021 clk_gen1_n numerator (n) for clock generator 1 0xf022 clk_gen2_m denominator (m) for clock generator 2 0xf023 clk_gen2_n numerator (n) for clock generator 2 0xf024 clk_gen3_m denominator (m) for clock generator 3 0xf025 clk_gen3_n numerator (n) for clock generator 3 0xf026 clk_gen3_src i nput reference fo r clock generator 3 0xf027 clk_gen3_lock lock bit for clock generator 3 input reference power supplies , voltage regulator , and hardware reset power supplies the adau1452 / adau1451 / adau1450 are supplied by four power supplies: iovdd, dvdd, avdd, and pvdd. ? iovdd (i nput/ output supply) sets the referen ce voltage for all di gital input and output pins. it can be any value ranging from 1.8 v ? 10% to 3.3 v + 10% . t o use the i 2 c/spi control ports or any of the digital input or output pins , the iovdd supply must be present . ? dvdd (d igital supply) powers the dsp core and supporting digital logic circuitry. it must be 1.2 v 5% . ? av dd (a nalog suppl y) powers the analog auxiliary adc circuitry. it must be supplied even if the auxiliary adcs are not in use. ? pvdd (pll supply) powers the pll and acts as a reference for the voltage controlled oscillator ( vco ). it must be supplied even if the pll is not in use. table 28 . power supply details supply voltage externally supplied? description iovdd (input/output) 1.8 v ? 10% to 3.3 v + 10% yes dvdd (digital) 1.2 v 5% optional can be derived from iovdd using an internal ldo regulator avdd (analog) 3.3 v 10% yes pvdd (pll) 3.3 v 10% yes voltage regulator the adau1452 / adau1451 / adau1450 include a linear regulator that can generate the 1.2 v supply required by the dsp core and other internal digital circuitry from an external supply. source t he linear regulator from the i/o supply (iovdd), which can range from 1.8 v ? 10% to 3.3 v + 10% . a simplified block diagram of the internal structure of the regulator i s shown in figure 23. for proper operation, the linear regulator requires several external components. a pnp bipolar junction transistor act s as an external pass device to bring the higher iovdd voltage down to t he lower dvdd voltage, thus externally dissipating the power of the ic package. ensure that t he current gain of the transistor () is 200 or greater and the transistor is ab le to dissipate at least 1 w in the worst case. place a 1 k resistor between the transistor emitter and base to help stabiliz e the regulator for varying loads. this resistor placement also guarantees that curr ent is always flowing into the vdrive pin, even for minimal regulator loads. figure 22 shows the connection of the external components. n vdrive iovdd dvdd 10f 100nf + 1 1486-027 figure 22 . external components required for volta ge regulator circuit if an external supply is provided to dvdd, ground the vdrive pin. the regulator continue s to draw a small amount of current (around 100 a) from the iovdd supply. do not use t he regulator to prov ide a voltage su p p ly to external ics. th ere are no control registers associated with the regulator. p ower reduction modes all sections of the ic have clock gating functionality that allows individual functional blocks to be disabled for power savings. functional blocks that can optionally be pow ered down include the following: ? clock generator 1, clock generator 2, and clock generator 3 ? s/pdif receiver ? s/pdif transmitter ? serial data input and output ports ? auxiliary adc ? asrcs (in two banks of eight channels each) ? pdm microphone inputs and decimatio n filters rev. c | page 32 of 180
data sheet adau1452/adau1451/adau1450 iovdd iovdd dvdd gnd internal 1.2v reference pmos device vdrive external stability resistor external pnp bipolar pass transistor 1 1486-026 figure 23 . simplified block diagram of regulator internal structure , including external components overview of power reduction registers an overview of the registers related to power reduction is shown in table 29 . for a more detailed description, refer to the power reduction registers section. table 29 . power reduction registers address register descriptio n 0xf050 power_enable0 disables clock generators, serial ports, and asrcs 0xf051 power_enable1 disables pdm microphone inputs, s/pdif interfaces, and auxiliary adcs hardware reset an active low hardware reset pin ( reset ) is availabl e for externally triggering a reset of the device. when this pin is tied to ground, all functional blocks in the device are disabled, and the current consumption decreases dramatically. the amount of current drawn depends on the leakage current of the sili con, which depends greatly on the ambient temperature and the properties of the die. when the reset pin is connected to iovdd, all control registers are reset to their power - on default values. the state of the ram is not guaranteed to be cleared after a reset, so the memory must be manually cleared by the dsp program. the default program generated by sigmastudio includes code that automatically clears the memory. to ensure that no chatter exists on the reset signal line , implement an external reset generation circuit in the system hardware design. figure 24 shows an example of the adm811 microprocessor super visory circuit with a push button connected, providing a method for manually generating a clean reset signal. for reliability purposes on the application level, place a weak pull - down resistor (in the range of several k) on the reset line to guarantee that the device is held in reset in the event that the reset supervisory circuitry fails. v cc mr gnd reset adm811 3.3v reset 100nf 3 2 1 4 1 1486-028 figure 24 . example manual reset ge neration circuit if the hardware reset function is not required in a system, pull the reset pin h igh to the iovdd supply, using a weak pull - up resistor (in the range of several k). the device is designed to boot properly even when the reset pin is permanently pulled high. dsp core current consumption the dsp core draws varying amounts of current, depending on the processing load required by the program it is running. figure 2 5 shows the relationship between program size and digital (dvdd) current draw. the minimum of 0 mips signifies the case where no program is running in the dsp core, and the maximum of 294 mips signifies that the dsp core is at full utilization, executing a typical audio processing program. 0 20 40 60 80 100 120 140 160 0 50 100 150 200 250 300 dvdd current (ma) program length (mips) 1 1486-124 figure 25 . adau1452 typical dvdd curren t draw vs. program mips at an ambient temperature of 25c and a sample rate of 48 khz temperature sensor diode the chip includes an on - board temperature sensor diode with a n approximate range of 0c to 120 c. the t emperature sensor function is enabled by the two sides of a diode connected to the thd_p and thd_m pins . v alue processing (calculating the actual temperature based on the current through the diode) is handled off chip by an external controller ic. the temperature value is not stored in an interna l register; it is available only in the external controller ic. t he t emperature sensor requires an external ic to operate properly. the temperature value cannot be read by the on - board auxiliary adc. rev. c | page 33 of 180
adau1452/adau1451/adau1450 data sheet 5 8 1 7 2 6 3 4 therm gnd alert sdata vdd d+ d? sclk adm1032 3.3v scl sda 100nf thd_ p thd_m 1 1486-029 figure 26 . example external temperature sensor circuit slave control port s a total of f our control ports are available : two slave ports and two master ports . the s lave i2c port and s lave spi port allow an external master device to modify the contents of the memory and registers. the m aster i 2 c port and m aster spi port allow the device to self boot and to send control messages to slave devices on the same bus. slave control port overview t o program the dsp and configure the control registers, a slave port is available that can communic ate using either the i 2 c or spi protocols. a separate master communications port can be used to self boot the chip by reading from an external eeprom, or to boot or control external ics by addressing them directly using i 2 c or spi. the slave communications port defaults to i 2 c mode ; however, it can be put into spi mode by toggling ss (ss/addr0) , the slave select pin, low three ti mes. each toggle should last at least the duration of one clock period of the clock on mclk (xtalin/mclk), the master clock input pin . until the pll locks, only the pll configuration registers (address 0xf000 to address 0xf004) are acces sible. for this reason, always write to the pll registers first after the chip powers up . after the pll locks , the remaining registers and the ram be come accessible. see the system initialization sequence section for more information . the control port is capable of full read/write operation for all addressable registers. the adau1452 / adau1451 / adau1450 must have a valid master clock to write to all regist ers, with the exception of register 0xf000 to register 0xf004. all addr esses can be accessed in both single address mode and burst mode. the first byte (byte 0) of a control port write contains the 7 - bit chip address plus the r/ w bit . the next two bytes (byte 1 and byte 2) together form the subaddress of the register location within the memory map s of the adau1452 / adau1451 / adau1450 . this subaddress must be two bytes long because the memory locations within the devices are directly addressable , and their sizes exceed the range of single byte addressing. all subse - quent bytes (starting with byte 3) contain the data, such as control port data, program data, or parameter data. the number of bytes per word depends on the type of data that is being written. the adau1452 / adau1451 / adau1450 have several mech - anisms for updating signa l processing parameters in real time without causing pops or clicks. if large blocks of data must be downloaded, halt the output of the ds p core (using register 0xf400 , hibernate ), load new data, and then restart the device (using register 0xf402 , start_co re) . this process is typically per formed during the b ooting sequence at start up or when loading a new program into ram. when updating a signal processing parameter while the dsp core is running, use the softwa re safeload function to avoid a situation where a parameter is updated over the boundary of an audio frame, which can lead to an audio artifact such as a click or pop sound. for more information, see the software safeload section. the slave control port pins are multifunctional, depending on the mode in which the device is operating. table 30 describes these multiple functions. burst mode writing and reading burst write and read modes are available for convenience wh en writing large amounts of data to contiguous registers. in these modes, the chip and memory addresses are written once, and then a large amount of data can follow uninterrupted. the sub - addresses are automatically incremented at the word boundaries. this increment happe ns automatically after a single word write or read unless a stop condition is encountered (i 2 c mode) or the slave select is disabled and brought high (spi mode). a burst write starts like a single word write, but , following the first data - w ord, the data - word for the next address can be written immediately without sending its 2 - byte address. the control registers in the adau1452 / adau1451 / adau1450 are two bytes wide, and the memories are four bytes wide. the autoincrement feature knows the word length at each subaddress ; therefore, it is not necessary to manually specify the subaddress for each address in a burst write. the subaddresses are automatic ally incremented by one address, following each read or write of a data - word, regardless of whether there is a valid register or ram word at that address. table 30 . control port pin functions pin name i 2 c slave mode spi slave mode ss/addr0 address 0 (bit 1 of the address word, input to the adau1452 / adau1451 / adau1450 ) slave select (input to the adau1452 / adau1451 / adau1450 ) cclk/scl clock (input to the adau1452 / adau1451 / adau1450 ) clock (input to the adau1452 / adau1451 / adau1450 ) mosi/addr1 address 1 (bit 2 of the address word, input to the adau1452 / adau1451 / adau1450 ) data; master out, slave in (in put to the adau1452 / adau1451 / adau1450 ) miso/ sda data (bidirectional, open collector) data; master in, slave out (output from the adau1452 / adau1451 / adau1450 ) rev. c | page 34 of 180
data sheet adau1452/adau1451/adau1450 i 2 c slave port the adau1452 / adau1451 / adau1450 support a 2 - wire serial (i 2 c - compatible) micro - processor bus driving multiple peripherals. the maximum clock frequency on the i 2 c slave port is 400 khz. two pins, serial data (sda) and serial clock (scl), carry information between the adau1452 / adau1451 / adau1450 and the system i 2 c master controller. in i 2 c mode, the adau1452 / adau1451 / adau1450 are always slave s on the bus, meaning that they cannot initiate a data transfer. each slave device is recognized by a unique address. the address bit sequence and the format of the read/w rite byte is shown in table 31 . the address resides in the first seven bits of the i 2 c write. the two address bits that follow can be set to assign the i 2 c slave address of the device, as follows: bit 1 can be set by pulling the ss/addr0 pin either to iovdd (by setting it to 1) or to gnd (by setting it to 0); and bit 2 can be set by pulling the mosi/addr1 pin either to iovdd (by setting it to 1) or to gnd (by setting it to 0). the lsb of the address (the r/ w bit) specifies either a read or write operation. logic level 1 corresponds to a read operation; logic level 0 corresponds to a write operation. table 31 describes the sequence of eight bits that def ine the i 2 c device address byte. table 32 describes the relationship between the state of the address pins (0 represents logic low and 1 represents logic high) and the i 2 c slave address. ensure that the address pi ns (ss/addr0 and mosi/addr1) are hardwired in the design. do not allow them to change states while the device is operating. place a 2 k pull - up resistor on each line connected to the sda and scl pins . ensure that the voltage on these signal lines does not exceed iovdd (1.8 v ? 10% to 3.3 v + 10%). table 31 . address bit sequence bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 1 1 0 addr1 (set by the mosi/addr1 pin) addr0 (set by the ss/addr0 pin) r/ w t able 32. i 2 c slave addresses mosi/ addr1 ss/ addr0 read/ write 1 slave address (eight b it s, i ncluding r/ w b it ) slave address ( seven b it s, e xcluding r/ w b it ) 0 0 0 0x70 0x38 0 0 1 0x71 0x38 0 1 0 0x72 0x39 0 1 1 0x73 0x39 1 0 0 0x74 0x3a 1 0 1 0x75 0x3a 1 1 0 0x76 0x3b 1 1 1 0x77 0x3b 1 0 = write, 1 = read. rev. c | page 35 of 180
adau1452/adau1451/adau1450 data sheet addressing initially, each device on the i 2 c bus is in an idle state and monitors the sda and scl l ines for a start condition and the proper address. the i 2 c master initiates a data transfer by establishing a start condition, defined by a high - to - low transition on sda while scl remains high. this indicates that an address/data stream follows. all device s on the bus respond to the start condition and shift the next eight bits (the 7 - bit address plus the r/ w bit) , msb first. the device that recognizes the transmitted address responds by pulling the data line low during the ninth cloc k pulse. this ninth bit is known as an acknowledge bit. all other devices withdraw from the bus at this point and return to the idle condition. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the first byte means that the master write s information to the peripheral, whereas a logic 1 means that the master read s information from the peripheral after writing the subaddress and repeating the start address. a data transfer occurs until a stop condition is encount ered. a stop condition occurs when sda transitions from low to high while scl is held high. figure 27 shows the timing of an i 2 c single word write operation , figure 28 shows the timing of an i 2 c burst mode write operation , and figure 29 shows an i 2 c burst mode read operation . stop and start conditions can be detected at any stage during the data transfer. if these conditions a re asserted out of sequence with normal read and write operations, the slave i 2 c port of the adau1452 / adau1451 / adau1450 immediately jumps to the idle condition. during a given scl high period, issue only one start condition and one stop condition, or a single stop condition followed by a single start condition. if the user issues an invalid subaddress , the adau1452 / adau1451 / adau1450 do not issue an acknowledge and return to the idle conditio n. note the following conditions: ? do not issue an autoincrement (burst) write command that exceeds the highest subaddress in the memory. ? do not issue an autoi ncrement (burst) write command that writes to subaddresses that are not defined in the global ram and control register map section . [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] stop data byte 1 data byte 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 20 22 23 24 25 26 27 28 29 31 30 32 33 34 35 36 37 38 39 41 40 42 43 44 45 0 1 1 1 0 addr1 addr0 r/w device address byte subaddress byte 1 subaddress byte 2 ack (slave) ack (slave) ack (slave) ack (slave) ack (slave) start sclk/scl miso/sda sclk/scl miso/sda 1 1486-030 figure 27 . i 2 c slave single word write operation (tw o byt e s) [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] data byte 1 data byte 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 20 22 23 24 25 26 27 28 29 31 30 32 33 34 35 36 37 38 39 41 40 42 43 44 0 1 1 1 0 addr1 addr0 r/w device address byte subaddress byte 1 subaddress byte 2 ack (slave) [7] [6] [5] [4] [3] [2] [1] [0] data byte n ack (slave) stop ack (slave) ack (slave) ack (slave) ack (slave) start sclk/scl miso/sda sclk/scl miso/sda 1 1486-031 figure 28 . i 2 c slave burst mode write operation (n bytes) [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] chip address byte data byte 1 from slave 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 20 22 23 24 25 26 27 28 29 31 30 32 33 34 35 36 37 38 39 41 40 42 43 44 0 1 1 1 0 addr1 addr0 r/w 0 1 1 1 0 addr1 addr0 r/w device address byte subaddress byte 1 subaddress byte 2 ack (slave) stop [7] [6] [5] [4] [3] [2] [1] [0] data byte n from slave ack (slave) ack (slave) ack (slave) ack (slave) ack (slave) start repeated start sclk/scl miso/sda sclk/scl miso/sda 1 1486-032 figure 29 . i 2 c slave burst mode read operation (n bytes ) rev. c | page 36 of 180
data sheet adau1452/adau1451/adau1450 rev. c | page 37 of 180 i 2 c read and write operations figure 30 shows the format of a single word write operation. every ninth clock pulse, the adau1452 / adau1451 / adau1450 issue an acknowledge by pulling sda low. figure 31 shows the simplified format of a burst mode write sequence. this figure shows an example of a write to sequential single byte registers. the adau1452 / adau1451 / adau1450 increment the subaddress register after every byte because the requested subaddress corresponds to a register or memory area with a 1-byte word length. figure 32 shows the format of a single word read operation. note that the first r/ w bit is 0, indicating a write operation. this is because the subaddress still needs to be written to set up the internal address. after the adau1452 / adau1451 / adau1450 acknowledge the receipt of the subaddress, the master must issue a repeated start command followed by the chip address byte with the r/ w bit set to 1 (read). this causes the sda pin of the device to reverse and begin driving data back to the master. the master then responds every ninth pulse with an acknowledge pulse to the device. figure 33 shows the format of a burst mode read sequence. this figure shows an example of a read from sequential single byte registers. the adau1452 / adau1451 / adau1450 increment the subaddress register after every byte because the requested subaddress corresponds to a register or memory area with a 1-byte word length. the adau1452 / adau1451 / adau1450 always decode the subaddress and set the auto-increment circuit such that the address increments after the appropriate number of bytes. figure 30 to figure 33 use the following abbreviations: s = start bit p = stop bit am = acknowledge by master as = acknowledge by slave s as subaddress, low as as as as ... as p chip address, r/w = 0 data byte 1 data byte 2 data byte n subaddress, high s = start bit, p = stop bit, am = acknowledge by master, as = acknowledge by slave. shows a one-word write, where each word has n bytes. 11486-033 figure 30. simplified single word i 2 c write sequence s a s a s a sa sa sa sa s a sa s ... p chip address, r/w = 0 subaddress, high subaddress, low data-word 1, byte 1 data-word 1, byte 2 data-word 2, byte 1 data-word 2, byte 2 data-word n, byte 1 data-word n, byte 2 s = start bit, p = stop bit, am = acknowledge by master, as = acknowledge by slave. shows an n-word write, where each word has two bytes. (other word lengths are possible, ranging from one to five bytes.) 11486-034 figure 31. simplified burst mode i 2 c write sequence s am am as am as s as as ... p chip address, r/w = 0 chip address, r/w = 1 data byte n data byte 2 data byte 1 subaddress, high subaddress, low s = start bit, p = stop bit, am = acknowledge by master, as = acknowledge by slave. shows a one-word write, where each word has n bytes. 11486-035 figure 32. simplified single word i 2 c read sequence s sa s a s a s a s a ma m a ma m ... p chip address, r/w = 0 subaddress, high subaddress, low data-word 1, byte 1 data-word 1, byte 2 data-word n, byte 1 data-word n, byte 2 chip address, r/w = 1 s = start bit, p = stop bit, am = acknowledge by master, as = acknowledge by slave. shows an n-word write, where each word has two bytes. (other word lengths are possible, ranging from one to five bytes.) 11486-036 figure 33. simplified burst mode i 2 c read sequence
adau1452/adau1451/adau1450 data sheet spi slave port by default, the slave port is in i 2 c mode, but it can be put into spi control mode by pulling ss/addr0 low three times. this can be done either by toggling the ss/addr 0 successively between logic high and logic low states, or by performing three dummy writes to the spi port , writing any arbitrary data to any arbitrary subaddress (the slave port does not acknowledge these three writes). after the ss/addr0 is toggled thre e times , data can be written to or read from the ic. an example of dummy writing is shown in figure 34 . once set in spi slave mode, the only way to revert back to i 2 c slave mode is by executing a full hardware re set using the reset pin or by power cycling the power supplies . the spi port uses a 4 - wire interface, consisting of the ss, mosi, miso, and sclk signals, and it is always a slave port. the ss signal go es low at the beginning of a transac tion and high at the end of a transaction. the sclk signal latches mosi on a low - to - high transition. miso data is shifted out of the device on the falling edge of s clk and must be clocked into a receiving device, such as a microcontroller, on the s clk risi ng edge. the mosi signal carries the serial input data, and the miso signal carries the serial output data. the miso signal remains three - state until a read operation is requested. this allows other spi - compatible peripherals to share the same miso line. a ll spi transactions have the same basic format shown in table 34 . a timing diagram is shown in figure 9 . write a ll data msb first. there is only one chip address ava i lable in spi mode. the 7 - bit chip address is 0b0000000. the lsb of the first byte of an spi transaction is a n r/ w bit. this bit determines whether the communication is a read (logic level 1) or a write (logic level 0). this format i s shown in table 33. table 33 . spi address and read/ write byte format bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 0 0 0 0 0 0 r/ w t he 16 - bit subaddress word is decoded into a location in one of the registers. this subaddress is the location of the appropriate register. the msbs of the subaddress are zero padded to bring the word to a full 2 - byte length. the format for the spi communi cations s lave port is commonly known as spi m ode 3, where clock polarity ( cpol ) = 1 and clock phase ( cpha ) = 1 (see figure 35) . the base value of the clock is 1 . data is captured on the rising edge of the clock, and data is propagated on the falling edge. the maximum read and write speed for the spi slave port is 22 mhz, but this speed is valid only after the pll is locked. before the pll locks, the maximum clock rate in the chip is limited to the frequency of the input clock to the pll. nominally, this is 3.072 mhz. therefore, the spi clock must not exceed 3.072 mhz until the pll lock completes. 0 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19 9 20 21 22 23 24 25 26 27 ss/addr0 sclk/scl mosi/addr1 1 1486-038 figure 34 . example of spi slave mode initialization sequence using dummy writes table 34 . generic control word sequence byte 0 byte 1 byte 2 byte 3 byte 4 and subsequent bytes chip address[6:0], r/ w subaddress[15:8] subaddress[7:0] data data 1 1486-037 cpol = 0 cpol = 1 sclk ss cpha = 0 cpha = 1 1 2 1 2 1 2 1 2 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 z miso cycle # mosi miso cycle # mosi 2 3 4 5 6 7 8 z 1 2 3 4 5 6 7 8 z z 1 2 3 4 5 6 7 8 z z z z figure 35 . clock pol arity and phase for spi slave port rev. c | page 38 of 180
data sheet adau1452/adau1451/adau1450 rev. c | page 39 of 180 a sample timing diagram for a multiple word spi write operation to a register is shown in figure 36. a sample timing diagram of a single word spi read operation is shown in figure 37. the miso/sda pin transitions from being three-state to being driven at the beginning of byte 3. in this example, byte 0 to byte 2 contain the addresses and the r/ w bit, and subsequent bytes carry the data. a sample timing diagram of a multiple word spi read operation is shown in figure 38. in figure 36 to figure 38, rising edges on sclk/scl are indicated with an arrow, signifying that the data lines are sampled on the rising edge. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 r/w ss/addr0 sclk/scl mosi/addr1 chip address[6:0] subaddress byte 1 subaddress byte 2 data byte 1 data byte 2 data byte n 11486-039 figure 36. spi slave write clocking (burst write mode, n bytes) 012345678910111213141516171819202122232425262728293031323334353637383940 ss/addr0 sclk/scl mosi/addr1 miso/sda data byte 1 data byte 2 chip address[6:0] subaddress byte 1 subaddress byte 2 11486-040 r/w figure 37. spi slave read clocking (single word mode, two bytes) 0123456789101112131415161718192021222324252627282930313233343536373839 ss/addr0 sclk/scl mosi/addr1 miso/sda data byte 1 data byte 2 data byte n chip address[6:0] subaddress byte 2 subaddress byte 1 11486-041 r/w figure 38. spi slave read clocking (burst read mode, n bytes)
adau1452/adau1451/adau1450 data sheet rev. c | page 40 of 180 master control ports the device contains a combined i 2 c and spi master control port that is accessible through a common interface. the master port can be enabled through a self boot operation or directly from the dsp core. the master control port can buffer up to 128 bits of data per single interrupt period. the smallest data transfer unit for both bus interfaces is one byte, and all transfers are 8-bit aligned. no error detection is supported, and single master operation is assumed. only one bus interface protocol (i 2 c or spi) can be used at a time. the master control port can be used for several purposes, as follows: ? self boot the adau1452 / adau1451 / adau1450 from an external serial eeprom. ? boot and control external slave devices such as codecs and amplifiers. ? read from and write to an external spi ram or flash memory. spi master interface the spi master supports up to seven slave devices (via the mpx pins) and speeds between 2.3 khz and 20 mhz. spi mode 0 (cpol = 0, cpha = 0) and spi mode 3 (cpol = 1, cpha = 1) are supported. communication is assumed to be half duplex, and the spi master does not support a 3-wire interface. there is no jtag or sgpio support. the spi interface uses a minimum of four general-purpose input/output pins of the processor and up to six additional mpx pins for additional slave select signals (ss). see table 35 for more information. the spi master clock frequency can range between 2.3 khz and 20 mhz. jtag and sgpio are not supported. data transfers are 8-bit aligned. by default, the spi master port is in mode 3 (cpol = 1, cpha = 1), which matches the mode of the spi slave port. the spi master port can be configured to operate in mode 0 (cpol = 0, cpha = 0) in the dsp program. no error detection or handling is implemented. single master operation is assumed; therefore, no other master devices can exist on the same spi bus. the spi master interface has been tested with eeprom, flash, and serial ram devices and has been confirmed to work in all cases. when the data rate is very high on the spi master interface (at 10 mhz or higher), a condition may arise where there is a high level of current draw on the iovdd supply, which can lead to sagging of the internal iovdd supply. to avoid potential issues, design the pcb such that the traces connecting the spi master interface to external devices are kept as short as possible, and the slew rate and drive strength for spi master interface pins are kept to a minimum to keep current draw as low as possible. keeping iovdd low (2.5 v or 1.8 v) also reduces the iovdd current draw. sigmastudio generates eeprom images for self boot systems, requiring no manual spi master port configuration or program- ming on the part of the user. i 2 c master interface the i 2 c master is 7-bit addressable and supports standard and fast mode operation with speeds between 20 khz and 400 khz. the serial camera control bus (sccb) and power management bus (pmbus) protocols are not supported. data transfers are 8-bit aligned. no error detection or correction is implemented. the i 2 c master interface uses two general-purpose input/output pins, mp2 and mp3. see table 36 for more information. table 35. spi master interface pin functionality pin name spi master function description mosi_m/mp1 mosi spi master port data output. sends data from the spi master port to slave devices on the spi master bus. scl_m/sclk_m/mp2 sclk spi master port serial clock. drives the clock signal to slave devices on the spi master bus. sda_m/miso_m/mp3 miso spi master port data input. receives data from slav e devices on the spi master bus. ss_m/mp0 ss spi master port slave select. acts as the primary slave select signal to slave device on the spi master bus. mp4 to mp13 ss spi master port slave select. these additional multipurpose pins can be configured to act as secondary slave select signals to additional slave devices on the spi master bus. up to seven slave devices, one per pin, are supported. table 36. i 2 c master interface pin functionality pin name i 2 c master function description scl_m/sclk_m/mp2 scl i 2 c master port serial clock. this pin functions as an open collector output and dr ives a serial clock to slave devices on the i 2 c bus. the line connected to this pin must have a 2.0 k pull-up resistor to iovdd. sda_m/miso_m/mp3 sda i 2 c master port serial data. this pin functions as a bidirectional open collector data line between the i 2 c master port and slave devices on the i 2 c bus. the line connected to this pin must have a 2.0 k pull-up resistor to iovdd.
data sheet adau1452/adau1451/adau1450 self boot the master control port is capab le of boo ting the device from a single eeprom by connecting the selfboot pin to logic high (iovdd) and powering up the power supplies while the reset pin is pulled high . this initiates a self boot operation, in which the master control p ort downloads all required memory and register settings and automatically start s executing the dsp program without requiring external interven tion or supervision. a self boot operation can also be triggered while the device is already in operation by initi ating a rising edge of the reset pin while the selfboot pin is held high . when the self boot operation begins, the state of the ss_m/mp0 pin determines whether the spi master or the i 2 c master carries out the self boot operation. if the ss_m/mp0 pin is connected to logic low, the i 2 c master port carries out the self boot operation. otherwise, connect this pin to the slave select pin of the external slave device. t he spi master port then carries out the self boot operation. when self booti ng from spi, the chip assumes the following: ? the slave eeprom is selected via the ss_m/mp0 pin. ? the slave eeprom has 16 - or 24 - bit addressing, giving it a total memory size of between 4 kb and 64 mb . ? the slave eeprom supports serial clock frequencies down to 1 mhz or lower (a majority of the self boot operation uses a much higher clock frequency, but the initial transactions are performed at a slower frequency). ? the data stored in the slave eeprom follows the format described in the eeprom self boot data format section. ? the data is stored in the slave eeprom with the msb first. ? the slave eeprom supports spi m ode 3 . ? the slave eeprom sequential read operation has the command of 0x03 . ? the slave eeprom can be accesse d immediately after it is powered up , with no manual configuration required. when self booting from i 2 c, the chip assumes the following: ? the slave eeprom has i 2 c address 0x50. ? the slave eeprom has 16 - bit addressing, giving it a size of between 16 kb and 512 kb . ? the slave eeprom supports standard mode clock frequencies of 100 khz and lower (a majority of the self boot operation uses a much higher clock frequency, but the initial transactions are performed at a slower frequency). ? the data stored in the sl ave eeprom follows the format described in the eeprom self boot data format section. ? the slave eeprom can be accessed immediately after it is powered, with no manual configuration required. self boot failure the spi or i 2 c master port attempts to self boot from the eeprom three times. if all three self boot attempts fail, the sigmadsp core issues a software panic and then enters a sleep state. during a self boot operation, the panic manager is unable to output a panic flag on a multipurpose pin. therefore , the only way to debug a self boot failure is by reading back the status of register 0xf427 (panic_flag) and register 0xf428 (panic_code). the contents of register 0xf428 indicate the nature of the failure. eepr om self boot data format the self boot eeprom image is generated using the sigmastudio software; thus, the user does not need to manually create the data that is stored in the eeprom. however, for reference, the details of the data format are described in this section. the eeprom self boot format consists of a fixed header, an arbitrary number of variable length blocks, and a fixed footer. the blocks themselves consist of a fixed header and a block of data with a variable length. each data block can be plac ed anywhere in the dsp memory through configuration of the block header. rev. c | page 41 of 180
adau1452/adau1451/adau1450 data sheet header format the self boot eeprom header consists of 16 bytes of data , starting at the beginning of the internal memory of the slave eeprom (address 0) . the header format (see figure 39) consists of the following: ? 8 - bit sentinel 0xaa (shown in figure 39 as 0b10101010) ? 24- bit address indicating the byte address of the header of the first block (nor mally this is 0x000010 , which is the address immediately following the header ) ? 64- bit pll configuration (pll_checksum = p ll_fb_div + mclk_out + pll_div) data block format following the header, several data blocks are stored in the eeprom memory (see figure 40). each data block consists of eight bytes that configure the length and address of the data, followed by a series of 4 - byte data packets. each block consists of the following: ? one lst bit , which signals the l ast block before the footer. l st = 0b1 indicates the last block ; l st = 0b0 indicates that additional blocks are still to follow. ? 13 bits that are reserved for future use. set these bits to 0 b0 . ? two mem bits that select the target data memory bank (0x0 = da ta m emory 0, 0x1 = data m emory 1, 0x2 = program memory). ? 16- bit base address that sets the memory address at which the master port start s writing when loading da ta from the block into memory. ? 16- bit d ata l ength that defines the number of 4 - byte data - words to be written. ? 16- bit j ump a ddress that tells the dsp core at which address in program memory it should begin execution when the self boot operation is complete. the jump address bits are ignored unless the l st bit is set to 0b1. ? a rbitrary number of packe ts of 32 - bit data. the number of packets is defined by the 16 - bit d ata l ength . footer format after all the data blocks, a footer signifies the end of the self boot eeprom memory (see figure 41 ). the footer consis ts of a 64 - bit checksum, which is the sum of the header and all blocks and all data as 32 - bit words. after the self boot operation completes, the checksum of the down - loaded data is calculated and the panic manager signals if it does not match the checksum in the eeprom. if the checksum is set to 0 dec , the checksum checking is disabled. byte 0 byte 1 byte 2 byte 3 1 0 1 0 1 0 1 0 address of first boot block byte 4 byte 5 byte 6 byte 7 0x00 pll_div 0x00 pll_fb_div byte 8 byte 9 byte 10 byte 11 0x00 pll_checksum 0x00 mclk_out byte 12 byte 13 byte 14 byte 15 eeprom speed configuration 1 1486-042 figure 39 . self boot eeprom header format byte 0 byte 1 byte 2 byte 3 lst reserved mem base address byte 4 byte 5 byte 6 byte 7 data length jump address byte 8 byte 9 byte 10 byte 11 data-word 1 byte 12 byte 13 byte 14 byte 15 data-word 2 fourth to last byte third to last byte second to last byte last byte data-word n continued until last word is reached? 1 1486-043 figure 40 . self boot eeprom data block format byte 0 byte 1 byte 2 byte 3 first four bytes of checksum byte 4 byte 5 byte 6 byte 7 last four bytes of checksum 1 1486-044 figure 41 . self boot eeprom footer format rev. c | page 42 of 180
data sheet adau1452/adau1451/adau1450 considerations w hen u sing a 1 mb i 2 c self boot eeprom because of the way i 2 c addressing works , 1 mb of i 2 c eeprom memory can be divided, with a portion of its address space at chip address 0x50 ; another portion of the memory can be located at a different address (for example, chip address 0x51). the memory allocation varies , depending on the eeprom design. in case s when the eeprom memory is divided , the memory portion that reside s at a different chip address must be handled as though it exists in a separate eeprom . considerations w hen u sing m ultiple eeproms on the spi master bus when multiple eeproms are connected on the same spi master bus, the self boot mechanism work s only with the first eeprom. audio signal routi ng a large number of audio inputs and outputs are available in the device, and control registers are available for configuring the way in which the audio is routed between different functional blocks. the adau1450 does not include an s/pdif receiver, s/pdif transmitter, or asrcs, so signals cannot be routed to or from those subsystems. all input channels are accessible by both the dsp core and the asrcs. each asrc can connect to a pair of audio channels from any of the input sources or from the dsp_to_asrc channels of the dsp core . the serial out puts can obtain their data from a number of sources, includi ng the dsp core, asrcs, pdm microphones, s/pdif receiver, or directly from the serial inputs. see figure 42 for a n overview of the audio routing matrix with its available audio data connections . to route audio to and from the dsp core, select the appropriate input and output cells in sigmastudio. these cells can be found in the io folder of the sigmastudio algorithm toolbox. 1 1486-045 input 0 to input 15 sdata_in0 (2 ch to 16 ch) sdata_in1 (2 ch to 16 ch) sdata_in2 (2 ch to 8 ch) sdata_in3 (2 ch to 8 ch) sdata_out0 (2 ch to 16 ch) sdata_out1 (2 ch to 16 ch) sdata_out2 (2 ch to 8 ch) sdata_out3 (2 ch to 8 ch) spdifin s/pdif rx dsp core asrcs (8) spdifout mp6 mp7 input 16 to input 31 input 32 to input 39 input 40 to input 47 asrc outputs input 0 to input 15 input 16 to input 31 input 32 to input 39 input 40 to input 47 pdm microphone inputs s/pdif receiver asrc outputs (16 channels) output 0 to output 15 output 16 to output 31 output 32 to output 39 output 40 to output 47 serial s/pdif tx serial output port 1 serial output port 2 serial output port 3 serial output port 0 16 ch 16 ch (2 ch 8 asrcs) 16 ch 16 ch 16 ch 16 ch 16 ch 8 ch 8 ch 16 ch 8 ch 8 ch 4 ch 2 ch 16 ch 16 ch 8 ch 8 ch 4 ch 2 ch 16 ch 16 ch 8 ch 8 ch 4 ch 2 ch input 0 to input 15 input 16 to input 31 input 32 to input 39 input 40 to input 47 pdm microphone inputs s/pdif receiver dsp to asrc (16 channels) asrc to dsp (16 channels) dsp core s/pdif out 2 ch input port 0 serial input port 1 serial input port 2 serial input port 3 pdm mic input adau1452/adau1451 figure 42 . audio routing overview rev. c | page 43 of 180
adau1452/adau1451/adau1450 data sheet serial audio inputs to ds p core the 48 serial input channels are mapped to four audio input cells in sigmastudio. each input cell corresponds to one of the serial input pins (see table 37 ) . depending on whether the serial port is configu red in 2 - channel, 4 - channel, 8 - channel, or 16 - channel mode, the available channels in sigmastudio change. the channel count for each serial port is configured in the serial_byte_x_0 registers , bits[2:0] ( tdm_mode ) , at address 0xf200 to address 0xf21c (in i ncrements of 0x4) . figure 43 shows how the input pins map to the input cells in sigmastudio, including their graphical appearance in the software. table 37 . serial input pin mapping to si gmastudio input cells serial input pin channels in sigmastudio sdata_in0 0 to 15 sdata_in1 16 to 31 sdata_in2 32 to 39 sdata_in3 40 to 47 table 38 . detailed serial input mapping to sigmastudio input channels 1 serial input pin position in i 2 s stream (2 - c hannel) position in tdm4 stream position in tdm8 stream position in tdm16 stream input channel in sigmastudio sdata_in0 left 0 0 0 0 sdata_in0 right 1 1 1 1 sdata_in0 n/a 2 2 2 2 sdata_in0 n/a 3 3 3 3 sdata_in0 n/a n/a 4 4 4 sdata_in0 n/a n/a 5 5 5 sdata_in0 n/a n/a 6 6 6 sdata_in0 n/a n/a 7 7 7 sdata_in0 n/a n/a n/a 8 8 sdata_in0 n/a n/a n/a 9 9 sdata_in0 n/a n/a n/a 10 10 sdata_in0 n/a n/a n/a 11 11 sdata_in0 n/a n/a n/a 12 12 sdata_in0 n/a n/a n/a 13 13 sdata_in 0 n/a n/a n/a 14 14 sdata_in0 n/a n/a n/a 15 15 sdata_in1 left 0 0 0 16 sdata_in1 right 1 1 1 17 sdata_in1 n/a 2 2 2 18 sdata_in1 n/a 3 3 3 19 sdata_in1 n/a n/a 4 4 20 sdata_in1 n/a n/a 5 5 21 sdata_in1 n/a n/a 6 6 22 sdata_in1 n/a n/a 7 7 23 sda ta_in1 n/a n/a n/a 8 24 sdata_in1 n/a n/a n/a 9 25 sdata_in1 n/a n/a n/a 10 26 sdata_in1 n/a n/a n/a 11 27 sdata_in1 n/a n/a n/a 12 28 sdata_in1 n/a n/a n/a 13 29 sdata_in1 n/a n/a n/a 14 30 sdata_in1 n/a n/a n/a 15 31 sdata_in2 left 0 0 0 32 sdat a_in2 right 1 1 1 33 sdata_in2 n/a 2 2 2 34 sdata_in2 n/a 3 3 3 35 sdata_in2 n/a n/a 4 4 36 sdata_in2 n/a n/a 5 5 37 sdata_in2 n/a n/a 6 6 38 sdata_in2 n/a n/a 7 7 39 rev. c | page 44 of 180
data sheet adau1452/adau1451/adau1450 serial input pin position in i 2 s stream (2 - c hannel) position in tdm4 stream position in tdm8 stream position in tdm16 stream input channel in sigmastudio sdata_in3 left 0 0 0 40 sdata_in3 right 1 1 1 41 sdata_in3 n/a 2 2 2 42 sdata_i n3 n/a 3 3 3 43 sdata_in3 n/a n/a 4 4 44 sdata_in3 n/a n/a 5 5 45 sdata_in3 n/a n/a 6 6 46 sdata_in3 n/a n/a 7 7 47 1 n/a = not applicable. input 0 to input 15 sdata_in0 (2 ch to 16 ch) sdata_in1 (2 ch to 16 ch) sdata_in2 (2 ch to 8 ch) sdata_in3 (2 ch to 8 ch) input 16 to input 31 input 32 to input 39 input 40 to input 47 serial input port 0 serial input port 1 serial input port 2 serial input port 3 1 1486-046 16 ch 16 ch 8 ch 8 ch figure 43 . serial port audio input mapping to dsp in sigmastudio pdm microphone inputs to dsp core the pdm microphone inputs are mapped to a single digital micro - phone input cell in sigmastudio (see table 39 and figure 44 ) . the corresponding hardware pins are configured in register 0xf560 (dmic_ctrl0) and register 0xf561 (dmic_ctrl1). table 39 . pdm microphone input mapping to sigmastudio channels pdm data channel pdm microphone input channel in sigmastudio left (dmic_ctrl0) 0 right (dmic_ctrl0) 1 l eft (dmic_ctrl1) 2 right (dmic_ctrl1) 3 mp6 mp7 pdm mic input 4 ch 1 1486-047 figure 44 . pdm microphone input mapping to dsp in sigmastudio s/pdif receiver inputs to dsp core the s/pdif r eceiver can be accessed directly in the dsp core by using the s/pdif input ce ll. however, in most applications, the s/pdif receiver input is asynchronous to the dsp core, so an asrc is typically required; in such cases , the s/pdif input cell must not be used. table 40 . s/pdif input mapping to sigmastudio cha nnels channel in s/pdif receiver data stream s/pdif input channels in sigmastudio left 0 right 1 2 ch spdifin s/pdif rx to asrc and output side 1 1486-048 figure 45 . s/pdif receiver direct input mapping to dsp in sigmastudio rev. c | page 45 of 180
adau1452/adau1451/adau1450 data sheet serial audio outputs from dsp core the 48 serial output ch annels are mapped to 48 separate audio output cells in sigmastudio. ea ch audio output cell corresponds to a single output channel. the first 16 channels are mapped to the sdata_out0 pin . the next 16 channels are mapped to the sdata_out1 pin . the following eight channels are mapped to the sdata_out2 pin . the last eight cha nnels are mapped to the sdata_out3 pin (see table 41 and figure 46 ) . table 41 . serial output pin mapping from sigmastudio channels 1 channel in sigmastudio serial output pin position in i 2 s stream (2 - channel) position in tdm4 stream position in tdm8 stream position in tdm16 stream 0 sdata_out0 left 0 0 0 1 sdata_out0 right 1 1 1 2 sdata_out0 n/a 2 2 2 3 sdata_out0 n/a 3 3 3 4 sdata_out0 n/a n/a 4 4 5 sdata_out0 n/a n/a 5 5 6 sdata_out0 n/a n/a 6 6 7 sdata_out0 n/a n/a 7 7 8 sdata_out0 n/a n/a n/a 8 9 sdata_out0 n/a n/a n/a 9 10 sdata_out0 n/a n/a n/a 10 11 sdata_out0 n/a n/a n/a 11 12 sdata_out0 n/a n/a n/a 12 13 sdata_out0 n/a n/a n/a 13 14 sdata_out0 n/a n/a n/a 14 15 sdata_out0 n/a n/a n/a 15 16 sdata_out1 left 0 0 0 17 sdata_out1 right 1 1 1 18 sdata_out1 n/a 2 2 2 19 sdata_out1 n/a 3 3 3 20 sdata_out1 n/ a n/a 4 4 21 sdata_out1 n/a n/a 5 5 22 sdata_out1 n/a n/a 6 6 23 sdata_out1 n/a n/a 7 7 24 sdata_out1 n/a n/a n/a 8 25 sdata_out1 n/a n/a n/a 9 26 sdata_out1 n/a n/a n/a 10 27 sdata_out1 n/a n/a n/a 11 28 sdata_out1 n/a n/a n/a 12 29 sdata_out1 n/ a n/a n/a 13 30 sdata_out1 n/a n/a n/a 14 31 sdata_out1 n/a n/a n/a 15 32 sdata_out2 left 0 0 0 33 sdata_out2 right 1 1 1 34 sdata_out2 n/a 2 2 2 35 sdata_out2 n/a 3 3 3 36 sdata_out2 n/a n/a 4 4 37 sdata_out2 n/a n/a 5 5 38 sdata_out2 n/a n/a 6 6 39 sdata_out2 n/a n/a 7 7 40 sdata_out3 left 0 0 0 41 sdata_out3 right 1 1 1 42 sdata_out3 n/a 2 2 2 43 sdata_out3 n/a 3 3 3 44 sdata_out3 n/a n/a 4 4 45 sdata_out3 n/a n/a 5 5 46 sdata_out3 n/a n/a 6 6 47 sdata_out3 n/a n/a 7 7 1 n/a = not app licable. rev. c | page 46 of 180
data sheet adau1452/adau1451/adau1450 output 0 to output 15 16 ch output 16 to output 31 16 ch output 32 to output 39 output 40 to output 47 8 ch 8 ch from serial inputs, pdm mics, s/pdif receiver, and asrcs sdata_out0 (2 ch to 16 ch) sdata_out1 (2 ch to 16 ch) sdata_out2 (2 ch to 8 ch) sdata_out3 (2 ch to 8 ch) serial output port 1 serial output port 2 serial output port 3 serial output port 0 1 1486-049 figure 46 . dsp to serial output mapping in sigmastudio the data that is output from each serial output pin is also configur able , via the sout_source x registers , to originate from one of the following sources: t h e d s p, t he serial inputs, the pdm microphone inputs, the s/pdif receiver, or the asrcs. these registers can be configured graphically in sigmastudio, as shown in figure 47. sout source 0 sout source 1 sout source 2 sout source 3 sout source 4 sout source 5 sout source 6 sout source 7 sdata_out0 serial output port 0 1 1486-050 figure 47 . configuri ng the serial output data channels (sout_source x registers) graphically in sigmastudio s/pdif audio outputs from dsp core to s/pdif transmitter the output signal of the s/pdif transmitter can come from the dsp core or directly from the s/pdif receiver. the selection is controlled by register 0xf1c0 ( spdiftx_input ) . s/pdif rx 0 s/pdif rx 1 s/pdif tx 0 s/pdif tx 1 dsp s/pdif out 0 dsp s/pdif out 1 spdifout s/pdif tx 1 1486-051 figure 48 . s/pdif transmitter source selection when the signal comes from the dsp core, use the s/pdif output cells in sigmastudio. table 42 . s/ pdif output mapping from sigmastudio channels s/pdif output channel in sigmastudio channel in s/pdif transmitter data stream 0 left 1 right spdifout s/pdif tx dsp core s/pdif out 2 ch from s/pdif receiver 1 1486-052 figure 49 . dsp to s/pdif transmitter output mapping in sigmastudio rev. c | page 4 7 of 180
adau1452/adau1451/adau1450 data sheet asynchronous s ample rate converter input routing any asynchronous input can be routed to the asrcs to be re synchronized to a desired target sample rate (see figure 50) . the source signals for any asrc can come from any of the serial inputs, any of the dsp - to - asrc channels, the s/pdif receiver, or the digital pdm microphone inputs. there are eight asrcs, each with two input channels and two output channels. this means a total of 16 channels can pass through the asrcs. asynchrono us input signals (either serial inputs, pdm microphone inputs, or the s/pdif input) typically need to be routed to an asrc and then synchronized to the dsp core rate. they are then available for input to the dsp core for processing. in the example shown in figure 51 , the two channels from the s/pdif receiver are routed to one of the asrcs and then to the dsp core. for this example, the corresponding asrc input selector register (register 0xf100 to register 0xf107, asrc_inputx), bits[2:0] (asrc_source) is set to 0b011 to take the input from the s/pdif receiver . l i kewise, the corresponding asrc output rate selector register (register 0xf140 to register 0xf147, asrc_ out_ratex , bits[3:0] (asrc_rate) ) is set to 0b0101 to synchronize the asrc output data to the dsp core sample rate. 1 1486-053 asrcs (8) input 0 to input 15 input 16 to input 31 input 32 to input 39 input 40 to input 47 pdm microphone inputs s/pdif receiver asrc outputs (16 channels) 16 ch (2 ch 8 asrcs) 16 ch 16 ch 16 ch 16 ch 8 ch 8 ch 4 ch 2 ch dsp to asrc (16 channels) asrc to dsp (16 channels) dsp core asrc outputs 16 ch adau1452/ adau1451 figure 50 . channel routing to asrc inputs asrcs (8) s/pdif receiver 16 ch 2 ch asrc to dsp (16 channels) dsp core 1 1486-054 figure 51 . example asrc routing for asynchronous input to the dsp core rev. c | page 48 of 180
data sheet adau1452/adau1451/adau1450 when the outputs of t he asrcs are required for processing in the sigmadsp core, the asrc input block must be selected in sigmastudio (see figure 52 and figure 53). in the case of the adau1450 , which has no asrcs, the asrc input cell does not generate any data. 1 1486-055 figure 52 . location of asrc - to- dsp input cell in sigmastudio toolbox asrc0 asrc out 0 asrc1 asrc2 asrc3 asrc4 asrc5 asrc6 asrc7 asrc out 1 asrc out 2 asrc out3 asrc out4 asrc out 5 asrc out 6 asrc out 7 asrc out 8 asrc out 9 asrc out 10 asrc out 11 asrc out 12 asrc out 13 asrc out 14 asrc out 15 1 1486-056 figure 53 . routing of asrc outputs to asrc - to - dsp input cell in sigmastudio rev. c | page 49 of 180
adau1452/adau1451/adau1450 data sheet asynchronous output signals (for example, serial outputs that are slaves to an ext ernal, asynchronous device) typically are routed from the dsp core into the asrcs, where they are synchronized to the serial output port that is acting as a slave to the external asynchronous master device. in the example shown in figure 54 , two (or more) audio channels from the dsp core are routed to one (or more) of the asrcs and then to the serial outputs. for this example, the corresponding asrc input selector register ( address 0xf100 t o address 0xf107 ( asrc_i nputx) , bits [2:0] ( asrc_source ) ) is set to 0b010 to take the data from the dsp core, and the corresponding asrc output rate selector register ( address 0xf140 to address 0xf147 ( asrc_out_ratex ) , bits [3:0] ( asrc_rate ) ) is set to one of the following: ? 0b0001 to synchronize the asrc output dat a to sdata_out0 ? 0b0010 to synchronize the asrc output data to sdata_out1 ? 0b0011 to synchronize the asrc output data to sdata_out2 0b0100 to synchronize th e asrc output data to sdata_out3 next , the corresponding serial ou tput port data source register ( address 0xf180 to address 0xf197 (sout_sourcex), bits [2:0] ( sout_source ) ) must be set to 0b011 to receive the d ata from the asrc outputs, and bits [5:3] ( sout_asrc_select ) must be configured to select the correct asrc from wh ich to receive the output data. dsp core asrcs (8) asrc outputs (16 channels) 16 ch (2 ch 8 asrcs) 16 ch dsp to asrc (16 channels) 1 1486-057 figure 54 . example asrc routing for asyn chronous serial output from the dsp core when signals must route from the dsp core to the asrcs, use the dsp - to - asrc output cell in sigmastudio (see figure 55). in the case of the adau1450 , which has no asrcs, dat a routed to the dsp - to - asrc output cells are lost. 1 1486-058 figure 55 . location of dsp - to - asrc output cell in sigmastudio toolbox to asrc0 to asrc1 to asrc2 to asrc3 to asrc4 to asrc5 to asrc6 to asrc7 1 1486-059 figure 56 . routing of dsp - to- asrc output cells in sigmastudio to asrc inputs the asrcs can also be used to take asynchronous inputs and convert them to a different sample rate without doing any processing in the dsp core. asrcs (8) input 0 to input 15 asrc outputs (16 channels) 16 ch (2 ch 8 asrcs) 16 ch 1 1486-060 figure 57 . example asrc routing , bypassing dsp core configure t he asrc routing registers using a simple graphical interface in the sigmastudio software (see figure 59). asynchronous sample rate converter output routing t he outputs of the asrcs are always available at both the dsp core and the serial outputs. no manual routing is necessary. to route asrc output data to serial output channels, configure register 0xf180 to register 0xf197 (sout_sourcex) accordingly. for more information, see figure 58 and table 43. asrcs (8) asrc outputs (16 channels) 16 ch (2 ch 8 asrcs) 16 ch asrc to dsp (16 channels) dsp core 1 1486-062 figure 58 . asrc outputs rev. c | page 50 of 180
data sheet adau1452/adau1451/adau1450 1 1486-061 figure 59 . configuring the asrc input source and target rate in sigmastudio rev. c | page 51 of 180
adau1452/adau1451/adau1450 data sheet audio signal routing registers a n overvi ew of t he registers related to audio r outing is listed in table 43 . for more detailed information , refer to the audio signal routing registers section. table 43 . audio routing matrix registers address register description 0xf100 asrc_input0 asrc input s elector ( asrc 0 , channel 0 and channel 1) 0xf101 asrc_input1 asrc input selector ( asrc 1 , channel 2 and channel 3) 0xf102 asrc_input2 asrc input select or ( asrc 2 , channel 4 and channel 5) 0xf103 asrc_input3 asrc input selector ( asrc 3 , channel 6 and channel 7) 0xf104 asrc_input4 asrc input selector ( asrc 4 , channel 8 and channel 9) 0xf105 asrc_input5 asrc input selector ( asrc 5 , channel 10 and channel 11) 0xf106 asrc_input6 asrc input selector ( asrc 6 , channel 12 and channel 13) 0xf107 asrc_input7 asrc input selector ( asrc 7 , channel 14 and channel 15) 0xf140 asrc_out_rate0 asrc output r ate ( asrc 0 , channel 0 and channel 1) 0xf141 asrc_out_rate1 as rc output rate ( asrc 1 , channel 2 and channel 3) 0xf142 asrc_out_rate2 asrc output rate ( asrc 2 , channel 4 and channel 5) 0xf143 asrc_out_rate3 asrc output rate ( asrc 3 , channel 6 and channel 7) 0xf144 asrc_out_rate4 asrc output rate ( asrc 4 , channel 8 and channel 9) 0xf145 asrc_out_rate5 asrc output rate ( asrc 5 , channel 10 and channel 11) 0xf146 asrc_out_rate6 asrc output rate ( asrc 6 , channel 12 and channel 13) 0xf147 asrc_out_rate7 asrc output rate ( asrc 7 , channel 14 and channel 15) 0xf180 sout_ source0 source of data for serial output port (channel 0 and channel 1) 0xf181 sout_source1 source of data for serial output port (channel 2 and channel 3) 0xf182 sout_source2 source of data for serial output port (channel 4 and channel 5) 0xf183 sout_s ource3 source of data for serial output port (channel 6 and channel 7) 0xf184 sout_source4 source of data for serial output port (channel 8 and channel 9) 0xf185 sout_source5 source of data for serial output port (channel 10 and channel 11) 0xf186 sout_ source6 source of data for serial output port (channel 12 and channel 13) 0xf187 sout_source7 source of data for serial output port (channe l 14 and channel 15) 0xf188 sout_source8 source of data for serial output port (channel 16 and channel 17) 0xf189 sout_source9 source of data for serial output port (channel 18 and channel 19) 0xf18a sout_source10 source of data for serial output port (channel 20 and channel 21) 0xf18b sout_source11 source of data for serial output port (channel 22 and channel 23) 0xf18c sout_source12 source of data for serial output port (channel 24 and channel 25) 0xf18d sout_source13 source of data for serial output port (channel 26 and channel 27) 0xf18e sout_source14 source of data for serial output port (channel 28 and chann el 29) 0xf18f sout_source15 source of data for serial output port (channel 30 and channel 31) 0xf190 sout_source16 source of data for serial output port (channel 32 and channel 33) 0xf191 sout_source17 source of data for serial output port (channel 34 a nd channel 35) 0xf192 sout_source18 source of data for serial output port (channel 36 and channel 37) 0xf193 sout_source19 source of data for serial output port (channel 38 and channel 39) 0xf194 sout_source20 source of data for serial output port (chan nel 40 and channel 41) 0xf195 sout_source21 source of data for serial output port (channel 42 and channel 43) 0xf196 sout_source22 source of data for serial output port (channel 44 and channel 45) 0xf197 sout_source23 source of data for serial output p o rt (channel 46 and channel 47) 0xf1c0 spdiftx_input s/pdif transmitter data s elector rev. c | page 52 of 180
data sheet adau1452/adau1451/adau1450 serial data input/ou tput there are four serial data input pins (sdata_in3 to sdata_in0) and four serial data output pins (sdata_out3 to sdata_ out0) . each pin is capa bl e of 2 - channel, 4 - channel, or 8 - channel mode . in addition, sdata_in0, sdata_in1, sdata_out0, and sdata_out1 are capable of 16 - channel mode. the serial ports have a very flexible configuration scheme that allows for completely independent and orthogonal c onfiguration of clock pin assignment, clock waveform type, clock polarity, channel count, position of the data bits within the stream, audio word length, slave or master operation, and sample rate. a detailed description of all possible serial port setting s is included in the serial port configuration registers section . the physical serial data input and output pins are connected to functional blocks called serial ports, which deal with handling the audio data and clocks as they pass in and out of the device. table 44 describes this relationship. table 44. relationship between hardware serial data pins and serial input/output p orts serial data pin serial port sdata_in0 serial input port 0 sdata_in1 serial input port 1 sdata_in2 serial input port 2 sdata_in3 serial input port 3 sdata_out0 serial output port 0 sdata_out1 serial output port 1 sdata_out2 serial output port 2 sdata_out3 serial ou tput port 3 there are 48 channels of serial audio data inputs and 48 channels of serial audio data outputs. the 48 audio input channels and 48 audio output channels are distributed among the four serial data input pins and the four serial data output pin s. this distri - bution is described in table 45. the maximum sample rate for the serial audio data on the serial ports is 192 khz. the minimum sample rate is 6 khz. sdata_in2, sdata_in3, sdata_out2, and sdata_out3 are capable of operating in a special mode called flexible tdm mod e, which allows for custom byte addressable configuration, where the data for each channel is located in the serial data stream. f lexible tdm mode is not a standard audio interface . use it only in cases where a customized serial data format is desired. see the flexible tdm interface section for more information. serial audio data format the serial data input and output ports are designed to work wi th audio data that is encoded in a linear pulse code modulation ( pcm ) format, based on the common i 2s standard. audio data - words can be 16, 24, or 32 bits in length. the serial ports can handle tdm formats with channel counts ranging from two channels to 1 6 channels on a single data line. a lmost every aspect of the serial audio data format can be con - figured using the serial_byte_x_0 and serial_byte_x_1 registers, and every setting can be configured independently . as a result, t here are more than 70,000 val id configurations for each serial audio port . serial audio data timing diagrams because it is impractical to show timing diagrams for each possible combination, timing diagrams for the more common configu - rations are shown in figure 60 to figure 65 . explanatory text accompanies each figure. table 45. relationship between data pin, audio channels, clock pins, and tdm o ptions serial data pin channe l numbering corresponding clock pins in master mode maximum tdm channels flexible tdm mode sdata_in0 channel 0 to channel 15 bclk_in0, lrclk_in0 16 channels no sdata_in1 channel 16 to channel 31 bclk_in1, lrclk_in1 16 channels no sdata_in2 channel 32 to channel 39 bclk_in2, lrclk_in2 8 channels yes sdata_in3 channel 40 to channel 47 bclk_in3, lrclk_in3 8 channels yes sdata_out0 channel 0 to channel 15 bclk_out0, lrclk_out0 16 channels no sdata_out1 channel 16 to channel 31 bclk_out1, lrclk_out1 16 cha nnels no sdata_out2 channel 32 to channel 39 bclk_out2, lrclk_out2 8 channels yes sdata_out3 channel 40 to channel 47 bclk_out3, lrclk_out3 8 channels yes rev. c | page 53 of 180
adau1452/adau1451/adau1450 data sheet rev. c | page 54 of 180 bclk ..0 ..0 ..16 ..8 7654321 0 54321 0 9 876 ..8 ..1 0 76543210 cycle number negative polarity positive polarity lrclk 50/50, negative polarity 50/50, positive polarity pulse, negative polarity pulse, positive polarity data start of new frame 24-bit, delay by 1 24-bit, delay by 0 24-bit, delay by 8 24-bit, delay by 16* 16-bit, delay by 1 16-bit, delay by 0 16-bit, delay by 8 16-bit, delay by 16 32-bit, delay by 1* 32-bit, delay by 0 32-bit, delay by 8* 32-bit, delay by 16* end of frame midpoint of frame 64-bit clock cycles 1234567891011121314151617181920 313233343536373839 414243444546474849 40 51 52 53 54 55 56 57 58 59 50 61 62 63 64 60 21 22 23 10 23456789 101112131415 161718192021 22 23 24 25 26 27 28 29 30 11486-063 10 23456789 1011 12 13 14 1516 17 18 1920212223 10 23456789 10111213 14 15 16 1718 1920 212223 10 23456789 10 11 12 13141516 17 1819 20212223 ..0 10 23456789 1011 12131415 10 23456789 101112 13 14 15 10 23456789 101112 13 1415 10 23456789 101112131415 16171819 2021 2223 10 23456789 101112131415 161718192021 22 23 10 23456789 1011 121314151617181920 21 2223 7. . 15.. 15.. 7.. 31.. 0.. 89 101112131415 16171819 2021 22 23 10 23456789 1011 12131415 10 23456789 1011 12131415 10 23456789 1011 12131415 10 23456789 101112 13 1415 10 2 34 56 7 89 10 11 12131415 10 2 34 56 7 89 10 11 121314 15 10 1112 13 1415 16 17 18 19 20 2122 23 2425 26 27 28 2931 30 54321 0 9 876 10 1112 13 1415 16 17 18 19 2021 22 23 2425 26 27 2829 31 30 54321 0 9 876 1011 12 13 1415 16 17 18 19 2021 22 23 2425 26 27 2829 31 30 54321 9 876 1011 121314151617181920 21 22 23 2425 26 2728 2931 30 54321 0 9 876 1011 12 13 14 1516 17 1819 20 21 22 2324 25 2627 28 29 31 30 9 8 10 11 12 13 1415 16 17 18 1920 21 22 2324 25 26 2728 29 31 30 16 17 1819 20 21 22 2324 25 2627 28 29 31 30 54321 0 9 876 1011 12 13 1415 16 17 18 1920 21 22 23 2425 26 2728 29 31 30 *it is possible for the user to configure the serial ports to operate in this mode. however, it is recommended that this mode not be used because the audio data crosses the threshold between two frames, which may violate the specifications of other devices in the system. figure 60. serial audio formats; two channels, 32 bits per channel figure 60 shows timing diagrams for possible serial port con- figurations in 2-channel mode, with 32 cycles of the bit clock signal per channel, for a total of 64 bit clock cycles per frame (see the serial_byte_x_0 registers, bits[2:0] (tdm_mode) = 0b000). different bit clock polarities are illustrated in figure 60 (serial_byte_x_0, bit 7 (bclk_pol)) as well as different frame clock waveforms and polarities (serial_byte_x_0, bit 9 (lrclk_mode) and bit 8 (lrclk_pol)). excluding flexible tdm mode, there are 12 possible combinations of settings for the audio word length (serial_byte_x_0, bits[6:5] (word_len)) and msb position (serial_byte_x_0, bits[4:3] (data_fmt)), all of which are shown in figure 60.
data sheet adau1452/adau1451/adau1450 rev. c | page 55 of 180 start of new frame end of frame midpoint of frame 24-bit, delay by 1 16-bit, delay by 1 24-bit, delay by 0 24-bit, delay by 8 24-bit, delay by 16* 16-bit, delay by 0 16-bit, delay by 8 16-bit, delay by 16 32-bit, delay by 1* 32-bit, delay by 0 32-bit, delay by 8* 32-bit, delay by 16* bclk lrclk data 128-bit clock cycles 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 8 bits idle 16 bits idle 16 bits idle 16 bits idle 16 bits idle 16 bits idle 16 bits idle 16 bits idle 16 bits idle 16 bits idle 16 bits idle 16 bits idle 16 bits idle 16 bits idle 16 bits idle 16 bits idle channel 3 channel 0 channel 0 channel 0 channel 0 channel 0 channel 0 channel 0 channel 0 channel 1 channel 1 channel 1 channel 2 channel 2 channel 2 channel 2 channel 2 channel 2 channel 2 channel 2 channel 2 channel 2 channel 2 channel 2 channel 3 channel 3 channel 3 channel 3 channel 3 channel 3 channel 3 channel 3 channel 3 channel 3 channel 3 channel 3 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 0 channel 0 channel 0 channel 0 previous sample previous sample 11486-064 *it is possible for the user to configure the serial ports to operate in this mode. however, it is recommended that this mode not be used because the audio data crosses the threshold between two frames, which may violate the specifications of other devices in the system. figure 61. serial audio data formats; four channels, 32 bits per channel figure 61 shows timing diagrams for possible serial port configurations in 4-channel mode, with 32 bit clock cycles per channel, for a total of 128 bit clock cycles per frame (refer to the serial_byte_x_0 registers, bits[2:0] (tdm_mode) = 0b001). the bit clock signal is omitted from the figure. excluding flexible tdm mode, there are 12 possible combinations of settings for the audio word length (serial_byte_x_0, bits[6:5] (word_len)) and msb position (serial_byte_x_0, bits[4:3] (data_fmt)), all of which are shown in figure 61.
adau1452/adau1451/adau1450 data sheet rev. c | page 56 of 180 start of new frame end of frame midpoint of frame 24-bit, delay by 1 24-bit, delay by 0 24-bit, delay by 8 24-bit, delay by 16* 16-bit, delay by 1 16-bit, delay by 0 16-bit, delay by 8 16-bit, delay by 16 32-bit, delay by 1* 32-bit, delay by 0 32-bit, delay by 8* 32-bit, delay by 16* bclk lrclk data 256-bit clock cycles channel 0 channel 0 channel 0 channel 0 channel 0 ch7... channel 0 channel 0 channel 0 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel 2 channel 2 channel 2 channel 2 channel 3 channel 3 channel 3 channel 3 channel 4 channel 4 channel 4 channel 4 channel 5 channel 5 channel 5 channel 5 channel 2 channel 2 channel 2 channel 2 channel 3 channel 3 channel 3 channel 3 channel 4 channel 4 channel 4 channel 4 channel 5 channel 5 channel 5 channel 5 channel 6 channel 6 channel 6 channel 6 channel 6 channel 6 channel 6 channel 6 channel 6 channel 6 channel 6 channel 6 channel 5 channel 5 channel 5 channel 5 channel 4 channel 4 channel 4 channel 4 channel 3 channel 3 channel 3 channel 3 channel 2 channel 2 channel 2 channel 2 channel 1 channel 1 channel 1 channel 1 channel 0 channel 0 channel 0 channel 0 channel 7 channel 7 channel 7 channel 7... channel 7 channel 7 channel 7... channel 7... channel 7 channel 7 channel 7 channel 7 previous sample previous sample 11486-065 *it is possible for the user to configure the serial ports to operate in this mode. however, it is recommended that this mode not be used because the audio data crosses the threshold between two frames, which may violate the specifications of other devices in the system. figure 62. serial audio data formats; eight channels, 32 bits per channel figure 62 shows timing diagrams for possible serial port con- figurations in 8-channel mode, with 32 bit clock cycles per channel, for a total of 256 bit clock cycles per frame (refer to the serial_byte_x_0 registers, bi ts[2:0] (tdm_mode) = 0b010). the bit clock signal is omitted from the figure. excluding flexible tdm mode, there are 12 possible combinations of settings for the audio word length (serial_byte_x_0, bits[6:5] (word_len)) and msb position (serial_byte_x_0, bits[4:3] (data_fmt)), all of which are shown in figure 62.
data sheet adau1452/adau1451/adau1450 rev. c | page 57 of 180 start of new frame end of frame midpoint of frame 24-bit, delay by 1 16-bit, delay by 1 32-bit, delay by 1* 32-bit, delay by 0 32-bit, delay by 8* 32-bit, delay by 16* 24-bit, delay by 0 24-bit, delay by 8 24-bit, delay by 16* 16-bit, delay by 0 16-bit, delay by 8 16-bit, delay by 16 bclk lrclk data ch 0 ch 0 ch 0 ch 0 ch 0 ch 1 ch 1 ch 1 ch 1 ch 2 ch 2 ch 2 ch 2 ch 3 ch 3 ch 3 ch 3 ch 0 ch 0 ch 0 ch 0 ch 1 ch 1 ch 1 ch 1 ch 2 ch 2 ch 2 ch 2 ch 3 ch 3 ch 3 ch 3 ch 4 ch 4 ch 4 ch 4 ch 5 ch 5 ch 5 ch 5 ch 6 ch 6 ch 6 ch 6 ch 7 ch 7 ch 7 ch 7 ch 4 ch 4 ch 4 ch 4 ch 5 ch 5 ch 5 ch 5 ch 6 ch 6 ch 6 ch 6 ch 7 ch 7 ch 7 ch 7 ch 8 ch 8 ch 8 ch 8 ch 9 ch 9 ch 9 ch 9 ch 0 ch 0 ch 0 ch 1 ch 1 ch 1 ch 1 ch 2 ch 2 ch 2 ch 2 ch 3 ch 3 ch 3 ch 3 ch 4 ch 4 ch 4 ch 4 ch 5 ch 5 ch 5 ch 5 ch 6 ch 6 ch 6 ch 6 ch 7 ch 7 ch 7 ch 7 ch 8 ch 8 ch 8 ch 8 ch 9 ch 9 ch 9 ch 9 ch 10 ch 10 ch 10 ch 10 ch 8 ch 8 ch 8 ch 8 ch 9 ch 9 ch 9 ch 9 ch 10 ch 10 ch 10 ch 10 ch 10 ch 10 ch 10 ch 10 ch 11 ch 11 ch 11 ch 11 ch 11 ch 11 ch 11 ch 11 ch 11 ch 11 ch 11 ch 11 ch 12 ch 12 ch 12 ch 12 ch 12 ch 12 ch 12 ch 12 ch 12 ch 12 ch 12 ch 12 ch 13 ch 13 ch 13 ch 13 ch 13 ch 13 ch 13 ch 13 ch 13 ch 13 ch 13 ch 13 ch 14 ch 14 ch 14 ch 14 ch 14 ch 14 ch 14 ch 14 ch 14 ch 14 ch 14 ch 15 ch 15 ch 15 ch 15 ch 15... ch 15 ch 15 ch 15 ch 15 ch 15 ch 15 ch 15 ch 14 prev samp prev samp ..15 11486-066 512-bit clock cycles *it is possible for the user to configure the serial ports to operate in this mode. however, it is recommended that this mode not be used because the audio data crosses the threshold between two frames, which may violate the specifications of other devices in the system. figure 63. serial audio data formats; 16 channels, 32 bits per channel figure 63 shows some timing diagrams for possible serial port configurations in 16-channel mode, with 32 bit clock cycles per channel, for a total of 512 bit clock cycles per frame (refer to the serial_byte_x_0 registers, bits[2:0] (tdm_mode) = 0b011). the bit clock signal is omitted from the figure. excluding flexible tdm mode, there are 12 possible combinations of settings for the audio word length (serial_byte_x_0, bits[6:5] (word_len)) and msb position (serial_byte_x_0, bits[4:3] (data_fmt)), all of which are shown in figure 63.
adau1452/adau1451/adau1450 data sheet rev. c | page 58 of 180 bclk cycle number negative polarity positive polarity lrclk data 16-bit, delay by 1* 16-bit, delay by 0 16-bit, delay by 8* 16-bit, delay by 16* start of new frame end of frame midpoint of frame 1234567891011121314151617181920 313233343536373839 414243444546474849 40 51 52 53 54 55 56 57 58 59 50 61 62 63 60 21 22 23 24 25 26 27 28 29 30 64-bit clock cycles channel 1 channel 1 channel 1 channel 1 channel 2 channel 2 channel 2 channel 2 channel 3 channel 3 channel 3 channel 0 channel 0 channel 0 channel 0 previous sample previous sample 64 11486-067 *it is possible for the user to configure the serial ports to operate in this mode. however, it is recommended that this mode not be used because the audio data crosses the threshold between two frames, which may violate the specifications of other devices in the system. figure 64. serial audio data formats; four channels, 16 bits per channel figure 64 shows some timing diagrams for possible serial port configurations in 4-channel mode, with 16 bit clock cycles per channel, for a total of 64 bit clock cycles per frame (refer to the serial_byte_x_0 registers, bi ts[2:0] (tdm_mode) = 0b100). different bit clock polarities are shown (refer to the serial_ byte_x_0 registers, bit 7 (bclk_pol)). the audio word length is fixed at 16 bits (refer to the serial_byte_x_0 registers, bits[6:5] (word_len) = 0b01), and there are four possible configurations for msb position (serial_byte_x_0, bits[4:3] (data_fmt)), all of which are shown in figure 64.
data sheet adau1452/adau1451/adau1450 rev. c | page 59 of 180 bclk cycle number negative polarity positive polarity lrclk data 16-bit, delay by 1* 16-bit, delay by 0 16-bit, delay by 8* 16-bit, delay by 16* start of new frame midpoint of frame 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 31 32 21 22 23 24 25 26 27 28 29 30 32-bit clock cycles end of frame channel 0 channel 0 channel 0 channel 1 channel 1 channel 1 previous sample previous sample channel 0 11486-068 *it is possible for the user to configure the serial ports to operate in this mode. however, it is recommended that this mode not be used because the audio data crosses the threshold between two frames, which may violate the specifications of other devices in the system. figure 65. serial audio data formats; two channels, 16 bits per channel figure 65 shows some timing diagrams for possible serial port configurations in two channel mode, with 16 bit clock cycles per channel, for a total of 32 bit clock cycles per frame (refer to the serial_byte_x_0 registers, register 0xf200 to register 0xf21c, bits[2:0] (tdm_mode) = 0b101). different bit clock polarities are illustrated (serial_byte_x_0, bit 7 (bclk_pol)). the audio word length is fixed at 16 bits (serial_byte_x_0, bits[6:5] (word_len) = 0b01), and there are four possible configurations for msb position (serial_ byte_x_0, bits[4:3] (data_fmt)), all of which are shown in figure 65.
adau1452/adau1451/adau1450 data sheet serial clock domains there are four input clock domains and four output clock domains. a clock domain consists of a pair of lrclk _outx and lrclk_inx (frame clock) and bclk _outx and bclk_inx ( bit clock) pins , which are used to synchronize the transmission of audio data to and from the device. there are eight total clock domains. four of them are input domains and four of them are output domains. in master mode ( refer to the serial_byte_ x _0 register s , register 0xf200 to register 0xf21c , bits [15:13] ( lrclk_ src ) = 0b100 and bits [12:10] ( bclk_src ) = 0b100) , each clock domain corresponds to exactly one serial data pin, one frame clock pin, and one bit clock pin. any serial data input can be clocked by any input clock domains when it is configured in slave mode ( refer to the serial_byte_ x _0 register s , bits [15:13] ( lrclk_ src ), which can be set t o 0b000, 0b001, 0b010, or 0b011; and bits [12:10] ( bclk_src ), which can be set to 0b000, 0b001, 0b010, or 0b011) . any serial data output can be clocked by any out put clock domain when it is configured in slave mode (see the serial_byte_ x _0 register s , bits [15:13] ( lrclk_src ), which can be set t o 0b000, 0b001, 0b010, or 0b011; and bits [12:10] ( bclk_src ), which can be set to 0b000, 0b001, 0b010, or 0b011) . table 46. relationship between serial data pins and clock pins in master or slave mode serial data pin corresponding clock pins in master mode corresponding clock pins in slave mode sdata_in0 bclk_in0, lrclk_in0 (lrclk_in0/mp10) bclk_in0, lrclk_in0 or bclk_in1, lrclk_in1 or bclk_in2, lrclk_in2 or bclk_in3, lrclk_in3 sdata_in1 bclk_in1, lrclk_in1 (lrclk_in1/mp11) bclk_in0, lrclk_in0 or bclk_in1, lrclk_in1 or bclk_in2, lrclk_in2 or bclk_in3, lrclk_in3 sdata_in2 bclk_in2, lrclk_in2 (lr clk_in2/mp12) bclk_in0, lrclk_in0 or bclk_in1, lrclk_in1 or bclk_in2, lrclk_in2 or bclk_in3, lrclk_in3 sdata_in3 bclk_in3, lrclk_in3 (lrclk_in3/mp13) bclk_in0, lrclk_in0 or bclk_in1, lrclk_in1 or bclk_in2, lrclk_in2 or bclk_in3, lrclk_in 3 sdata_out0 bclk_out0, lrclk_out0 (lrclk_out0/mp4) bclk_out0, lrclk_out0 or bclk_out1, lrclk_out1 or bclk_out2, lrclk_out2 or bclk_out3, lrclk_out3 sdata_out1 bclk_out1, lrclk_out1 (lrclk_out1/mp5) bclk_out0, lrclk_out0 or bclk_out1, lrclk_o ut1 or bclk_out2, lrclk_out2 or bclk_out3, lrclk_out3 sdata_out2 bclk_out2, lrclk_out2 (lrclk_out2/mp8) bclk_out0, lrclk_out0 or bclk_out1, lrclk_out1 or bclk_out2, lrclk_out2 or bclk_out3, lrclk_out3 sdata_out3 bclk_out3, lrclk_out3 (lrcl k_out3/mp9) bclk_out0, lrclk_out0 or bclk_out1, lrclk_out1 or bclk_out2, lrclk_out2 or bclk_out3, lrclk_out3 rev. c | page 60 of 180
data sheet adau1452/adau1451/adau1450 serial input ports there is a one - to - one mapping between the serial input ports and the audio input channels in the dsp and the asrc i nput selectors , which is described in table 47. table 47. relationship between serial input p ort and corresponding channel numbers on the dsp and asrc i nputs serial port audio input channe ls in the dsp and asrc serial input 0 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 serial input 1 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 serial input 2 32, 33, 34, 35, 36, 37, 38, 39 serial input 3 40, 41, 42, 43, 44, 45 , 46, 47 if a serial input port is configured using the serial_byte_ x _0 register s , bits [2:0] ( tdm_mode ) for a number of channels that is less than its maximum channel count, the unused channels carry zero data. for example, if serial input 0 is set in 8 - channel (tdm8) mode, the first eight channels ( channel 0 to channel 7) carry data; and the unused channels ( channel 8 t o channel 15) carry no data. there are four options for the word length of each serial input port: 24 bit s , 16 bit s , 32 bit s , or flexible tdm. the flexible tdm option is described in the flexible tdm input section. in 32 - bit mode (see figure 66) , the 32 bits received on the serial input are mapped direct ly to a 32 - bit word in the dsp core. t o use 32 - bit mode, the special 32 - bit input cells must be used in sigmastudio. 24-bit audio sample 8-bit d at a routing m a trix 24-bit audio sample lsb 32-bit input port 32-bit seria l audio input stream 8-bit data 24-bit audio sample 8-bit data lsb msb msb ds p core 1 1486-069 audio lsb audio msb audio lsb audio msb audio lsb audio msb figure 66 . 32 - b it serial input example in 24 - bit mode (see figure 68) , the 24 - bit audio sample (in 1.23 format) is padded with eight zeros below its lsb (in 1.31 format) as it is input to the routing matrix. then, the audio data is shifted s uch that the audio sample has seven sign - extended zeros on top, one padded zero on the bottom, and 24 bits of data in the middle (8.24 format). whereas 16- bit mode is similar to 24 - bit mode, the 16 - bit audio data has 16 zeros below its lsb instead of just eight zeros (in the 24- bit case). the resulting 8.24 sample , therefore , has seven s ign - extended zeros on top, nine padded zeros on the bottom, and 16 bits of data in the middle (8.24 format). serial output ports t here is a one - to - one mapping between the serial output ports and the output audio channels in the dsp (see table 48) . table 48. relationship between serial input port and corresponding dsp output channel numbers serial input port audio output channels from the dsp serial output 0 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 , 11, 12, 13, 14, 15 serial output 1 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 serial output 2 32, 33, 34, 35, 36, 37, 38, 39 serial output 3 40, 41, 42, 43, 44, 45, 46, 47 if a serial output port is configured using the serial_by te_ x _0 register s , bits [2:0] ( tdm_mode ) , for a number of channels that is less than its maximum channel count , the unused channels are ignored. for example, if serial output port 0 is set in 8 - channel (tdm8) mode, and data is routed to it from the dsp, the first eight dsp output channels ( channel 0 through channel 7) are output on sdata_out0, but the remaining channels ( channel 8 through channel 15) are not output from the device. there are four options for the word length of each serial output port: 24 bit s , 16 bit s , 32 bit s , or flexible tdm. see the flexible tdm output section for more information . in 32 - bit mode (see figure 67) , all 32 bits from the 8.24 word in the dsp core are copied directly to the serial output. to use 32 - bit mode, the special 32 - bit output cells must be used in sigmastudio. routing ma trix 32-bit word 32-bit word 32-bit word 32-bit output port lsb msb 1 1486-071 32-bit seria l audio output stream audio lsb audio msb audio lsb audio msb audio lsb audio msb figure 67 . 32 - bit serial output example in 24 - bit mode, the top seven msbs of the 8.24 audio word in the dsp core are saturated, and the resulting 1.23 word is output from the serial port, with eight zeros padded under the lsb (see figure 69). in 16 - bit mode, the top seven msbs of the 8.24 audio word in the dsp core are saturated, and the resulting 1.23 word is then truncated to a 1.15 word by removing the eight lsbs. the resulting 1.15 word is then zero padded with 16 zeros under the lsb and output from the serial port. rev. c | page 61 of 180
adau1452/adau1451/adau1450 data sheet 1.23 audio sample 24-bit seria l audio input stream routing m a trix 1.23 audio sample lsb zeros 1.23 audio sample lsb msb sign extended zero msb ds p core lsb msb 1 1486-070 24-bit input port audio lsb audio msb audio lsb audio msb audio lsb audio msb figure 68 . 24 - bit serial input example routing m a trix 1.23 audio sample 1.23 audio sample 8 zeros audio lsb audio msb lsb msb lsb msb 24-bit output port 24-bit seria l audio output stream 24-bits 7 msbs lsb msb ds p core s a tur a ted t o 1 if output is >1 1 lsb trunc a ted s a tur a t or/ clipper +1 +1 ?1 ?1 ?128 +127.999... x: dsp core output y: serial port output 1 1486-072 audio lsb audio msb audio lsb audio msb figure 69 . 24 - b it serial output example rev. c | page 62 of 180
data sheet adau1452/adau1451/adau1450 serial port registers an overview of the registers related to the serial ports is shown in table 49 . for a more detailed description , see the serial port configuration registers section. table 49 . serial port registers address register description 0xf200 serial_byte_0_0 serial port control 0 (sdata_in0 pin ) 0xf20 1 serial_byte_0_1 serial port control 1 (sdata_in0 pin ) 0xf204 serial_byte_1_0 serial port control 0 (sdata_in1 pin ) 0xf205 serial_byte_1_1 serial port control 1 (sdata_in1 pin ) 0xf208 serial_byte_2_0 serial port control 0 (sdata_in2 pin ) 0xf209 serial _byte_2_1 serial port control 1 (sdata_in2 pin ) 0xf20c serial_byte_3_0 serial port control 0 (sdata_in3 pin ) 0xf20d serial_byte_3_1 serial port control 1 (sdata_in3 pin ) 0xf210 serial_byte_4_0 serial port control 0 (sdata_out0 pin ) 0xf211 serial_byte_4 _1 serial port control 1 (sdata_out0 pin ) 0xf214 serial_byte_5_0 serial port control 0 (sdata_out1 pin ) 0xf215 serial_byte_5_1 serial port control 1 (sdata_out1 pin ) 0xf218 serial_byte_6_0 serial port control 0 (sdata_out2 pin ) 0xf219 serial_byte_6_1 s erial port control 1 (sdata_out2 pin ) 0xf21c serial_byte_7_0 serial port control 0 (sdata_out3 pin ) 0xf21d serial_byte_7_1 serial port control 1 (sdata_out3 pin ) rev. c | page 63 of 180
adau1452/adau1451/adau1450 data sheet flexible tdm interfa ce the flexible tdm interface is available as an optional mode of o peration on the sdata_in2 and sdata_in3 serial input ports, as well as on the sdata_out2 and sdata_ out3 serial output ports . t o use flexible tdm mode, the corresponding serial ports must be set in flexible tdm mode (serial_byte_x _0 register , bits [6:5] ( wor d_len ) = 0b11 and serial_byte_x _0 register , bits [2:0] = 0b010). flexible tdm input mode requires that both sdata_in2 and sdata_in3 be configured for flexible tdm mode. likewise, flexible tdm output mode requires that both sdata_out2 and sdata_out3 pins be configured for flexible tdm mode. the flexible tdm interface provides byte addressable data place - ment in the input and output data streams on the corresponding serial data input/output pins. each data stream is configured like a standard 8 - channel tdm int erface, with a total of 256 data bits (or 32 bytes) in the span of an audio frame. because flexible tdm mode runs on two pins simultaneously, and each pin has 32 bytes of data, this means that there are a total of 64 data bytes. in flexible tdm input mode, each input channel inside the device can select its source data from any of the 64 input data bytes. in flexible tdm output mode, any serial output channel can be routed to any of the 64 output data bytes. flexible tdm input in f lexible tdm input mode, tw o 256 - bit data streams are input to the sdata_in2 and sdata_in3 pins. these 256 bits of data compose eight channels of four bytes each, for a total of 32 bytes on each pin, and a total of 64 bytes when both input pins are combined. the flexible tdm input f unctional block ro utes the desired input byte to a given byte in the serial input channels. those serial input channels are then available as normal audio data in the audio routing matrix. the data can be passed to the dsp core, the asrc inputs, or the ser ial outputs as needed. there are a total of 64 control registers (ftdm_in x ) that can be configured to set up the mapping of input data bytes to the corresponding bytes in the serial input channels. each byte in each serial input channel has a correspondin g control register, which selects the incoming data byte on the serial input pins that must be mapped to it. figure 70 shows, from left to right, the data streams entering the serial input pins, the serial input channels, and the registers ( see ftdm_in x , register 0xf300 to register 0xf33f ) that correspond to each byte in the serial input channels. flexible tdm output in fl exible tdm output mode, two 256 - bit data streams are output from the sdata_out2 and sdata_out 3 pins. these 256 bits of data compose eight channels of four bytes each, for a total of 32 bytes on each pin, and a total of 64 bytes when both input pins are combined. the flexible tdm output functional block routes the desired byte from the desired seri al output channel to a given byte in the output streams. the serial output channels originate from the audio routing matrix, which is configured using the sout_source x control registers. there are a total of 64 control registers ( see ftdm_outx , register 0x f3880 to register 0xf3bf ) that can be configured to set up the mapping of the bytes in the serial output channels and the bytes in the data streams exiting the serial output pins. each byte in the data streams being output from the serial output pins has a corresponding control register, which selects the desired byte from the desired serial output channel. figure 71 shows, from left to right, the serial output channels originating from the routing matrix, the ser ial output pins and data streams, and the control registers (ftdm_out x ) that correspond to each byte in the serial output data streams. rev. c | page 64 of 180
data sheet adau1452/adau1451/adau1450 b it s [ 31 : 24 ] b it s [ 23 : 16 ] b it s [ 15 : 8 ] b it s [ 7 : 0 ] se r i a l input chann e l 3 2 flexible tdm block ftdm_in0 se r i a l input chann e l 3 3 ftdm_in4 se r i a l input chann e l 3 4 ftdm_in8 se r i a l input chann e l 3 5 ftdm_in12 se r i a l input chann e l 3 6 ftdm_in16 se r i a l input chann e l 3 7 ftdm_in20 se r i a l input chann e l 3 8 ftdm_in24 se r i a l input chann e l 3 9 ftdm_in28 se r i a l input chann e l 4 0 ftdm_in32 se r i a l input chann e l 4 1 ftdm_in36 se r i a l input chann e l 4 2 ftdm_in40 se r i a l input chann e l 4 3 ftdm_in44 se r i a l input chann e l 4 4 ftdm_in48 se r i a l input chann e l 4 5 ftdm_in52 se r i a l input chann e l 4 6 ftdm_in56 se r i a l input chann e l 4 7 ftdm_in60 ftdm_in1 ftdm_in5 ftdm_in9 ftdm_in13 ftdm_in17 ftdm_in21 ftdm_in25 ftdm_in28 ftdm_in33 ftdm_in37 ftdm_in41 ftdm_in45 ftdm_in49 ftdm_in53 ftdm_in57 ftdm_in2 ftdm_in6 ftdm_in10 ftdm_in14 ftdm_in18 ftdm_in22 ftdm_in26 ftdm_in30 ftdm_in34 ftdm_in38 ftdm_in42 ftdm_in46 ftdm_in50 ftdm_in54 ftdm_in58 ftdm_in3 ftdm_in7 ftdm_in11 ftdm_in15 ftdm_in19 ftdm_in23 ftdm_in27 ftdm_in31 ftdm_in35 ftdm_in39 ftdm_in43 ftdm_in47 ftdm_in51 ftdm_in55 ftdm_in59 ftdm_in61 ftdm_in62 ftdm_in63 sdata_in2 channel 7 0 1 2 3 channel 6 0 1 2 3 channel 5 0 1 2 3 channel 4 0 1 2 3 channel 3 0 1 2 3 channel 2 0 1 2 3 channel 1 0 1 2 3 channel 0 0 1 2 3 sdata_in3 channel 7 0 1 2 3 channel 6 0 1 2 3 channel 5 0 1 2 3 channel 4 0 1 2 3 channel 3 0 1 2 3 channel 2 0 1 2 3 channel 1 0 1 2 3 channel 0 0 1 2 3 1 1486-073 figure 70 . flexible tdm input mapping rev. c | page 65 of 180
adau1452/adau1451/adau1450 data sheet bits [31:24] bits [23:16] bits [15:8] bits [7:0] serial output channel 32 0 1 2 3 serial output channel 33 0 1 2 3 serial output channel 34 0 1 2 3 serial output channel 35 0 1 2 3 serial output channel 36 0 1 2 3 serial output channel 37 0 1 2 3 serial output channel 38 0 1 2 3 serial output channel 39 0 1 2 3 serial output channel 40 0 1 2 3 serial output channel 41 0 1 2 3 serial output channel 42 0 1 2 3 serial output channel 43 0 1 2 3 serial output channel 44 0 1 2 3 serial output channel 45 0 1 2 3 serial output channel 46 0 1 2 3 serial output channel 47 0 1 2 3 tdm8 channel byte ft d m _ o u t 0 ft d m _ o u t 1 ft d m _ o u t 2 ft d m _ o u t 3 ft d m _ o u t 4 ft d m _ o u t 5 ft d m _ o u t 6 ft d m _ o u t 7 ft d m _ o u t 8 ft d m _ o u t 9 ft d m _ o u t 1 0 ft d m _ o u t 1 1 ft d m _ o u t 1 2 ft d m _ o u t 1 3 ft d m _ o u t 1 4 ft d m _ o u t 1 5 ft d m _ o u t 1 6 ft d m _ o u t 1 7 ft d m _ o u t 1 8 ft d m _ o u t 1 9 ft d m _ o u t 2 0 ft d m _ o u t 2 1 ft d m _ o u t 2 2 ft d m _ o u t 2 3 ft d m _ o u t 2 4 ft d m _ o u t 2 5 ft d m _ o u t 2 6 ft d m _ o u t 2 7 ft d m _ o u t 2 8 ft d m _ o u t 2 9 ft d m _ o u t 3 0 ft d m _ o u t 3 1 tdm8 channel byte ft d m _ o u t 3 2 ft d m _ o u t 3 3 ft d m _ o u t 3 4 ft d m _ o u t 3 5 ft d m _ o u t 3 6 ft d m _ o u t 3 7 ft d m _ o u t 3 8 ft d m _ o u t 3 9 ft d m _ o u t 4 0 ft d m _ o u t 4 1 ft d m _ o u t 4 2 ft d m _ o u t 4 3 ft d m _ o u t 4 4 ft d m _ o u t 4 5 ft d m _ o u t 4 6 ft d m _ o u t 4 7 ft d m _ o u t 4 8 ft d m _ o u t 4 9 ft d m _ o u t 5 0 ft d m _ o u t 5 1 ft d m _ o u t 5 2 ft d m _ o u t 5 3 ft d m _ o u t 5 4 ft d m _ o u t 5 5 ft d m _ o u t 5 6 ft d m _ o u t 5 7 ft d m _ o u t 5 8 ft d m _ o u t 5 9 ft d m _ o u t 6 0 ft d m _ o u t 6 1 ft d m _ o u t 6 2 ft d m _ o u t 6 3 channel 7 channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 2 channel 3 channel 4 channel 5 channel 6 s d a t a _ o u t 3 s d a t a _ o u t 2 flexible tdm block channel 0 channel 1 1 1486-074 figure 71 . flexible tdm ou tput mapping rev. c | page 66 of 180
data sheet adau1452/adau1451/adau1450 flexible tdm registers a n overview o f the registers related to the f lexible tdm i nterface is shown in table 50 . for a more detailed description, see the fle xible tdm interface registers section. table 50 . flexible tdm registers address register description 0xf300 ftdm_in0 ftdm mapping for the serial inputs (channel 32, bits [31:24]) 0xf301 ftdm_in1 ftdm mapping for the serial inputs (channel 32, bits [23:16]) 0xf302 ftdm_in2 ftdm mapping for the serial inputs (channel 32, bits [15:8]) 0xf303 ftdm_in3 ftdm mapping for the serial inputs (channel 32, bits [7:0]) 0xf304 ftdm_in4 ftdm mapping for the serial inputs (channel 33, bits [31:24]) 0xf305 ftdm_in5 ftdm mapping for the serial inputs (channel 33, bits [23:16]) 0xf306 ftdm_in6 ftdm mapping for the serial inputs (channel 33, bits [15:8]) 0xf307 ftdm_in7 ftdm mapping for the serial inputs channel 33, bits[ 7:0]) 0xf308 ftdm_in8 ftdm map ping for the serial inputs (channel 34, bits [31:24]) 0xf309 ftdm_in9 ftdm mapping for the serial inputs (channel 34, bits [23:16]) 0xf30a ftdm_in10 ftdm mapping for the serial inputs (channel 34, bits [15:8]) 0xf30b ftdm_in11 ftdm mapping for the serial i nputs (channel 34, bits [7:0]) 0xf30c ftdm_in12 ftdm mapping for the serial inputs (channel 35, bits [31:24]) 0xf30d ftdm_in13 ftdm mapping for the serial inputs (channel 35, bits [23:16]) 0xf30e ftdm_in14 ftdm mapping for the serial inputs (channel 35, bi ts [15:8]) 0xf30f ftdm_in15 ftdm mapping for the serial inputs (channel 35, bits [7:0]) 0xf310 ftdm_in16 ftdm mapping for the serial inputs (channel 36, bits [31:24]) 0xf311 ftdm_in17 ftdm mapping for the serial inputs (channel 36, bits [23:16]) 0xf312 ftd m_in18 ftdm mapping for the serial inputs (channel 36, bits [15:8]) 0xf313 ftdm_in19 ftdm mapping for the serial inputs (channel 36, bits [7:0]) 0xf314 ftdm_in20 ftdm mapping for the serial inputs (channel 37, bits [31:24]) 0xf315 ftdm_in21 ftdm mapping fo r the serial inputs (channel 37, bits [23:16]) 0xf316 ftdm_in22 ftdm mapping for the serial inputs (channel 37, b its [15:8]) 0xf317 ftdm_in23 ftdm mapping for the serial inputs (channel 37, bits [7:0]) 0xf318 ftdm_in24 ftdm mapping for the serial inputs (c hannel 38, bits [31:24]) 0xf319 ftdm_in25 ftdm mapping for the serial inputs (channel 38, bits [23:16]) 0xf31a ftdm_in26 ftdm mapping for the serial inputs (channel 38, bits [15:8]) 0xf31b ftdm_in27 ftdm mapping for the serial inputs (channel 38, bits [7:0] ) 0xf31c ftdm_in28 ftdm mapping for the serial inputs (channel 39, bits [31:24]) 0xf31d ftdm_in29 ftdm mapping for the serial inputs (channel 39, bits [23:16]) 0xf31e ftdm_in30 ftdm mapping for the serial inputs (channel 39, bits [15:8]) 0xf31f ftdm_in31 ftdm mapping for the serial inputs (channel 39, bits [7:0]) 0xf320 ftdm_in32 ftdm mapping for the serial inputs (channel 40, bits [31:24]) 0xf321 ftdm_in33 ftdm mapping for the serial inputs (channel 40, bits [23:16]) 0xf322 ftdm_in34 ftdm mapping for the serial inputs (channel 40, bits [15:8]) 0xf323 ftdm_in35 ftdm mapping for the serial inputs (channel 40, bits [7:0]) 0xf324 ftdm_in36 ftdm mapping for the serial inputs (channel 41, bits [31:24]) 0xf325 ftdm_in37 ftdm mapping for the serial inputs (channel 41, bits [23:16]) 0xf326 ftdm_in38 ftdm mapping for the serial inputs (channel 41, bits [15:8]) 0xf327 ftdm_in39 ftdm mapping for the serial inputs (channel 41, bits [7:0]) 0xf328 ftdm_in40 ftdm mapping for the serial inputs (channel 42, bits [31:24]) 0xf 329 ftdm_in41 ftdm mapping for the serial inputs (channel 42, bits [23:16]) 0xf32a ftdm_in42 ftdm mapping for the serial inputs (channel 42, bits [15:8]) 0xf32b ftdm_in43 ftdm mapping for the serial inputs (channel 42, bits [7:0]) 0xf32c ftdm_in44 ftdm map ping for the serial inputs (channel 43, bits [31:24]) 0xf32d ftdm_in45 ftdm mapping for the serial inputs (channel 43, bits [23:16]) 0xf32e ftdm_in46 ftdm mapping for the serial inputs (channel 43, bits [15:8]) 0xf32f ftdm_in47 ftdm mapping for the serial inputs (channel 43, bits [7:0]) rev. c | page 67 of 180
adau1452/adau1451/adau1450 data sheet address register description 0xf330 ftdm_in48 ftdm mapping for the serial inputs (ch annel 44, bits [31:24]) 0xf331 ftdm_in49 ftdm mapping for the serial inputs (channel 44, bits [23:16]) 0xf332 ftdm_in50 ftdm mapping for the serial inputs (channel 44, b its [15:8]) 0xf333 ftdm_in51 ftdm mapping for the serial inputs (channel 44, bits [7:0]) 0xf334 ftdm_in52 ftdm mapping for the serial inputs (channel 45, bits [31:24]) 0xf335 ftdm_in53 ftdm mapping for the serial inputs (channel 45, bits [23:16]) 0xf336 ft dm_in54 ftdm mapping for the serial inputs (channel 45, bits [15:8]) 0xf337 ftdm_in55 ftdm mapping for the serial inputs (channel 45, bits [7:0]) 0xf338 ftdm_in56 ftdm mapping for the serial inputs (channel 46, bits [31:24]) 0xf339 ftdm_in57 ftdm mapping f or the serial inputs (channel 46, bits [23:16]) 0xf33a ftdm_in58 ftdm mapping for the serial inputs (channel 46, bits [15:8]) 0xf33b ftdm_in59 ftdm mapping for the serial inputs (channel 46, bits [7:0]) 0xf33c ftdm_in60 ftdm mapping for the serial inputs ( channel 47, bits [31:24]) 0xf33d ftdm_in61 ftdm mapping for the serial inputs (channel 47, bits [23:16]) 0xf33e ftdm_in62 ftdm mapping for the serial inputs (channel 47, bits [15:8]) 0xf33f ftdm_in63 ftdm mapping for the serial inputs (channel 47, bits [7:0 ]) 0xf380 ftdm_out0 ftdm mapping for the serial outputs (port 2, channel 0, bits [31:24]) 0xf381 ftdm_out1 ftdm mapping for the serial outputs (port 2, channel 0, bits [23:16]) 0xf382 ftdm_out2 ftdm mapping for the serial outputs (port 2, channel 0, bits [ 15:8]) 0xf383 ftdm_out3 ftdm mapping for the serial outputs (port 2, channel 0, bits [7:0]) 0xf384 ftdm_out4 ftdm mapping for the serial outputs (port 2, channel 1, bits [31:24]) 0xf385 ftdm_out5 ftdm mapping for the serial outputs (port 2, channel 1, bit s [23:16]) 0xf386 ftdm_out6 ftdm mapping for the serial outputs (port 2, channel 1, bits [15:8]) 0xf387 ftdm_out7 ftdm mapping for the serial outputs (port 2, channel 1, bits [7:0]) 0xf388 ftdm_out8 ftdm mapping for the serial outputs (port 2, channel 2, b its [31:24]) 0xf389 ftdm_out9 ftdm mapping for the serial outputs (port 2, channel 2, bits [23:16]) 0xf38a ftdm_out10 ftdm mapping for the serial outputs (port 2, channel 2, bits [15:8]) 0xf38b ftdm_out11 ftdm mapping for the serial outputs (port 2, channe l 2, bits [7:0]) 0xf38c ftdm_out12 ftdm mapping for the serial outputs (port 2, channel 3, bits [31:24]) 0xf38d ftdm_out13 ftdm mapping for the serial outputs (port 2, channel 3, bits [23:16]) 0xf38e ftdm_out14 ftdm mapping for the serial outputs (port 2, channel 3, bits [15:8]) 0xf38f ftdm_out15 ftdm mapping for the serial outputs (port 2, channel 3, bits [7:0]) 0xf390 ftdm_out16 ftdm mapping for the serial outputs (port 2, channel 4, bits [31:24]) 0xf391 ftdm_out17 ftdm mapping for the serial outputs (por t 2, channel 4, bits [23:16]) 0xf392 ftdm_out18 ftdm mapping for the serial outputs (port 2, channel 4, bi ts [15:8]) 0xf393 ftdm_out19 ftdm mapping for the serial outputs (port 2, channel 4, bits [7:0]) 0xf394 ftdm_out20 ftdm mapping for the serial outputs (port 2, channel 5, bits [31:24]) 0xf395 ftdm_out21 ftdm mapping for the serial outputs (port 2, cha nnel 5, bits [23:16]) 0xf396 ftdm_out22 ftdm mapping for the serial outputs (port 2, channel 5, bits [15:8]) 0xf397 ftdm_out23 ftdm mapping for the serial outputs (port 2, channel 5, bits [7:0]) 0xf398 ftdm_out24 ftdm mapping for the serial outputs ( port 2, channel 6, bits [31:24]) 0xf399 ftdm_out25 ftdm mapping for the serial outputs (port 2, channel 6, bits [23:16]) 0xf39a ftdm_out26 ftdm mapping for the s erial outputs (port 2, channel 6, bits [15:8]) 0xf39b ftdm_out27 ftdm mapping for the serial outputs (port 2, channel 6, bits [7:0]) 0xf39c ftdm_out28 ftdm mapping for the serial outputs (port 2, channel 7, bits [31:24]) 0xf39d ftdm_out29 ftdm mapping for the serial outputs (port 2, channel 7, bits [23:16]) 0xf39e ftdm_out30 ftdm mapping for the serial outputs (port 2, channel 7, bits [15:8]) 0xf39f ftdm_out31 ftdm mapping for the serial outputs (port 2, channel 7, bits [7:0]) 0xf3a0 ftdm_out32 ftdm mapping for the serial outputs (port 3, channel 0, bits [31:24]) 0xf3a1 ftdm_out33 ftdm mapping for the serial outputs (port 3, channel 0, bits [23:16]) 0xf3a2 ftdm_out34 ftdm mapping for the serial outputs (port 3, channel 0, bits [15:8]) 0xf3a3 ftdm_out35 ftdm mapping for the serial outputs (port 3, channel 0, bits [7:0]) 0xf3a4 ftdm_out36 ftdm mapping for the serial outputs (port 3, channel 1, bits [31:24]) 0xf3a5 ftdm_out37 ftdm mapping for the serial outputs (port 3, channel 1, bits [23:16]) rev. c | page 68 of 180
data sheet adau1452/adau1451/adau1450 rev. c | page 69 of 180 address register description 0xf3a6 ftdm_out38 ftdm mapping for the serial outputs (port 3, channel 1, bits[15:8]) 0xf3a7 ftdm_out39 ftdm mapping for the serial outputs (port 3, channel 1, bits[7:0]) 0xf3a8 ftdm_out40 ftdm mapping for the serial outputs (port 3, channel 2, bits[31:24]) 0xf3a9 ftdm_out41 ftdm mapping for the serial outputs (port 3, channel 2, bits[23:16]) 0xf3aa ftdm_out42 ftdm mapping for the serial outputs (port 3, channel 2, bits[15:8]) 0xf3ab ftdm_out43 ftdm mapping for the serial outputs (port 3, channel 2, bits[7:0]) 0xf3ac ftdm_out44 ftdm mapping for the serial outputs (port 3, channel 3, bits[31:24]) 0xf3ad ftdm_out45 ftdm mapping for the serial outputs (port 3, channel 3, bits[23:16]) 0xf3ae ftdm_out46 ftdm mapping for the serial outputs (port 3, channel 3, bits[15:8]) 0xf3af ftdm_out47 ftdm mapping for the serial outputs (port 3, channel 3, bits[7:0]) 0xf3b0 ftdm_out48 ftdm mapping for the serial outputs (port 3, channel 4, bits[31:24]) 0xf3b1 ftdm_out49 ftdm mapping for the serial outputs (port 3, channel 4, bits[23:16]) 0xf3b2 ftdm_out50 ftdm mapping for the serial outputs (port 3, channel 4, bits[15:8]) 0xf3b3 ftdm_out51 ftdm mapping for the serial outputs (port 3, channel 4, bits[7:0]) 0xf3b4 ftdm_out52 ftdm mapping for the serial outputs (port 3, channel 5, bits[31:24]) 0xf3b5 ftdm_out53 ftdm mapping for the serial outputs (port 3, channel 5, bits[23:16]) 0xf3b6 ftdm_out54 ftdm mapping for the serial outputs (port 3, channel 5, bits[15:8]) 0xf3b7 ftdm_out55 ftdm mapping for the serial outputs (port 3, channel 5, bits[7:0]) 0xf3b8 ftdm_out56 ftdm mapping for the serial outputs (port 3, channel 6, bits[31:24]) 0xf3b9 ftdm_out57 ftdm mapping for the serial outputs (port 3, channel 6, bits[23:16]) 0xf3ba ftdm_out58 ftdm mapping for the serial outputs (port 3, channel 6, bits[15:8]) 0xf3bb ftdm_out59 ftdm mapping for the serial outputs (port 3, channel 6, bits[7:0]) 0xf3bc ftdm_out60 ftdm mapping for the serial outputs (port 3, channel 7, bits[31:24]) 0xf3bd ftdm_out61 ftdm mapping for the serial outputs (port 3, channel 7, bits[23:16]) 0xf3be ftdm_out62 ftdm mapping for the serial outputs (port 3, channel 7, bits[15:8]) 0xf3bf ftdm_out63 ftdm mapping for the serial outputs (port 3, channel 7, bits[7:0]) asynchronous sample rate converters sixteen channels of integrated asynchronous sample rate converters are available in the adau1452 and adau1451 . these sample rate converters are capable of receiving audio data input signals, along with their corresponding clocks, and resynchronizing the data stream to an arbitrary target sample rate. the sample rate converters use some filtering to accomplish this task; therefore, the data output from the sample rate converter is not a bit- accurate representation of the data input. the adau1450 has no asrcs, so any data routed to the asrcs using the audio routing matrix or dsp core are lost. the 16 channels of sample rate converters are grouped into eight stereo sets. these eight stereo sample rate converters are indivi- dually configurable and are referred to as asrc 0 through asrc 7. channel 0 and channel 1 belong to asrc 0, channel 2 and channel 3 belong to asrc 1, channel 4 and channel 5 belong to asrc 2, channel 6 and channel 7 belong to asrc 3, channel 8 and channel 9 belong to asrc 4, channel 10 and channel 11 belong to asrc 5, channel 12 and channel 13 belong to asrc 6, and channel 14 and channel 15 belong to asrc 7. audio is routed to the sample rate converters using the asrc_inputx registers, and the target sample rate of each asrc is configured using the asrc_out_ratex registers. a complete description of audio routing is included in the audio signal routing section. asynchronous sample rate converter group delay the group delay of the sample rate converter is dependent on the input and output sampling frequencies as described in the following equations: for f s_out > f s_in , insins ff gds _ _ 3216 ?? for f s_out < f s_in , ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? outs ins ins ins f f ff gds _ _ _ _ 3216 where gds is the group delay in seconds.
adau1452/adau1451/adau1450 data sheet asrc lock each asrc monitors the incoming signal and attempts to lock on to the clock and data signals. when a valid signal is detected and several consecutive valid samples are received , and there is a valid output target sample rate , the corresponding bit in register 0xf580 ( asrc_lock ) signifies that the asrc has successfully locked to the in coming signal. asrc muting the asrc outputs can be manually muted at any time using the corresponding bits in register 0xf581 ( asrc_mute ) . however, for creating a smooth volume ramp when muting audio signals, more options are available in the dsp core; the refore, in most cases, using the dsp program to manually mute signals is preferable to using register 0xf581. asynchronous sample rate converters registers a n overview o f the registers related to the asrcs is shown in table 51 . for a more detailed description, refer to the asrc status and control registers section. table 51 . asynchronous sample rate converters registers address register descriptio n 0xf580 asrc_lock asrc lock status 0xf581 asrc_mute asrc m ute 0xf582 asrc0_ratio asrc ratio ( asrc 0 , channel 0 and channel 1) 0xf583 asrc1_ratio asrc ratio ( asrc 1 , channel 2 and channel 3) 0xf584 asrc2_ratio asrc ratio ( asrc 2 , channel 4 and channel 5) 0xf585 asrc3_ratio asrc ratio ( asrc 3 , channel 6 and channel 7) 0xf586 asrc4_ratio asrc ratio ( asrc 4 , channel 8 and channel 9) 0xf587 asrc5_ratio asrc r a tio ( asrc 5 , channel 10 and channel 11) 0xf588 asrc6_ratio asrc ratio ( asrc 6 , channel 12 and channel 13) 0xf589 asrc7_ratio asrc ratio ( asrc 7 , channel 14 and channel 15) s/pdif interface for easy interfacing on the system level, wire the o n - chip s/pdif receiver and transmitter data ports directly to other s/pdif - compatible equipment. the s/pdi f receiver consists of two audio channels input on one hardware pin (spdifi n ). the clock signal is embedded in the data using biphase mark code. the s/pdif transmitter consists of two audio channels output on one hardware pin (spdifo ut ). the clock signal i s embedded in the data using biphase mark code. the s/pdif input and output word lengths can be independently set to 16, 20, or 24 bits. the s/pdif interface meets the s/pdif consumer performance specification. it does not meet the aes3 professional specif i - cation. the adau1450 does not include s/pdif interfaces, so its spdifin and spdifout pins are nonf unctional and should remain disconnected. s/pdif receiver the s/pdif input port is designed to accept both ttl and bipolar signals, provided there is an ac coupling capacitor on the input pin of the chip. because the s/pdif input data is most likely asynch ronous to the dsp core, it must be routed through an asrc. the s/pdif receiver works at a wide range of sampling frequencies between 18 khz and 96 khz. the s/pdif receiver input is a comparator that is centered at iovdd/2 and requires an input signal level of at least 200 mv p - p to operate properly. in addition to audio data, s/pdif streams contain user data, channel status, validity bit, virtual lrclk, and block start infor - mation. the receiver decodes audio data and sends it to the corresponding registers in the control register map, where the information can be read over the i 2 c or spi slave port. for improved jitter performance, t he s/pdif clock recovery implementation is completely digital. the s/pdif ports are designed to meet the following aes and ebu specifications: a jitter of 0.25 ui p - p at 8 khz and above, a jitter of 10 ui p - p below 200 hz, and a minimum signal voltage of 200 mv. s/pdif transmitter the s/pdif transmitter outputs two channels of audio data directly from the dsp core at the core rat e. the extra nonaudio data bits on the transmitted signal can be copied directly from the s/pdif receiver or programmed manually, using the corresponding registe rs in the control register map. rev. c | page 70 of 180
data sheet adau1452/adau1451/adau1450 auxiliary output mode the received data on the s/pdif receiver can be converted to a tdm8 stream, bypass the sigmadsp core, and be output directly on a serial data output pin. this mode of operation is called auxiliary output mode. configure t his mode using r egister 0xf608 ( spdif_aux_en ) . the tdm8 output from the s/p dif receiver regroups the recovered data in a tdm - like format, as shown in table 52. the s/pdif receiver, when operating in auxiliary output mode, also recovers the embedded bclk_outx and lrclk_outx signals in th e s/pdif stream and outputs them on the corre - sponding bclk_outx and lrclk_outx pins in master mode when register 0xf608 (spdif_aux_en), bits[3:0] (tdmout), are configured to enable auxiliary output mode. the selected bclk_outx signal has a frequency of 25 6 the recovered sample rate, and the lrc lk _outx signal is a 50- 50 duty cycle square wave that has the same frequency as the audio sample rate (see table 130). table 52 . s/pdif auxiliary ou tput mode, tdm8 data format tdm8 channel description of data format 0 8 zero bits followed by 24 audio bits, recovered from the left audio channel of the s/pdif stream 1 28 zero bits followed by the left parity bit, left validity bit, left user data, and left channel status 2 30 zero bits followed by the compression type bit (0b0 = ac3, 0b1 = d ts) and the audio type bit (0 = pcm, 1 = compressed) 3 no data 4 8 zero bits followed by 24 audio bits, recovered from the right audio channel of the s/pdif stre am 5 28 zero bits followed by the right parity bit, right validity bit, right user data, and right channel status 6 no data 7 31 zero bits followed by the block start signal s/pdif interface registers a n overview of the r egisters related to the s/pdif i nterface is shown in table 53 . for a more detailed description, refer to the s/pdif interface registers section . table 53 . s/pdif interface r egisters address register description 0xf600 spdif_lock_det s/pdif receiver lock bit detection 0xf601 spdif_rx_ctrl s/pdif receiver control 0xf602 spdif_rx_decode decoded signals from the s/pdif receiver 0xf603 spdif_rx_comprmode compression mode from the s/pdif receiver 0xf604 spdif_restart automatically r esume s/pdif receiver audio input 0xf605 spdif_loss_of_lock s/pdif receiver loss of lock detection 0xf608 spdif_aux_en s/pdif receiver auxiliary outputs enable 0xf60f spdif_rx_auxbit_ready s/pdif receiver auxiliary bits ready flag 0xf610 to 0xf61b spdif_rx_cs_left_x s/pdif receiver channel status bits (left) 0xf620 to 0xf62b spdif_rx_cs_right_x s/pdif receiver channel status bits (right) 0xf630 to 0xf63b spdif_rx_ud_left_x s/pdif receiver user d ata bits (left) 0xf640 to 0xf64b spdif_rx_ud_right_x s/pdif receiver user data bits (right) 0xf650 to 0xf65b spdif_rx_vb_left_x s/pdif receiver validity bits (left) 0xf660 to 0xf66b spdif_rx_vb_right_x s/pdif receiver validity bits (right) 0xf670 to 0x f67b spdif_rx_pb_left_x s/pdif receiver parity bits (left) 0xf680 to 0xf68b spdif_rx_pb_right_x s/pdif receiver parity bits (right) 0xf690 spdif_tx_en s/pdif transmitter enable 0xf691 spdif_tx_ctrl s/pdif transmitter control 0xf69f spdif_tx_auxbit_sour ce s/pdif transmitter auxiliary bits source select 0xf6a0 to 0xf6ab spdif_tx _cs_left_x s/pdif transmitter channel status bits (left) 0xf6b0 to 0xf6bb spdif_tx_cs_right_x s/pdif transmitter channel status bits (right) 0xf6c0 to 0xf6cb spdif_tx_ud_left_x s/pdif transmitter user data bits (left) 0xf6d0 to 0xf6db spdif_tx_ud_right_ x s/pdif transmitter user data bits (right) 0xf6e0 to 0xf6eb spdif_tx_vb_left_x s/pdif transmitter validity bits (left) 0xf6f0 to 0xf6fb spdif_tx_vb_right_x s/pdif transmitter v alidity bits (right) 0xf700 to 0xf70b spdif_tx_pb_left_x s/pdif transmitter parity bits (left) 0xf710 to 0xf71b spdif_tx_pb_right_x s/pdif transmitter parity bits (right) rev. c | page 71 of 180
adau1452/adau1451/adau1450 data sheet digital pdm microphone interface up to four pulse density modulation (pdm ) micr ophones can be connected as audio inputs. each pair of microphon es can share a single data line; therefore , using four pdm microphones requires two gpio pins. any multipurpose pin can be used as a microphone data input , with up to two microphones conn e cted to each pin. this configuration is set up using the corresponding mpx_mode and dmic_ctrlx registers. a bit clock pin from one of the serial input clock domains (bclk _inx ) or one of the serial output clock domains (bclk_ outx) must be a master clock source , and its output signal must be connected to the pdm microphones to provide them with a clock. pdm microphones , such as the admp522 from invensense , typically require a bit clock frequen cy in the range of 1 mhz to 3.3 mhz, corresponding to audi o sample rat es of 15.625 khz to 51.5625 khz. t his means that the serial port corresponding to the bclk_inx pin or bclk_outx pin driving the pdm microphones should operate in 2 - channel m ode at a sample rate between 16 khz and 48 khz. pdm microphone inputs are automatic ally routed through deci - mation filters and then are available for use at the dsp core, the asrcs , and the serial output ports. figure 72 shows an example circuit with two admp522 pdm output mems microphones con nected to the adau1452 . any of the bclk_in x pins or bclk_outx pins can be used to provide a clock sign al to the microphones, and the data output of the microphones can be connected to any mp x pin that has been configured as a pdm microphone data input. bclk_inx or bclk_outx adau1452/ adau1451/ adau1450 gnd mpx admp522 iovdd gnd l/r select v dd clk data admp522 gnd l/r select v dd clk data 0.1f 0.1f 1.8v to 3.3v 1 1486-075 figure 72 . example stereo pdm microphone input circuit digital pdm microphone interface registers a n overview of the registers related to the digital microphone interface is shown in table 54 . for a more detailed description, see the digital pdm m icrophone control register . table 54 . digital pdm microphone interface registers address register description 0xf560 dmic_ctrl0 digital pdm m icrophone control (channel 0 and channel 1) 0xf561 dmic_ctrl1 digital pdm microphon e control (channel 2 and channel 3) rev. c | page 72 of 180
data sheet adau1452/adau1451/adau1450 multipurpose pins a total of 14 pins are available for use as general - purpose input s or output s (gpio) that are multiplexed with other functions, such as clock inputs/outputs. because these pins have multiple function s, they are referred to as multipurpose pins, or mp x pins. multipurpose pins can be configured in several modes using the mp x _mode registers : ? hardware input from pin ? software input (written via i 2 c or spi slave control port) ? hardware output with internal p ull - up ? hardware output without internal pull - up ? pdm microphone data input ? flag output from panic manager ? slave select line for master spi port when configured in hardware input mode, a debounce circuit is available to avoid data glitches. when operating in gpio mode, pin status is updated once per sample. this means that the state of a gpio (mpx pin ) cannot change more than once in a sample period. general - purpose inputs to the dsp core when a multipurpose pin is configured as a general - purpose input, its v alue can be used as a control logic signal in the dsp program, which is configured using sigmastudio. figure 73 shows the location of the general - purpose input cell within the sigmastudio toolbox. the 14 availabl e general - purpose inputs in sigmastudio map to the corresponding 14 multipurpose pins, but their data is valid only if the corresponding multipurpose pin has been configured as an input using the mpx_mode registers. figure 75 shows all of the general - purpose inputs as they appear in the sigmastudio signal flow. 1 1486-076 figure 73 . general - purpose input in the sigmastudio toolbox general - purpose outputs from the dsp core when a multipurpose pin is configured as a general - purpose out - put, a boolean value is output from the dsp program to the corresponding multipurpose pin. figure 74 sh ows the location of the general - purpose input cell within the sigmastudi o toolbox. 1 1486-078 figure 74 . general - purpose output in the sigmastudio toolbox 1 1486-077 figure 75 . complete set of general - purpose inputs in sigmastudio rev. c | page 73 of 180
adau1452/adau1451/adau1450 data sheet the 14 available general - purpose outputs in sigmastudio map to the corresponding 14 multipurpose pins, but their data is output to the pin only if the corresponding multipurpose pin is configured as an output using the mpx_mode registers. figure 76 shows all of the general - purpose inputs as they appear in the sigmastudio signal flow. 1 1486-079 figure 76 . complete set of general - purpose outputs in sigmastudio rev. c | page 74 of 180
data sheet adau1452/adau1451/adau1450 multipurpose pin registers a n overview of the registers related to gpio is shown in table 55 . for a more detailed description, refer to the multipurpose pin configuration registers section. table 55 . multipurpose pins registers address registe r description 0xf510 mp0_mode multipurpose pin mode (ss_m/mp0) 0xf511 mp1_mode multipurpose pin mode (mosi_m/mp1) 0xf512 mp2_mode multipurpose pin mode (scl_m/sclk_m/mp2) 0xf513 mp3_mode multipurpose pin mode (sda_m/ miso_m/mp3) 0xf514 mp4_mode multipu rpose pin mode (lrclk_out0/mp4) 0xf515 mp5_mode multipurpose pin mode (lrclk_out1/mp5) 0xf516 mp6_mode multipurpose pin mode (mp6) 0xf517 mp7_mode multipurpose pin mode (mp7) 0xf518 mp8_mode multipurpose pin mode (lrclk_out2/mp8) 0xf519 mp9_mode multi purpose pin mode (lrclk_out3/mp9) 0xf51a mp10_mode multipurpose pin mode (lrclk_in0/mp10) 0xf51b mp11_mode multipurpose pin mode (lrclk_in1/mp11) 0xf51c mp12_mode multipurpose pin mode (lrclk_in2/mp12) 0xf51d mp13_mode multipurpose pin mode (lrclk_in3/ mp13) 0xf520 mp0_write multipurpose pin write value (ss_m/mp0) 0xf521 mp1_write multipurpose pin write value (mosi_m/mp1) 0xf522 mp2_write multipurpose pin write value (scl_m/sclk_m/mp2) 0xf523 mp3_write multipurpose pin write value (sda_m/miso_m/mp3) 0xf524 mp4_write multipurpose pin write value (lrclk_out0/mp4) 0xf525 mp5_write multipurpose pin write value (lrclk_out1/mp5) 0xf526 mp6_write multipurpose pin write value (mp6) 0xf527 mp7_write multipurpose pin write value (mp7) 0xf528 mp8_write mult ipurpose pin write value (lrclk_out2/mp8) 0xf529 mp9_write multipurpose pin write value (lrclk_out3/mp9) 0xf52a mp10_write multipurpose pin write value (lrclk_in0/mp10) 0xf52b mp11_write multipurpose pin write value (lrclk_in1/mp11) 0xf52c mp12_write m ultipurpose pin write value (lrclk_in2/mp12) 0xf52d mp13_write multipurpose pin write v alue (lrclk_in3/mp13) 0xf530 mp0_read multipurpose pin read v alue (ss_m/mp0) 0xf531 mp1_read multipurpose pin read value (mosi_m/mp1) 0xf532 mp2_read multipurpose pi n read value (scl_m/sclk_m/mp2) 0xf533 mp3_read multipurpose pin read value (sda_m/miso_m/mp3) 0xf534 mp4_read multipurpose pin read value (lrclk_out0/mp4) 0xf535 mp5_read multipurpose pin read value (lrclk_out1/mp5) 0xf536 mp6_read multipurpose pin re ad value (mp6) 0xf537 mp7_read multipurpose pin read value (mp7) 0xf538 mp8_read multipurpose pin read value (lrclk_out2/mp8) 0xf539 mp9_read multipurpose pin read value (lrclk_out3/mp9) 0xf53a mp10_read multipurpose pin read value (lrclk_in0/mp10) 0x f53b mp11_read multipurpose pin read value (lrclk_in1/mp11) 0xf53c mp12_read multipurpose pin read value (lrclk_in2/mp12) 0xf53d mp13_read multipurpose pin read value (lrclk_in3/mp13) rev. c | page 75 of 180
adau1452/adau1451/adau1450 data sheet auxiliary adc there are six auxiliary adc inputs with 10 bits of a ccuracy . they are intended to be used as control signal inputs, such as potentiometer outputs or battery monitor signals. the auxiliary adc samples each channel at a frequency of the core system clock divided by 6144. in the case of a default clocking sche me, the system clock is 294.912 mhz; thus, the auxiliary adc sample rate is 48 khz. if the system clock is scaled down by configuring the pll to generate a lower output fr e quency, the auxiliary adc sample rate is scaled down proportionately. the auxiliary adc is referenced so that a full - scale input is achieved when the input voltage is equal to avdd, and an input of zero is achieved when the input is connected to ground. the input impedance of the aux iliary adc is approximately 200 k at dc (zero h ertz) . a uxiliary adc inputs can be used directly in the dsp program (as configured in the sigmastudio software). the instantaneous value of each adc is also available in the adc_read x registers, which are accessible via the i 2 c or spi slave control port. auxiliar y adc inputs to the dsp core auxiliary adc inputs can be used as control signals in the dsp program as configured by sigmastudio. figure 77 shows the location of the auxiliary adc input cell in the sigmastudio to olbox. 1 1486-080 figure 77 . auxiliary adc input cell in the sigmastudio toolbox the six auxiliary input pins map to the corresponding six auxiliary adc input cells. figure 78 shows the complete s et of auxiliary adc input cells in sigmastudio. 1 1486-081 figure 78 . complete set of auxiliary adc inputs in sigmastudio auxiliary adc registers a n overview of the registers related to the a uxiliary adc is shown in table 56 . for a more detailed description, see the auxiliary adc registers section . table 56 . auxiliary adc registers address register description 0xf5a0 adc_read0 auxi liary adc read v alue (auxadc0) 0xf5a1 adc_read1 auxiliary adc read value (auxadc1) 0xf5a2 adc_read2 auxiliary adc read value (auxadc2) 0xf5a3 adc_read3 auxiliary adc read value (auxadc3) 0xf5a4 adc_read4 auxiliary adc read value (auxadc4) 0xf5a5 adc_r ead5 auxiliary adc read value (auxadc5) s igma dsp core the sigmadsp core operates at a maximum frequency of 294. 912 mhz (or 147.456 mhz in the adau1450 ) , which is equivalent to 6144 clock cycles per sample at a sample rate of 48 khz (or 3072 clock cycles per sample in the adau1450 ) . for a sample rate of 48 khz, the largest program possible consist s of 6144 program instructions per sample (or 3072 instructions per sample in the adau1450 ) . if the system clock remains at 294.912 mhz but the audio frame rate of the dsp core is decreased, programs consis ting of more than 6144 instructions per sample are possible. the p rogram ram is 8192 words long, s o the largest program possible (but only at lower sample rates) is 8192 instructions per frame. the core consists of four multipliers and two accumu lators . at an operating frequency of 294. 912 mhz, the core perfor m s 1.2 billion mac operations per second. at maximum efficiency, the core process es 3072 iir biquad filters (single or double precision) per sample at a sample rate of 48 khz. at maxi mum efficiency, th e core process es approximately 24 , 000 fir filter taps per sample at a sample rate of 48 khz. the instruction set is a s i ngle i nstruction , m ultipl e d ata (simd) computing model . the dsp core is 32 - bit fixed - point, with an 8.24 data format for audio. rev. c | page 76 of 180
data sheet adau1452/adau1451/adau1450 the fo ur multipliers are 64- bit double precision, capable of multiplying an 8.56 format number by an 8.24 number. the multiply accumulators consist of 1 6 registers, with a depth of 80 bits. the core can access ram with a load/store width of 256 bits ( eight 32 - bi t words per frame). the two alu s ha ve an 80- bit width and operate on numbers in 24.56 format. the 24.56 - bit format provides more than 42 db of headroom. it is possible to c reate combination s of time domain and frequency domain processing , using block and s ample frame interrupts . sixteen data address generator (dag) registers are available, and circular buffer addressing is possible. many of the signal processing functions are c oded using full, 64- bit, double precision arithmetic. the serial port input and o utput word lengths are 24 bits, but eight extra headroom bits are used in the processor to allow internal gains of up to 48 db without clipping. additional gains can be achieved by initially scaling down the input signal in the dsp signal flow. numeric fo rmats dsp systems commonly use a standard numeric format. fractional number systems are specified by an a.b format, where a is the number of bits to the left of the decimal point and b is the number of bits to the right of the decimal point. the same numer ic format is used for both the parameter and data values. a digital clipper circuit is used within the dsp core before outputting to the serial port outputs, asrcs, and s/pdif. this clips the top seven bits (and the least significant bit) of the signal to produce a 24 - bit output with a range of + 1.0 (minus 1 lsb) to ? 1.0. figure 79 shows the maximum signal levels at each point in the data flow in both binary and decibel levels. serial input port 1.23 format maximum 0dbfs dynamic range = 144db dsp core 8.24 format 42db of headroom dynamic range = 192db serial output port 1.23 format maximum 0dbfs dynamic range = 144db 24-bits 24-bits 32-bits (headroom) (headroom) 1 1486-082 figure 79 . signal range for 1.23 format (serial ports, asrcs) and 8.24 format (dsp core) numerical format: 8.24 linear range: ? 128.0 to (+128.0 ? 1 lsb) dynamic range (ratio of the largest possible signal level to the smallest possible non - zero signal level): 192 db examples: 0b 1000 0000 0000 0000 0000 0000 0000 0000 = 0x80000000 = ?128.0 0b 1110 0000 0000 0000 0000 0000 0000 0000 = 0xe0000000 = ?32.0 0b 1111 1000 0000 0000 0000 0000 0000 0000 = 0xf8000000 = ?8.0 0b 1111 1110 0000 0000 0000 0000 0000 0000 = 0xfe000000 = ?2 0b 1111 1111 0000 0000 0000 0000 0000 0000 = 0xff000000 = ?1 0b 1111 1111 1000 0000 0000 0000 0000 0000 = 0xff800000 = ?0.5 0b 1111 1111 1110 0110 0110 0110 0110 0110 = 0xffe66666 = ?0.1 0b 1111 1111 1111 1111 1111 1111 1111 1111 = 0xffffffff = ?0.00000005 (1 lsb below 0.0) 0b 0000 0000 0000 0000 0000 0000 0000 0000 = 0x00000000 = 0.0 0b 0000 0000 0000 0000 0000 0000 0000 0001 = 0x00000001 = 0.00000005 (1 lsb above 0.0) 0b 0000 0000 0001 1001 1001 1001 1001 1001 = 0x00199999 = 0.1 0b 0000 0000 0100 0000 0000 0000 0000 0000 = 0x00400000 = 0.25 0b 0000 0000 1000 0000 0000 0000 0000 0000 = 0x00800000 = 0.5 0b 0000 0001 0000 0000 0000 0000 0000 0000 = 0x01000000 = 1.0 0b 0000 0010 0000 0000 0000 0000 0000 0000 = 0x02000000 = 2.0 0b 0111 1111 1111 1111 1111 1111 1111 1111 = 0x7fffffff = 127.99999994 (1 lsb below 128.0) rev. c | page 77 of 180
adau1452/adau1451/adau1450 data sheet numerical format: 32.0 the 32.0 format is used for logic signals in the dsp program flow that are integers. linear range: ?2, 147,483,648 to + 2, 147,483,647 dynamic range (ratio of the largest possible signal level to the smallest possible non - zero sig nal level): 192 db examples: 0b 1000 0000 0000 0000 0000 0000 0000 0000 = 0x80000000 = ?2147483648 0b 1000 0000 0000 0000 0000 0000 0000 0001 = 0x80000001 = ?2147483647 0b 1000 0000 0000 0000 0000 0000 0000 0010 = 0x80000002 = ?2147483646 0b 1100 0000 0000 0000 0000 0000 0000 0000 = 0xc0000000 = ?1073741824 0b 1110 0000 0000 0000 0000 0000 0000 0000 = 0xe0000000 = ?536870912 0b 1111 1111 1111 1111 1111 1111 1111 1100 = 0xfffffffc = ?4 0b 1111 1111 1111 1111 1111 1111 1111 1110 = 0xfffffffe = ?2 0b 1111 1111 1111 1111 1111 1111 1111 1111 = 0xffffffff = ?1 0b 0000 0000 0000 0000 0000 0000 0000 0000 = 0x00000000 = 0 0b 0000 0000 0000 0000 0000 0000 0000 0001 = 0x00000001 = 1 0b 0000 0000 0000 0000 0000 0000 0000 0010 = 0x00000002 = 2 0b 0000 0000 0000 0000 0000 0000 0000 0011 = 0x00000003 = 3 0b 0000 0000 0000 0000 0000 0000 0000 0100 = 0x00000004 = 4 0b 0111 1111 1111 1111 1111 1111 1111 1110 = 0x7ffffffe = 2147483646 0b 0111 1111 1111 1111 1111 1111 1111 1111 = 0x7fffffff = 2147483647 hardware accelerators th e core includes accelerators like division, square root, barrel shifters, base - 2 logarithm, base - 2 exponential, slew, and a psuedorandom number generator. this reduces the number of instruc tions required for complex audio processing algorithms. the divisio n accelerator enables efficient processing for audio algorithms like compression and limiting. the square root accel - erator enables efficient processing for audio algorithms such as loudness, rms envelopes, and filter coefficient calculations. the logarith m and exponent accelerators enable efficient processing for audio algorithms involving decibel conversion. the slew accelerators provide for click - free updates of parameters that must change slowly over time, allowing for audio processing algorithms such a s mixers, crossfaders, dynamic filters, and dynamic volume controls. the pseudorandom number generator can efficiently produce white noise, pink noise, and dither. programming the sigmadsp core the sigmadsp is programmable via the sigmastudio graphical dev elopment tools. when the sigmadsp core is running a program and the user needs to reprogram the program and data memories during operation of the device, the core must be stopped while the memory is being updated to avo id undesired noises on the dsp output s. the following sequence of steps is appropriate for programming the memories at boot time, or reprogrammin g the memories during operation: 1. en able soft reset ( register 0xf 890 ( soft_reset ), bit 0 ( soft_reset ) = 0b0 ) , then disable soft reset (register 0xf 890 (soft_reset), bit 0 (soft_reset) = 0b1) . 2. if the dsp is in the process of executing a program, w ait for the current sample or block to finish processing. for programs with no block processing elements in the signal flow , use the length of one sample . fo r example, at a sample rate of 48 khz, one sample is 1/48000 sec, or 20.83 s . for programs with block processing elements in the signal flow, use the lengt h o f one block. for example, at a sample rate of 48 khz, with a block size of 256 samples, one block is 256/48 , 000 sec, or 53.3 ms. 3. after waiting the appropriate amount of time , as defined i n t he previous step, d ownload the new program and dat a m emory contents to the corresponding memory locations using the i 2 c/spi slave control port. 4. start the dsp core ( register 0xf402 ( start_core ), bit 0 ( start_core ) = 0b1). 5. wait at least two audio samples for the dsp initialization to execute . for example, at a sample rate of 48 khz, two samples are equal to 2/48 , 000 sec, or 41.66 s. rev. c | page 78 of 180
data sheet adau1452/adau1451/adau1450 reliability features several reli ability feature s are controlled by a panic manager subsystem that monitors the state of the sigmadsp core and memories and generates alerts if error conditions are encountered. the panic manager indicates error conditions to the user via register flags and gpio outputs. the origin of the error can be traced to different functional blocks such as the watchdog, memory, stack, software program, and core op codes. although designed mostly as an aid for software development, the panic manager is also useful in m onitoring the state of the memor ies over long periods of time, such as in applications where the system operates unattended for an extended period, and resets are infrequent. the memories in the device have a built - in self test feature that runs automatic ally while the device is in operation. if a memory corruption is detected, the appropriate flag is signaled in the panic manager. the program running in the dsp core can monitor the state of the panic manager and can mute the audio outputs if an error is e ncountered, and external devices , such as microcontrollers , can poll the panic manager registers or monitor the multipurpose pi ns to perform some pre programmed action , if necessary. dsp core and reliability registers a n overview of the registers related to the dsp c ore is shown in table 57 . for a more detailed description, see the dsp core control registers section and debug and reliability registers section . table 57 . dsp core and reliability registers address register description 0xf400 hibernate hibernate s etting 0xf401 start_pulse start pulse selection 0xf402 start_core instruction to start the co re 0xf403 kill_core instruction to stop the core 0xf404 start_address start address of the program 0xf405 core_status core s tatus 0xf421 panic_clear clear the panic manager 0xf422 panic_parity_mask panic parity 0xf423 panic_software_mask panic mask 0 0xf424 panic_wd_mask panic mask 1 0xf425 panic_stack_mask panic mask 2 0xf426 panic_loop_mask panic mask 3 0xf427 panic_flag panic flag 0xf428 panic_code panic code 0xf432 execute_count execute stage error program count 0xf443 watchdog_maxcount wat chdog maximum count 0xf444 watchdog_prescale watchdog pres cale 0xf450 blockint_en enable block interrupts 0xf451 blockint_value value for the block interrupt counter 0xf460 prog_cntr0 program c ounter , bits [23:16] 0xf461 prog_cntr1 program c ounter , bit s [15:0] 0xf462 prog_cntr_clear program counter c lear 0xf463 prog_cntr_length0 program counter l ength , bits [23:16] 0xf464 prog_cntr_length1 program counter l ength , bits [15:0] 0xf465 prog_cntr_maxlength0 program counter maximum l ength , bits [23:16] rev. c | page 79 of 180
adau1452/adau1451/adau1450 data sheet software features software safeload to update parameters in real time while avoiding pop and click noises on the output, a software safeload mechanism has been implemented by default in the sigmastudio compiler. sigmastudio automatically sets up the necess ary code and parameters for all new projects. the safeload code, together with other initialization code, fills the beginning section of program ram. several data memory locations are reserved by the compiler for use with the software safeload feature. the exact parameter addresses are not fixed, so the addresses must be obtained by reading the log file g enerated by the compiler. in most cases, the addresses for softwar e safeload parameters match the defaults shown in table 58. table 58 . software safeload memory address defaults address (hex) parameter function 0x0014 data_safeload[0] safeload data slot 0 0x0015 data_safeload[1] safeload data slot 1 0x0016 data_safeload[2] safeload data s lot 2 0x0017 data_safeload[3] safeload data slot 3 0x0018 data_safeload[4] safeload data slot 4 0x0019 address_safeload target address for safeload transfer 0x001a num_safeload number of words to write/safeload trigger the first five addresses in table 58 are the five data_safeload parameters, which are slots for storing the data that is going to be transferred into another target memory location. the safeload parameter space contains five data slots , by def ault , because most standard signal processing algorithms have five parameters or fewer. the address_safeload parameter is the target address in parameter ram. this designates the first address to be written in the safe - load transfer . if more than one word is written, the address increments au tomatically for each data - word. the num_safeload parameter designates the number of words to be written. for a biquad filter algorithm , th e number of words to be written is five because there are five coefficients in a biquad iir filter . for a simple mono gain algorithm , the number of words to be written is one. this parameter also serves as the trigger; when it is written, a safeload write is triggered on the next frame. the safeload mechanism is software based and exec utes once per audio frame. therefore, system designers must take care when designing the communication protocol. a delay that is equal to or greater than the sampling period (the inverse of the sampling frequency) is required between each safeload write. a t a sample rate of 48 khz, this equates to a delay of 20.83 s. not observing this delay corrupts the downloaded data . because the compiler has contr ol over the addresses used for soft - ware s afeload, the addresses assigned to each parameter may differ fro m the default values in table 58 . the compiler generates a file named compiler_output.log in the project folder where the sigmastudio project is stored on the hard drive. in this file, the addresses assigned to t he software s afeload parameters can be confirm ed. figure 80 shows an example of the software s afeload parameter definitions in an excerpt from the compiler_output.log file. the following steps are necessary for e xecuting a software safeload: 1. confirm that no safeload operation has been executed in the span of the last audio sample. 2. write the desired data to the data_safeload, bit x parameters, starting at data_safeload, bit 0, and incrementing, as needed, up to a m aximum of five parameters. 3. write the desired starting target address to the address_safeload parameter. 4. write the number of words to be transferred to the num_safeload parameter. the minimum write length is one word, and the maximum write length is five wo rds. 5. wait one audio frame for the safeload operation to complete. 1 1486-083 figure 80 . compil er log output excerpt with safel oad module definitions rev. c | page 80 of 180
data sheet adau1452/adau1451/adau1450 soft reset function the soft reset function allows the device to enter a state similar t o when the hardware reset pin is connected to ground. all control registers are reset to their default values, except the pll registers, as follows: register 0xf000 (pll_ctrl0), register 0xf001 (pll_ctrl1), register 0xf002 (pll_clk_src), register 0xf003 (pll_enable), register 0xf004 (pll_lock), register 0xf005 (mclk_out), and register 0xf006 (pll_watchdog), as well as the registers related to the panic manager. table 59 shows a n overview of the register related to the soft reset function . for more details , see the soft reset register section. table 59 . soft reset register address name description 0xf890 soft_reset software reset pin drive strength, slew rate, and pull configuration every digital output pin has configurable drive strength and slew rate. this allows the current sourcing ability of the driver to be modified to fit the application circuit. in general, higher drive strength is needed to improve signal integrity when driving high frequency clocks over long distances. lower drive strength can be used for lower frequency clock signals, shorter traces, or in cases where reduced system emi (electromagnetic interference) i s desired. slew rate can be increased if the edges of the clock signal have rise or fall times that are too long. to achieve adequate signal integrity and minimize electromagnetic emissions, use t he drive strength and slew rate settings in combination with good mixed - signal pcb design practices. pin drive strength, slew rate, and pull configuration registers a n overview of the registers related to pin drive strength, slew rate, and pull configuration is shown in ta ble 60 . for a more detailed description, see the hardware interfacing registers section. table 60 . pin drive strength, slew rate, and pull configuration registers address register descri ption 0xf780 bclk_in0_pin bclk input pin drive strength and slew r ate (bclk_in0) 0xf781 bclk_in1_pin bclk input pin drive strength and slew rate (bclk_in1) 0xf782 bclk_in2_pin bclk input pin drive strength and slew rate (bclk_in2) 0xf783 bclk_in3_pin b clk input pin drive strength and slew rate (bclk_in3) 0xf784 bclk_out0_pin bclk output pin drive strength and slew rate (bclk_out0) 0xf785 bclk_out1_pin bclk output pin drive strength and slew rate (bclk_out1) 0xf786 bclk_out2_pin bclk output pin drive strength and slew rate (bclk_out2) 0xf787 bclk_out3_pin bclk output pin drive strength and slew rate (bclk_out3) 0xf788 lrclk_in0_pin lrclk input pin drive strength and slew rate (lrclk_in0) 0xf789 lrclk_in1_pin lrclk input pin drive strength and slew r ate (lrclk_in1) 0xf78a lrclk_in2_pin lrclk input pin drive strength and slew rate (lrclk_in2) 0xf78b lrclk_in3_pin lrclk input pin drive strength and slew rate (lrclk_in3) 0xf78c lrclk_out0_pin lrclk output pin drive strength and slew rate (lrclk_out0) 0xf78d lrclk_out1_pin lrclk output pin drive strength and slew rate (lrclk_out1) 0xf78e lrclk_out2_pin lrclk output pin drive strength and slew rate (lrclk_out2) 0xf78f lrclk_out3_pin lrclk output pin drive strength and slew rate (lrclk_out3) 0xf790 sd ata_in0_pin sdata input pin drive strength and slew rate (sdata_in0) 0xf791 sdata_in1_pin sdata input pin drive strength and slew rate (sdata_in1) 0xf792 sdata_in2_pin sdata input pin drive strength and slew rate (sdata_in2) 0xf793 sdata_in3_pin sdata i nput pin drive strength and slew rate (sdata_in3) 0xf794 sdata_out0_pin sdata output pin drive strength and slew rate (sdata_out0) 0xf795 sdata_out1_pin sdata output pin drive strength and slew rate (sdata_out1) 0xf796 sdata_out2_pin sdata output pin dr ive strength and slew rate (sdata_out2) 0xf797 sdata_out3_pin sdata output pin drive strength and slew rate (sdata_out3) 0xf798 spdif_tx_pin s/pdif t ransmitter pin drive strength and slew rate 0xf799 sclk_scl_pin sclk/scl pin drive strength and slew rat e 0xf79a miso_sda_pin miso/sda pin drive strength and slew rate 0xf79b ss_pin ss/addr0 pin drive strength and slew rate 0xf79c mosi_addr1_pin mosi/addr1 pin drive strength and slew rate 0xf79d sclk_scl_m_pin scl_m/sclk_m/mp2 pin drive strength and slew rate rev. c | page 81 of 180
adau1452/adau1451/adau1450 data sheet address register descri ption 0xf79e miso_sda_m_pin sda_m/miso_m/mp3 pin drive strength and slew rate 0xf79f ss_m_pin ss_m/mp0 pin drive strength and slew rate 0xf7a0 mosi_m_pin mosi_m/mp1 pin drive strength and slew rate 0xf7a1 mp6_pin mp6 pin drive strength and slew rate 0 xf7a2 mp7_pin mp7 pin drive strength and slew rate 0xf7a3 clkout_pin clkout pin drive strength and slew rate rev. c | page 82 of 180
data sheet adau1452/adau1451/adau1450 global ram and contr ol register map the complete set of addresses accessible via the slave i 2 c/spi control port is described in this section. th e addresses are divided into two main parts: memory and registers. random access memory the adau1452 h as 1.28 mb of data (40 kwords storing 32 - bit data) . the adau1451 has 512 kb of data (16 kwords stori ng 32- bit data). the adau1450 has 256 kb of data (8 kwords storing 32 - bit data). the adau1452 / adau1451 / adau1450 ha ve eight kwords of program memor y. program memory consists of 32 bit words. op codes for the dsp core are either 32 bits or 64 bits ; therefore, program instructions can take up one or two addresses in memory. the program memory has parity bit protection. the panic manager flag s parity er rors when they are detected. program memory can only be w ritten or read when the core is stopped. the program memory is hardware protected so it cannot be accidentally overwritten or corrupted at run time. the dsp core is able to directly access all memory and registers. data memory acts as a storage area for both audio data and signal processing parameters, such as filter coefficients. the data memory has parity bit protection. the panic manager flag s parity errors when they are detected. modulo memory add ressing is used in severa l audio processing algorithms. the b oundaries between the fixed and rotating memories are set in sigmastudio by the compiler , and they require no action on the part of the user. data and parameters assignment to the different memo ry spaces are handled in software. the modulo boundary locations are flexible. a rom table ( of over seven kw ords) , containing a set of commonly used constants , can be accessed by the dsp core. this memory is used to increase th e efficiency of audio process ing algorithm deve lopment. the table includes inf o r mation such as t rigonometric tables, including sine, cosine, tangent, and hyper - bolic tangent , t widdle factors for frequency domain processing , r eal mathematical constants, such as pi and factors of 2 , and c omplex constants . the rom table is not accessible from the i 2 c or spi slave control port. all memory addresses store 32 bits ( four bytes) of data. the memory spaces for the adau1452 are defined in table 61. the memory spaces for the adau1451 are defined in table 62 . the memory spaces for the adau1450 are defined in table 63. table 61. adau1452 memory map address range length memory data - word size 0x0000 to 0x4fff 20480 words dm0 (data memory 0) 32 bits 0x6000 to 0xafff 20480 words dm1 (data memory 1) 32 bits 0xc000 to 0xdfff 8192 words program memory 32 bits table 62. adau145 1 memory map address range length memory data - word size 0x0000 to 0x3fff 16384 words dm0 (data memory 0) 32 bits 0x6000 to 0x9fff 16384 words dm1 (data memory 1) 32 bits 0xc000 to 0xdfff 8192 words program memory 32 bits table 63. adau1450 memory map address range length memory data - word size 0x0000 to 0x1fff 8192 words dm0 (data memory 0) 32 bits 0x6000 to 0x7fff 8192 words dm1 (data memory 1) 32 bits 0xc000 to 0xdfff 8192 words program memory 32 bits rev. c | page 83 of 180
adau1452/adau1451/adau1450 data sheet control registers all control registers store 16 bits (two bytes) of data. the register map for the adau1452 / adau1451 / adau1450 is defined in table 64. table 64 . control register summary address register name description reset rw 0xf000 pll_ctrl0 pll feedback divi der 0x0060 rw 0xf001 pll_ctrl1 pll prescale d ivider 0x0000 rw 0xf002 pll_clk_src pll clo ck source 0x0000 rw 0xf003 pll_enable pll e nable 0x0000 rw 0xf004 pll_lock pll l ock 0x0000 r 0xf005 mclk_out clkout c ontrol 0x0000 rw 0xf006 pll_watchdog analog pll watchdog c ontrol 0x0001 rw 0xf020 clk_gen1_m denominator (m) for clock generator 1 0x0 006 rw 0xf021 clk_gen1_n numerator (n) for clock generator 1 0x0001 rw 0xf022 clk_gen2_m denominator (m) for clock generator 2 0x0009 rw 0xf023 clk_gen2_n numerator (n) for clock generator 2 0x0001 rw 0xf024 clk_gen3_m denominator (m) for clock generat or 3 0x0000 rw 0xf025 clk_gen3_n numerator for (n) clock generator 3 0x0000 rw 0xf026 clk_gen3_src input reference for clock generator 3 0x000e rw 0xf027 clk_gen3_lock lock bit for clock generato r 3 input r eference 0x0000 r 0xf050 power_enable0 power e nable 0 0x0000 rw 0xf051 power_enable1 power enable 1 0x0000 rw 0xf100 asrc_input0 asrc input selector ( asrc 0 , channel 0 and channel 1) 0x0000 rw 0xf101 asrc_input1 asrc input selector ( asrc 1 , channel 2 and channel 3) 0x0000 rw 0xf102 asrc_input2 asr c input selector ( asrc 2 , channel 4 and channel 5) 0x0000 rw 0xf103 asrc_input3 asrc input selector ( asrc 3 , channel 6 and channel 7) 0x0000 rw 0xf104 asrc_input4 asrc input selector ( asrc 4 , channel 8 and channel 9) 0x0000 rw 0xf105 asrc_input5 asrc in put selector ( asrc 5 , channel 10 and channel 11) 0x0000 rw 0xf106 asrc_input6 asrc input selector ( asrc 6 , channel 12 and channel 13) 0x0000 rw 0xf107 asrc_input7 asrc input selector ( asrc 7 , cha nnel 14 and channel 15) 0x0000 rw 0xf140 asrc_out_rate0 a s rc output rate ( asrc 0 , channel 0 and channel 1) 0x0000 rw 0xf141 asrc_out_rate1 a src output rate ( asrc 1 , channel 2 and channel 3) 0x0000 rw 0xf142 asrc_out_rate2 a src output rate ( asrc 2 , channel 4 and channel 5) 0x0000 rw 0xf143 asrc_out_rate3 a src o utput rate ( asrc 3 , channel 6 and channel 7) 0x0000 rw 0xf144 asrc_out_rate4 a src output rate ( asrc 4 , channel 8 and channel 9) 0x0000 rw 0xf145 asrc_out_rate5 a src output rate ( asrc 5 , channel 10 and channel 11) 0x0000 rw 0xf146 asrc_out_rate6 asrc out put rate ( asrc 6 , channel 12 and channel 13) 0x0000 rw 0xf147 asrc_out_rate7 a src output rate ( asrc 7 , channel 14 and channel 15) 0x0000 rw 0xf180 sout_source0 source of data for serial output ports (channel 0 and channel 1) 0x0000 rw 0xf181 sout_source 1 source of data for serial output ports (channel 2 and channel 3) 0x0000 rw 0xf182 sout_source2 source of data for serial output ports (channel 4 and channel 5) 0x0000 rw 0xf183 sout_source3 source of data for serial output ports (channel 6 and channel 7) 0x0000 rw 0xf184 sout_source4 source of data for serial output ports (channel 8 and channel 9) 0x0000 rw 0xf185 sout_source5 source of data for serial output ports (channel 10 and channel 11) 0x0000 rw 0xf186 sout_source6 source of data for serial ou tput ports (channel 12 and channel 13) 0x0000 rw 0xf187 sout_source7 source of data for serial output ports (channel 14 and channel 15) 0x0000 rw 0xf188 sout_source8 source of data for serial output ports (channel 16 and channel 17) 0x0000 rw 0xf189 sou t_source9 source of data for serial output ports (channel 18 and channel 19) 0x0000 rw 0xf18a sout_source10 source of data for serial output ports (channel 20 and channel 21) 0x0000 rw 0xf18b sout_source11 source of data for serial output ports (channel 22 and channel 23) 0x0000 rw 0xf18c sout_source12 source of data for serial output ports (chann el 24 and channel 25) 0x0000 rw 0xf18d sout_source13 source of data for serial output ports (channel 26 and channel 27) 0x0000 rw 0xf18e sout_source14 source of data for serial output ports (channel 28 and channel 29) 0x0000 rw 0xf18f sout_source15 source of data for serial output ports (channel 30 and channel 31) 0x0000 rw 0xf190 sout_source16 source of data for serial output ports (channel 32 and channel 33) 0x0000 rw rev. c | page 84 of 180
data sheet adau1452/adau1451/adau1450 address register name description reset rw 0xf191 sout_source17 source of data for serial output ports (channel 34 and channel 35) 0x0000 rw 0xf192 sout_source18 source of data for serial output ports (channel 36 and channel 37) 0x0000 rw 0xf193 sout_source19 source of data for seria l output ports (channel 38 and channel 39) 0x0000 rw 0xf194 sout_source20 source of data for serial output ports (channel 40 and channel 41) 0x0000 rw 0xf195 sout_source21 source of data for serial output ports (channel 42 and channel 43) 0x0000 rw 0xf1 96 sout_source22 source of data for serial output ports (channel 44 and channel 45) 0x0000 rw 0xf197 sout_source23 source of data for serial output ports (channel 46 and channel 47) 0x0000 rw 0xf1c0 spdiftx_input s/pdif transmitter data selector 0x0000 r w 0xf200 serial_byte_0_0 serial port control 0 (sdata_in0) 0x0000 rw 0xf201 serial_byte_0_1 serial port control 1 (sdata_in0) 0x0002 rw 0xf204 serial_byte_1_0 serial port control 0 (sdata_in1) 0x0000 rw 0xf205 serial_byte_1_1 serial port control 1 (sda ta_in1) 0x0002 rw 0xf208 serial_byte_2_0 serial port control 0 (sdata_in2) 0x0000 rw 0xf209 serial_byte_2_1 serial port control 1 (sdata_in2) 0x0002 rw 0xf20c serial_byte_3_0 serial port control 0 (sdata_in3) 0x0000 rw 0xf20d serial_byte_3_1 serial por t control 1 (sdata_in3) 0x0002 rw 0xf210 serial_byte_4_0 serial port control 0 (sdata_out0) 0x0000 rw 0xf211 serial_byte_4_1 serial port control 1 (sdata_out0) 0x0002 rw 0xf214 serial_byte_5_0 serial port control 0 (sdata_out1) 0x0000 rw 0xf215 serial_ byte_5_1 serial port control 1 (sdata_out1) 0x0002 rw 0xf218 serial_byte_6_0 serial port control 0 (sdata_out2) 0x0000 rw 0xf219 serial_byte_6_1 serial port control 1 (sdata_out2) 0x0002 rw 0xf21c serial_byte_7_0 serial port control 0 (sdata_out3) 0x000 0 rw 0xf21d serial_byte_7_1 serial port control 1 (sdata_out3) 0x0002 rw 0xf300 ftdm_in0 ftdm mapping for the serial inputs (channel 32, bits [31:24]) 0x0000 rw 0xf301 ftdm_in1 ftdm mapping for the serial inputs (channel 32, bits [23:16]) 0x0000 rw 0xf30 2 ftdm_in2 ftdm mapping for the serial inputs (channel 32, bits [15:8]) 0x0000 rw 0xf303 ftdm_in3 ftdm mapping for the serial inputs (channel 32, bits [7:0]) 0x0000 rw 0xf304 ftdm_in4 ftdm mapping for the serial inputs (channel 33, bits [31:24]) 0x0000 rw 0xf305 ftdm_in5 ftdm mapping for the serial inputs (channel 33, bits [23:16]) 0x0000 rw 0xf306 ftdm_in6 ftdm mapping for the serial inputs (channel 33, bits [15:8]) 0x0000 rw 0xf307 ftdm_in7 ftdm mapping for the serial inputs (channel 33, bits [7:0]) 0x0000 rw 0xf308 ftdm_in8 ftdm mapping for the serial inputs (channel 34, bits [31:24]) 0x0000 rw 0xf309 ftdm_in9 ftdm mapping for the serial inputs (channel 34, bits [23:16]) 0x0000 rw 0xf30a ftdm_in10 ftdm mapping for the serial inputs (channel 34, bits [15:8] ) 0x0000 rw 0xf30b ftdm_in11 ftdm mapping for the serial inputs (channel 34, bits [7:0]) 0x0000 rw 0xf30c ftdm_in12 ftdm mapping for the serial inputs (channel 35, bit s [31:24]) 0x0000 rw 0xf30d ftdm_in13 ftdm mapping for the serial inputs (channel 35, bi ts [23:16]) 0x0000 rw 0xf30e ftdm_in14 ftdm mapping for the serial inputs (channel 35, bits [15:8]) 0x0000 rw 0xf30f ftdm_in15 ftdm mapping for the serial inputs (ch annel 35, bits [7:0]) 0x0000 rw 0xf310 ftdm_in16 ftdm mapping for the serial inputs (channe l 36, bits [31:24]) 0x0000 rw 0xf311 ftdm_in17 ftdm mapping for the serial inputs (channel 36, bits [23:16]) 0x0000 rw 0xf312 ftdm_in18 ftdm mapping for the serial inputs (channel 36, bits [15:8]) 0x0000 rw 0xf313 ftdm_in19 ftdm mapping for the serial inpu ts (channel 36, bits [7:0]) 0x0000 rw 0xf314 ftdm_in20 ftdm mapping for the serial inputs (channel 37, bits [31:24]) 0x0000 rw 0xf315 ftdm_in21 ftdm mapping for the serial inputs (channel 37, bits [23:16]) 0x0000 rw 0xf316 ftdm_in22 ftdm mapping for the se rial inputs (channel 37, bits [15:8]) 0x0000 rw 0xf317 ftdm_in23 ftdm mapping for the serial inputs (channel 37, bits [7:0]) 0x0000 rw 0xf318 ftdm_in24 ftdm mapping for the serial inputs (channel 38, bits [31:24]) 0x0000 rw 0xf319 ftdm_in25 ftdm mapping fo r the serial inputs (channel 38, bits [23:16]) 0x0000 rw 0xf31a ftdm_in26 ftdm mapping for the serial inputs (channel 38, bits [15:8]) 0x0000 rw 0xf31b ftdm_in27 ftdm mapping for the serial inputs (channel 38, bits [7:0]) 0x0000 rw 0xf31c ftdm_in28 ftdm ma pping for the serial inputs (channel 39, bits [31:24]) 0x0000 rw 0xf31d ftdm_in29 ftdm mapping for the serial inputs (channel 39, bits [23:16]) 0x0000 rw rev. c | page 85 of 180
adau1452/adau1451/adau1450 data sheet address register name description reset rw 0xf31e ftdm_in30 ftdm mapping for the serial inputs (channel 39, bits [15:8]) 0x0000 rw 0xf31f ftdm_in 31 ftdm mapping for the serial inputs (channel 39, bits [7:0]) 0x0000 rw 0xf320 ftdm_in32 ftdm mapping for the serial inputs (channel 40, bits [31:24]) 0x0000 rw 0xf321 ftdm_in33 ftdm mapping for the serial inputs (channel 40, bits [23:16]) 0x0000 rw 0xf32 2 ftdm_in34 ftdm mapping for the serial inputs (channel 40, bits [15:8]) 0x0000 rw 0xf323 ftdm_in35 ftdm mapping for the serial inputs (channel 4 0, bits [7:0]) 0x0000 rw 0xf324 ftdm_in36 ftdm mapping for the serial inputs (channel 41, bits [31:24]) 0x0000 r w 0xf325 ftdm_in37 ftdm mapping for the serial inputs (channel 41, bits [23:16]) 0x0000 rw 0xf326 ftdm_in38 ftdm mapping for the serial inputs (channel 41, bits [15:8]) 0x0000 rw 0xf327 ftdm_in39 ftdm mapping for the serial inputs (channel 41, bits [7:0]) 0x0000 rw 0xf328 ftdm_in40 ftdm mapping for the serial inputs (channel 42, bits [31:24]) 0x0000 rw 0xf329 ftdm_in41 ftdm mapping for the serial inputs (channel 42, bits [23:16]) 0x0000 rw 0xf32a ftdm_in42 ftdm mapping for the serial inputs (channel 42, bi ts [15:8]) 0x0000 rw 0xf32b ftdm_in43 ftdm mapping for the serial inputs (channel 42, bits [7:0]) 0x0000 rw 0xf32c ftdm_in44 ftdm mapping for the serial inputs (channel 43, bits [31:24]) 0x0000 rw 0xf32d ftdm_in45 ftdm mapping for the serial inputs (channe l 43, bits [23:16]) 0x0000 rw 0xf32e ftdm_in46 ftdm mapping for the serial inputs (channel 43, bits [15:8]) 0x0000 rw 0xf32f ftdm_in47 ftdm mapping for the serial inputs (channel 43, bits [7:0]) 0x0000 rw 0xf330 ftdm_in48 ftdm mapping for the serial inputs (channel 44, bits [31:24]) 0x0000 rw 0xf331 ftdm_in49 ftdm mapping for the serial inputs (channel 44, bits [23:16]) 0x0000 rw 0xf332 ftdm_in50 ftdm mapping for the serial inputs (channel 44, bits [15:8]) 0x0000 rw 0xf333 ftdm_in51 ftdm mapping for the ser ial inputs (channel 44, bits [7:0]) 0x0000 rw 0xf334 ftdm_in52 ftdm mapping for the serial inputs (channel 45, bits [31:24]) 0x0000 rw 0xf335 ftdm_in53 ftdm mapping for the serial inputs (channel 45, bits [23:16]) 0x0000 rw 0xf336 ftdm_in54 ftdm mapping fo r the serial inputs (channel 45, bits [15:8]) 0x0000 rw 0xf337 ftdm_in55 ftdm mapping for the serial inputs (channel 45, bits[7:0]) 0x0000 rw 0xf338 ftdm_in56 ftdm mapping for the serial inputs (channel 46, bits [31:24]) 0x0000 rw 0xf339 ftdm_in57 ftdm ma pping for the serial inputs (channel 46, bits [23:16]) 0x0000 rw 0xf33a ftdm_in58 ftdm mapping for the serial inputs (chan nel 46, bits [15:8]) 0x0000 rw 0xf33b ftdm_in59 ftdm mapping for the serial inputs (channel 46, bits [7:0]) 0x0000 rw 0xf33c ftdm_in60 ftdm mapping for the serial inputs (channel 47, bits [31:24]) 0x0000 rw 0xf33d ftdm_in61 ftdm mapping for the serial inputs (channel 47, bits [23:16]) 0x0000 rw 0xf33e ftdm_in62 ftdm mapping for the serial inputs (channel 47, bits [15:8]) 0x0000 rw 0xf33f ftdm_in63 ftdm mapping for the serial inputs (channel 47, bits [7:0]) 0x0000 rw 0xf380 ftdm_out0 ftdm mapping for the serial outputs (port 2, channel 0, bits [31:24]) 0x0000 rw 0xf381 ftdm_out1 ftdm mapping for the serial outputs (port 2, channel 0, bits [ 23:16]) 0x0000 rw 0xf382 ftdm_out2 ftdm mapping for the serial outputs (port 2, channel 0, bits [15:8]) 0x0000 rw 0xf383 ftdm_out3 ftdm mapping for the serial outputs (port 2, channel 0, bits [7:0]) 0x0000 rw 0xf384 ftdm_out4 ftdm mapping for the serial o utputs (port 2, channel 1, bits [31:24]) 0x0000 rw 0xf385 ftdm_out5 ftdm mapping for the serial outputs (p ort 2, channel 1, bits [23:16]) 0x0000 rw 0xf386 ftdm_out6 ftdm mapping for the serial outputs (port 2, channel 1, bits [15:8]) 0x0000 rw 0xf387 ftdm_ out7 ftdm mapping for the serial outputs (port 2, channel 1, bits [7:0]) 0x0000 rw 0xf388 ftdm_out8 ftdm mapping for the serial outputs (port 2, channel 2, bits [31:24]) 0x0000 rw 0xf389 ftdm_out9 ftdm mapping for the serial outputs (port 2, channel 2, bit s [23:16]) 0x0000 rw 0xf38a ftdm_out10 ftdm mapping for the serial outputs (port 2, channel 2, bits [15:8]) 0x0000 rw 0xf38b ftdm_out11 ftdm mapping for the serial outputs (port 2, channel 2, bits [7:0]) 0x0000 rw 0xf38c ftdm_out12 ftdm mapping for the ser ial outputs (port 2, channel 3, bits [31:24]) 0x0000 rw 0xf38d ftdm_out13 ftdm mapping for the serial outputs (port 2, channel 3, bits [23:16]) 0x0000 rw 0xf38e ftdm_out14 ftdm mapping for the serial outputs (port 2, channel 3, bits [15:8]) 0x0000 rw 0xf38 f ftdm_out15 ftdm mapping for the serial outputs (port 2, channel 3, bits [7:0]) 0x0000 rw 0xf390 ftdm_out16 ftdm mapping for the serial outputs (port 2, channel 4, bits [31:24]) 0x0000 rw 0xf391 ftdm_out17 ftdm mapping for the serial outputs (port 2, chan nel 4, bits [23:16]) 0x0000 rw 0xf392 ftdm_out18 ftdm mapping for the serial outputs (port 2, channel 4, bits [15:8]) 0x0000 rw 0xf393 ftdm_out19 ftdm mapping for the serial outputs (port 2, channel 4, bits [7:0]) 0x0000 rw rev. c | page 86 of 180
data sheet adau1452/adau1451/adau1450 address register name description reset rw 0xf394 ftdm_out20 ftdm mapping f or the serial outputs (port 2, channel 5, bits [31:24]) 0x0000 rw 0xf395 ftdm_out21 ftdm mapping for the serial outputs (port 2, channel 5, bits [23:16]) 0x0000 rw 0xf396 ftdm_out22 ftdm mapping for the serial outputs (port 2, channel 5, bits [15:8]) 0x0000 rw 0xf397 ftdm_out23 ftdm mapping for the serial outputs (port 2, ch annel 5, bits [7:0]) 0x0000 rw 0xf398 ftdm_out24 ftdm mapping for the serial outputs (port 2, channel 6, bits [31:24]) 0x0000 rw 0xf399 ftdm_out25 ftdm mapping for the serial outputs (po rt 2, channel 6, bits [23:16]) 0x0000 rw 0xf39a ftdm_out26 ftdm mapping for the serial outputs (port 2, channel 6, bits [15:8]) 0x0000 rw 0xf39b ftdm_out27 ftdm mapping for the serial outputs (port 2, channel 6, bits [7:0]) 0x0000 rw 0xf39c ftdm_out28 ftdm mapping for the serial outputs (port 2, channel 7, bits [31:24]) 0x0000 rw 0xf39d ftdm_out29 ftdm mapping for the serial outputs (port 2, channel 7, bits [23:16]) 0x0000 rw 0xf39e ftdm_out30 ftdm mapping for the serial outputs (port 2, channel 7, bits [15: 8]) 0x0000 rw 0xf39f ftdm_out31 ftdm mapping for the serial outputs (port 2, channel 7, bits [7:0]) 0x0000 rw 0xf3a0 ftdm_out32 ftdm mapping for the serial outputs (port 3, channel 0, bits [31:24]) 0x0000 rw 0xf3a1 ftdm_out33 ftdm mapping for the serial o utputs (port 3, channel 0, bits [23:16]) 0x0000 rw 0xf3a2 ftdm_out34 ftdm mapping for the serial outputs (port 3, channel 0, bits [15:8]) 0x0000 rw 0xf3a3 ftdm_out35 ftdm mapping for the serial outputs (port 3, channel 0, bits [7:0]) 0x0000 rw 0xf3a4 ftdm_ out36 ftdm mapping for the serial outputs (p ort 3, channel 1, bits [31:24]) 0x0000 rw 0xf3a5 ftdm_out37 ftdm mapping for the serial outputs (port 3, channel 1, bits [23:16]) 0x0000 rw 0xf3a6 ftdm_out38 ftdm mapping for the serial outputs (port 3, channel 1 , bits [15:8]) 0x0000 rw 0xf3a7 ftdm_out39 ftdm mapping for the serial outputs (port 3, channel 1, bits [7:0]) 0x0000 rw 0xf3a8 ftdm_out40 ftdm mapping for the serial outputs (port 3, channel 2, bits [31:24]) 0x0000 rw 0xf3a9 ftdm_out41 ftdm mapping for th e serial outputs (port 3, channel 2, bits [23:16]) 0x0000 rw 0xf3aa ftdm_out42 ftdm mapping for the serial outputs (port 3, channel 2, bits [15:8]) 0x0000 rw 0xf3ab ftdm_out43 ftdm mapping for the serial outputs (port 3, channel 2, bits [7:0]) 0x0000 rw 0x f3ac ftdm_out44 ftdm mapping for the serial outputs (port 3, channel 3, bits [31:24]) 0x0000 rw 0xf3ad ftdm_out45 ftdm mapping for the serial outputs (port 3, channel 3, bits [23:16]) 0x0000 rw 0xf3ae ftdm_out46 ftdm mapping for the serial outputs (port 3, channel 3, bits [15:8]) 0x0000 rw 0xf3af ftdm_out47 ftdm mapping for the serial outputs (port 3, channel 3, bits [7:0]) 0x0000 rw 0xf3b0 ftdm_out48 ftdm mapping for the serial outputs (port 3, channel 4, bits [31:24]) 0x0000 rw 0xf3b1 ftdm_out49 ftdm mapp ing for the serial outputs (port 3, channel 4, bits [23:16]) 0x0000 rw 0xf3b2 ftdm_out50 ftdm mapping for the serial outputs (port 3, channel 4, bits [15:8]) 0x0000 rw 0xf3b3 ftdm_out51 ftdm mapping for the serial outputs (port 3, channel 4, bits [7:0]) 0x0 000 rw 0xf3b4 ftdm_out52 ftdm mapping for the serial outputs (port 3, channel 5, bits [31:24]) 0x0000 rw 0xf3b5 ftdm_out53 ftdm mapping for the serial outputs (port 3, channel 5, bits [23:16]) 0x0000 rw 0xf3b6 ftdm_out54 ftdm mapping for the serial output s (port 3, channel 5, bits [15:8]) 0x0000 rw 0xf3b7 ftdm_out55 ftdm mapping for the serial outputs (port 3, channel 5, bits [7:0]) 0x0000 rw 0xf3b8 ftdm_out56 ftdm mapping for the serial outputs (port 3, channel 6, bits [31:24]) 0x0000 rw 0xf3b9 ftdm_out57 ftdm mapping for the serial outputs (port 3, channel 6, bits [23:16]) 0x0000 rw 0xf3ba ftdm_out58 ftdm mapping for the serial outputs (port 3, channel 6, bits [15:8]) 0x0000 rw 0xf3bb ftdm_out59 ftdm mapping for the serial outputs (port 3, channel 6, b its [7:0]) 0x0000 rw 0xf3bc ftdm_out60 ftdm mapping for the serial outputs (port 3, channel 7, bits [31:24]) 0x0000 rw 0xf3bd ftdm_out61 ftdm mapping for the serial outputs (port 3, channel 7, bits [23:16]) 0x0000 rw 0xf3be ftdm_out62 ftdm mapping for the ser ial outputs (port 3, channel 7, bits [15:8]) 0x0000 rw 0xf3bf ftdm_out63 ftdm mapping for the serial outputs (port 3, channel 7, bits [7:0]) 0x0000 rw 0xf400 hibernate hibernate s etting 0x0000 rw 0xf401 start_pulse start pulse selection 0x0002 rw 0xf402 start_core instruction to start the core 0x0000 rw 0xf403 kill_core instruction to stop the core 0x0000 rw 0xf404 start_address start address of the program 0x0000 rw 0xf405 core_status core s tatus 0x0000 r 0xf421 panic_clear clear the panic manager 0x 0000 rw 0xf422 panic_parity_mask panic p arity 0x0003 rw 0xf423 panic_software_mask panic mask 0 0x0000 rw 0xf424 panic_wd_mask panic mask 1 0x0000 rw rev. c | page 87 of 180
adau1452/adau1451/adau1450 data sheet address register name description reset rw 0xf425 panic_stack_mask panic mask 2 0x0000 rw 0xf426 panic_loop_mask panic mask 3 0x0000 rw 0xf427 panic_flag panic f lag 0x0000 r 0xf428 panic_code panic c ode 0x0000 r 0xf432 execute_count execute stage error program count 0x0000 r 0xf443 watchdog_maxcount watchdog maximum count 0x0000 rw 0xf444 watchdog_prescale watchdog pres cale 0x0000 rw 0xf450 blockint_en enable block interrupts 0x0000 rw 0xf451 blockint_value value for the block interrupt counter 0x0000 rw 0xf460 prog_cntr0 program c ounter , bits [23:16] 0x0000 r 0xf461 prog_cntr1 program c ounter , bits [15:0] 0x0000 r 0xf462 prog_cntr_clear pr ogram counter c lear 0x0000 rw 0xf463 prog_cntr_length0 program counter l ength , bits [23:16] 0x0000 r 0xf464 prog_cntr_length1 program counter length, bits [15:0] 0x0000 r 0xf465 prog_cntr_maxlength0 program counter max length, bits [23:16] 0x0000 r 0xf466 prog_cntr_maxlength1 program counter max l ength , bits [15:0] 0x0000 r 0xf510 mp0_mode multipurpose pin mode (ss_m/mp0) 0x0000 rw 0xf511 mp1_mode multipurpose pin mode (mosi_m/mp1) 0x0000 rw 0xf512 mp2_mode multipurpose pin mode (scl_m/sclk_m/mp2) 0x0000 rw 0xf513 mp3_mode multipurpose pin mode (sda_m,miso_m/mp3) 0x0000 rw 0xf514 mp4_mode multipurpose pin mode (lrclk_out0/mp4) 0x0000 rw 0xf515 mp5_mode multipurpose pin mode (lrclk_out1/mp5) 0x0000 rw 0xf516 mp6_mode multipurpose pin mode (mp6) 0x0000 rw 0xf517 mp7_mode multipurpose pin mode (mp7) 0x0000 rw 0xf518 mp8_mode multipurpose pin mode (lrclk_out2/mp8) 0x0000 rw 0xf519 mp9_mode multipurpose pin mode (lrclk_out3/mp9) 0x0000 rw 0xf51a mp10_mode multipurpose pin mode (lrclk_in0/mp10) 0x0000 rw 0xf51b mp11_mode multipurpose pin mode (lrclk_in1/mp11) 0x0000 rw 0xf51c mp12_mode multipurpose pin mode (lrclk_in2/mp12) 0x0000 rw 0xf51d mp13_mode multipurpose pin mode (lrclk_in3/mp13) 0x0000 rw 0xf520 mp0_write multipurpose pin write value (ss_m/m p0) 0x0000 rw 0xf521 mp1_write multipurpose pin write value (mosi_m/mp1) 0x0000 rw 0xf522 mp2_write multipurpose pin write value scl_m/sclk_m/mp2) 0x0000 rw 0xf523 mp3_write multipurpose pin write value (sda_m,miso_m/mp3) 0x0000 rw 0xf524 mp4_write mul tipurpose pin write value (lrclk_out0/mp4) 0x0000 rw 0xf525 mp5_write multipurpose pin write value (lrclk_out1/mp5) 0x0000 rw 0xf526 mp6_write multipurpose pin write value (mp6) 0x0000 rw 0xf527 mp7_write multipurpose pin write value (mp7) 0x0000 rw 0x f528 mp8_write multipurpose pin write value (lrclk_out2/mp8) 0x0000 rw 0xf529 mp9_write multipurpose pin write value (lrclk_out3/mp9) 0x0000 rw 0xf52a mp10_write multipurpose pin write value (lrclk_in0/mp10) 0x0000 rw 0xf52b mp11_write multipurpose pin write value (lrclk_in1/mp11) 0x0000 rw 0xf52c mp12_write multipurpose pin write value (lrclk_in2/mp12) 0x0000 rw 0xf52d mp13_write multipurpose pin write value (lrclk_in3/mp13) 0x0000 rw 0xf530 mp0_read multipurpose pin read value (ss_m/mp0) 0x0000 r 0 xf531 mp1_read multipurpose pin read value (mosi_m/mp1) 0x0000 r 0xf532 mp2_read multipurpose pin read value (scl_m/sclk_m/mp2) 0x0000 r 0xf533 mp3_read multipurpose pin read value (sda_m,miso_m/mp3) 0x0000 r 0xf534 mp4_read multipurpose pin read value (lrclk_out0/mp4) 0x0000 r 0xf535 mp5_read multipurpose pin read value (lrclk_out1/mp5) 0x0000 r 0xf536 mp6_read multipurpose pin read value (mp6) 0x0000 r 0xf537 mp7_read multipurpose pin read value (mp7) 0x0000 r 0xf538 mp8_read multipurpose pin read value (lrclk_out2/mp8) 0x0000 r 0xf539 mp9_read multipurpose pin read value (lrclk_out3/mp9) 0x0000 r rev. c | page 88 of 180
data sheet adau1452/adau1451/adau1450 address register name description reset rw 0xf53a mp10_read multipurpose pin read value (lrclk_in0/mp10) 0x0000 r 0xf53b mp11_read multipurpose pin read value (lrclk_in1/mp11) 0x0000 r 0xf53c m p12_read multipurpose pin read value (lrclk_in2/mp12) 0x0000 r 0xf53d mp13_read multipurpose pin read value (lrclk_in3/mp13) 0x0000 r 0xf560 dmic_ctrl0 digital pdm microphone control (channel 0 and channel 1) 0x4000 rw 0xf561 dmic_ctrl1 digital pdm micr ophone control (channel 2 and channel 3) 0x4000 rw 0xf580 asrc_lock asrc lock s tatus 0x0000 r 0xf581 asrc_mute asrc m ute 0x0000 rw 0xf582 asrc0_ratio asrc ratio ( asrc 0 , channel 0 and channel 1) 0x0000 r 0xf583 asrc1_ratio asrc ratio ( asrc 1 , channel 2 and channel 3) 0x0000 r 0xf584 asrc2_ratio a src ratio ( asrc 2 , channel 4 and channel 5) 0x0000 r 0xf585 asrc3_ratio asrc ratio ( asrc 3 , channel 6 and channel 7) 0x0000 r 0xf586 asrc4_ratio asrc ratio ( asrc 4 , channel 8 and channel 9) 0x0000 r 0xf587 a src5_ratio asrc ratio ( asrc 5 , channel 10 and channel 11) 0x0000 r 0xf588 asrc6_ratio asrc ratio ( asrc 6 , channel 12 and channel 13) 0x0000 r 0xf589 asrc7_ratio asrc ratio ( asrc 7 , channel 14 and channel 15) 0x0000 r 0xf5a0 adc_read0 auxiliary adc read v alue (auxadc0) 0x0000 r 0xf5a1 adc_read1 auxiliary adc read value (auxadc1) 0x0000 r 0xf5a2 adc_read2 auxiliary adc read value (auxadc2) 0x0000 r 0xf5a3 adc_read3 auxiliary adc read value (auxadc3) 0x0000 r 0xf5a4 adc_read4 auxiliary adc read value (a uxadc4) 0x0000 r 0xf5a5 adc_read5 auxiliary adc read value (auxadc5) 0x0000 r 0xf600 spdif_lock_det s/pdif receiver lock bit d etection 0x0000 r 0xf601 spdif_rx_ctrl s/pdif receiver c ontrol 0x0000 rw 0xf602 spdif_rx_decode decoded signals from the s/pdi f r eceiver 0x0000 r 0xf603 spdif_rx_comprmode compression m ode f rom the s/pdif r eceiver 0x0000 r 0xf604 spdif_restart automatically r esume s/pdif r eceiver a udio i nput 0x0000 rw 0xf605 spdif_loss_of_lock s/pdif receiver loss of lock detection 0x0000 r 0 xf608 spdif_aux_en s/pdif receiver auxiliary outputs enable 0x0000 rw 0xf60f spdif_rx_auxbit_ready s/pdif receiver auxiliary bits ready flag 0x0000 r 0xf610 spdif_rx_cs_left_0 s/pdif receiver channel status bits (left) 0x0000 r 0xf611 spdif_rx_cs_left_1 s/pdif receiver channel status bits (left) 0x0000 r 0xf612 spdif_rx_cs_left_2 s/pdif receiver channel status bits (left) 0x0000 r 0xf613 spdif_rx_cs_left_3 s/pdif receiver channel status bits (left) 0x0000 r 0xf614 spdif_rx_cs_left_4 s/pdif receiver ch annel status bits (left) 0x0000 r 0xf615 spdif_rx_cs_left_5 s/pdif receiver channel status bits (left) 0x0000 r 0xf616 spdif_rx_cs_left_6 s/pdif receiver channel status bits (left) 0x0000 r 0xf617 spdif_rx_cs_left_7 s/pdif receiver channel status bits ( left) 0x0000 r 0xf618 spdif_rx_cs_left_8 s/pdif receiver channel status bits (left) 0x0000 r 0xf619 spdif_rx_cs_left_9 s/pdif receiver channel status bits (left) 0x0000 r 0xf61a spdif_rx_cs_left_10 s/pdif receiver channel status bits (left) 0x0000 r 0x f61b spdif_rx_cs_left_11 s/pdif receiver channel status bits (left) 0x0000 r 0xf620 spdif_rx_cs_right_0 s/pdif receiver channel status bits (right) 0x0000 r 0xf621 spdif_rx_cs_right_1 s/pdif receiver channel status bits (right) 0x0000 r 0xf622 spdif_rx_ cs_right_2 s/pdif receiver channel status bits (right) 0x0000 r 0xf623 spdif_rx_cs_right_3 s/pdif receiver channel status bits (right) 0x0000 r 0xf624 spdif_rx_cs_right_4 s/pdif receiver channel status bits (right) 0x0000 r 0xf625 spdif_rx_cs_right_5 s/ pdif receiver channel status bits (right) 0x0000 r 0xf626 spdif_rx_cs_right_6 s/pdif receiver channel status bits (right) 0x0000 r 0xf627 spdif_rx_cs_right_7 s/pdif receiver channel status bits (right) 0x0000 r 0xf628 spdif_rx_cs_right_8 s/pdif receiver channel status bits (right) 0x0000 r 0xf629 spdif_rx_cs_right_9 s/pdif receiver channel status bits (right) 0x0000 r 0xf62a spdif_rx_cs_right_10 s/pdif receiver channel status bits (right) 0x0000 r 0xf62b spdif_rx_cs_right_11 s/pdif receiver channel st atus bits (right) 0x0000 r rev. c | page 89 of 180
adau1452/adau1451/adau1450 data sheet address register name description reset rw 0xf630 spdif_rx_ud_left_0 s/pdif receiver user data bits (left) 0x0000 r 0xf631 spdif_rx_ud_left_1 s/pdif receiver user data bits (left) 0x0000 r 0xf632 spdif_rx_ud_left_2 s/pdif receiver user data bits (left) 0x0000 r 0xf633 spdif_rx_ud_left_3 s/pdif receiver user data bits (left) 0x0000 r 0xf634 spdif_rx_ud_left_4 s/pdif receiver user data bits (left) 0x0000 r 0xf635 spdif_rx_ud_left_5 s/pdif receiver user data bits (left) 0x0000 r 0xf636 spdif_rx_ud_left_6 s/pdif receive r user data bits (left) 0x0000 r 0xf637 spdif_rx_ud_left_7 s/pdif receiver user data bits (left) 0x0000 r 0xf638 spdif_rx_ud_left_8 s/pdif receiver user data bits (left) 0x0000 r 0xf639 spdif_rx_ud_left_9 s/pdif receiver user data bits (left) 0x0000 r 0xf63a spdif_rx_ud_left_10 s/pdif receiver user data bits (left) 0x0000 r 0xf63b spdif_rx_ud_left_11 s/pdif receiver user data bits (left) 0x0000 r 0xf640 spdif_rx_ud_right_0 s/pdif receiver user data bits (right) 0x0000 r 0xf641 spdif_rx_ud_right_1 s/p dif receiver user data bits (right) 0x0000 r 0xf642 spdif_rx_ud_right_2 s/pdif receiver user data bits (right) 0x0000 r 0xf643 spdif_rx_ud_right_3 s/pdif receiver user data bits (right) 0x0000 r 0xf644 spdif_rx_ud_right_4 s/pdif receiver user data bits (right) 0x0000 r 0xf645 spdif_rx_ud_right_5 s/pdif receiver user data bits (right) 0x0000 r 0xf646 spdif_rx_ud_right_6 s/pdif receiver user data bits (right) 0x0000 r 0xf647 spdif_rx_ud_right_7 s/pdif receiver user data bits (right) 0x0000 r 0xf648 spd if_rx_ud_right_8 s/pdif receiver user data bits (right) 0x0000 r 0xf649 spdif_rx_ud_right_9 s/pdif receiver user data bits (right) 0x0000 r 0xf64a spdif_rx_ud_right_10 s/pdif receiver user data bits (right) 0x0000 r 0xf64b spdif_rx_ud_right_11 s/pdif re ceiver user data bits (right) 0x0000 r 0xf650 spdif_rx_vb_left_0 s/pdif receiver validity bits (left) 0x0000 r 0xf651 spdif_rx_vb_left_1 s/pdif receiver validity bits (left) 0x0000 r 0xf652 spdif_rx_vb_left_2 s/pdif receiver validity bits (left) 0x0000 r 0xf653 spdif_rx_vb_left_3 s/pdif receiver validity bits (left) 0x0000 r 0xf654 spdif_rx_vb_left_4 s/pdif receiver validity bits (left) 0x0000 r 0xf655 spdif_rx_vb_left_5 s/pdif receiver validity bits (left) 0x0000 r 0xf656 spdif_rx_vb_left_6 s/pdif r eceiver validity bits (left) 0x0000 r 0xf657 spdif_rx_vb_left_7 s/pdif receiver validity bits (left) 0x0000 r 0xf658 spdif_rx_vb_left_8 s/pdif receiver validity bits (left) 0x0000 r 0xf659 spdif_rx_vb_left_9 s/pdif receiver validity bits (left) 0x0000 r 0xf65a spdif_rx_vb_left_10 s/pdif receiver validity bits (left) 0x0000 r 0xf65b spdif_rx_vb_left_11 s/pdif receiver validity bits (left) 0x0000 r 0xf660 spdif_rx_vb_right_0 s/pdif receiver validity bits (right) 0x0000 r 0xf661 spdif_rx_vb_right_1 s/pd if receiver validity bits (right) 0x0000 r 0xf662 spdif_rx_vb_right_2 s/pdif receiver validity bits (right) 0x0000 r 0xf663 spdif_rx_vb_right_3 s/pdif receiver validity bits (right) 0x0000 r 0xf664 spdif_rx_vb_right_4 s/pdif receiver validity bits (righ t) 0x0000 r 0xf665 spdif_rx_vb_right_5 s/pdif receiver validity bits (right) 0x0000 r 0xf666 spdif_rx_vb_right_6 s/pdif receiver validity bits (right) 0x0000 r 0xf667 spdif_rx_vb_right_7 s/pdif receiver validity bits (right) 0x0000 r 0xf668 spdif_rx_vb _right_8 s/pdif receiver validity bits (right) 0x0000 r 0xf669 spdif_rx_vb_right_9 s/pdif receiver validity bits (right) 0x0000 r 0xf66a spdif_rx_vb_right_10 s/pdif receiver validity bits (right) 0x0000 r 0xf66b spdif_rx_vb_right_11 s/pdif receiver vali dity bits (right) 0x0000 r 0xf670 spdif_rx_pb_left_0 s/pdif receiver parity bits (left) 0x0000 r 0xf671 spdif_rx_pb_left_1 s/pdif receiver parity bits (left) 0x0000 r 0xf672 spdif_rx_pb_left_2 s/pdif receiver parity bits (left) 0x0000 r 0xf673 spdif_rx _pb_left_3 s/pdif receiver parity bits (left) 0x0000 r 0xf674 spdif_rx_pb_left_4 s/pdif receiver parity bits (left) 0x0000 r 0xf675 spdif_rx_pb_left_5 s/pdif receiver parity bits (left) 0x0000 r rev. c | page 90 of 180
data sheet adau1452/adau1451/adau1450 address register name description reset rw 0xf676 spdif_rx_pb_left_6 s/pdif receiver parity bits (lef t) 0x0000 r 0xf677 spdif_rx_pb_left_7 s/pdif receiver parity bits (left) 0x0000 r 0xf678 spdif_rx_pb_left_8 s/pdif receiver parity bits (left) 0x0000 r 0xf679 spdif_rx_pb_left_9 s/pdif receiver parity bits (left) 0x0000 r 0xf67a spdif_rx_pb_left_10 s/p dif receiver parity bits (left) 0x0000 r 0xf67b spdif_rx_pb_left_11 s/pdif receiver parity bits (left) 0x0000 r 0xf680 spdif_rx_pb_right_0 s/pdif receiver parity bits (right) 0x0000 r 0xf681 spdif_rx_pb_right_1 s/pdif receiver parity bits (right) 0x0000 r 0xf682 spdif_rx_pb_right_2 s/pdif receiver parity bits (right) 0x0000 r 0xf683 spdif_rx_pb_right_3 s/pdif receiver parity bits (right) 0x0000 r 0xf684 spdif_rx_pb_right_4 s/pdif receiver parity bits (right) 0x0000 r 0xf685 spdif_rx_pb_right_5 s/pdif receiver parity bits (right) 0x0000 r 0xf686 spdif_rx_pb_right_6 s/pdif receiver parity bits (right) 0x0000 r 0xf687 spdif_rx_pb_right_7 s/pdif receiver parity bits (right) 0x0000 r 0xf688 spdif_rx_pb_right_8 s/pdif receiver parity bits (right) 0x0000 r 0xf689 spdif_rx_pb_right_9 s/pdif receiver parity bits (right) 0x0000 r 0xf68a spdif_rx_pb_right_10 s/pdif receiver parity bits (right) 0x0000 r 0xf68b spdif_rx_pb_right_11 s/pdif receiver parity bits (right) 0x0000 r 0xf690 spdif_tx_en s/pdif transm itter enable 0x0000 rw 0xf691 spdif_tx_ctrl s/pdif transmitter control 0x0000 rw 0xf69f spdif_tx_auxbit_source s/pdif transmitter auxiliary bits source select 0x0000 rw 0xf6a0 spdif_tx_cs_left_0 s/pdif transmitter channel status bits (left) 0x0000 rw 0 xf6a1 spdif_tx_cs_left_1 s/pdif transmitter channel status bits (left) 0x0000 rw 0xf6a2 spdif_tx_cs_left_2 s/pdif transmitter channel status bits (left) 0x0000 rw 0xf6a3 spdif_tx_cs_left_3 s/pdif transmitter channel status bits (left) 0x0000 rw 0xf6a4 s pdif_tx_cs_left_4 s/pdif transmitter channel status bits (left) 0x0000 rw 0xf6a5 spdif_tx_cs_left_5 s/pdif transmitter channel status bits (left) 0x0000 rw 0xf6a6 spdif_tx_cs_left_6 s/pdif transmitter channel status bits (left) 0x0000 rw 0xf6a7 spdif_tx _cs_left_7 s/pdif transmitter channel status bits (left) 0x0000 rw 0xf6a8 spdif_tx_cs_left_8 s/pdif transmitter channel status bits (left) 0x0000 rw 0xf6a9 spdif_tx_cs_left_9 s/pdif transmitter channel status bits (left) 0x0000 rw 0xf6aa spdif_tx_cs_lef t_10 s/pdif transmitter channel status bits (left) 0x0000 rw 0xf6ab spdif_tx_cs_left_11 s/pdif transmitter channel status bits (left) 0x0000 rw 0xf6b0 spdif_tx_cs_right_0 s/pdif transmitter channel status bits (right) 0x0000 rw 0xf6b1 spdif_tx_cs_right_ 1 s/pdif transmitter channel status bits (right) 0x0000 rw 0xf6b2 spdif_tx_cs_right_2 s/pdif transmitter channel status bits (right) 0x0000 rw 0xf6b3 spdif_tx_cs_right_3 s/pdif transmitter channel status bits (right) 0x0000 rw 0xf6b4 spdif_tx_cs_right_4 s/pdif transmitter channel status bits (right) 0x0000 rw 0xf6b5 spdif_tx_cs_right_5 s/pdif transmitter channel status bits (right) ) 0x0000 rw 0xf6b6 spdif_tx_cs_right_6 s/pdif transmitter channel status bits (right) ) 0x0000 rw 0xf6b7 spdif_tx_cs_right_ 7 s/pdif transmitter channel status bits (right) 0x0000 rw 0xf6b8 spdif_tx_cs_right_8 s/pdif transmitter channel status bits (right) 0x0000 rw 0xf6b9 spdif_tx_cs_right_9 s/pdif transmitter channel status bits (right) 0x0000 rw 0xf6ba spdif_tx_cs_right_1 0 s/pdif transmitter channel status bits (right) 0x0000 rw 0xf6bb spdif_tx_cs_right_11 s/pdif transmitter channel status bits (right) 0x0000 rw 0xf6c0 spdif_tx_ud_left_0 s/pdif transmitter user data bits (left) 0x0000 rw 0xf6c1 spdif_tx_ud_left_1 s/pdif transmitter user data bits (left) 0x0000 rw 0xf6c2 spdif_tx_ud_left_2 s/pdif transmitter user data bits (left) 0x0000 rw 0xf6c3 spdif_tx_ud_left_3 s/pdif transmitter user data bits (left) 0x0000 rw 0xf6c4 spdif_tx_ud_left_4 s/pdif transmitter user data bits (left) 0x0000 rw 0xf6c5 spdif_tx_ud_left_5 s/pdif transmitter user data bits (left) 0x0000 rw 0xf6c6 spdif_tx_ud_left_6 s/pdif transmitter user data bits (left) 0x0000 rw 0xf6c7 spdif_tx_ud_left_7 s/pdif transmitter user data bits (left) 0x0000 rw 0xf6c8 spdif_tx_ud_left_8 s/pdif transmitter user data bits (left) 0x0000 rw rev. c | page 91 of 180
adau1452/adau1451/adau1450 data sheet address register name description reset rw 0xf6c9 spdif_tx_ud_left_9 s/pdif transmitter user data bits (left) 0x0000 rw 0xf6ca spdif_tx_ud_left_10 s/pdif transmitter user data bits (left) ) 0x0000 rw 0xf6cb spdif_tx_ud _left_11 s/pdif transmitter user data bits (left) 0x0000 rw 0xf6d0 spdif_tx_ud_right_0 s/pdif transmitter user data bits (right) 0x0000 rw 0xf6d1 spdif_tx_ud_right_1 s/pdif transmitter user data bits (right) 0x0000 rw 0xf6d2 spdif_tx_ud_right_2 s/pdif t ransmitter user data bits (right) 0x0000 rw 0xf6d3 spdif_tx_ud_right_3 s/pdif transmitter user data bits (right) 0x0000 rw 0xf6d4 spdif_tx_ud_right_4 s/pdif transmitter user data bits (right) 0x0000 rw 0xf6d5 spdif_tx_ud_right_5 s/pdif transmitter user data bits (right) 0x0000 rw 0xf6d6 spdif_tx_ud_right_6 s/pdif transmitter user data bits (right) 0x0000 rw 0xf6d7 spdif_tx_ud_right_7 s/pdif transmitter user data bits (right) 0x0000 rw 0xf6d8 spdif_tx_ud_right_8 s/pdif transmitter user data bits (right ) 0x0000 rw 0xf6d9 spdif_tx_ud_right_9 s/pdif transmitter user data bits (right) 0x0000 rw 0xf6da spdif_tx_ud_right_10 s/pdif transmitter user data bits (right) 0x0000 rw 0xf6db spdif_tx_ud_right_11 s/pdif transmitter user data bits (right) 0x0000 rw 0 xf6e0 spdif_tx_vb_left_0 s/pdif transmitter validity bits (left) 0x0000 rw 0xf6e1 spdif_tx_vb_left_1 s/pdif transmitter validity bits (left) 0x0000 rw 0xf6e2 spdif_tx_vb_left_2 s/pdif transmitter validity bits (left) 0x0000 rw 0xf6e3 spdif_tx_vb_left_3 s/pdif transmitter validity bits (left) 0x0000 rw 0xf6e4 spdif_tx_vb_left_4 s/pdif transmitter validity bits (left) 0x0000 rw 0xf6e5 spdif_tx_vb_left_5 s/pdif transmitter validity bits (left) 0x0000 rw 0xf6e6 spdif_tx_vb_left_6 s/pdif transmitter validi ty bits (left) 0x0000 rw 0xf6e7 spdif_tx_vb_left_7 s/pdif transmitter validity bits (left) 0x0000 rw 0xf6e8 spdif_tx_vb_left_8 s/pdif transmitter validity bits (left) 0x0000 rw 0xf6e9 spdif_tx_vb_left_9 s/pdif transmitter validity bits (left) 0x0000 rw 0xf6ea spdif_tx_vb_left_10 s/pdif transmitter validity bits (left) 0x0000 rw 0xf6eb spdif_tx_vb_left_11 s/pdif transmitter validity bits (left) 0x0000 rw 0xf6f0 spdif_tx_vb_right_0 s/pdif transmitter validity bits (right) 0x0000 rw 0xf6f1 spdif_tx_vb_r ight_1 s/pdif transmitter validity bits (right) 0x0000 rw 0xf6f2 spdif_tx_vb_right_2 s/pdif transmitter validity bits (right) 0x0000 rw 0xf6f3 spdif_tx_vb_right_3 s/pdif transmitter validity bits (right) 0x0000 rw 0xf6f4 spdif_tx_vb_right_4 s/pdif trans mitter validity bits (right) 0x0000 rw 0xf6f5 spdif_tx_vb_right_5 s/pdif transmitter validity bits (right) 0x0000 rw 0xf6f6 spdif_tx_vb_right_6 s/pdif transmitter validity bits (right) 0x0000 rw 0xf6f7 spdif_tx_vb_right_7 s/pdif transmitter validity bit s (right) 0x0000 rw 0xf6f8 spdif_tx_vb_right_8 s/pdif transmitter validity bits (right) 0x0000 rw 0xf6f9 spdif_tx_vb_right_9 s/pdif transmitter validity bits (right) 0x0000 rw 0xf6fa spdif_tx_vb_right_10 s/pdif transmitter validity bits (right) 0x0000 r w 0xf6fb spdif_tx_vb_right_11 s/pdif transmitter validity bits (right) 0x0000 rw 0xf700 spdif_tx_pb_left_0 s/pdif transmitter parity bits (left) 0x0000 rw 0xf701 spdif_tx_pb_left_1 s/pdif transmitter parity bits (left) 0x0000 rw 0xf702 spdif_tx_pb_left _2 s/pdif transmitter parity bits (left) 0x0000 rw 0xf703 spdif_tx_pb_left_3 s/pdif transmitter parity bits (left) 0x0000 rw 0xf704 spdif_tx_pb_left_4 s/pdif transmitter parity bits (left) 0x0000 rw 0xf705 spdif_tx_pb_left_5 s/pdif transmitter parity bi ts (left) 0x0000 rw 0xf706 spdif_tx_pb_left_6 s/pdif transmitter parity bits (left) 0x0000 rw 0xf707 spdif_tx_pb_left_7 s/pdif transmitter parity bits (left) 0x0000 rw 0xf708 spdif_tx_pb_left_8 s/pdif transmitter parity bits (left) 0x0000 rw 0xf709 spd if_tx_pb_left_9 s/pdif transmitter parity bits (left) 0x0000 rw 0xf70a spdif_tx_pb_left_10 s/pdif transmitter parity bits (left) 0x0000 rw 0xf70b spdif_tx_pb_left_11 s/pdif transmitter parity bits (left) 0x0000 rw 0xf710 spdif_tx_pb_right_0 s/pdif trans mitter parity bits (right) 0x0000 rw 0xf711 spdif_tx_pb_right_1 s/pdif transmitter parity bits (right) 0x0000 rw 0xf712 spdif_tx_pb_right_2 s/pdif transmitter parity bits (right) 0x0000 rw rev. c | page 92 of 180
data sheet adau1452/adau1451/adau1450 address register name description reset rw 0xf713 spdif_tx_pb_right_3 s/pdif transmitter parity bits (right ) 0x0000 rw 0xf714 spdif_tx_pb_right_4 s/pdif transmitter parity bits (right) 0x0000 rw 0xf715 spdif_tx_pb_right_5 s/pdif transmitter parity bits (right) 0x0000 rw 0xf716 spdif_tx_pb_right_6 s/pdif transmitter parity bits (right) 0x0000 rw 0xf717 spdif _tx_pb_right_7 s/pdif transmitter parity bits (right) 0x0000 rw 0xf718 spdif_tx_pb_right_8 s/pdif transmitter parity bits (right) 0x0000 rw 0xf719 spdif_tx_pb_right_9 s/pdif transmitter parity bits (right) 0x0000 rw 0xf71a spdif_tx_pb_right_10 s/pdif tr ansmitter parity bits (right) 0x0000 rw 0xf71b spdif_tx_pb_right_11 s/pdif transmitter parity bits (right) 0x0000 rw 0xf780 bclk_in0_pin bclk input pins drive strength and slew rate (bclk_in0) 0x0018 rw 0xf781 bclk_in1_pin bclk input pins drive strength and slew rate (bclk_in1) 0x0018 rw 0xf782 bclk_in2_pin bclk input pins drive strength and slew rate (bclk_in2) 0x0018 rw 0xf783 bclk_in3_pin bclk input pins drive strength and slew rate (bclk_in3) 0x0018 rw 0xf784 bclk_out0_pin bclk output pins drive s trength and slew rate (bclk_out0) 0x0018 rw 0xf785 bclk_out1_pin bclk output pins drive strength and slew rate (bclk_out1) 0x0018 rw 0xf786 bclk_out2_pin bclk output pins drive strength and slew rate (bclk_out2) 0x0018 rw 0xf787 bclk_out3_pin bclk outpu t pins drive strength and slew rate (bclk_out3) 0x0018 rw 0xf788 lrclk_in0_pin lrclk input pins drive strength and slew rate (lrclk_in0) 0x0018 rw 0xf789 lrclk_in1_pin lrclk input pins drive strength and slew rate (lrclk_in1) 0x0018 rw 0xf78a lrclk_in2_ pin lrclk input pins drive strength and slew rate lrclk_in2) 0x0018 rw 0xf78b lrclk_in3_pin lrclk input pins drive strength and slew rate (lrclk_in3) 0x0018 rw 0xf78c lrclk_out0_pin lrclk output pins drive strength and slew rate (lrclk_out0) 0x0018 rw 0 xf78d lrclk_out1_pin lrclk output pins drive strength and slew rate (lrclk_out1) 0x0018 rw 0xf78e lrclk_out2_pin lrclk output pins drive strength and slew rate (lrclk_out2) 0x0018 rw 0xf78f lrclk_out3_pin lrclk output pins drive strength and slew rate (l rclk_out3) 0x0018 rw 0xf790 sdata_in0_pin sdata input pins drive strength and slew rate (sdata_in0) 0x0018 rw 0xf791 sdata_in1_pin sdata input pins drive strength and slew rate (sdata_in1) 0x0018 rw 0xf792 sdata_in2_pin sdata input pins drive strength a nd slew rat e (sdata_in2) 0x0018 rw 0xf793 sdata_in3_pin sdata input pins drive strength and slew rate (sdata_in3) 0x0018 rw 0xf794 sdata_out0_pin sdata output pins drive strength and slew rate (sdata_out0) 0x0008 rw 0xf795 sdata_out1_pin sdata output pi ns drive strength and slew rate (sdata_out1) 0x0008 rw 0xf796 sdata_out2_pin sdata output pins drive strength and slew rate (sdata_out2) 0x0008 rw 0xf797 sdata_out3_pin sdata output pins drive strength and slew rate (sdata_out3) 0x0008 rw 0xf798 spdif_t x_pin s/pdif t ransmitter pin drive strength and slew rate 0x0008 rw 0xf799 sclk_scl_pin sclk/scl p in drive strength and slew rate 0x0008 rw 0xf79a miso_sda_pin miso/sda p in drive strength and slew rate 0x0008 rw 0xf79b ss_pin ss/addr0 p in drive strength and slew rate 0x0018 rw 0xf79c mosi_addr1_pin mosi/addr1 p in drive strength and slew rate 0x0018 rw 0xf79d sclk_scl_m_pin scl_m/sclk_m/mp2 pin drive strength and slew rate 0x0008 rw 0xf79e miso_sda_m_pin sda_m/miso_m/mp3 pin drive strength and slew rat e 0x0008 rw 0xf79f ss_m_pin ss_m/mp0 pin drive strength and slew rate 0x0018 rw 0xf7a0 mosi_m_pin mosi_m/mp1 pin drive strength and slew rate 0x0018 rw 0xf7a1 mp6_pin mp6 pin drive strength and slew rate 0x0018 rw 0xf7a2 mp7_pin mp7 pin drive strength and slew rate 0x0018 rw 0xf7a3 clkout_pin clkout pin drive strength and slew rate 0x0008 rw 0xf890 soft_reset soft r eset 0x0001 rw rev. c | page 93 of 180
adau1452/adau1451/adau1450 data sheet control register details pll configuration re gisters pll feedback divider register address: 0xf000, reset: 0x0060, name: pll_ctrl0 this register is the value of the feedback divider in the pll. this value effectively multiplies the frequency of the input clock to the pll, creating the output system clock, which clocks the dsp core and other digital circuit blocks. the format of the value stored in this register is binary integer in 7.0 format. for example, the default feedback divider value of 96 is stored as 0x60. the value written t o this register does not take effect until register 0xf003 ( pll_enable ), bit 0 ( pll_enable ) c hanges state from 0b0 to 0b1. table 65 . bit descriptions for pll_ctrl0 bits bit name settings description reset access [15:7] reserved 0x0 rw [6:0] pll_fbdivider pll feedback divider. this is the value of the feedback divider i n the pll, which effectively multiplies the frequency of the input clock to the pll, creating the output system clock, which clocks the dsp core and other digital circuit blocks. the format of the value stored in this register is binary integer in 7.0 f orm at. for example, the default feedback divider value of 96 is stored as 0x60. 0x60 rw pll prescale d ivider register address: 0xf001, reset: 0x0000, name: pll_ctrl1 t his register sets the input pre scale divider for the pll. the value written to this regist er does not take effect until register 0xf003 (pll_enable), bit 0 (pll_enable) changes state from 0b0 to 0b1. table 66 . bit descriptions for pll_ctrl1 bits bit name settings description reset access [15:2] reserved 0x0 rw [1:0] pll_div pl l input clock divider. this pre scale clock divider creates the pll input clock from the externally input master clock. the nominal frequency of the pll input is 3.072 mhz. therefore, if the input master clock frequency is 3.072 mhz, set the pre s cal e clock divider to divide by 1 . if the input cl ock is 12.288 mhz, set the pre scale c lock divider to divide by 4 . the goal is to make the input to the pll as close to 3.072 mhz as possible. 0x0 rw 00 divide by 1 01 divide by 2 10 divide by 4 11 divide by 8 rev. c | page 94 of 180
data sheet adau1452/adau1451/adau1450 pll clock source register address: 0xf002, reset: 0x0000, name: pll_clk_src this register selects the source of the clock used for input to the core and the clock generators. the clock can either be ta ken directly from the signal on the xtalin/mclk pin or from the output of the pll. in almost every case, the pll clock should be used. the value written to this register does not take effect until register 0xf003 ( pll_enable ), bit 0 ( pll_enable ) changes state from 0b0 to 0b1. table 67 . bit descriptions for pll_clk_src bits bit name settings description reset access [15:1] reserved 0x0 rw 0 clksrc clock source select. the pll output is nominally 294.912 mhz, which is the nominal operating frequency of the core and the clock generator inputs. in most use cases, do not use the direct xtalin/mclk input option because the range of allowable frequencies on the xtalin/mclk pin is has an upper limit that is significantly lower in frequency than the nominal system cloc k frequency. 0x0 rw 0 direct from xtalin/mclk pin 1 pll clock pll enable register address: 0xf003, reset: 0x0000, name: pll_enable this register enables or disables the pll. the pll does not attempt to lock to an incoming clock until bit 0 ( pll _enable ) is enabled. when bit 0 ( pll_enable ) is set to 0b0, the pll does not output a clock signal, causing all other clock circuits in the device that rely o n the pll to become idle. when bit 0 ( pll_enable ) transitions fr om 0b0 to 0b1, the settings in reg ister 0xf000 ( pll_ctrl0 ) , register 0xf001 ( pll_ctrl1 ) , register 0xf002 ( pll_clk_src ) , and register 0xf005 ( mclk_out ) are activated . table 68 . bit descriptions for pll_enable bits bit name settings description reset access [15:1] re served 0x0 rw 0 pll_enable pll enable. load the values of register 0xf000, register 0xf001, regi - ster 0xf002, and register 0xf005 when this bit transitions from 0b0 to 0b1. 0x0 rw 0 pll disabled 1 pll enabled rev. c | page 95 of 180
adau1452/adau1451/adau1450 data sheet pll lock register address: 0xf 004, reset: 0x0000, name: pll_lock this register contain s a flag that represents the lock status of the pll . lock status has four prerequisites: a stable input clock is being routed to the pll, the related pll registers ( register 0xf000 ( pll_ctrl0 ) , regist er 0xf001 ( pll_ctrl1 ) , and register 0xf002 ( pll_clk_src ) ) are set appropriately, the pll is enabled ( register 0xf003 ( pll_enable ), bit 0 ( pll_enable ) = 0b1) , and the pll has had adequate time to adjust its feedback path and provide a stable output clock to the rest of the device. the amount of time required to achieve lock to a new input clock signal varies based on system conditions, so bit 0 ( pll_lock ) provides a clear indication of when lock has been achieved. table 69 . bit descri ptions for pll_lock bits bit name settings description reset access [15:1] reserved 0x0 rw 0 pll_lock pll lock flag (read only). 0x0 r 0 pll unlocked 1 pll locked clkout control register address: 0xf005, reset: 0x0000, name: mclk_out this register enable s and configure s the signal output from the clkout pin. the value written to this register does not take effect until register 0xf003 ( pll_enable ), bit 0 ( pll_enable ) , changes state from 0b0 to 0b1. rev. c | page 96 of 180
data sheet adau1452/adau1451/adau1450 table 70 . bit desc riptions for mclk_out bits bit name settings description reset access [15:3] reserved 0x0 rw [2:1] clkout_rate frequency of clkout. frequency of the signal output from the clkout pin. these bits set the frequency of the signal on the clkout pin. the f requencies documented in table 70 are examples that are valid for a master clock input that is a binary multiple of 3.072 mhz. in this case, the options for output rates are 3.072 mhz, 6.144 mhz, 12.288 mhz, or 24. 576 mhz. if the input master clock is scaled down (for example, to a binary multiple of 2.8224 mhz ), the possible output rates are 2.8224 mhz, 5.6448 mhz, 11.2896 mhz, or 22.5792 mhz). 0x0 rw 00 pre divider output. this is 3.072 mhz for a nominal system clock of 294.912 mhz. 01 double the pre divider output. this is 6.144 mhz for a nominal system clock of 294.912 mhz. 10 four times the pre divider output. this is 12.288 mhz for a nominal system clock of 294.912 mhz. 11 eight times the pre divi der output. this is 24.576 mhz for a nominal system clock of 294.912 mhz. 0 clkout_enable clkout enable. when this bit is enabled, a clock signal is output from the clkout pin of the device. when disabled, the clkout pin is high impedance. 0x0 rw 0 clkout pin disabled 1 clkout pin enabled analog pll watchdog control register address: 0xf006, reset: 0x0001, name: pll_watchdog the pll watchdog is a feature that monitors the pll and automatically resets it in the event that it reaches an u nstab le condition. the pll reset s itself and automatically attempt s to lock to the incoming clock signal again, with the same settings as before. this functionality requires no intera ction on the part of the user. ensure that t he pll watchdog is enabled at all times. table 71 . bit descriptions for pll_watchdog bits bit name settings description reset access [15:1] reserved 0x0 rw 0 pll_watchdog pll watchdog. 0x1 rw 0 pll watchdog disabled 1 pll watchdog enabled rev. c | page 97 of 180
adau1452/adau1451/adau1450 data sheet clock gene rator registers denominator (m) for clock generator 1 register address: 0xf020, reset: 0x0006, name: clk_gen1_m the denominator (m) for clock generator 1. table 72 . bit descriptions for clk_gen1_m bits bit name settings description reset access [15:9] reserved 0x0 rw [8:0] clockgen1_m clock g enerator 1 m (denominator). format is binary integer. 0x006 rw numerator (n) for clock generator 1 register address: 0xf021, reset: 0x0001, name: clk_gen1_n the numerator (n) for clock gen erator 1. table 73 . bit descriptions for clk_gen1_n bits bit name settings description reset access [15:9] reserved 0x0 rw [8:0] clockgen1_n clock g enerator 1 n (numerator). format is binary integer. 0x001 rw denominator (m) for clock generator 2 register address: 0xf022, reset: 0x0009, name: clk_gen2_m the denominator (m) for clock generator 2. table 74 . bit descriptions for clk_gen2_m bits bit name settings description reset access [15:9] reserved 0x0 rw [8:0] clockgen2_m clock g enerator 2 m (denominator). format is binary integer. 0x009 rw rev. c | page 98 of 1 80
data sheet adau1452/adau1451/adau1450 numerator (n) for clock generator 2 register address: 0xf023, reset: 0x0001, name: clk_gen2_n the numerator (n) for clock generator 2. table 75 . bit descriptions for clk_gen2_n bits bit name settings description reset access [15:9] reserved 0x0 rw [8:0] clockgen2_n clock g enerator 2 n (numerator). format is binary integer. 0x001 rw denominator (m) for clock generator 3 register a ddress: 0xf024, reset: 0x0000, name: clk_gen3_m the denominator (m) for clock generator 3. table 76 . bit descriptions for clk_gen3_m bits bit name settings description reset access [15:0] clockgen3_m clock g enerator 3 m (denominat or). format is binary integer. 0x0000 rw numerator for (n) clock generator 3 register address: 0xf025, reset: 0x0000, name: clk_gen3_n the numerator (n) for clock generator 3. table 77 . bit descriptions for clk_gen3_n bits bit nam e settings description reset access [15:0] clockgen3_n clock g enerator 3 n (numerator). format is binary integer. 0x0000 rw rev. c | page 99 of 180
adau1452/adau1451/adau1450 data sheet input reference for clock generator 3 register address: 0xf026, reset: 0x000e, name: clk_gen3_src clock g enerator 3 can generate audio clocks using the pll output (system clock) as a reference, or it can optionally use a reference clock entering the device from an ex ternal source either on a multi purpose pin (mpx) or the s/pdif receiver. this register d etermines the source of the r eference signal. table 78 . bit descriptions for clk_gen3_src bits bit name settings description reset access [15:5] reserved 0x0 rw rev. c | page 100 of 180
data sheet adau1452/adau1451/adau1450 bits bit name settings description reset access 4 clk_gen3_src reference source for clock g enerator 3. th is bit selects the reference of clock g enerator 3. if set to use an external reference clock, bits [3:0] define the source pin. otherwise, the pll output is used as the reference clock. when an extern al reference clock is used for clock g enerator 3, the resu lting base output frequency of clock g enerator 3 is the frequency of the input reference clock multiplied by the clock generator 3 numerato r, divided by 1024. for example: if bit 4 ( c lk_gen3_src ) = 0b1 (an external reference clock is used) ; bits [3:0] ( fref_pin ) = 0b1110 (the input signal of t he s/pdif receiver is used as the reference source) ; the sample rate of the s/pdif input signal = 48 khz; and the numerator of clock generator 3 = 2048; the resulting bas e output sample rate of clock g enerator 3 is 48 khz 2048/ 1024 = 96 khz. 0x0 rw 0 reference signal provided by pll output; multiply the frequency of that signal by m and divide it by n 1 reference signal provided by the signal input to the hardware pin defined by bits [3:0] ( fref_pin ) ; multiply the frequency of that signal by n (and then divide by 1024) t o get the resulting sample rate ; m is ignored [3:0] fref_pin input reference for clock g enerator 3. if clock generator 3 is set up to lock to an external reference clock ( bit 4 ( clk_gen3_src ) = 0b1), these bits allow the user to specify which pin is receiving the reference clock. the signal input to the corresponding pin should be a 50% duty cycle square wave clock representing the reference sample rate. 0xe rw 0000 input reference source is ss_m/mp0 0001 input reference s ource is mosi_m/mp1 0010 input reference source is scl_m/sclk_m/mp2 0011 input reference source is sda_m/miso_m/mp3 0100 input reference source is lrclk_out0/mp4 0101 input reference source is lrclk_out1/mp5 0110 input reference so urce is mp6 0111 input reference source is mp7 1000 input reference source is lrclk_out2/mp8 1001 input reference source is lrclk_out3/mp9 1010 input reference source is lrclk_in0/mp10 1011 input reference source is lrclk_in1/mp11 1100 input reference source is lrclk_in2/mp12 1101 input reference source is lrclk_in3/mp13 1110 input reference source is s/pdif receiver (recovered frame clock) lock bit for clock generator 3 input reference register address: 0xf027, re set: 0x0000, name: clk_gen3_lock this re gister monitors whether or not clock g enerator 3 has locked to its reference clock source, regardless of whether it is coming from the pll output or from an external reference signal , which is configured in register 0xf026 , bit 4 ( clk_gen3_src ) . table 79 . bit descriptions for clk_gen3_lock bits bit name settings description reset access [15:1] reserved 0x0 rw 0 gen3_lock lock bit. 0x0 r 0 not locked 1 locked rev. c | page 101 of 180
adau1452/adau1451/adau1450 data sheet power reduction regi sters power enable 0 register address: 0xf050, reset: 0x0000, name: power_enable0 for the purpose of power savings, t his register allows the clock generators, asrcs, and serial ports to be disabled when not in use. when these functional blocks are disabled , the current draw on the corresponding supply pins decrease s. table 80 . bit descriptions for power_enable0 bits bit name settings description reset access [15:13] reserved 0x0 rw 12 clk_gen3_pwr h igh precision clock generator (clock g enerator 3) power enab le. when this bit is disabled, clock generator 3 is disabled and cease s to output audio clocks. any functional block in hardware, including the dsp core, that has been configured to be clocked by clock generator 3 cease s to fu nction while this bit is disabled. 0x0 rw 0 power disabled 1 power enabled 11 clk_gen2_pwr clock g enerator 2 power enab le. when this bit is disabled, c lo ck g enerator 2 is disabled and cease s to output audio clocks. any lrclk _outx, lrclk_inx or bclk _outx, bclk_inx pins that have been configured to output clocks generated by clock g enerator 2 o utput a logic low signal while clock g enerator 2 is disabled. any functional block in hardware, including the dsp core, that has be en configured to be clock ed by clock g enerator 2 cease s to function while this bit is disabled. 0x0 rw 0 power disabled 1 power enabled rev. c | page 102 of 180
data sheet adau1452/adau1451/adau1450 bits bit name settings description reset access 10 clk_gen1_pwr clock g enerator 1 power enable. when this bit is disabled, clock generator 1 is disabled and cease s to output audio c locks. any lrclk_outx, lrclk_inx or bclk_outx, bclk_inx pins that are configured to output clocks generated by clock g enerator 1 o utput a logic low signal while clock g enerator 1 is disabled. any functional block in hardware, including the dsp core, that i s configured to be clocked by clock g enerator 1 cease s to function when this bit is disabled. 0x0 rw 0 power disabled 1 power enabled 9 asrcbank1_pwr asrc 4 , asrc 5 , asrc 6 , asrc 7 power enable. w hen this bit is disabled, asrc channel 8 to chan nel 15 are disabled, and their output data stream s cease. 0x0 rw 0 power disabled 1 power enabled 8 asrcbank0_pwr asrc 0 , asrc 1 , asrc 2 , asrc 3 power enable. when this bit is disabled, asrc channel 0 to channel 7 are disabled, and their output data stream s cease. 0x0 rw 0 power disabled 1 power enabled 7 sout3_pwr sdata_out3 power enable. when this bit is disabled, the sdata_out3 pin and associated serial port circuitry are also disabled. lrclk_out3 and bclk_out3 are not affected. 0 x0 rw 0 power disabled 1 power enabled 6 sout2_pwr sdata_out2 power enable. when this bit is disabled, the sdata_out2 pin and associated serial port circuitry is disabled. lrclk_out2 and bclk_out2 are not affected. 0x0 rw 0 power disabled 1 power enabled 5 sout1_pwr sdata_out1 power enable. when this bit is disabled, the sdata_out1 pin and associated serial port circuitry are also disabled. lrclk_out1 and bclk_out1 are not affected. 0x0 rw 0 power disabled 1 power enabled 4 sout0_pwr sdata_out0 power enable. when this bit is disabled, the sdata_out0 pin and associated serial port circuitry are disabled. lrclk_out0 and bclk_out0 are not affected. 0x0 rw 0 power disabled 1 power enabled 3 sin3_pwr sdata_in3 power enable. when this bit is disabled, the sdata_in3 pin and associated serial port circuitry are disabled. lrclk_in3 and bclk_in3 are not affected. 0x0 rw 0 power disabled 1 power enabled 2 sin2_pwr sdata_in2 power enable. when this bit is disabl ed, the sdata_in2 pin and associated serial port circuitry are disabled. lrclk_in2 and bclk_in2 are not affected. 0x0 rw 0 power disabled 1 power enabled 1 sin1_pwr sdata_in1 power enable. when this bit is disabled, the sdata_in1 pin and associ ated serial port circuitry are disabled. the lrclk_in1 and bclk_in1 pins are not affected. 0x0 rw 0 power disabled 1 power enabled 0 sin0_pwr sdata_in0 power enable. when this bit is disabled, the sdata_in0 pin and associated serial port circui try are disabled. the lrclk_in0 and bclk_in0 pins are not affected. 0x0 rw 0 power disabled 1 power enabled rev. c | page 103 of 180
adau1452/adau1451/adau1450 data sheet power enable 1 register address: 0xf051, reset: 0x0000, name: power_enable1 for the purpose of power savings, t his register allows the pd m microphone interfaces, s/pdif interfaces, and auxiliary adcs to be disabled when not in use. when these functional blocks are disabled, the current draw on the corresponding supply pins decrease s. table 81 . bit descriptions for po wer_enable1 bits bit name settings description reset access [15:5] reserved 0x0 rw 4 pdm1_pwr pdm microphone channel 2 and pdm microphone channel 3 power enable. when this bit is disabled, pdm microphone channel 2 and pdm microphone channel 3 and thei r associated circuitry are disabled, and their data values cease to update. 0x0 rw 0 power disabled 1 power enabled 3 pdm0_pwr pdm microphone channel 0 and pdm microphone channel 1 power enable. when this bit is disabled, pdm microphone channel 0 and pdm microphone channel 1 and their associated circuitry are disabled, and their data values cease to update. 0x0 rw 0 power disabled 1 power enabled 2 tx_pwr s/pdif transmitter power enable. this bit disables the s/pdif transmitter circu it. clock and data cease s to output from the s/pdif transmitter pin , and the output is held at logic low as long as this bit is disabled. 0x0 rw 0 power disabled 1 power enabled 1 rx_pwr s/pdif receiver power enable. this bit disables the s/pdi f receiver circuit. clock and data recovery from the s/pdif input stream cease s until this bit is re enabled. 0x0 rw 0 power disabled 1 power enabled 0 adc_pwr auxiliary adc power enable. when this bit is disabled, the auxiliary adcs are powered down , their outputs cease to update , and they hold their last value. 0x0 rw 0 power disabled 1 power enabled rev. c | page 104 of 180
data sheet adau1452/adau1451/adau1450 audio signal routing registers asrc input selector register address: 0xf100 to address 0xf107 (increments of 0x1), reset: 0x0000, name : asrc_input x these eight registers configure the input signal to the correspondin g eight stereo asrcs on the adau1452 and adau1451 . asrc _input0 configures asrc channel 0 and asrc channel 1, asrc_input1 c onfigures asrc channel 2 and asrc channel 3, and so on. valid input s ignals to the asrcs include serial input channel 0 to serial input channel 47, t he pdm microphone input channel 0 to pdm microphone input channel 3, and the s/pdif receiver channel 0 to s /pdif receiver channel 1. rev. c | page 105 of 180
adau1452/adau1451/adau1450 data sheet table 82. bit descriptions for asrc_inputx bits bit name settings description reset access [15:8] reserved 0x0 rw [7:3] asrc_sin_channel if bits [2:0] ( asrc_source ) = 0b001, th ese bits select which seri al input channel is routed to the asrc. 0x00 rw 00000 serial input c hannel 0 and serial input channel 1 00001 serial input c hannel 2 and serial input channel 3 00010 serial input c hannel 4 and serial input channel 5 00011 serial input c ha nnel 6 and serial input channel 7 00100 serial input c hannel 8 and serial input channel 9 00101 serial input c hannel 10 and serial input channel 11 00110 serial input c hannel 12 and serial input channel 13 00111 serial input c hannel 14 and serial input channel 15 01000 serial input c hannel 16 and serial input channel 17 01001 serial input c hannel 18 and serial input channel 19 01010 serial input c hannel 20 and serial input channel 21 01011 serial input c hannel 22 and serial input channel 23 01100 serial input c hannel 24 and serial input channel 25 01101 serial input c hannel 26 and serial input channel 27 01110 serial input c hannel 28 and serial input channel 29 01111 serial input c hannel 30 and seri al input channel 31 10000 serial input c hannel 32 and serial input channel 33 10001 serial input c hannel 34 and serial input channel 35 10010 serial input c hannel 36 and serial input channel 37 10011 serial input c hannel 38 and serial i nput channel 39 10100 serial input c hannel 40 and serial input channel 41 10101 serial input c hannel 42 and serial input channel 43 10110 serial input c hannel 44 and serial input channel 45 10111 serial input c hannel 46 and serial input channel 47 [2:0] asrc_source asrc source select. 0x0 rw 000 not used 001 from serial input ports; select channels using bits [7:3] ( asrc_sin_channel ) 010 from dsp core outputs 011 from s/pdif receiver 100 from digital pdm microph one input c hannel 0 and pdm microphone input channel 1 101 from digital pdm microphone input c hannel 2 and pdm microphone input channel 3 rev. c | page 106 of 180
data sheet adau1452/adau1451/adau1450 asrc output rate selector register address: 0xf140 to address 0xf147 (increments of 0x1), reset: 0x0000, name : asrc_out_rate x these eight registers configure the target output sam ple rates of the corresponding eight stereo asrcs on the adau1452 and adau1451 . the asrc take s any arbitrary input sample rate and aut omatically attempt s to re sample the data in that signal and output it at the target sample rate as configured by these registers. each of the eight registers corresponds to one of the eight stereo asrcs. asrc_out_rate0 configures asrc channel 0 and asrc ch annel 1, asrc_input1 configures asrc channel 2 and asrc channel 3, asrc_out_rate2 configures asrc channel 4 and asrc channel 5, asrc_out_rate3 configures asrc channel 6 and asrc channel 7, asrc_out_rate4 configures asrc channel 8 and asrc channel 9, asrc_o ut_rate5 configures asrc channel 10 and asrc channel 11, asrc_out_rate6 configures asrc channel 12 and asrc channel 13, and asrc_out_rate7 configures asrc channel 14 and asrc channel 15. the asrcs lock their output frequencies to the audio sample rate s of any of th e serial output ports, the dsp start pulse rate of the core , or one of several internally generated sample rates coming from the clock generators. rev. c | page 107 of 180
adau1452/adau1451/adau1450 data sheet table 83 . bit descriptions for asrc_out_rate x bits bit name settings descrip tion reset access [15:4] reserved 0x0 rw [3:0] asrc_rate asrc target audio output sample rate. the corresponding asrc can lock its output to a serial output port, the dsp core, or an internally generated rate. 0x0 rw 0000 no output rate selected 0001 use sample rate of sdata_out0 ( register 0xf211 ( serial_byte_4_1 ), bits [4:0]) 0010 use sample rate of sdata_out1 ( register 0xf215 ( serial_byte_5_1 ), bits [4:0]) 0011 use sample rate of sdata_out2 ( register 0xf219 ( serial_byte_6_1 ), bits [4:0 ]) 0100 use sample rate of sdata_out3 ( register 0xf21d ( serial_byte_7_1 ), bits [4:0]) 0101 use dsp core audio sampling rate ( register 0xf401 ( start_pulse ), bits [4:0]) 0110 internal rate ( the base output rate of clock generator 1 ) ; see registe r 0xf020 ( clk_gen1_m ) and register 0xf021 ( clk_gen1_n) 0111 internal rate 2 ( the doubled output rate of clock generator 1 ) ; see register 0xf020 (clk_gen1_m) and register 0xf021 (clk_gen1_n) 1000 internal rate 4 ( the quadrupled output rate of clock generator 1 ) ; see register 0xf020 (clk_gen1_m) and register 0xf021 (clk_gen1_n) 1001 internal rate (1/2 ) the halved output rate of clock generator 1 ); see register 0xf020 (clk_gen1_m) and register 0xf021 (clk_gen1_n) 1010 internal rate (1/3) (halved output of clock generator 2 ) ; see register 0xf022 ( clk_gen2_m ) and register 0xf023 ( clk_gen2_n) 1011 internal rate (1/4) ( quartered output of clock generator 1 ); see register 0xf020 (clk_gen1_m) and register 0xf021 (clk_gen1_n) 1100 internal rate (1/6) ( quartered output of clock generator 2 ); see register 0xf022 (clk_gen2_m) and register 0xf023 (clk_gen2_n) rev. c | page 108 of 180
data sheet adau1452/adau1451/adau1450 source of data for serial output ports register address: 0xf180 to 0xf197 (i ncrements of 0x1), reset: 0x0000, name: sout _source x these 24 registers correspond to the 24 pairs of output channels used by the serial output ports. each register corresponds t o two audio channel s. sout_source0 corresponds to channel 0 and channel 1, sout_source1 corresponds to channel 2 and chann el 3, and so on. sout_source0 to sout_source7 map to the 16 total channels ( channel 0 to channel 15) that are fed to sdata_out0. sout_source8 to sout_source15 map to the 16 total channels ( channel 16 to channel 31) that are fed to sdata_out1. sout_source16 to sout_source19 map to the eight total channels ( channel 32 to channel 39) that are fed to sdata_out2. sout_source20 to sout_source23 map to the eight total channels ( channel 40 to channel 47) that are fed to sdata_out3. data originates from several plac es, including directly from the corresponding input audio channels from the serial input ports, from the corresponding audio output channels of the dsp core , from an asrc output pair, or directly from the pdm microphone inputs. table 84 . bit descriptions for sout_source x bits bit name settings description reset access [15:6] reserved 0x000 rw [5:3] sout_asrc_select asrc output channels. if bits [2:0] ( sout_source ) are set to 0b011, these bits select which asrc channels are routed to the serial output channels. 0x0 rw 000 asrc 0 (channel 0 and channel 1) on the adau1452 and adau1451 001 asrc 1 ( channel 2 and channel 3) on the adau1452 and adau1451 010 asrc 2 ( channel 4 and channel 5) on the adau1452 and adau1451 011 asrc 3 ( channel 6 and channel 7) on the adau1452 and adau1451 100 asrc 4 ( channel 8 and channel 9) on the adau1452 and adau1451 101 asrc 5 ( channel 10 and channel 11) on the adau1452 and ad au1451 110 asrc 6 ( channel 12 and channel 13) on the adau1452 and adau1451 111 asrc 7 ( channel 14 and channel 15) on the adau1452 and adau1451 rev. c | page 109 of 180
adau1452/adau1451/adau1450 data sheet bits bit name settings description reset access [2:0] sout_source audio data source for these serial audio output channels. if these bits are set to 0b001, the corresponding o utput channels output a copy of the data from the corresponding input channels . f or example, if address 0xf180 , bits [2:0] are set to 0b001, serial input channel 0 and serial input channel 1 copy to serial out - put channel 0 and serial output channel 1, respectively. if these bits are set to 0b010, dsp output channel 0 and dsp output channel 1 copy to serial o ut - put channel 0 a nd serial out put channel 1, respectively . if these bits are set to 0b011, bits [5:3] ( sout_asrc_select ) must be configured to select the desired asrc output. 0x0 rw 000 disabled; these output channels are not used 001 direct copy of data from corres ponding serial input channels 010 data from corresponding dsp core output channels 011 from asrc (select channel using bits [5:3] , sout_asrc_select ) on the adau1452 and adau1451 100 digital pdm m icr o phone input c hannel 0 and digital pdm microphone input channel 1 101 digital pdm microphone input channel 2 and digital pdm microphone input channel 3 s/pdif transmitter data selector register address: 0xf1c0, reset: 0x0000, name: spdiftx _input this register configures which data source feed s the s/pdif transmitter on the adau1452 and adau1451 . data can originate from the s/pdif outputs of the dsp core or directly from the s/pdif receiver . table 85 . bit descriptions for spdiftx_input bits bit name settings description reset access [15:2] reserved 0x0 rw [1:0] spdiftx_source s/pdif transmitter source. 0x0 rw 00 disables s/pdif transmitter 01 data origina tes f rom s/pdif output channel 0 and s/pdif output channel 1 of the dsp core , as configured in the dsp program 10 data c opied directly from s/pdif receiver channel 0 and s/pdif receiver channel 1 to s/pdif transmitter channel 0 and s/pdif transmitter channel 1, respectively rev. c | page 110 of 180
data sheet adau1452/adau1451/adau1450 serial port configur ation registers serial port control 0 register address: 0xf200 to 0xf21c (increments of 0x4), reset: 0x0000, name: serial_byte_ x _0 these eight registers configure several settings for the corresponding serial input and serial output ports. channe l count, msb position, data - word length, clock polarity, clock sources, and clock type are configured using these registers. on the input side, register 0xf200 ( serial_by te_0_0) corresponds to sdata_in0; register 0xf20 4 ( serial_by te_1_0) corresponds to sdata_in1; register 0xf208 ( serial_byte_2_0 ) corresponds to sdata_in2; and register 0xf20c ( serial_byte_3_0 ) corresponds to sdata_in3. on the output side, register 0xf210 ( serial_byte_4_0 ) c orresponds to sdata_out0; regis ter 0xf214 ( serial_byte_5_0 ) corresponds to sdata_out1; register 0xf218 ( serial_byte_6_0 ) corresponds to sdata_out2; and register 0xf21c ( serial_byte_7_0 ) corresponds to sdata_out3. rev. c | page 111 of 180
adau1452/adau1451/adau1450 data sheet table 86 . bit descriptions for serial_byte_ x _0 bit s bit name settings description reset access [15:13] lrclk_src lrclk pin selection. these bits configure whether the corresponding serial port is a frame clock master or slave. when configured as a master, the corresponding lrclk pin (lrclk_in x for sdata _in pins and lrclk_out x for sdata_out pins) with the same number as the serial port (for example, lrclk_out0 for sdata_out0) actively drive s out a clock signal. when configured as a slave, the serial port can receive its clock signal from any of the four c orresponding lrclk pins (lrclk_in x pins for sdata_in x pins or lrclk_out x pins for sdata_out x pins). 0x0 rw 000 slave from lrclk_in0 or lrclk_out0 001 slave from lrclk_in1 or lrclk_out1 010 slave from lrclk_in2 or lrclk_out2 011 slave from lrclk_in3 or lrclk_out3 100 master mode; corresponding lrclk pin actively output s a clock signal [12:10] bclk_src bclk pin selection. these bits configure whether the corresponding serial port is a bit clock master or slave. when configured as a master, the corresponding bclk pin (bclk_in x for sdata_in x pins and bclk_out x for sdata_out x pins) with the same number as the serial port (for example, bclk_out0 for sdata_out0) actively drive s out a clock signal. when configured as a slave, the serial po rt can receive its clock signal from any of the four corresponding bclk pins ( bclk _in x pins for sdata_in x pins or b clk_out x pins for sdata_out x pins). 0x0 rw 000 slave from bclk_in0 or bclk_out0 001 slave from bclk_in1 or bclk_out1 010 slave f rom bclk_in2 or bclk_out2 011 slave from bclk_in3 or bclk_out3 100 master mode; corresponding bclk pin actively output s a clock signal 9 lrclk_mode lrclk waveform type. the frame clock can be a 50/50 duty cycle square wave or a short pulse. 0 x0 rw 0 50% duty cycle clock (square wave) 1 pulse with a width equal to one bit clock cycle 8 lrclk_pol lrclk polarity. this bit sets the frame clock polarity on the corresponding serial port. negative polarity means that the frame starts on t he falling edge of the frame clock. this conforms to the i 2 s standard audio format. 0x0 rw 0 negative polarity; frame starts on falling edge of frame clock 1 positive polarity; frame starts on rising edge of frame clock 7 bclk_pol bclk polarity . this bit sets the bit clock polarity on the corresponding serial port. negative polarity means that the data signal transitions on the falling edge of the bit clock. this conforms to the i 2 s standard audio format. 0x0 rw 0 negative polarity; data tran sitions on falling edge of bit clock 1 positive polarity; data transitions on rising edge of bit clock [6:5] word_len a udio data - word length. these bits set the word length of the audio data channels on the corresponding serial port. for serial in put ports, if the input data has more words than the length as configured by these bits, the extra data bits are ignored. for output serial ports, if the word length , as configured by these bits , is shorter than the data length coming from the data source (the dsp, asrcs, s/pdif receiver, pdm inputs, or serial inputs), the extra data bits are truncated and output as 0 s. if bits [6:5] ( word_len ) are set to 0b10 for 32 - bit mode , the corresponding 32 - bit input or output cells are required in sigmastudio. 0x0 rw 00 24 bits 01 16 bits 10 32 bits 11 flexible tdm mode (config ure using register 0xf300 to register 0xf33f, ftdm_i n x , and r egister 0xf380 to register 0xf3b f, ftdm_outx ) rev. c | page 112 of 180
data sheet adau1452/adau1451/adau1450 bit s bit name settings description reset access [4:3] data_fmt msb position. these bits set the positioning of th e data in the frame on the corresponding serial port. 0x0 rw 00 i 2 s (delay data by one bclk cycle) 01 left justified (delay data by zero bclk cycles) 10 right justified for 24 - bit data (delay data by 8 bclk cycles) 11 right justified for 16- bit data (delay data by 16 bclk cycles) [2:0] tdm_mode channels per frame and bclk cycles per channel. these bits set the number of channels per frame and the number of bit clock cycles per frame on the corresponding serial port. 0x0 rw 000 2 cha nnels, 32 bit clock cycles per channel, 64 bit clock cycles per frame 001 4 channels, 32 bit clock cycles per channel, 128 bit clock cycles per frame 010 8 channels, 32 bit clock cycles per channel, 256 bit clock cycles per frame 011 16 chan nels, 32 bit clock cycles per channel, 512 bit clock cycles per frame 100 4 channels, 16 bit clock cycles per channel, 64 bit clock cycles per frame 101 2 channels, 16 bit clock cycles per channel, 32 bit clock cycles per frame serial port co ntrol 1 register address: 0xf201 to 0xf21d (increments of 0x4), reset: 0x0002, name: serial_byte_ x _1 these eight registers configure several settings for the corresponding serial input and serial output ports. clock generator, sample rate , and behavior dur ing inactive channels are configured with these registers. on the input side, register 0xf201 ( serial_byte_0_1 ) corresponds to sdata_in0; register 0xf205 ( serial_byte_1_1 ) corresponds to sdata_in1; register 0xf209 ( serial_byte_2_1 ) corresponds to sdata_in2 ; and register 0xf20d ( serial_byte_3_1 ) corresponds to sdata_in3. on the output side, register 0xf21 1 ( serial_byte_4_1 ) corresponds to sdata_out0; register 0xf215 ( serial_byte_5_1 ) corresponds to sdata_out1; register 0xf21 9 ( serial_byte_6_1 ) corresponds to sdata_out2; and register 0xf21d ( serial_byte_7_1 ) corresponds to sdata_out3. table 87 . bit descriptions for serial_byte_ x _1 bits bit name settings description reset access [15:6] reserved 0x000 rw 5 tristate tristate unused ou tput channels. this bit has no effect on serial input ports. 0x0 rw 1 the corresponding serial data output pin is high impedance during unused output channels 0 drive every output channel rev. c | page 113 of 180
adau1452/adau1451/adau1450 data sheet bits bit name settings description reset access [4:3] clk_domain selects the clock generator to use for the serial port . these bits select the clock generator to use for this serial port when it is configured as a clock master. this setting is valid only when bits[15:13] (lrclk_src) of the corresponding serial_byte_ x _0 register are set to 0b100 (master mode) and bits [12:10] ( bclk_src ) are set to 0b100 (master mode). 0x0 rw 00 clock g enerator 1 01 clock g enerator 2 10 clock g enerator 3 (high precision clock generator) [2:0] fs sample rate. these bits set the sample rate to use for the serial p ort when it is configured as a clock master. this setting is valid only when bits[15:13] (lrclk_src) of the corresponding serial_byte_ x_0 register are set to 0b100 (master mode) and bits [12:10] bclk_src are set to 0b100 (master mode). bits [4:3] ( clk_domain ) select which clock generator to use, and bits [2:0] ( fs ) select which of the five clock generator outputs to use. 0x2 rw 000 quarter rate of selected clock generator 001 half rate of selected clock generator 010 base rate of selected clock ge nerator 011 double rate of selected clock generator 100 quadruple rate of selected clock generator flexible tdm interface registers ftdm mapping for the serial inputs register address: 0xf300 to 0xf33f (increments of 0x1), reset: 0x0000, name : ftdm_in x these 64 registers correspond to the 64 bytes of data that combine to form the 16 audio channels derived from the data stream s being input to the sdata_in2 and sdata_in3 pins. rev. c | page 114 of 180
data sheet adau1452/adau1451/adau1450 table 88 . bit descriptions for ftdm_inx bits bit name settings description reset access [15:8] reserved 0x0 rw 7 slot_enable_in enables the corresponding input byte. this bit determines whether or not the slot is active. if active, valid data is input from the corresponding data slot on the sele cted channel of the se lected input pin. if disabled, input data from the corresponding data slot on the selected channel of the selected input pin is ignored. 0x0 rw 0 disable byte 1 enable byte 6 reverse_in_byte reverses the order of bits in t he byte (big endian or little endian). this bit change s the endianness of the data bits within the byte by optionally reversing the order of the bits from msb to lsb. 0x0 rw 0 do not reverse bits (big endian) 1 reverse bits (little endian) 5 ser ial_in_sel serial input pin selector (sdata_in2 or sdata_in3). if this bit = 0b0, the slot is mapped to audio channel 32 to audio channel 39. if this bit = 0b1, the slot is mapped to audio channel 40 to audio channel 47. the exact channel assi gnment is de termined by bits [4:2] ( channel_in_pos ) . 0x0 rw 0 select data from the flexible tdm stream on the sdata_in2 pin 1 select data from the flexible tdm stream on the sdata_in3 pin [4:2] channel_in_pos source channel selector. these bits map the slot to an audio input channel. if bit 5 ( serial_in_sel ) = 0b0, position 0 maps to channel 32, position 1 maps to c hannel 33, and so on. . if bit 5 (serial_in_sel) = 0b1, position 0 maps to channel 40, position 1 maps to c hannel 41, and so on. 0x0 rw 000 ch annel 0 (in the tdm8 stream) 001 channel 1 (in the tdm8 stream) 010 channel 2 (in the tdm8 stream) 011 channel 3 (in the tdm8 stream) 100 channel 4 (in the tdm8 stream) 101 channel 5 (in the tdm8 stream) 110 channel 6 (in the tdm8 stream) 111 channel 7 (in the tdm8 stream) [1:0] byte_in_pos byte selector for source channel. these bits determine which byte the slot fill s in the channel selected by bit 5 (serial_in_sel) and bits [4:2] ( channel_in_pos ) . each channel consis ts of four bytes that are selectable by the four options available in this bit field. 0x0 rw 00 byte 0; bits [31:24] 01 byte 1; bits [23:16] 10 byte 2; bits [15:8] 11 byte 3; bits [7:0] rev. c | page 115 of 180
adau1452/adau1451/adau1450 data sheet ftdm mapping for the serial outputs register address : 0xf380 to 0xf3bf (increments of 0x1), reset: 0x0000, name: ftdm_out x these 64 registers correspond to the 64 data slots for the flexible tdm output modes on the sdata _out2 and sdata_out3 pins. slot 0 to slot 31 are availa ble for use on sdata_out2, and sl ot 32 to slot 63 are available for use on sdata_out3. each slot can potentially hold one byte of data. slots are mapped to corresponding audio c hannels in the serial ports by bits [5:0] in these registers. table 89 . bit descriptions for ftdm_out x bits bit name settings description reset access [15:8] reserved 0x0 rw 7 slot_enable_out enables the corresponding output byte. this bit determines whether or not the slot is active. if bit 7 ( slot_enable_out ) = 0b0 and bit 5 (tristate) of the co rresponding serial output port = 0b1, the corresponding output pin is high impedance during the period in which the correspondi ng flexible tdm slot is output. if bit 7 (slot_enable_out) = 0b0 , and bit 5 (tristate) of the corresponding serial outpu t port = 0b0, the corre - sponding output pin drive s logic low during the period in which the correspondi ng flexible tdm slot is output. if bit 7 (slot_enable_out) = 0b1, the corresponding serial output pin output s valid data during the period in which the c orresponding flexible tdm slot is output. 0x0 rw 0 disable byte 1 enable byte 6 reverse_out_byte reverses the bits in the byte (big endian or little endian). this bit change s the endianness of the data bits within the corresponding flexible tdm slot by optionally reversing the order of the bits from msb to lsb. 0x0 rw 0 do not reverse byte (big endian) 1 reverse byte (little endian) 5 serial_out_sel source serial output channel group. this bit, together with bits [4:2] ( channel_out_po s) , selects which serial output channel is the source of data for the corresponding flexible tdm output slot. 0x0 rw 0 serial output channel 32 to serial output channel 39 1 serial output channel 40 to serial output channel 47 rev. c | page 116 of 180
data sheet adau1452/adau1451/adau1450 bits bit name settings description reset access [4:2] channel_out_ pos source serial output chan ne l. these bits, along with bit 5 ( serial_out_sel ) , select which serial output channel is the source of data for the corre - spondin g flexible tdm output slot. if bit 5 ( serial_out_sel ) = 0b0, bits [4:2] ( channel_out_pos ) select serial output channels between serial output channel 32 and serial output channel 39. if bit 5 ( serial_out_sel ) = 0b1, bits [4:2] ( channel_out_pos ) s elect s serial output channels between serial output channel 40 and serial output channel 47. 0x0 rw 000 s erial output channel 32 or serial output channel 40 001 serial output channel 33 or serial output channel 41 010 serial output channel 34 or serial output channel 42 011 serial output channel 35 or serial output channel 43 100 serial ou tput channel 36 or serial output channel 44 101 serial output channel 37 or serial output channel 45 110 serial output channel 38 or serial output channel 46 111 serial output channel 39 or serial output channel 47 [1:0] byte_out_pos sou rce data byte. these bits determine which data byte is used from the corresponding serial output channel (selected by setting bit 5 ( serial_ out_sel ) and bits [4:2] ( channel_out_pos ) ) . because there c an be up to 32 bits in the data - word, four bytes are avai lable. 0x0 rw 00 byte 0; bits [31:24] 01 byte 1; bits [23:16] 10 b yte 2; bits [15:8] 11 byte 3; bits [7:0] rev. c | page 117 of 180
adau1452/adau1451/adau1450 data sheet dsp core control reg isters hibernate setting register address: 0xf400, reset: 0x0000, name: hibernate when hibernation mode is acti vated, the dsp core continue s processing the current audio sample or block, and then enter s a low power hibernation state. if bit 0 ( hibernate ) is set to 0b1 when the dsp core is processing audio, wait at least the duration of one sample before attempting to modify any other control registers. if bit 0 ( hibernate ) is set to 0b1 when the dsp core is processing audio , and block processing is used in the signal flow, wait at least the duration of one block plus the duration of one sample before attempt ing to m odify any other control registers. during hibernation, interrupts to the core are disabled. this prevents audio from flowing into o r out of the dsp core. because dsp processing ceases when hibernation is active, there is a significant drop in the current c onsumption on the dvdd supply. table 90 . bit descriptions for h ibernate bits bit name settings description reset access [15:1] reserved 0x0 rw 0 hibernate enter hibernation mode. this bit disables incoming interrupts and tells the dsp core to go to a low power sleep mode after the next audio sample or block has finished processing. it c auses the dsp to enter hibernation mode by masking all interrupts. 0x0 rw 0 not hibernating; i nterrupts enabled. 1 enter hibernation ; i nt errupts disabled. rev. c | page 118 of 180
data sheet adau1452/adau1451/adau1450 start pulse selection register address: 0xf401, reset: 0x0002, name: start_pulse this register selects the start pulse that marks the beginning of each audio frame in the dsp core. this effectively sets the sample rate of the audio go ing through the dsp. this start pulse can originate from either an internally generated pulse (from clock generator 1 or clock generator 2) or from an external clock that is received on one of the lrclk pins of one of the serial ports . any audio input or o utput from the dsp core that is asynchronous to this dsp start pulse rate must go through an asrc. if asynchronous audio sign als (that is, signals that are not synchronized to whatever start pulse is selected) are input to the dsp without first going throu gh an asrc, samples are skipped or doubled, leading to distortion and audible artifacts in the audio signal. rev. c | page 119 of 180
adau1452/adau1451/adau1450 data sheet table 91 . bit descriptions for start_pulse bits bit name settings description reset access [15:5] reserved 0x0 rw [4:0] start_pulse start pulse selection. 0x02 rw 00000 base sample rate 4 (12 khz for 48 khz base sample rate) ( 1/4 output of clock generator 1 ) 00001 base sample rate 2 (24 khz for 48 khz base sample rate) ( 1/2 output of clock generator 1 ) 00 010 base sample rate (48 khz for 48 khz base sample rate) ( 1 output of clock generator 1 ) 00011 base sample rate 2 (96 khz for 48 khz base sample rate) ( 2 output of clock generator 1 ) 00100 base sample rate 4 (192 khz for 48 khz base sample rate) ( 4 output of clock generator 1 ) 00101 base sample rate 6 (8 khz for 48 khz base sample rate) ( 1/4 output of clock generator 2 ) 00110 base sample rate 3 (16 khz for 48 khz base sample rate) ( 1/2 output of clock generator 2 ) 00111 2 base sample rate 3 (32 khz for 48 khz base sample rate) ( 1 output of clock generator 2 ) 01000 serial input p ort 0 sample rate ( register 0xf201 ( serial_byte_0_1 ), bits [4:0]) 01001 serial input port 1 sample rate ( register 0xf205 ( serial_byte _1_1 ), bits[4:0] ) 01010 serial input port 2 sample rate ( register 0xf209 ( serial_byte_2_1 ), bits[4:0]) 01011 serial input port 3 sample rate ( register 0xf20d ( serial_byte_3_1 ), bits[4:0]) 01100 serial output p ort 0 sample rate ( register 0xf2 11 ( serial_byte_4_1 ), bits[4:0]) 01101 serial output port 1 sample rate ( register 0xf215 ( serial_byte_5_1 ), bits[4:0]) 01110 serial output port 2 sample rate ( register 0xf219 ( serial_byte_6_1 ), bits[4:0]) 01111 serial output port 3 sample ra te ( register 0xf21d ( serial_byte_7_1 ), bits[4:0]) 10000 s/pdif receiver sample rate (derived from the s/pdif input stream) instruction to start the core register address: 0xf402, reset: 0x0000, name: start_core e nables the dsp core and initiates t he program counter, which then begin s incrementing through the program memory and executing instruc ti on codes. this register is edge triggered, mean ing that a rising edge on bit 0 ( start_core ), that is, a trans ition from 0b0 to 0b1, initiate s the prog ram c ounter. a falling edge on bit 0 ( start_c ore ), that is, a transition from 0b1 to 0b0, has no effect. t o stop the dsp core, use register 0xf400 ( hibernate), bit 0 (hibernate) . table 92 . bit descriptions for start_core bits bit name se ttings description reset access [15:1] reserved 0x0 rw rev. c | page 120 of 180
data sheet adau1452/adau1451/adau1450 bits bit name se ttings description reset access 0 start_core a transition of this bit from 0b 0 to 0b 1 enable s the dsp core to start executing its program. a transition from 0b 1 to 0b 0 does not affect the dsp core. 0x0 rw 0 a t ransition from 0b0 to 0b1 enables the dsp core to start program execution 1 a t ransition from 0b1 to 0b0 does not affect the dsp core instruction to stop the core register address: 0xf403, reset: 0x0000, name: kill_core bit 0 ( kill_core ) halt s the dsp core immed iately, even when it is in an undefined state. because h alting the dsp core immediately can lead to memory corruption, and it must be used only in debugging situations. this register is edg e triggered, mean ing that a rising edge on bit 0 ( kill_core ), that is, a transition from 0b0 to 0b1, halt s th e core. a falling edge on bit 0 ( kill_core ), that is, a transition from 0b1 to 0b0, has no effect. t o stop the dsp core after the next audio frame or block, use register 0xf400 ( hibernate ), bit 0 (hibernate) . tab le 93 . bit descriptions for kill_core bits bit name settings description reset access [15:1] reserved 0x0 rw 0 kill_core immediately halt s the core. when this bit transitions from 0b0 to 0b1 , the core immediately halt s . this ca n bring about undesired effects and , therefore , should be used only in debugging. to stop the core while it is running, use register 0xf400 ( hibernate ) to halt the core in a controlled manner. 0x0 rw 0 a t ransition from 0b0 to 0b1 immediately halts the co re 1 a transition from 0b1 to 0b0 has no effect start address of the program register address: 0xf404, reset: 0x0000, name: start_address this register sets the program address where the program counter begin s after the dsp c ore is enabled, using register 0xf402 , bit 0 ( start_core). the sigmastudio compiler automatically set s the program start address; therefore, the user is not required to manually modify the value of this register. table 94 . bit descriptions for start_address bits bit name settings description reset access [15:0] start_address program start address. 0x0000 rw rev. c | page 121 of 180
adau1452/adau1451/adau1450 data sheet core status register address: 0xf405, reset: 0x0000, name: core_status this read only register allows the user to check the status of the dsp core . t o manually modify t he core status , use register 0xf400 ( hibernate ) , register 0xf402 ( start_core ) , and register 0xf403 ( kill_core ) . table 95 . bit descriptions for core_status bits bit name settings description reset access [15:3] reserved 0x0 rw [2:0] core_status dsp core status. these bits display the status of the dsp core at the moment the value is read. 0x0 rw 000 core is not running. this is the default state when the device boots. when the core is manually stopped usi ng register 0xf403 ( kill_core ) , the core returns to this state. 001 core is running normally. 010 core is paused. the clock signal is cut off from the core, preserving its state until the clock resumes. this state occur s only if a pause instructi on is explicitly defined in the dsp program. 011 core is in sleep mode (the core may be actively running a program, but it has finished executing instructions and is waiting in an idle state for the next audio sample to arrive). this state occur s only if a sleep instruction is explicitly called in the dsp program. 100 core is stalled. this occurs when the dsp core is attempting to service more than one request , and it must stop execution for a few cycles t o do so in a timely manner. the core conti nue s execution immediately after the requests are serviced. rev. c | page 122 of 180
data sheet adau1452/adau1451/adau1450 debug and reliabilit y registers clear the panic manager register address: 0xf421, reset: 0x0000, name: panic_clear when register 0xf427 ( pa nic _fl ag ) signals that an error has occurred, use re gister 0xf421 ( panic_clear ) to reset it . toggle bit 0 ( panic_clear ) of this register from 0b0 to 0b1 and then back to 0b0 again to clear the flag and reset the state of the panic manager. table 96 . bit descriptions for panic_clear b its bit name settings description reset access [15:1] reserved 0x0 rw 0 panic_clear clear the panic manager. t o reset the panic_flag register, toggle this bit on and then off again. 0x0 rw 0 panic manager is not cleared 1 clear panic manager ( on a rising edge of this bit) rev. c | page 123 of 180
adau1452/adau1451/adau1450 data sheet panic parity register address: 0xf422, reset: 0x0003, name: panic_parity_mask the panic manager check s and report s memory parity mask errors. register 0xf422 ( panic_parity_mask ) allows the user to configure which memories, if any, should be subject to error reporting. table 97 . bit descriptions for panic_parity_mask bits bit name settings description reset access [15:12] reserved 0x0 rw 11 dm1_bank3_mask dm1 b ank 3 mask. 0x0 rw 0 report dm1_b ank3 parity mask errors 1 do not report dm1_bank3 parity mask errors 10 dm1_bank2_mask dm1 b ank 2 mask. 0x0 rw 0 report dm1_bank2 parity mask errors 1 do not report dm1_bank2 parity mask errors 9 dm1_bank1_mask dm1 b ank 1 mask. 0x0 rw 0 report dm1_bank1 parity mask errors 1 do not report dm1_bank1 parity mask errors 8 dm1_bank0_mask dm1 b ank 0 mask. 0x0 rw 0 report dm1_bank0 parity mask errors 1 do not report dm1_bank0 parity mask errors 7 dm0_bank3_mask dm0 b ank 3 mask. 0x0 rw 0 report dm0_bank3 parity mask errors 1 do not report dm0_bank3 parity mask errors rev. c | page 124 of 180
data sheet adau1452/adau1451/adau1450 bits bit name settings description reset access 6 dm0_bank2_mask dm0 b ank 2 mask. 0x0 rw 0 report dm0_bank2 parity mask errors 1 do not report dm0_bank2 parity mask errors 5 dm0_bank 1_mask dm0 b ank 1 mask. 0x0 rw 0 report dm0_bank1 parity mask errors 1 do not report dm0_bank1 parity mask errors 4 dm0_bank0_mask dm0 b ank 0 mask. 0x0 rw 0 report dm0_bank0 parity mask errors 1 do not report dm0_bank0 parity mask erro rs 3 pm1_mask pm1 parity mask. 0x0 rw 0 report pm1 parity mask errors 1 do not report pm1 parity mask errors 2 pm0_mask pm0 parity mask. 0x0 rw 0 report pm0 parity mask errors 1 do not report pm0 parity mask errors 1 asrc1_mask asrc 1 parity mask. 0x1 rw 0 report asrc 1 parity mask errors 1 do not report asrc 1 parity mask errors 0 asrc0_mask asrc 0 parity mask. 0x1 rw 0 report asrc 0 parity mask errors 1 do not report asrc 0 parity mask errors panic mask 0 register address: 0xf423, reset: 0x0000, name: panic_software_mask the panic manager checks and reports software errors. register 0xf423 ( panic_software_mask ) allows the user to configure whether software errors are reported to the panic manager or ignor ed. table 98 . bit descriptions for panic_software_mask bits bit name settings description reset access [15:1] reserved 0x0 rw 0 panic_software software mask. 0x0 rw 0 report parity errors 1 do not report parity errors rev. c | page 125 of 180
adau1452/adau1451/adau1450 data sheet panic mask 1 register address: 0xf424, reset: 0x0000, name: panic_wd_mask the panic manager checks and reports watchdog errors. register 0xf424 ( panic_wd_mask ) allows the user to configure whether watchdog errors are reported to the panic manager or ign ored. table 99 . bit descriptions for panic_wd_mask bits bit name settings description reset access 15:1 reserved 0x0 rw 0 panicwd watchdog mask. 0x0 rw 0 report watchdog errors 1 do not report watchdog errors pan ic mask 2 register address: 0xf425, reset: 0x0000, name: panic_stack_mask the panic manager checks and reports stack errors. register 0xf425 ( panic_stack_mask ) allows the user to configure whether stack errors are reported to the panic manager or ignored. table 100 . bit descriptions for panic_stack_mask bits bit name settings description reset access [15:1] reserved 0x0 rw 0 panic_stack stack mask. 0x0 rw 0 report stack errors 1 do not report stack errors rev. c | page 126 of 180
data sheet adau1452/adau1451/adau1450 panic mask 3 register address: 0xf426, reset: 0x0000, name: panic_loop_mask the panic manager checks and reports software errors related to looping code sections. register 0xf426 ( panic_loop_mask ) allows the user to configure whether loop errors are reported to the p anic manager or ignored. table 101 . bit descriptions for panic_loop_mask bits bit name settings description reset access 15:1 reserved 0x0 rw 0 panicloop loop mask. 0x0 rw 0 report loop errors 1 do not report loop er rors panic flag register address: 0xf427, reset: 0x0000, name: panic_flag this register acts as the master error flag for the panic manager. if any error is encountered in any functional block whose panic manager mask is disabled, this register log s th at an error has occurred. individual functional block masks are configured using register 0xf422 ( panic_parity_mask ) , register 0xf423 ( panic_software_mask ) , register 0xf424 ( panic_wd_mask ) , register 0xf425 ( panic_stack_mask ) , and register 0xf426 ( panic_loo p_mask ) . table 102 . bit descriptions for panic_flag bits bit name settings description reset access 15:1 reserved 0x0 rw 0 panicflag error flag from panic manager. this error flag bit is sticky. when an error is reported, th is bit go es high, and it stay s high until the user resets it using register 0xf421 ( panicclear ) . 0x0 r 0 no error 1 error rev. c | page 127 of 180
adau1452/adau1451/adau1450 data sheet panic code register address: 0xf428, reset: 0x0000, name: panic_code when register 0xf427 ( panic_flag ) indicates that an error has occurred, this register provide s details revealing which subsystem is reporting an error. if several errors occur, this register reports only the first error that occurs . subsequent errors are ignored until the register is cleared by toggling reg ister 0xf421 ( panic_clear ). table 103 . bit descriptions for panic_code bits bit name settings description reset access 15 err_soft error from software panic. 0x0 r 0 no error from the software panic 1 error from the softwa re panic 14 err_loop error from loop overrun. 0x0 r 0 no error from the loop overrun 1 error from the loop overrun 13 err_stack error from stack overrun. 0x0 r 0 no error from the stack overrun 1 error from the stack overrun 12 e rr_watchdog error from the watchdog counter. 0x0 r 0 no error from the watchdog counter 1 error from the watchdog counter 11 err_dm1b3 error in dm1 b ank 3. 0x0 r 0 no error in dm1 bank 3 1 error in dm1 bank 3 rev. c | page 128 of 180
data sheet adau1452/adau1451/adau1450 bits bit name settings description reset access 10 err_dm1b2 error in dm1 b ank 2. 0x0 r 0 no error in dm1 bank 2 1 error in dm1 bank 2 9 err_dm1b1 error in dm1 b ank 1. 0x0 r 0 no error in dm1 bank 1 1 error in dm1 bank 1 8 err_dm1b0 error in dm1 b ank 0. 0x0 r 0 no error in dm1 bank 0 1 error i n dm1 bank 0 7 err_dm0b3 error in dm0 b ank 3. 0x0 r 0 no error in dm0 bank 3 1 error in dm0 bank 3 6 err_dm0b2 error in dm0 b ank 2. 0x0 r 0 no error in dm0 bank 2 1 error in dm0 bank 2 5 err_dm0b1 error in dm0 b ank 1. 0x0 r 0 no error in dm0 bank 1 1 error in dm0 bank 1 4 err_dm0b0 error in dm0 b ank 0. 0x0 r 0 no error in dm0 bank 0 1 error in dm0 bank 0 3 err_pm1 error in pm1. 0x0 r 0 no error in pm1 1 error in pm1 2 err_pm0 error in pm0. 0x0 r 0 no error in pm0 1 error in pm0 1 err_asrc1 error in asrc 1 . 0x0 r 0 no error in asrc 1 1 error in asrc 1 0 err_asrc0 error in asrc 0 . 0x0 r 0 no error in asrc 0 1 error in asrc 0 execute stage error program count reg ister address: 0xf432, reset: 0x0000, name: execute_count when a software error occurs, this register logs the program instruction count at the time when the error occurred for software debugging purposes. table 104 . bit description s for execute_count bits bit name settings description reset access 15:0 executecount program count in the execute stage when the error occurred. 0x0000 rw rev. c page 129 of 180
adau1452/adau1451/adau1450 data sheet watchdog maximum count register address: 0xf443, reset: 0x0000, name: watchdog_maxcount this r egister is d esigned to start counting at a specified number and decrement by 1 for each clock cycle of the system clock in the core. the counter is reset to the maximum value each time the program counter jumps to the beginning of the program to begin proc essing another audio frame (this is implemented in the dsp program code generated by sigmastudio). if the counter reaches 0 , a watchdog error flag is raised in the panic manager. the watchdog is typically set to begin counting from a number slightly larger than the maximum number of instructions expected to execute in the program, such that an error occur s if the program does not finish in time for the next incoming sample. table 105 . bit descriptions for watchdog_maxcount bits bit n ame settings description reset access [15:13] reserved 0x0 rw [12:0] wd_maxcount value from which the watchdog counter should begin counting down. 0x0000 rw watchdog pres cale register address: 0xf444, reset: 0x0000, name: watchdog_prescale the watch dog prescaler is a number that is multiplied by the setting in register 0xf443 ( watchdog_maxcount ) to achieve very large counts for the watchdog, if necessary. using the largest prescale factor of 128 1024 and the largest watchdog maximum count of 64 1 024, a very large watchdog counter , on the order of 8.5 billion clock cycles , can be achieved. rev. c | page 130 of 180
data sheet adau1452/adau1451/adau1450 table 106 . bit descriptions for watchdog_prescale bits bit name settings description reset access [15:4] reserved 0x0 rw [3:0] wd_pre scale watchdog counter pre scale setting. 0x0 rw 0000 increment every 64 clock cycles 0001 increment every 128 clock cycles 0010 increment every 256 clock cycles 0011 increment every 512 clock cycles 0100 increment every 1024 clock c ycles 0101 increment every 2048 clock cycles 0110 increment every 4096 clock cycles 0111 increment every 8192 clock cycles 1000 increment every 16 , 384 clock cycles 1001 increment every 32 , 768 clock cycles 1010 increment every 65, 536 clock cycles 1011 increment every 131 , 072 clock cycles dsp program executio n registers enable block interrupts register address: 0xf450, reset: 0x0000, name: blockint_en this register enables block interrupts, which are necessary when frequ ency domain processing is required in the audio processing program. if block processing algorithms are used in sigmastudio, sigmastudio automatically set s this register accordingly. the user does not need to manually change the value of this register after sigmastudio has configured it. table 107 . bit descriptions for blockint_en bits bit name settings description reset access [15:1] reserved 0x0 rw 0 blockint_en enable block interrupts. 0x0 rw 0 disable block interrupts 1 enable block interrupts rev. c | page 131 of 180
adau1452/adau1451/adau1450 data sheet value for the block interrupt counter register address: 0xf451, reset: 0x0000, name: blockint_value this 16 - bit register controls the duration in audio frames of a block. a counter increment s each time a new frame start pulse is received by the dsp core. when the counter reaches the value determined by this register, a block interrupt is generated and the counter is reset. if block processing algorithms are used in sigmastudio, sigmastudio automatically set s this register acco rdingly. the user does not need to manually change the value of this register after sigmastudio has configured it. table 108 . bit descriptions for blockint_value bits bit name settings description reset access [15:0] blockint_value value for the block interrupt counter. 0x0000 rw program counter , bits [23:16] register address: 0xf460, reset: 0x0000, name: prog_cntr0 this register, in combination with register 0xf461 ( prog_cntr1 ) , stores the current value of the program counter. table 109 . bit descriptions for prog_cntr0 bits bit name settings description reset access [15:8] reserved 0x0 rw [7:0] prog_cntr_msb program counter , bits [23:16]. 0x00 r program counter , bits [15:0] register address: 0xf461, re set: 0x0000, name: prog_cntr1 this register, in combination with register 0xf460 ( prog_cntr0 ) , stores the current value of the program counter. table 110 . bit descriptions for prog_cntr1 bits bit name settings description reset acce ss [15:0] prog_cntr_lsb program counter , bits [15:0]. 0x0000 r rev. c | page 132 of 180
data sheet adau1452/adau1451/adau1450 program counter clear register address: 0xf462, reset: 0x0000, name: prog_cntr_clear enabling and disabling b it 0 ( prog_cntr_clear ) resets register 0xf465 ( prog_cntr_maxlength0 ) and register 0xf466 ( prog_cntr_maxlength1 ) . table 111 . bit descriptions for prog_cntr_clear bits bit name settings description reset access [15:1] reserved 0x0 rw 0 prog_cntr_clear clears the program counter. 0x0 rw 0 allow the program counter to update itself 1 clear the program counter and disable it from updating itself program counter length , bits [23:16] register address: 0xf463, reset: 0x0000, name: prog_cntr_length0 this register, in combination with register 0xf464 ( prog_ cntr_length1 ) , keeps track of the peak value reached by the program counter during the last audio frame or block. it can be cleared using register 0xf462 ( prog_cntr_clear ) . table 112 . bit descriptions for prog_cntr_length0 bits bit name settings description reset access [15:8] reserved 0x0 rw [7:0] prog_length_msb program counter length , bits [23:16]. 0x00 r program counter length , bits [15:0] register address: 0xf464, reset: 0x0000, name: prog_cntr_length1 this register, in com bination with register 0xf463 ( prog_cntr_length0 ) , keeps track of the peak value reached by the program counter during the last audio frame or bl ock. it can be cleared using reg i ster 0xf462 ( prog_cntr_clear ) . table 113 . bit descript ions for prog_cntr_length1 bits bit name settings description reset access [15:0] prog_length_lsb program counter length , bits [15:0]. 0x0000 r rev. c | page 133 of 180
adau1452/adau1451/adau1450 data sheet program counter max length , bits [23:16] register address: 0xf465, reset: 0x0000, name: prog_cntr_maxlength0 th is register, in combination with register 0xf46 6 ( prog_cntr_maxlength1 ) , keeps track of the highest peak value reached by the program counter since the dsp core started. it can be cleared using register 0xf462 ( prog_cntr_clear ) . table 114 . bit descriptions for prog_cntr_maxlength0 bits bit name settings description reset access [15:8] reserved 0x0 rw [7:0] prog_maxlength_msb program counter max imum length , bits [23:16]. 0x00 r program counter max length , bits [15:0] register add ress: 0xf466, reset: 0x0000, name: prog_cntr_maxlength1 this register, in combination with reg i ster 0xf465 ( prog_cntr_maxlength0 ) , keeps track of the highest peak value reached by the program counter since the dsp core started. it can be cleared using regi ster 0xf462 ( prog_cntr_clear ) . table 115 . bit descriptions for prog_cntr_maxlength1 bits bit name settings description reset access [15:0] prog_maxlength_lsb program counter max imum length , bits [15:0]. 0x0000 r rev. c | page 134 of 180
data sheet adau1452/adau1451/adau1450 multipurpose pin configuration regist ers multipurpose pin mode register address: 0xf510 to 0xf51d (increments o f 0x1), reset: 0x0000, name: mpx _mode these 14 registers configure the multipurpose pins. certain multipurpose pins can function as audio clock pin s, control bus pins, or general - purpose input or output (gpio) pins. table 116 . bit descriptions for mp x _mode bits bit name settings description reset access [15:11] reserved 0x0 rw [10:8] ss_select master port slave select channel selection. if the pin is conf igured as a slave select line (bits [3:1] ( mp_mode ) = 0b 110), these bits configure which slave select channel the pin correspond s to. this allows multiple slave devices to be connected to the spi master port, all using different slave sel ect lines. the first slave select signal (slave s elect 0) is always routed to the ss_m/mp0 pin. the remaining six slave select lines can be routed to any multipurpose pin that has been configured as a slave select output. 0x0 rw 000 slave select c hannel 1 001 slave select channel 2 010 slave select channel 3 011 slave select channel 4 100 slave select channel 5 101 slave select channel 6 rev. c | page 135 of 180
adau1452/adau1451/adau1450 data sheet bits bit name settings description reset access [7:4] debounce_value debounce circuit setting. these bits configure the duration of the d ebounce circuitry when the corresponding pin is configured as an input (bits [3:1] ( mp_mode ) = 0b 000). 0x0 rw 0001 0.3 ms debounce 0010 0.6 ms debounce 0011 0.9 ms debounce 0100 5.0 ms debounce 0101 10.0 ms debounce 0110 20.0 ms debounce 0111 40.0 ms debounce 0000 no debounce [3:1] mp_mode pin mode (when multipurpose function is enabled). these bits select the function of the corresponding pin if it is enabled in multipur pose mode (bit 0 ( mp_enable ) = 0b 1). 0x0 rw 000 general - purpose digital input 001 general - purpose input , driven by control port; sends its value to the dsp core, but that value can be overwritten by a direct register write 010 general - purpose output with pull -up 011 general - purpose o utput without pull - up 100 pdm microphone data input 101 panic manager error flag output 110 s lave select line for the master spi port 0 mp_enable function selection (multipurpose or clock/control). this bit selects whether the correspon ding pin is used as a multipurpose pin or as its primary function (which could be either an audio clock or control bus pin) . 0x0 rw 0 audio c lock or control port function enabled ; the settings of the mpx_mode, mpx_write, and mpx_read registers are ignor ed 1 multipurpose function enabled multipurpose pin write value register address: 0xf520 to 0xf52d (increments o f 0x1), reset: 0x0000, name: mpx _write if a multipurpose pin is configured as an out put driven by the control port (the corresponding b its [3:1] ( mp_mode ) = 0b 001), the value that is output from the dsp core can be configured by directly writing to these registers. table 117 . bit descriptions for mp x _write bits bit name settings description reset access [15:1] rese rved 0x0 w 0 mp_reg_write multipurpose pin output state when pin is configured as an output written by the control port. this register configures the value seen by the dsp core for the corresponding multipurpose pin input. the pin can have two states: logic low ( off ) or logic high (on) . 0x0 w 0 multipurpose pin output low 1 multipurpose pin output hig h rev. c | page 136 of 180
data sheet adau1452/adau1451/adau1450 multipurpose pin read value register s address: 0xf530 to 0xf53d (increments of 0x1), reset: 0x0000, name: mp x _read these registers log the c urrent state of the multipurpose pins when they are configured as inputs. the pins can have two states: logic low (off ) or logic high (on ). table 118 . bit descriptions for mpx _read bits bit name settings description reset access [1 5:1] reserved 0x0 r 0 mp_reg_read multipurpose pin read value. 0x0 r 0 multipurpose pin input low 1 multipurpose pin input high rev. c | page 137 of 180
adau1452/adau1451/adau1450 data sheet digital pdm microphone control register address: 0xf560 to 0xf561 (increments of 0x1), reset: 0x4000, name: dmic _ctrl x these registers configure the digital pdm microphone interface. t wo registers are used to con trol up to four pdm microphones: register 0xf560 ( dmic_ctrl0 ) configures pdm microphone channel 0 and pdm microphone channel 1, and register 0x f561 ( dmic_ct rl1 ) configures pdm microphone channel 2 and pdm microphone channel 3. table 119 . bit descriptions for dmic_ctrl x bits bit name settings description reset access 15 reserved 0x0 rw 14:12 cutoff high - pass filter cut off frequen cy. these bits configure the cutoff frequency of an optional high - pass filter designed to remove dc components from the microphone data signal(s). to use these bits, bit 3 ( hpf ) , must be enabled. 0x4 rw 000 59.9 hz 001 29.8 hz 010 14.9 hz 011 7.46 hz 100 3.73 hz 101 1.86 hz 110 0.93 hz rev. c page 138 of 180
data sheet adau1452/adau1451/adau1450 bits bit name settings description reset access [11:8] mic_data_src digital pdm microphone data source pin. these bits configure which hardware pin act s as a data input from the pdm microphone (s) . up to two microphones can be connected to a single pin. 0x0 rw 0000 ss_m/mp0 0001 mosi_m/mp1 0010 scl_m/sclk_m/mp2 0011 sda_m/miso_m/mp3 0100 lrclk_out0/mp4 0101 lrclk_out1/mp5 0110 mp6 0111 mp7 1000 lrclk_out2/mp8 1001 lrclk_out3/mp9 1010 lr clk_in0/mp10 1011 lrclk_in1/mp11 1100 lrclk_in2/mp12 1101 lrclk_in3/mp13 7 reserved 0x0 rw [6:4] dmic_clk digital pdm microphone clock select. a valid bit clock signal must be assigned to the pdm microphones. any of the four bclk_inpu t x or four bclk_output x signals can be used. a trace must connect the selected pin to the clock input pin on the corresponding pdm microphone(s). if the corresponding bclk _x pin is not configured in master mode, use an external clock source , with the bclk _ x pin and the pdm microphone acting as slaves. 0x0 rw 000 bclk_in0 001 bclk_in1 010 bclk_in2 011 bclk_in3 100 bclk_out0 101 bclk_out1 110 bclk_out2 111 bclk_out3 3 hpf high - pass filter enable. this bit enables or d isables a high - pass filter to remove dc components from the microphone data signals. the cutoff of t he filter is controlled by bits [14:12] ( cutoff ) . 0x0 rw 0 hpf disabled 1 hpf enabled 2 dmpol data polarity swap. when this bit is set to 0b 0, a logic high data input is treated as logic high , and a logic low data input is treated as logic low . when this bit is set to 0b 1, the opposite is true: a logic high data input is treated as a logic low, and a logic low data input i s treated as logic high . t his effectively inverts the amplitude of the incoming audio data. 0x0 rw 0 data polarity normal 1 data polarity inverted 1 dmsw digital pdm microphone channel swap. in dmic_ctrl0, this bit swap s pdm microphone c han nel 0 and pdm microphone chann el 1. in the dmic_ctrl1 register , this bit swap s pdm microphone channel 2 and pdm microphone channel 3. 0x0 rw 0 normal 1 swap left and right channels 0 dmic_en digital pdm microphone enable. this bit enables or disables the data input from the pdm microphones. 0x0 rw 0 digital pdm microphone disabled 1 digital pdm microphone enabled rev. c | page 139 of 180
adau1452/adau1451/adau1450 data sheet asrc status and cont rol registers asrc lock status register address: 0xf580, reset: 0x0000, name: asrc_lock this register contains eight bits that repre sent the lock status of each asrc stereo pair on the adau1452 and adau1451 . lock status requires three conditions: the output target rate is set, the input rate is steady and has been detected, and the ra tio between input and output rates has been calculated. if all of these conditions are true for a given stereo asrc, the corresponding lock bit is low. if any of these conditions is not true, the corresponding lock bit is high. table 120 . bit descriptions for asrc_lock bits bit name settings description reset access [15:8] reserved 0x0 rw 7 asrc7l asrc 7 lock status. 0x0 r 0 locked 1 unlocked 6 asrc6l asrc 6 lock status. 0x0 r 0 locked 1 unlocked 5 asrc5l asrc 5 lock status. 0x0 r 0 locked 1 unlocked 4 asrc4l asrc 4 lock status. 0x0 r 0 locked 1 unlocked 3 asrc3l asrc 3 lock status. 0x0 r 0 locked 1 unlocked 2 asrc2l asrc 2 lock status. 0x0 r 0 locked 1 unlocked rev. c | page 140 of 180
data sheet adau1452/adau1451/adau1450 bits bit name settings description reset access 1 asrc1l a src 1 lock status. 0x0 r 0 l ocked 1 u nlocked 0 asrc0l a src 0 lock status. 0x0 r 0 l ocked 1 u nlocked asrc mute register address: 0xf581, reset: 0x0000, name: asrc_mute this register contains controls related to the muting of audio on asrc channels. bits[7:0] (a srcxm) are individual mute controls for each stereo asrc on the adau1452 and adau1451. bit 8 (a src_ramp0) and bit 9 (a src_ramp1) enable or disable an optional vol ume r amp - up a nd ramp - down t o smoothly transition b etween m uted a nd u nmuted st ates. t he m ute a nd u n mute ramps a re linear. t he duration of t he ra mp i s d etermined by t he sample rate o f the d sp core, w hich is s et b y register 0xf 401 ( start_pulse ) . the r amp t ake s exactly 2048 input s amples to c omplete. for ex ample, i f the sample rate of a udio entering an a src c hannel is 4 8 kh z, t he d uration o f the ramp i s 2048 /48 ,0 00 = 42.7 ms. if t he s ample r ate o f a udio entering an a src c hannel is 6 kh z, t he d uration o f the ra m p i s 2048/ 6000 = 341.3 ms. bit 1 0 ( lockmute ) allows th e a srcs to a utomatically mute th emselves i n th e e vent that lock s tatus i s l ost or n o t attained. t able 121 . bit descriptions for asrc_mute bits bit name settings description reset access [15:11] reserved 0x 0 rw rev. c | page 14 1 of 180
adau1452/adau1451/adau1450 data sheet bits bit name settings description reset access 10 lockmute mute s asrcs when lock is lost. when this bit is enabled, individual stereo asrcs automatically mute on the event that lock status is lost (for example, if the sample rate of the input suddenly c hanges and th e asrc needs to re attain lock), provided that the corresponding asrc_ramp x bit is set to 0b0 (enabled). this automatic mute uses a volume ramp instead of an instantaneous mute to avoid click - and - pop noises on the output. when lock status is attained again (and the corresponding asrc_ramp x and asrc x m bits are set to 0b0 (enabled) and 0b0 (unmuted), respectively), the asrc automatically un mute s using a volume ramp. however, because there is a period of uncertainty when the asrc is attaining lock, there still may be noise on the asrc outputs when the input signal returns. measures must be taken in the dsp program to delay the un muting of the asrc output signals if this noise is not desired. the individual asrc x m mute bits override the automatic lockmute behavio r. 0x0 rw 0 do not mute when lock is lost 1 mute when lock is lost, and unmute when lock is re attained 9 asrc_ramp1 asrc 7 to asrc 4 mute disable. asrc 7 to asrc 4 (channel 15 to channel 8 ) are defined as asrc b lock 1. this bit enables or disab les mute ramping for all asrcs in b lock 1. if this bit is 0b1, bit 7 ( asrc7m ), bit 6 ( asrc6m ), bit 5 ( asrc5m ), and bit 4 ( asrc4m ) are ignored, and the outputs of asrc 7 to asrc 4 are active at all times. 0x0 rw 0 enabled 1 disabled; asrc 7 to asrc 4 never mute automatically and cannot be muted manually 8 asrc_ramp0 asrc 3 to asrc 0 mute disable. asrc 3 to asrc 0 (channel 7 to channel 0 ) are defined as asrc b lock 0. this bit enables or disables mute ramping for all asrcs in b lo ck 0. if this bit i s 0b1, bit 3 ( asrc3m ), bit 2 ( asrc2m ), bit 1 ( asrc1m ), and bit 0 ( asrc0m ) are ignored, and the outputs of asrc 3 to asrc 0 are active at all times. 0x0 rw 0 enabled 1 disabled; asrc 3 to asrc 0 never m ute automatically and cannot be muted manually 7 asrc7m asrc 7 manual mute. 0x0 rw 0 not muted 1 m uted 6 asrc6m asrc 6 manual mute. 0x0 rw 0 not muted 1 muted 5 asrc5m asrc 5 manual mute. 0x0 rw 0 not muted 1 muted 4 asrc4m asrc 4 manual mute. 0x0 rw 0 not mut ed 1 muted 3 asrc3m asrc 3 manual mute. 0x0 rw 0 not muted 1 muted 2 asrc2m asrc 2 manual mute. 0x0 rw 0 not muted 1 muted 1 asrc1m asrc 1 manual mute. 0x0 rw 0 not muted 1 muted 0 asrc0m asrc 0 manual mute. 0x0 rw 0 not muted 1 muted rev. c | page 142 of 180
data sheet adau1452/adau1451/adau1450 asrc ratio register s address: 0xf582 to 0xf589 (increments of 0x1), reset: 0x0000, name: asrc x _ratio th ese eight read only register s contain the sample rate conversion ratio of the corresponding asrc on the adau1452 and adau1451 , which is calculated as the ratio between the detected input rate and the selected target output rate. the format of the value stored in th ese register s is 4.12 format. for example, a ratio of 1 i s shown as 0b0001000000000000 (0x1000). a ratio of 2 is shown as 0b0010000000000000 (0x2000). a ratio of 0.5 is shown as 0b0000100000000000 (0x0800). table 122 . bit descriptions for asrc x _ratio bits bit name settings description res et access [15:0] asrc_ratio output rate of the asrc in 4.12 format. the value of this register represents the input to output rate of the corresponding asrc. it is stored in 4.12 format. 0x0000 rw auxiliary adc regist ers auxiliary adc read value regist er address: 0xf5a0 to 0xf5a5 (increments of 0x1), reset: 0x0000, name: adc_read x th ese six register contains the output data of the auxiliary adc for the corresponding channel. each of the six channels of the adc are updated once per audio frame. the forma t for the value in this register is 6.10 format, but the top six bits are always zero, meaning that the ef fective format is 0.10 format. if, for example, the input to the corresponding auxiliary adc channel is equal to avdd (the full - scale analog input vol tage), this register read s its maximum value of 0b0000001111111111 (0x3ff). if the input to the auxiliary adc channel is avdd/2, this register read s 0b0000001000000000 (0x200). if the input to the auxiliary adc channel is avdd/4, this register read s 0b0000 000100000000 (0x100). table 123 . bit descriptions for adc_read x bits bit name settings description reset access [15:0] adc_value adc input value in 0.10 format, as a proportion of avdd. instantaneous value of the sampled data on t he adc input. the top six bits are not used, and the least significant 10 bits contain the value of the adc input. the minimum value of 0 maps to 0 v , and the maximum value of 1023 maps to 3.3 v 10% (equal to the avdd supply). values between 0 and 1023 a re linearly mapped to dc voltages between 0 v and avdd. 0x0000 rw rev. c | page 143 of 180
adau1452/adau1451/adau1450 data sheet s/pdif interface registers s/pdif receiver lock bit detection register address: 0xf600, reset: 0x0000, name: spdif_lock_det this register contains a flag that monitors the s/pdif receiver on the adau1452 and adau1451 and provides a way to check the validity of the input signal. table 124 . bit descriptions for spdif_lock_det bits bit name settings description reset a ccess [15:1] reserved 0x0 rw 0 lock s/pdif input lock. 0x0 r 0 no lock acquired; no valid input stream detected 1 successful lock to input stream s/pdif receiver control register address: 0xf601, reset: 0x0000, name: spdif_rx_ctrl this reg ister provides controls that govern the behavior of the s/pdif receiver on the adau1452 and adau1451 . table 125 . bit descriptions for spdif_rx_ctrl bits bit name settings descripti on reset access [15:4] reserved 0x0 rw 3 fastlock s/pdif receiver locking speed. 0x0 rw 0 normal (locks after 64 consecutive valid samples) 1 fast (locks after eight consecutive valid samples) rev. c | page 144 of 180
data sheet adau1452/adau1451/adau1450 bits bit name settings descripti on reset access 2 fsoutstrength s/pdif receiver behavior in th e event that lock is lost. fsoutstrength applies to the output of the recovered frame clock from the s/pdif receiver. 0x0 rw 0 strong ; output is continued as well as is possible w hen the receiver notices a loss of lock condition, which may result in som e data corruption 1 weak ; output is interrupted as soon as receiver notices a loss of lock condition [1:0] rx_lengthctrl s/pdif receiver audio word length. 0x0 rw 00 24 bits 01 20 bits 10 16 bits 11 automatic (determined by chann el status bits detected in the input stream) decoded signals from the s/pdif receiver register address: 0xf602, reset: 0x0000, name: spdif_rx_decode this reg ister monitors the embedded non audio data bits in the incoming s /pdif stream on the adau1452 and adau1451 and decodes them, providing insight into the data format of the s/pdif input stream. table 126 . bit descriptions for spdif_rx_decode bits bit name settings description r eset access [15:10] reserved 0x0 rw [9:6] rx_wordlength_r s/pdif receiver detected word length in the right channel. 0x0 r 0010 16 bit word (maximum 20 bits) 1100 17 bit word (maximum 20 bits) 0100 18 bit word (maximum 20 bits) 1000 19 bit word (maximum 20 bits) 1010 20 bit word (maximum 20 bits) 1101 21 bit word (maximum 24 bits) 0101 22 bit word (maximum 24 bits) 1001 23 bit word (maximum 24 bits) 1011 24 bit word (maximum 24 bits) 0011 20 bit word (max imum 24 bits) rev. c | page 145 of 180
adau1452/adau1451/adau1450 data sheet bits bit name settings description r eset access [5:2] rx_wordlength_l s/pdif receiver detected word length in the left channel. 0x0 r 0010 16 bit word (maximum 20 bits) 1100 17 bit word (maximum 20 bits) 0100 18 bit word (maximum 20 bits) 1000 19 bit word (maximum 20 bits) 1010 20 bit word (maximum 20 bits) 1101 21 bit word (maximum 24 bits) 0101 22 bit word (maximum 24 bits) 1001 23 bit word (maximum 24 bits) 1011 24 bit word (maximum 24 bits) 0011 20 bit word (maximum 24 bits) 1 compr _type ac3 or dts compression (valid only if bit 0 ( audio_type ) = 0b1 (compressed) . 0x0 r 0 ac3 1 dts 0 audio_type linear pcm or compressed audio. 0x0 r 0 linear pcm 1 compressed compression mode from the s/pdif receiver register ad dress: 0xf603, reset: 0x0000, name: spdif_rx_comprmode if the incoming s/pdif data on the adau1452 and adau1451 has been encoded using a compression algorithm, this register display s the 16 - bit code that represents the type of compression being used. table 127 . bit descriptions for spdif_rx_comprmode bits bit name settings description reset access [15:0] compr_mode compression mode detected by the s/pdif receiver. 0x0000 r rev. c | page 146 of 180
data sheet adau1452/adau1451/adau1450 autom atically resume s/pdif receiver audio input register address: 0xf604, reset: 0x0000, name: spdif_restart w hen the s/pdif receiver on the adau1452 and adau1451 loses lock on the incoming s/pdif signal, whi ch can occur due to issues with signal integrity, the receiver automatically mute s itself. this register determines whether the s/pdif receiver then automatically resume s outputting data if the s/pdif receiver subsequently begins to receive valid data and a lock condition is re attained. by default, the s/pdif receiver does not automatically resume audio when lock is lost ( register 0xf604 ( spdif_restart ), bit 0 ( restart_audio ) = 0b0); and , therefore , the user must manu ally reset the s/pdif receiver by toggli ng register 0xf604 (spdif_restart), bit 0 ( restart_audio ) , from 0b0 to 0b1 and then back to 0b0 again . t o ensure that the s/pdif receiver always begin s outputting data when a valid input signal is detected, set register 0xf604 ( spdif_restart ), bit 0 ( resta rt_audio ) , to 0b1 at all times. table 128 . bit descriptions for spdif_restart bits bit name settings description reset access [15:1] reserved 0x0 rw 0 restart_audio allow s the s/pdif receiver to automatically resume outputting audio when it successfully recovers from a loss of lock. 0x0 rw 0 do not automatica lly restart the audio when a re lock occur s 1 restarts the audio automatically when a relock occurs , and resets register 0xf605 ( spdif_loss_of_lock ), bit 0 ( loss_of_l ock ) rev. c | page 147 of 180
adau1452/adau1451/adau1450 data sheet s/pdif receiver loss of lock detection register address: 0xf605, reset: 0x0000, name: spdif_loss_of_lock this bit monitors the s/pdif lock status and checks to see if the lock is lost during operation of the s/pdif receiver on the adau1452 and adau1451 . this condition can arise when, for example, a valid s/pdif input signal was present for an extended period of time, but signal integrity worsened for a brief period, causing the receiver to then lo se its lock to the in put signal. in this case, bit 0 ( loss_of_lock ) transition s from 0b0 to 0b1 and remain s set at 0b1 indefinitely. this indicate s that , at some point during the operation of the device, lock to the input str eam was lost. bit 0 ( loss_of_lo ck ) stay s high at 0b1 until register 0xf604 ( spdif_restart ), bit 0 ( restart_audio ), is set to 0b1, which clears bit 0 ( loss_of_lock ) back to 0b0. at that point, register 0xf604 ( spdif_restart ), bit 0 ( restart_audio ), can be reset to 0b0 if required. tabl e 129 . bit descriptions for spdif_loss_of_lock bits bit name settings description reset access [15:1] reserved 0x0 rw 0 loss_of_lock s/pdif loss of lock detection (sticky bit). 0x0 r 0 s/pdif receiver is locked to the input st ream and has not lost lock since acquiring the input signal 1 s/pdif receiver acquired a lock on the input stream but then , subsequently , lost lock rev. c | page 148 of 180
data sheet adau1452/adau1451/adau1450 s/pdif receiver auxiliary outputs enable register address: 0xf608, reset: 0x0000, name: spdif_aux_e n the s/pdif re ceiver on the adau1452 and adau1451 decodes embedded non audio data bits on the incoming data stream, including channel status, user data, validity bits, and parity bits. this information, t ogether with the decoded audio data, can optionally be output on one of the sdata_outx pins using register 0xf608 ( spdif_aux_en ) . the serial output port selected by bits [3:0] ( tdmout ) output s an 8 - channel tdm stream containing this decoded information. cha nnel 0 in the tdm8 stream contain s the 24 audio bits from the left s/pdif input channel, followed by eight zero bits. channel 1 in the tdm8 stream contain s 20 zero bits, the parity bit, validity bit, user data bit, and the channel status bit from the left s/pdif input channel, followed by eight zero bits. channel 2 in the tdm8 stream contains 22 zero bits , followed by the compression type bit (0b0 represents ac3 and 0b1 represents dts) and the audio type bit (0b0 represents pcm and 0b1 represents compressed ), followed by eight zero bits. channel 3 in the tdm8 stream contains 32 zero bits. channel 4 in the tdm8 stream contains the 24 audio bits from the right s/pdif input channel, followed by eight zero bits. channel 5 in the tdm8 stream contains 20 zero bits followed by the parity bit, validity bit, user data bit, and channel status bit from the right s/pdif input channel, followed by eight zero bits. channel 6 in the tdm8 stream contain s 32 zero bits. channel 7 in the tdm8 stream contains 23 zero bits, the b lock start bit, and eight zero bits. table 130 . bit descriptions for spdif_aux_en bits bit name settings description reset access [15:5] reserved 0x0 rw 4 tdmout_clk s/pdif tdm clock source. when bits [3:0] ( tdmout ) are configur ed to output s/pdif receiver data on one of the sdata_out x pins, the corresponding serial port m ust be set in master mode; and bit 4 ( tdmout_clk ) configures w hich clock signals are used on the corresponding bclk_out x and lrclk_out x pins. if bit 4 ( tdmout_c lk ) = 0b0, the clock signals recovered from the s/pdif input signal are used to clock the serial output. if bit 4 ( tdmout_ clk ) = 0b1, the output of clock generator 3 is used to clock serial output; and register 0xf026 ( clk_gen3_src ), bits [3:0] ( fref_pin ) , must be 0b1110 , and register 0xf026 (clk_gen3_src) , bit 4 ( clk_gen3_src ) , must be 0b1 . 0x0 rw 0 use clocks derived from s/pdif receiver stream 1 use filtered clocks from internal clock generator [3:0] tdmout s/pdif tdm output channel selection. 0x0 rw 0001 output on sdata_out0 0010 output on sdata_out1 0100 output on sdata_out2 1000 output on sdata_out3 0000 disable s/pdif tdm output rev. c | page 149 of 180
adau1452/adau1451/adau1450 data sheet s/pdif receiver auxiliary bits ready flag register address: 0xf60f, reset: 0x0000, name : spdif_rx_auxbit_ready the decoded channel status, user data, validity, and parity bits are recovered from the input signal one frame at a time unti l a full block of 192 frames is received on the adau1452 and adau1451 . when all of the 192 frames are received and decoded, bit 0 ( auxbits_ready ) , change s state from 0b0 to 0b1, indicating that the full block of data has been recovered and is available to be read from the corresponding registers. table 131 . bit descriptions for spdif_rx_auxbit_ready bits bit name settings description reset access [15:1] reserved 0x0 rw 0 auxbits_ready auxiliary bits are ready flag. 0x0 r 0 auxiliary bits are not ready to be output 1 auxiliar y bits are ready to be output s/pdif receiver channel status bits (left) register address: 0xf610 to 0xf61b (increments of 0x1), reset: 0x0000, name: spdif_rx_cs_left_ x these 12 registers store the 192 channel status bits decoded from the left channel of the s/pdif input stream on the adau1452 and adau1451 . table 132 . bit descriptions for spdif_rx_cs_left_ x bits bit name settings description reset access [15:0] spdif_rx_cs_left s/pdif receiver channel status bits (left). 0x0000 r s/pdif receiver channel status bits (right) register address: 0xf620 to 0xf62b (increments of 0x1), reset: 0x0000, name: spdif_rx_cs_right_ x these 12 registers store the 192 channel status bits decod ed from the right channel of the s/pdif input stream on the adau1452 and adau1451 . table 133 . bit desc riptions for spdif_rx_cs_right_x bits bit name settings description reset acce ss [15:0] spdif_rx_cs_right s/pdif receiver channel status bits (right). 0x0000 r rev. c | page 150 of 180
data sheet adau1452/adau1451/adau1450 s/pdif receiver user data bits (left) register address: 0xf630 to 0xf63b (increments of 0x1), reset: 0x0000, name: spdif_rx_ud_left_ x these 12 registers store the 192 user data bits decoded from the left channel of the s/pdif input stream on the adau1452 and adau1451 . table 134 . bit descriptions for spdif_rx_ud _left_x bits bit name settings descript ion reset access [15:0] spdif_rx_ud_left s/pdif receiver user data bits (left). 0x0000 r s/pdif receiver user data bits (right) register address: 0xf640 to 0xf64b (increments of 0x1), reset: 0x0000, name: spdif_rx_ud_right_ x these 12 registers store th e 192 user data bits decoded from the right channel of the s/pdif input stream on the adau1452 and adau1451 . table 135 . bit descriptions for spdif_rx_ud_right_ x bits bit name setti ngs description reset access [15:0] spdif_rx_ud_right s/pdif receiver user data bits (right). 0x0000 r s/pdif receiver validity bits (left) register address: 0xf650 to 0xf65b (increments of 0x1), reset: 0x0000, name: spdif_rx_vb_left_ x these 12 registe rs store the 192 validity bits decoded from the left channel of the s/pdif input stream on the adau1452 and adau1451 . table 136 . bit descriptions for spdif_rx_vb_left_ x bits bit na me settings description reset access [15:0] spdif_rx_vb_left s/pdif receiver validity bits (left). 0x0000 r rev. c | page 151 of 180
adau1452/adau1451/adau1450 data sheet s/pdif receiver validity bits (right) register address: 0xf660 to 0xf66b (increments of 0x1), reset: 0x0000, name: spdif_rx_vb_right_ x these 12 registers store the 192 validity bits decoded from the left channel of the s/pdif input stream on the ad au1452 and adau1451 . table 137 . bit descriptions for spdif_rx_vb_right_ x bit s bit name settings description reset access 15:0 spdifrxvbright s/pdif receiver validity bits (right). 0x0000 r s/pdif receiver parity bits (left) register address: 0xf670 to 0xf67b (increments of 0x1), reset: 0x0000, name: spdif_rx_pb_left_ x the se 12 registers store the 192 parity bits decoded from the left channel of the s/pdif input stream on the adau1452 and adau1451 . table 138 . bit descriptions for spdif_rx_pb_left_ x bits bit name settings description reset access [15:0] spdif_rx_pb_left s/pdif receiver parity bits (left). 0x0000 r s/pdif receiver parity bits (right) register address: 0xf680 to 0xf68b (increments of 0x1), reset: 0x0000, name: spdif_rx_pb_right_ x th ese 12 registers store the 192 parity bits decoded from the right channel of the s/pdif input stream on the adau1452 and adau1451 . table 139 . bit descriptions for spdif_rx_pb_right _ x bits bit name settings description reset access [15:0] spdif_rx_pb_right s/pdif receiver parity bits (right). 0x0000 r rev. c | page 152 of 180
data sheet adau1452/adau1451/adau1450 s/pdif transmitter enable register address: 0xf690, reset: 0x0000, name: spdif_tx_en this register enables or disables the s/pdif transmitter on the adau1452 and adau1451 . when the transmitter is disabled, it output s a constant stream of zero data. when the s/pdif transmitter is disabled, it still consume s power. to power down the s /pdif transmitter for the purpose of power savings, set re g ister 0xf051 ( power_enable1 ), bit 2 ( tx_pwr ) = 0b0. table 140 . bit descriptions for spdif_tx_en bits bit name settings description reset access [15:1] reserved 0x0 rw 0 txen s/pdif transmitter output enable. 0x0 rw 0 disabled 1 enabled s/pdif transmitter control register address: 0xf691, reset: 0x0000, name: spdif_tx_ctrl this register contro ls the length of the audio data - words output by the s/pdif transmitt er on the adau1452 and adau1451 . the maximum word length is 24 bits. if a shorter word length is selected using bits [1:0] ( tx_lengthctrl ) , the extraneous bits are truncated, starting with the least signif icant bit. if bits [1:0] ( tx_lengthctrl ) = 0b11, the decoded channel status bits on the input stream of the s/pdif receiver automatically set the word length on the s/pdif transmitter. table 141 . bit descriptions for spdif_tx_ctrl bi ts bit name settings description reset access [15:2] reserved 0x0 rw [1:0] tx_lengthctrl s/pdif transmitter audio word length. 0x0 rw 00 24 bits 01 20 bits 10 16 bits 11 automatic (determined by channel status bits detected in the s/ pdif input stream) rev. c | page 153 of 180
adau1452/adau1451/adau1450 data sheet s/pdif transmitter auxiliary bits source select register address: 0xf69f, reset: 0x0000, name: spdif_tx_auxbit_source this register configur es whether the encoded non audio data bits in the output data stream of the s/pdif transmitter on the adau1452 and adau1451 are copied directly from the s/pdif receiver or set manually using the corresponding control registers. if the data is configured manually, all channel status, parity, user d ata, and validity bits can be manually set using the following registers: spdif_tx_cs_left_ x , spdif_tx_cs_right_ x , spdif_tx_ud_left_x, spdif_tx_ud_right_x, spdif_tx_vb_left_x, spdif_tx_vb_right_x, spdif_tx_pb_left_ x , and spdif_tx_pb_right_ x . table 142 . bit descriptions for spdif_tx_auxbit_source bits bit name settings description reset access [15:1] reserved 0x0 rw 0 tx_auxbits_source auxiliary bits source. 0x0 rw 0 source from register map (user programmable) 1 source f rom s/pdif receiver (derived from input data stream) s/pdif transmitter channel status bits (left) register address: 0xf6a0 to 0xf6ab (increments of 0x1), reset: 0x0000, name: spdif_tx_cs_left_ x these 12 registers allow the 192 channel status bits enco ded on the left channel of the output data stream of the s/pdif transmitter on the adau1452 and adau1451 to be manually configured. f or these bits to be output properly on the s/pdif transmitter, register 0xf69f ( spdif_tx_auxbit_source ), bit 0 ( tx_auxbits_source ) , must be set to 0b0. table 143 . bit des criptions for spdif_tx_cs_left_x bits bit name settings description reset access [15:0] spdif_tx_cs_left s/pdif transmitter channel status bits (left). 0x0000 rw s/pdif transmitter channel status bits (right) register address: 0xf6b0 to 0xf6bb (increments of 0x1), reset: 0x0000, name: spdif_tx_cs_right_ x these 12 registers allow the 192 channel status bits encoded on the right chann el of the output data stream of the s/pdif transmitter on the adau1452 and adau1451 to be manually configured. f or these bits to be output properly on the s/pdif transmitter, register 0xf69f ( spdif_tx_aux bit_source ), bit 0 ( tx_auxbits_source ) , must be set to 0b0. table 144 . bit descriptions for spdif_tx_cs_right_ x bits bit name settings description reset access 15:0 spdiftxcsright s/pdif receiver channel status bits (right). 0x0000 rw rev. c page 154 of 180
data sheet adau1452/adau1451/adau1450 s/pdif transmitter user data bits (left) register address: 0xf6c0 to 0xf6cb (increments of 0x1), reset: 0x0000, name: spdif_tx_ud_left_ x these 12 registers allow the 192 user data bits encoded on the left channel of the output data stream of the s/pdif transmitter on the adau1452 and adau1451 to be manually configured. f or these bits to be output properly on the s/pdif transmitter, register 0xf69f ( spdif_tx_auxbit_source ), bit 0 ( tx_auxbits_sour ce ) , must be set to 0b0. table 145 . bit descriptions for spdif_tx_ud_left_ x bits bit name settings description reset access [15:0] spdif_tx_ud_left s/pdif transmitter user data bits (left). 0x0000 rw s/pdif transmitter user data bits (right) register address: 0xf6d0 to 0xf6db (increments of 0x1), reset: 0x0000, name: spdif_tx_ud_right_ x these 12 registers allow the 192 user data bits encoded on the right channel of the output data stream of the s/pdif transmitter on the adau1452 and adau1451 to be manually configured. f or these bits to be output properly on the s/pdif transmitter, register 0xf69f (spdif_tx_auxbit_source), bit 0 ( tx_auxbits_source ) , must be set to 0b0. table 146 . bit descriptions for spdif_tx_ud_right_ x bits bit name settings description reset access [15:0] spdif_tx_ud_right s/pdif transmitter user data bits (right). 0x0000 rw s/pdif transmitter validity bits (left) register address: 0xf 6e0 to 0xf6eb (increments of 0x1), reset: 0x0000, name: spdif_tx_vb_left_ x these 12 registers allow the 192 validity bits encoded on the left channel of the output data stream of the s/pdif transmitter on the adau1452 and adau1451 to be manually configured. f or these bits to be output properly on the s/pdif transmitter, r egister 0xf69f ( spdif_tx_auxbit_source ), bit 0 ( tx_auxbits_source ) , must be set to 0b0. table 147 . bit descriptio ns for spdif_tx_vb_left_ x bits bit name settings description reset access [15:0] spdif_tx_vb_left s/pdif transmitter validity bits (left). 0x0000 rw rev. c | page 155 of 180
adau1452/adau1451/adau1450 data sheet s/pdif transmitter validity bits (right) register address: 0xf6f0 to 0xf6fb (increments of 0x1), reset: 0x0000, name: spdif_tx_vb_right_ x these 12 registers allow the 192 validity bits encoded on the right channel of the output data stream of the s/pdif transmitter on the adau1452 and adau1451 to be manual ly configured. for these bits to be output properly on the s/pdif transmitter, register 0xf69f ( spdif_tx_auxbit_source ), bit 0 ( tx_auxbits_source ), must be set to 0b0. table 1 48 . bit descriptions for spdif_tx_vb_right_ x bits bit nam e settings description reset access [15:0] spdif_tx_vb_right s/pdif transmitter validity bits (right). 0x0000 rw s/pdif transmitter parity bits (left) register address: 0xf700 to address 0xf70b (increments of 0x1), reset: 0x0000, name: spdif_tx_pb_left _ x these 12 registers allow the 192 parity bits encoded on the left channel of the output data stream of the s/pdif transmitter on the adau1452 and adau1451 to be manually configured. f or these bits to be output properly on the s/pdif transmitter, register 0xf69f ( spdif_tx_auxbit_source ), bit 0 ( tx_auxbits_source ), must be set to 0b0. table 149 . bit descriptions for spdif_tx_pb_left_ x bits bit name settings description reset access [15:0] spdif_tx_pb_left s/pdif transmitter parity bits (left). 0x0000 rw s/pdif transmitter parity bits (right) register address: 0xf710 to address 0xf71b (increments of 0x1), reset: 0x0000, name: spdif_tx_pb_right_ x these 12 registers allow the 192 pa rity bits encoded on the right channel of the output data stream of the s/pdif transmitter on the adau14 52 and adau1451 to be manually configured. f or these bits to be output properly on the s/pdif transm itter, register 0xf69f ( spdif_tx_auxbit_source ) , bit 0 ( tx_auxbits_source ) , must be set to 0b0. table 150 . bit descriptions for spdif_tx_pb_right_ x bits bit name settings description reset access [15:0] spdif_tx_pb_right s/pdif tr ansmitter parity bits (right). 0x0000 rw rev. c | page 156 of 180
data sheet adau1452/adau1451/adau1450 hardware interfacing registers bclk input pins drive strength and slew rate register address: 0xf780 to 0xf783 (increments of 0x1 ), reset: 0x0018, name: bclk_inx _pin these registers configure the drive strength, s lew rate, and pull resistors for the bclk_inx pins. register 0xf780 corresponds to bclk_in0 , register 0xf781 corresponds to bclk_in1, register 0xf782 corresponds to bclk_in2, and register 0xf783 corresponds to bclk_in3. table 151 . b it descriptions for bclk_in x _pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 bclk_in_pull bclk_in x pull - down. 0x1 rw 0 pull - down disabled 1 pull - down enabled [3:2] bclk_in_slew bclk_in x slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest [1:0] bclk_in_drive bclk_in x drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 157 of 180
adau1452/adau1451/adau1450 data sheet bclk output pins drive strength and slew rate register address: 0xf784 to 0xf787 (increments of 0x1), reset: 0x0018, name: bclk_out x _pin these registers configure the drive strength, slew rate, and pull resistors for the bclk_out x pins. register 0xf784 corresponds to bclk_out0, register 0xf785 corresponds to bclk_out1, register 0xf786 corresponds to bclk_out2, and register 0xf787 corresponds to bclk_out3. table 152 . bit descriptions for bclk_outx _pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 bclk_out_pull bclk_out x pull - down. 0x1 rw 0 pull - down disabled 1 pull - down enabled [3:2] bclk_out_slew bclk_out x slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest [1:0] bclk_out_drive bclk_out x drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 158 of 180
data sheet adau1452/adau1451/adau1450 lrclk input pins drive strength and slew rate register address: 0xf788 to 0xf78b (increments of 0x1), reset: 0x0018, name: lrclk_in x _pin these registers configure the drive strength, slew rate, and pull resistors for the lrclk_in x pins. registe r 0xf78 8 corresponds to lrclk_in0/mp10, register 0xf78 9 corresponds to lrclk_in1/mp11, register 0xf78a corresponds to lrclk_in2/ mp12, and register 0xf78b corresponds to lrclk_in3/mp13. table 153 . bit descriptions for lrclk_inx _pin b its bit name settings description reset access [15:5] reserved 0x0 rw 4 lrclk_in_pull lrclk_in x pull - down. 0x1 rw 0 pull - down disabled 1 pull - down enabled [3:2] lrclk_in_slew lrclk_in x slew rate. 0x2 rw 00 slowest 01 slow 10 f ast 11 fastest [1:0] lrclk_in_drive lrclk_in x drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 159 of 180
adau1452/adau1451/adau1450 data sheet lrclk output pins drive strength and slew rate register address: 0xf78c to 0xf78f (increments of 0x1), reset: 0x0018, na me: lrclk_outx _pin these registers configure the drive strength, slew rate, and p ull resistors for the lrclk_outx pins. register 0xf78c corresponds to lrclk_out0/mp4, register 0xf78 d corresponds to lrclk_out1/mp5, register 0xf78 e corresponds to lrclk_out2/ mp8, and register 0xf78f corresponds to lrclk_out3/mp9. table 154 . bit descriptions for lrclk_ outx _pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 lrclk_out_pull lrclk_out x pull - down. 0x1 rw 0 pu ll - down disabled 1 pull - down enabled [3:2] lrclk_out_slew lrclk_out x slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest [1:0] lrclk_out_drive lrclk_out x drive strength. 0x0 rw 00 lowest 01 low 10 high 1 1 highest rev. c | page 160 of 180
data sheet adau1452/adau1451/adau1450 sdata input pins drive strength and slew rate register address: 0xf790 to 0xf793 (increments of 0x1), reset: 0x0018, name: sdata_in x _pin these registers configure the drive strength, slew rate, and pull resistors for the sdata_in x pins. regis ter 0xf790 corresponds to sdata_in0 , register 0xf791 corresponds to sdata_in1, register 0xf792 corresponds to sdata_in2, and register 0xf793 corresponds to sdata_in3. table 155 . bit descriptions for sdata_inx _pin bits bit name setti ngs description reset access [15:5] reserved 0x0 rw 4 sdata_in_pull sdata_in x pull - down. 0x1 rw 0 pull - down disabled 1 pull - down enabled [3:2] sdata_in_slew sdata_in x slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastes t [1:0] sdata_in_drive sdata_in x drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 161 of 180
adau1452/adau1451/adau1450 data sheet sdata output pins drive strength and slew rate register address: 0xf794 to 0xf797 (increments of 0x1), reset: 0x0008, name: sdata_out x _pin these registers configure the drive strength, slew rate, and pull resistors for the sdata_out x pins. register 0xf 794 corresponds to sdata_out0, register 0 xf795 corresponds to sdata_out1, register 0 xf796 corresponds to sdata_out2, and register 0xf797 corre sponds to sdata_out3. table 156 . bit descriptions for sdata_outx _pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 sdata_out_pull sdata_out x pull - down. 0x0 rw 0 pull - down disabled 1 pull - down enabled [3:2] sdata_out_slew sdata_out x slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest [1:0] sdata_out_drive sdata_out x drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 162 of 180
data sheet adau1452/adau1451/adau1450 rev. c | page 163 of 180 s/pdif transmitter pin drive stre ngth and slew rate register address: 0xf798, reset: 0x0008, name: spdif_tx_pin this register configures the drive strength, slew rate, and pull resistors for the spdifout pin on the adau1452 and adau1451 . table 157. bit descriptions for spdif_tx_pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 spdif_tx_pull spdifout pull-down. 0x0 rw 0 pull-down disabled 1 pull-down enabled [3:2] spdif_tx_slew spdifout slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest [1:0] spdif_tx_drive spdifout drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest
adau1452/adau1451/adau1450 data sheet sclk/scl pin drive strength and slew ra te register address: 0xf799, reset: 0x0008, name: sclk_scl_pin this register configures the drive strength, slew rate, and pull resistors for the sclk/scl pin. table 158 . bit descriptions for sclk_scl_pin bits bit name settings desc ription reset access 15:5 reserved 0x0 rw 4 sclksclpull sclk/scl pull - up. 0x0 rw 0 pull - up disabled 1 pull - up enabled 3:2 sclksclslew sclk/scl slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest 1:0 sclk scldrive sclk/scl drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 164 of 180
data sheet adau1452/adau1451/adau1450 miso/sda pin drive strength and slew rate register address: 0xf79a, reset: 0x0008, name: miso_sda_pin this register configures the drive strength, slew rate, and pull resistors for the miso/sda pin. table 159 . bit descriptions for miso_sda_pin bits bit name settings description reset access 15:5 reserved 0x0 rw 4 misosdapull miso/sda pull - up. 0x0 rw 0 pull - up disabled 1 pull - up enabled 3:2 misosdaslew miso/sda slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest 1:0 misosdadrive miso/sda drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 165 of 180
adau1452/adau1451/adau1450 data sheet ss/addr0 pin drive strength and slew rate register address: 0xf79b, reset: 0x0018, name: ss_pin this register configures the drive strength, slew rate, and pull resistors for the ss/addr0 pin. table 160 . bit descriptions for ss_pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 ss_pull ss/addr0 pull - up. 0x1 rw 0 pull - up disabled 1 pull - up enabled [3:2] ss_slew ss/addr0 slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest [1:0] ss_drive ss/addr0 drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 166 of 180
data sheet adau1452/adau1451/adau1450 mosi/addr1 pin drive strength and slew rate register address: 0xf79c, reset: 0x0018, name: mosi_addr1_pin thi s register configures the drive strength, slew rate, and pull resistors for the mosi/addr1 pin. table 161 . bit descriptions for mosi_addr1_pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 mosi_addr1_p ull mosi/addr1 pull - up. 0x1 rw 0 pull - up disabled 1 pull - up enabled [3:2] mosi_addr1_slew mosi/addr1 slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest [1:0] mosi_addr1_drive mosi/addr1 drive strength. 0x0 rw 00 l owest 01 low 10 high 11 highest rev. c | page 167 of 180
adau1452/adau1451/adau1450 data sheet scl_m/sclk_m/mp2 pin drive strength and slew rate register address: 0xf79d, reset: 0x0008, name: sclk_scl_m_pin this register configures the drive strength, slew rate, and pull resistors for the scl_m/sclk _m/mp2 pin. table 162 . bit descriptions for sclk_scl_m_pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 sclk_scl_m_pull scl_m/sclk_m/mp2 pull - up. 0x0 rw 0 pull - up disabled 1 pull - up enabled [3:2] sclk_scl_m_slew scl_m/sclk_m/mp2 slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest [1:0] sclk_scl_m_drive scl_m/sclk_m/mp2 drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 168 of 180
data sheet adau1452/adau1451/adau1450 sda_m/miso_m/mp 3 pin drive strength and slew rate register address: 0xf79e, reset: 0x0008, name: miso_sda_m_pin this register configures the drive strength, slew rate, and pull resistors for the sda_m/miso_m/mp3 pin. table 163 . bit descriptions fo r miso_sda_m_pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 miso_sda_m_pull sda_m/miso_m/mp3 pull - up. 0x0 rw 0 pull - up disabled 1 pull - up enabled [3:2] miso_sda_m_slew sda_m/miso_m/mp3 slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest [1:0] miso_sda_m_drive sda_m/miso_m/mp3 drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 169 of 180
adau1452/adau1451/adau1450 data sheet ss_m/mp0 pin drive strength and slew rate register address: 0xf79f, reset: 0x0018 , name: ss_m_pin this register configures the drive strength, slew rate, and pull resistors for the ss_m/mp0 pin. table 164 . bit descriptions for ss_m_pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 ss_m_pull ss_m/mp0 pull - up. 0x1 rw 0 pull - up disabled 1 pull - up enabled [3:2] ss_m_slew ss_m/mp0 slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest [1:0] ss_m_drive ss_m/mp0 drive strength. 0x0 rw 00 lowest 0 1 low 10 high 11 highest rev. c | page 170 of 180
data sheet adau1452/adau1451/adau1450 mosi_m/mp1 pin drive strength and slew rate register address: 0xf7a0, reset: 0x0018, name: mosi_m_pin this register configures the drive strength, slew rate, and pull resistors for the mosi_m/mp1 pin. table 165 . bit descriptions for mosi_m_pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 mosi_m_pull mosi_m/mp1 pull - up. 0x1 rw 0 pull - up disabled 1 pull - up enabled [3:2] mosi_m_slew mosi_m/mp1 slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest [1:0] mosi_m_drive mosi_m/mp1 drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 171 of 180
adau1452/adau1451/adau1450 data sheet mp6 pin drive strength and slew rate register address: 0xf7a1, reset: 0x0018, name: mp6_pin this register configures the drive strength, slew rate, and pull resistors for the mp6 pin. table 166 . bit descriptions for mp6_pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 mp6_pull mp6 pull - down. 0x1 rw 0 pull - down disabled 1 pull - down enabled [3:2] mp6_slew mp6 slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest [1:0] mp6_drive mp6 drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 172 of 180
data sheet adau1452/adau1451/adau1450 mp7 pin drive strength and slew rate register address: 0xf7a2, reset: 0x0018, name: mp7_pin this register configures the drive strength, slew rate, and pull resistors for the mp7 pin. table 167 . bit descriptions f or mp7_pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 mp7_pull mp7 pull - down. 0x1 rw 0 pull - down disabled 1 pull - down enabled [3:2] mp7_slew mp7 slew rate. 0x2 rw 00 slowest 01 slow 10 fast 1 1 fastest [1:0] mp7_drive mp7 drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 173 of 180
adau1452/adau1451/adau1450 data sheet clkout pin drive strength and slew rate register address: 0xf7a3, reset: 0x0008, name: clkout_pin this register configures the drive strength , slew rate, and pull resistors for the clkout pin. table 168 . bit descriptions for clkout_pin bits bit name settings description reset access [15:5] reserved 0x0 rw 4 clkout_pull clkout pull - down. 0x0 rw 0 pull - down disable d 1 pull - down enabled [3:2] clkout_slew clkout slew rate. 0x2 rw 00 slowest 01 slow 10 fast 11 fastest [1:0] clkout_drive clkout drive strength. 0x0 rw 00 lowest 01 low 10 high 11 highest rev. c | page 174 of 180
data sheet adau1452/adau1451/adau1450 soft reset regi ster address: 0xf890, reset: 0x0001, name: soft_reset soft_reset provides the capability to reset all control registers in the device o r put it into a state similar to a hardware reset, where the reset pin is pulled low to ground. all co ntrol registers are reset to their default values, except for the pll registers : register 0xf000 ( pll_ctrl0 ), register 0xf001 (pll_ctrl1), register 0xf002 (pll_clk_src), register 0xf003 (pll_enable), register 0xf004 (pll_lock), register 0xf005 (mclk_out), and register 0xf006 ( pll_watchdog) , as well as registers related to the panic manager. the i 2 c and spi slave ports remain operational, and the user can write new values to the pll registers while the soft reset is active. if spi slave mode is enabled, the device remain s in spi slave mode during and after the soft reset state. t o reset the device to i 2 c slave mode, the device must undergo a hardware reset by pulling the reset pin low to ground. bit 0 ( soft_reset ) is acti ve low, meaning tha t setting it to 0b1 e nables normal operation and setting it to 0b0 enables the soft reset state. table 169 . bit descriptions for soft_reset bits bit name settings description reset access 15:1 reserved 0x0 rw 0 softreset sof t reset. 0x1 rw 0 soft reset enabled 1 soft re set disabled normal operation rev. c | page 175 of 180
adau1452/adau1451/adau1450 data sheet applications informa tion pcb design considera tions a solid ground pl ane is a necessity for maintain ing signal integrity and minimizing emi radiation. if the pcb has two ground planes, they can be stitched together using vias that are spre ad evenly throughout the board. power supply bypass capacitors bypass e ach power supply pin to its nearest appropriate ground pin with a single 100 nf capacitor and , optionally , with an addi - tional 10 nf capacitor in parallel . make t he connections to each side of the capacitor as short as possible, and keep the trace on a single layer with no vias. for maximum effectiveness, place the capacitor either equidistant from the power and gr ound pins or, when equidistant placement is not possible, sli ghtly nearer to the power pin (see figure 81) . establish the t hermal connections to the planes on the f ar side of the capacitor. power ground to ground to power capacitor 1 1486-087 figure 81 . recommended power supply bypass capacitor layout typically, a single 100 nf c apacitor for each power ground pin pair is sufficient. however, if there is excessi ve high frequency noise in the system, use an additional 10 nf capacitor in para llel (see figure 82) . in that case, place the 10 nf capacitor between the devices and the 100 nf capacitor , and establish th e thermal connections on the far side of the 100 nf capacitor. via to power plane dvdd dgnd via to ground plane 10nf 100nf 1 1486-088 figure 82 . layout for multiple power supply bypass capacitors to provide a current reservoir in case of sudden current spikes, use a 10 f capacitor for each named supply (dvdd, avdd, pvdd, and iovdd) as shown in figure 83. bulk bypass capacitors 3.3v avdd pvdd iovdd dvdd 10 f + 10 f + 10 f + 10 f + 1 1486-089 figure 83 . bulk capacitor schematic parts placement place a ll 100 nf bypass capacitors, which are recommended for every analog, digital, and pll power ground pair, as near as possible to the adau1452 / adau1451 / adau1450 . bypass each of t he avdd, dvdd, pvdd, and i ovdd supply signals on the board with an additional single bulk capacitor (10 f to 47 f). keep a ll traces in the crystal resonator circuit (see figure 15) as short as possible to minimize stray capacitance. do not connect any long board traces to the crystal oscillator circuit components because such traces may affect crystal startup and operation. grounding use a single ground plane in the application layout. place all c omponents in an analog signal path away f rom digital signals. exposed pad pcb design the device package includes an exposed pad for improved heat dissipation. when designing a board for such a package, give special consideration to the following: ? place a copper layer , equal in size to the exposed pad , on all layers of the bo ard, from top to bottom. c onnect the copper layer s to a dedicated copper board layer (see figure 84). t o p p o w er g r o u n d b o t t o m c o ppe r s q ua r es v i a s 1 1486 - 09 0 figure 84 . exposed pad layout example side view ? place v ias such that all layers of copper are connected , allowing for efficient heat and energy conductivity. for an example, see figure 85 , which shows 49 vias arranged in a 7 7 grid in the pad area. 1 1486 - 09 1 figure 85 . exposed pad layout example top view pll filter to minimize jitter, connect t he single resistor and two capacitors in the pll filter to the pll filt and pvdd pins with short traces. rev. c | page 176 of 180
data sheet adau1452/adau1451/adau1450 power supply isolation with ferrite beads f errite beads can be used for supply isolation. when using ferrite beads , always place the beads outside the local high frequency decoupling capacitors, as shown in figure 86 . if the ferrite beads are placed between the supply pin and the decoupling cap a citor, high frequency noise is reflected back into the ic because there is no suitable return path to ground. as a result, emi increases, creating noisy supplies. eos/esd protection although the adau1452 / adau1451 / adau1450 has robust internal protection circuitry again st overvoltages and electrostatic discharge, an external transient voltage supp ressor (tvs) is recommended for all systems to prevent damage to the ic. for examples, see the an - 311 appli cation note . dgnd iovdd iovdd 3.3v dvdd 1.2v vdrive 100nf (bypass) 100nf (bypass) 1k dvdd 10 f or 4.7f reservoir main 3.3v supply ferrite bead + 10 f or 4.7f reservoir + dgnd 1 1486-092 1 3 2 71 72 figure 86 . ferrite bead power supply isolation circuit example typical applications block diagram multimedia can bus micro- controller spi eflash class ab/d 4-channel amplifier class ab/d 4-channel amplifier i 2 c spdif rx adau1452/ adau1451/ adau1450 pdm microphones analog microphones speakers can transceiver can 0 spi spi ad1938/ ad1939 codec 8-channel dac head unit adau1977 microphone adc pdm 1 1486-095 figure 87 . automotive infotainment amplifier block diagram rev. c | page 177 of 180
adau1452/adau1451/adau1450 data sheet example pcb layout seve ral e xternal components, such as capacitors, resistors, and a transistor, are required for proper operation of the device. an example of the connection and layout of these components is shown in figure 88. thick black lines represent traces, gray rectangles represent components, and white circles with a thick black ring represent thermal via connections to power or ground planes. if a 1.2 v supply is available in the system, the transistor circuit (including the a ssociated 1 k resistor) can be removed, and 1.2 v can be connected directly to the dvdd power net, with the vdrive pin left floating. the analog (avdd), pll (pvdd), and interface (iovdd) supply pins each have local 100 nf bypass capacitors to provide high frequency return currents with a short path to ground. the digital (dvdd) supply pins each have up to three local bypass capacitors, as follows: ? the 10 nf bypass capacitor, placed closest to the pin, acts as a return path for very high frequency current s resulting from the nominal 294 mhz operating frequency of the dsp core . ? the 100 nf bypass capacitor acts as a return path for hi gh frequency currents from the dsp and other digital circuitry. ? the 1 f bypass capacitor is required to provide a local current supply for sudden spikes in current that occur at the beginning of each audio frame when the dsp core switches from idle mode to operating mode. o f these three bypass capacitors, the most importa nt is the 100 nf bypass capacitor, which is required for proper power supply bypassing. the 10 nf and 1 f capacitors can optionally be used to improve the emi/emc performance of the system. ) bypass ) bypass )'9'' current reservoir )'9'' current reservoir ),29'' current reservoir )39'' current reservoir pll loop filter dvdd regulator iovdd iovdd dgnd pllfilt pvdd pgnd avdd agnd dgnd dgnd dgnd dvdd dvdd vdrive iovdd adau1452/ adau1451/ adau1450 (top view) c c e b std2805t4 100nf bypass 100nf bypass 100nf bypass 100nf bypass 100nf bypass 10nf bypass 10nf bypass 100nf bypass 100nf bypass 100nf bypass 100nf bypass p i n 1 10nf 100nf 100nf 100nf 100nf 100nf ) 10nf 100nf 100nf 100nf 100nf ) ) ) ) iovdd dgnd dgnd dgnd dvdd dvdd ) bypass 10nf bypass 100nf bypass 10nf 100nf ) ) bypass 10nf bypass 100nf bypass 10nf 100nf ) ) n 150pf n 5.6nf 1 1486-093 figure 88 . supporting component place ment and layout rev. c | page 178 of 180
data sheet adau1452/adau1451/adau1450 pcb manufacturing gu idelines the soldering profile in figure 89 is recommended for the lfcsp package. see the an - 772 applicat ion note for more information about pcb manufacturing guidelines. temperature (c) time (second) ramp down 6c/second max 217c 150c to 200c 260c 5c ramp up 3c/second max 60 seconds to 150 seconds 60 seconds to 180 seconds 20 seconds to 40 seconds 480 seconds max 1 1486-094 figure 89 . soldering profile 5 . 25 mm 0.30mm 0.55mm 0.55mm 0.30mm 0. 5 mm 0. 5 mm 10mm 8.5mm 10mm analog devices lfcsp_vq (cp-72-6) rev a 1 1486-097 figure 90 . pcb decal dimensions rev. c | page 179 of 180
adau1452/adau1451/adau1450 data sheet outline dimensions compliant to jedec standards mo-220-vnnd-4 0.20 ref 0.80 max 0.65 ty p 1.00 0.85 0.80 0.05 max 0.02 nom 1 18 54 37 19 36 72 55 0.50 0.40 0.30 8.50 ref pin 1 indic a t or se a ting plane 12 max 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 0.50 bsc pin 1 indic a t or coplanarit y 0.08 06-25-2012-c for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. t o p view exposed p ad bot t om view 10.10 10.00 sq 9.90 9.85 9.75 sq 9.65 0.25 min 5.45 5.30 sq 5.15 figure 91 . 72 - lead lea d frame chip scale p ackage [ l f cs p_vq] 10 mm 10 mm body, very t hin quad (cp - 72 - 6) dimensions shown in millimeters ordering guide model 1 , 2 temperature range package description package option adau1452 wbcpz ?40c to +105c 72- lead lead frame chip scale pa ckage [lfcsp_vq] cp -72-6 adau1452 wbcpz -rl ?40c to +105c 72- lead lead frame chip scale package [lfcsp_vq] , 13 tape and reel cp -72-6 adau1451 wbcpz ?40c to +105c 72- lead lead frame chip scale package [lfcsp_vq] cp -72-6 adau1451 wbcpz -rl ?40c to +105c 72- lead lead frame chip scale package [lfcsp_vq] , 13 tape and reel cp -72-6 adau1450 wbcpz ?40c to +105c 72- lead lead frame chip scale package [lfcsp_vq] cp -72-6 adau1450 wbcpz -rl ?40c to +105c 72- lead lead frame chip scale package [lfcsp_vq] , 13 tap e and reel cp -72-6 eval - adau1452 z evaluation board eval - adau1452 miniz evaluation board 1 z = rohs compliant part. 2 w = qualified for automotive applications. automotive products the adau1452w / adau1451w / adau1450w models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these autom otive models may have specifications that differ from the commercial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applicatio ns. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliab ility reports for these models. i 2 c refers to a communications protocol originally developed by philips semi conductors (now nxp semiconductors). ? 2013 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11486 - 0- 7/14(c) rev. c | page 180 of 180

▲Up To Search▲

Price & Availability of EVAL-ADAU1452MINIZ

	To Download EVAL-ADAU1452MINIZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .