LDV5010 dvc read channel ldic 1 ldic confidential 1. LDV5010 feature overview the LDV5010 channel is tailored to run on the 41.85mhz digital video camera (dvc) platform. the main function is to read the signal from the media (presented by the preamp), extracting the data and the data clock for the controller. the secondary function is to detect the automatic tracking frequencies of 465khz and 697.5khz. in the dvc system, the LDV5010 interfaces to the preamp, microprocessor and controller. channel performance information is available through LDV5010?s quality engine, which can be used as a metric to help optimize the channel?s bit-error-rate. the LDV5010 utilizes a 0.18 micron cmos process technology for low power consumption and a small die area. the part requires two power supplies: 3.3v +/-10% and 1.8v +/-10% or one power supply of 3.3v +/-10% (with internal 1.8v voltage regulator enabled). the part is available in a 64-pin tqfp package. 2. chip features 2.1. general features ? fully integrated 41.85 mhz read channel device ? supports constant density recording of 41.85mbps with no external component changes ? fabricated in .18 micron cmos technology ? operating supply voltages: 3.3 10% and 1.8 +/-10% volts or one 3.3 10% (with internal 1.8v voltage regulator enabled). ? available in a 64-pin tqfp package. 2.2. read data conditioning ? full-differential analog front-end ? pr4 automatic sampled-time gain control loop algorithm ? 4-banded variable gain amplifier to accommodate input signal ranges of 30-300mvppd ? normalize the incoming data within 100-300 samples ? optional vga initial gain shadow registers for each head/field combination ? locks to random or 6t acquisition fields ? 7 th -order bessel continuous time filter ? programmable filter supports cut-offs from 6 to 30 mhz ? filter boost programmable from 0 to 10db ? flat group delay +/- 5% up to 1.5* fc, without boost ? 6-bit analog-to-digital converter ? automatic offset correction ? pr4 sampled-time timing recovery loop to frequency and phase acquire ? acquires to the incoming data within 100 to 300 samples on a 6t acquisition field ? locks to random data or a 6t acquisition field ? digital full-lms adaptive equalizer ? correlation detector detects highly correlated fields (2t, 4t, 6t or 12t) and stops adaptation
LDV5010 dvc read channel ldic 2 ldic confidential ? pr4 viterbi for data detection ? programmable drop-out detection 2.3. user programmable fields for system optimization ? programmable head recovery delay ? programmable idle times after drop-out, excess zeros and gaps ? programmable length of lowz after readgate (rg pin) assertion ? programmable acquisition field lengths for gain and timing recovery loops 2.4. head and field sensitive features ? when applicable, unique user defined parameters are provided for audio, and non-audio fields for head0 or head1 combinations in order to optimize for each head/field combination. 2.5. atf detector ? the LDV5010 includes a digital heterodyne tuner to detect the servo automatic tracking frequencies (atf) ? servo tone amplitude difference is provided on the stdif output pin. 2.6. trick mode support ? due to the programmable registers, the user is able to configure the part to work properly in various modes of operation, such as ntsc lp forward and lp reverse. ? dropouts are automatically detected via the dropout detector block 2.7. channel optimization vehicles ? quality metrics for use in channel optimization ? 8-bit digital test bus for testability and channel optimization 2.8. test modes ? built-in-test logic to minimize test vectors and allow fault testing in the field ? analog test inputs and outputs are provided for control and observation of internal analog blocks ? an 8-bit digital test bus is provided for digital and some analog testability 2.9. user interface ? three-bit serial interface port for access of internal configuration registers ? to load and verify register contents ? to monitor status ? to collect chip feedback 2.10. powerdown modes ? register controlled powerdown of analog blocks ? during non-read mode, the clock to the digital logic is shut-off to conserve power
LDV5010 dvc read channel ldic 3 ldic confidential ? an internal power-on-circuit (por) monitors the voltage level. when the voltage is too small, the chip is placed in powerdown mode, until the voltage assumes a working level. ? external power-down pin 3. absolute maximum ratings input voltages: cmos digital pins........... .................. ......... -0.3 v +3.6 v analog pins................. .................. ......... -0.3 v +3.6 v storage temperature, t stg .... .................. ......... -65 o c to 150 o c junction temperature, t j .... .................. ......... 0 o c to 110 o c thermal impedance, ja : still air................... .................. ......... 51 o c/w 200 fpm air flow............ .................. ......... 38 o c/w 600 fpm air flow............ .................. ......... 27 o c/w maximum power consumption: power supply maximum drawn current (with internal 1.8v regulator enabled @v cc = 3.3v).................. ....... 70ma 4. LDV5010 chip i/o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 44 43 42 41 40 39 38 37 36 35 34 33 61 53 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ldv5000 vsc rct vdc enreg vdg rab vsg dip din vsb rfil vdb ato1n vse ato1p vde vsa atip vda atin vdt ctr vst fref vsd4 rck vdd4 rd vdi2 rstb vsi2 pd vsd1 ato2p vdd1 ato2n vdf stdif vsd2 tb0 vdd2 tb1 vdi1 tb2 vsi1 tb3 vsf difref sm ssadet rg adphl d vdd3 do vsd3 sd sen sck tb7 tb6 tb5 tb4 hdsel lock 64 LDV5010 pin assignments for LDV5010 in a 64-pin tqfp package.
LDV5010 dvc read channel ldic 4 ldic confidential l d v 5 0 1 0 b l o ck diagram vg a di p din vg x vg y ctf vg x vg y ctx cty a f adrd afrd cdcd dd afrd ddrd ad c ctx cty adrd afrd adrd slrd trsl adafrd trd pherr adafrd slrd phadj tr a pherr phadj trck fref adrd afrd adafrd gcsl slrd gcd gcnewus slrd adafrd gcerr gcdac paddip paddin slgcrd ddrd sltrrd ddrd padrd ck rsck trck fref padfref cc do padrg qe afrd tb adrd gcerr gcnewus trerr adrg afrg lowz updo up reg_sel padsen padsd padsck updi updo up w upr padsen padsd padsck reg_selects updi updo up w upr adrd afrd adrg afrg lowz trerr gcerr gcnewus padtb pg pgrd pgrg pgrg pgrd test data s a updo rd padrg gcnewus gcnewus gcerr gcdac padxz updo io_tl padatoac padatix padatiy padatodc padatix padatiy padatoacx/y padatodcx/y por porb v d v d porb padrg cd cdcd slrd cdcd cdcd note: grey shading indicates an analog block xz ccgctrk cctrtrk ccgcrg cctrrg lowz cciacq gcda c td xz iorg gcnewus do paddo LDV5010 data path block diagram
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