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? semiconductor components industries, llc, 2013 september, 2013 ? rev. 0 1 publication order number: n01s830ha/d n01s830ha, n01s830ba 1 mb ultra-low power serial sram standard spi interface and multiplex dual and quad interface overview the on semiconductor serial sram family includes several integrated memory devices including this 1 mb serially accessed static random access memory, internally organized as 128 k words by 8 bits. the devices are designed and fabricated using on semiconductor?s advanced cmos technology to provide both high-speed performance and low power. the devices operate with a single chip select (cs ) input and use a simple serial peripheral interface (spi) protocol. in spi mode, a single data-in (si) and data-out (so) line is used along with the clock (sck) to access data within the device. in dual mode, two multiplexed data-in/data-out (sio0-sio1) lines are used and in quad mode, four multiplexed data-in/data-out (sio0-sio3) lines are used with the clock to access the memory. the devices can operate over a wide temperature range of ? 40 c to +85 c and are available in a 8-lead tssop package. the n01s830xa device has two different variations, a hold version that allows communication to the device to be paused and a battery back-up (bbu) version to be used with a battery to retain data when power is lost. features ? power supply range: 2.5 to 5.5 v ? very low typical standby current < 4 a ? very low operating current < 10 ma ? simple serial interface ? single-bit spi access ? dual-bit and quad-bit spi-like access ? flexible operating modes ? word mode ? page mode ? burst mode (full array) ? high frequency read and write operation ? clock frequency 20 mhz ? functional options ? hold pin for pausing operation ? vbat pin for battery ? back up ? built-in write protection (cs high) ? high reliability ? unlimited write cycles ? these devices are pb ? free and are rohs compliant ? green tssop table 1. device options device / part number power supply speed package function N01S830HAT22I hv 2.5 v ? 5.5 v 20 mhz tssop ? 8 hold n01s830bat22i hv 2.5 v ? 5.5 v 20 mhz tssop ? 8 bbu ? battery back-up http://onsemi.com tssop8 3x4.4 case 948bh package configuration 1 2 8 5 7 6 3 4 cs so / sio1 nc / sio2 vss vcc hold / sio3 sck si / sio0 hold version 1 2 8 5 7 6 3 4 cs so / sio1 nc vss vcc vbat sck si / sio0 bbu version device package shipping ? ordering information N01S830HAT22I tssop ? 8 (pb ? free) 100 units / tube N01S830HAT22It tssop ? 8 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. n01s830bat22i tssop ? 8 (pb ? free) 100 units / tube n01s830bat22it tssop ? 8 (pb ? free) 3000 / tape & reel
n01s830ha, n01s830ba http://onsemi.com 2 table 2. pin names pin name pin function cs chip select sck serial clock si / sio0 data input ? spi mode data input/output 0 ? dual and quad mode so / sio1 data output ? spi mode data input/output 1 ? dual and quad mode nc / sio2 no connect ? spi and dual mode data input/output 2 ? quad mode hold / sio3 hold version hold input ? spi and dual mode data input/output 3 ? quad mode vbat bbu version battery supply ? spi and dual mode v cc power v ss ground figure 1. functional block diagram sram array control logic interface circuitry decode logic data flow circuitry cs si / sio0 so / sio1 sio2 hold / sio3 sck battery controls vbat (hold version) (bbu version) table 3. control signal descriptions signal mode used name description cs all chip select a low level selects the device and a high level puts the device in standby mode. if cs is brought high during a program cycle, the cycle will complete and then the device will enter standby mode. when cs is high, so is in high-z. cs must be driven low after power-up prior to any sequence being started. sck all serial clock synchronizes all activities between the memory and controller. all incoming addresses, data and instructions are latched on the rising edge of sck. data out is updated after the falling edge of sck. si spi serial data in receives instructions, addresses and data on the rising edge of sck. so spi serial data out data is transferred out after the falling edge of sck. hold spi and dual hold a high level is required for normal operation. once the device is selected and a serial sequence is started, this input may be taken low to pause serial communication without resetting the serial sequence. the pin must be brought low while sck is low for immediate use. if sck is not low, the hold function will not be invoked until the next sck high to low transition. the device must remain selected during this sequence. so is high-z during the hold time and si and sck are inputs are ignored. to resume operations, hold must be pulled high while the sck pin is low. lowering the hold input at any time will take to so output to high-z. vbat spi and dual battery voltage provides the battery power connection to retain data in battery backed mode.
n01s830ha, n01s830ba http://onsemi.com 3 table 3. control signal descriptions signal description name mode used sio0 - 1 dual serial data input / output receives instructions, addresses and data on the rising edge of sck. data is transferred out after the falling edge of sck. the instruction must be set after power-up to enable the dual access mode. sio0 - 3 quad serial data input / output receives instructions, addresses and data on the rising edge of sck. data is transferred out after the falling edge of sck. the instruction must be set after power-up to enable the quad access mode. basic operation the 1 mb serial sram is designed to interface directly with a standard serial peripheral interface (spi) common on many standard micro-controllers in the default state. it may also interface with other non-spi ports by programming discrete i/o lines to operate the device. the serial sram contains an 8-bit instruction register and is accessed via the si pin. the cs pin must be low and the hold pin must be high for the entire operation. data is sampled on the first rising edge of sck after cs goes low. if the clock line is shared, the user can assert the hold input and place the device into a hold mode. after releasing the hold pin, the operation will resume from the point where it was held. the hold operation is only supported in spi and dual modes. by programming the device through a command instruction, the dual and quad access modes may be initiated. in these modes, multiplexed i/o lines take the place of the spi si and so pins and along with the cs and sck control the device in a spi-like, two bit (dual) and four bit (quad) wide serial manner. once the device is put into either the dual or quad mode, the device will remain operating in that mode until powered down or the reset mode operation is programmed. the following table contains the possible instructions and formats. all instructions, addresses and data are transferred msb first and lsb last. table 4. instruction set instruction command description read 03h read data from memory starting at selected address write 02h write (program) data to memory starting at selected address eqio 38h enable quad i/o access edio 3bh enable dual i/o access rstqio ffh reset from quad and dual to spi i/o access rdmr 05h read mode register wrmr 01h write mode register
n01s830ha, n01s830ba http://onsemi.com 4 device operations read operation the serial sram read operation is started by by enabling cs low. first, the 8-bit read instruction is transmitted to the device through the si (or sio0-3) pin(s) followed by the 24-bit address with the 7 msbs of the address being ?don?t care? bits and ignored. in spi mode, after the read instruction and address bits are sent, the data stored at that address in memory is shifted out on the so pin after the output valid time. additional ?dummy? clock cycles (four in dual and two in quad) are required to follow the instruction and address inputs prior to the data being driven out on the sio0-3 pins while operating in these two modes. by continuing to provide clock cycles to the device, data can continue to be read out of the memory array in sequentially. the internal address pointer is automatically incremented to the next higher address after each byte of data is read out until the highest memory address is reached. when the highest memory address is reached, 1ffffh, the address pointer wraps to the address 00000h. this allows the read cycles to be continued indefinitely. all read operations are terminated by pulling cs high. figure 2. spi read sequence (single byte) cs instruction si 04 3 25 169 810 7 11 sck 23 22 21 20 210 7 6543 210 high ? z 24 ? bit address data out so 29 31 30 32 36 37 38 39 34 35 33 000 0 0011 figure 3. spi read sequence (sequential bytes) cs instruction si 04 3 25 169 810 7 11 sck 23 22 21 20 210 7 6543 210 high ? z 24 ? bit address data out from addr 1 so 29 31 30 32 36 37 38 39 34 35 33 000 0 0 011 7 6543 210 data out from addr 2 7 6543 210 7 6543 210 ... 40 42 41 43 47 48 49 50 45 46 44 51 53 52 54 55 don?t care don?t care addr 1 data out from addr 3 data out from addr n
n01s830ha, n01s830ba http://onsemi.com 5 figure 4. dual read sequence cs sio[1:0] 04 3 25 11215 14 16 13 17 sck a11 a0 18 20 19 c3 c2 a10 a3 a2 a1 h0 h0 l0 l0 h1 h1 l1 l1 msb msb notes: instruction 24 ? bit address data out x x 21 22 c1 c0 x x 23 24 25 26 c[3:0] = 03h h0 = 2 high order bits of data byte 0 l0 = 2 low order bits of data byte 0 h1 = 2 high order bits of data byte 1 l1 = 2 low order bits of data byte 1 figure 5. quad read sequence cs sio[3:0] 04 3 25 169 810 711 sck a5 a0 12 14 13 c1 c0 a4 a3 a2 a1 h0 l0 h1 l1 h2 l2 h3 l3 msb msb notes: instruction 24 ? bit address data out x x 15 16 c[1:0] = 03h h0 = 4 high order bits of data byte 0 l0 = 4 low order bits of data byte 0 h1 = 4 high order bits of data byte 1 l1 = 4 low order bits of data byte 1 write operation the serial sram write is selected by enabling cs low. first, the 8-bit write instruction is transmitted to the device followed by the 24-bit address with the 7 msbs being don?t care. after the write instruction and addresses are sent, the data to be stored in memory is shifted in on the si pin. if operating in page mode, after the initial word of data is shifted in, additional data words can be written as long as the address requested is sequential on the same page. simply write the data on si pin and continue to provide clock pulses. the internal address pointer is automatically incremented to the next higher address on the page after each word of data is written in. this can be continued for the entire page length of 32 words long. at the end of the page, the addresses pointer will be wrapped to the 0 word address within the page and the operation can be continuously looped over the 32 words of the same page. the new data will replace data already stored in the memory locations. if operating in burst mode, after the initial word of data is shifted in, additional data words can be written to the next sequential memory locations by continuing to provide clock pulses. the internal address pointer is automatically incremented to the next higher address after each word of data is read out. this can be continued for the entire array and when the highest address is reached, 1ffffh, the address counter wraps to the address 00000h. this allows the burst write cycle to be continued indefinitely. again, the new data will replace data already stored in the memory locations. all write operations are terminated by pulling cs high.
n01s830ha, n01s830ba http://onsemi.com 6 figure 6. spi write sequence cs instruction si 04 3 25 169 810 7 11 sck 23 22 21 20 2107 6543 210 high ? z 24 ? bit address data in to addr 1 so 29 31 30 32 36 37 38 39 34 35 33 000 0 0 010 7 6543 210 data in to addr 2 7 6543 210 7 6543 210 ... 40 42 41 43 47 48 49 50 45 46 44 51 53 52 54 55 addr 1 data in to addr 3 data in to addr n high ? z figure 7. dual write sequence h0 h0 l0 l0 h1 h1 ln ln data in msb notes: cs sio1:0] 04 3 25 11215 14 16 13 17 sck a11 a0 18 20 19 c3 c2 a10 a3 a2 a1 msb instruction 24 ? bit address 21 c1 c0 c[3:0] = 02h h0 = 2 high order bits of data byte 0 l0 = 2 low order bits of data byte 0 h1 = 2 high order bits of data byte 1 l1 = 2 low order bits of data byte 1
n01s830ha, n01s830ba http://onsemi.com 7 figure 8. quad write sequence cs 04 3 25 169 810 7 11 sck 12 13 instruction sio[3:0] a5 a0 24 ? bit address c1 c0 a4 a3 a2 a1 h0 l0 h1 l1 h2 l2 hn ln data in msb msb notes: c[1:0] = 02h h0 = 4 high order bits of data byte 0 l0 = 4 low order bits of data byte 0 h1 = 4 high order bits of data byte 1 l1 = 4 low order bits of data byte 1 read mode register (rdmr) this instruction provides the ability to read the mode register. the register may be read at any time including during a write operation. the read mode register operation is executed by driving cs low, then sending the rdmr instruction to the device. immediately after the instruction, the device outputs data on the so (sio0-3) pin(s). to complete the operation, drive cs high to terminate the register read. figure 9. spi read mode register sequence (rdmr) cs instruction si 04 3 25 169 810 711 sck 7 6543 210 high ? z mode register data out so 00 0 00 1 0 12 13 14 15 1 figure 10. dual read mode register sequence (rdmr) c[3:0] = 05h notes: cs instruction 03 2 1 sck c3 c2 h l msb mode bits sio[1:0] 45 l h c1 c0 67
n01s830ha, n01s830ba http://onsemi.com 8 figure 11. quad read mode register sequence (rdmr) c[1:0] = 05h notes: cs instruction 03 2 1 sck c1 c0 h l msb mode bits sio[3:0] write mode register (wrmr) this instruction provides the ability to write the mode register. the write mode register operation is executed by driving cs low, then sending the wrmr instruction to the device. immediately after the instruction, the data is driven to the device on the so (sio0-3) pin(s). to complete the operation, drive cs high to terminate the register write. figure 12. spi write mode register sequence cs instruction si 04 3 25 169 810 711 sck 7 6543 210 high ? z mode register data in so 00 0 00 1 0 12 13 14 15 0 figure 13. dual write mode register sequence c[3:0] = 01h notes: cs instruction 03 2 1 sck c3 c2 h l msb mode bits sio[1:0] 45 l h c1 c0 67 figure 14. quad write mode register sequence cs instruction 03 2 1 sck c1 c0 h l c[1:0] = 01h notes: msb mode bits sio[3:0]
n01s830ha, n01s830ba http://onsemi.com 9 table 5. mode register bit function 0 hold function 1 = hold function disabled 0 = hold function enabled (default) 1 reserved 2 reserved 3 reserved 4 reserved 5 reserved 6 operating mode bit 7 bit 6 0 0 = word mode 1 0 = page mode 0 1 = burst mode (default) 1 1 = reserved 7 power-up state the serial sram enters a know state at power-up time. the device is in low-power standby state with cs = 1. a low level on cs is required to enter a active state. battery back-up operation the battery back-up function is available on the bbu version of the serial sram. this version of the sram cannot operate in the quad mode since the sio3 input is used for the vbat connection. a standard coin cell battery should be connected to the vbat pin. on chip circuitry monitors the v cc pin and when it is determined that the main v cc power supply is turning off, the device automatically switches the memory array to vbat power input. when in battery back-up mode and 3.0 to 3.4 v power supplied to the vbat input, memory data is retained in the sram array and all existing interface and operating mode information is retained. figure 15. battery back-up version schematics so nc vss vcc sck si coin cell battery 3.0 to 3.4 v vbat serial sram cs table 6. absolute maximum ratings item symbol rating units voltage on any pin relative to v ss v in,out ?0.3 to v cc + 0.3 v voltage on v cc supply relative to v ss v cc ?0.3 to 5.5 v power dissipation p d 500 mw storage temperature t stg ?40 to 125 c operating temperature t a -40 to +85 c soldering temperature and time t solder 260 c, 10 sec c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 7. operating characteristics (over specified temperature range) item symbol test conditions min typ (note 1) max units supply voltage v cc 2.5 5.5 v data retention voltage (note 2) v dr 1.0 v input high voltage v ih 0.7 v cc v cc + 0.3 v input low voltage v il ? 0.3 0.1 v cc v output high voltage v oh i oh = ? 0.4 ma v cc ? 0.2 v output low voltage v ol i ol = 1 ma 0.2 v input leakage current i li cs = v cc , v in = 0 to v cc 1.0 a output leakage current i lo cs = v cc , v out = 0 to v cc 1.0 a operating current i cc f = 20 mhz, i out = 0, spi / dual 10 ma f = 20 mhz, i out = 0, quad 20 standby current i sb cs = v cc , v in = v ss or v cc 4 10 a 1. typical values are measured at v cc = v cc typ., t a = 25 c and are not 100% tested. 2. typical lower limit of vcc when data will be retained in the memory array, not 100% tested.
n01s830ha, n01s830ba http://onsemi.com 10 table 8. capacitance (note 3) item symbol test conditions min max units input capacitance c in v in = 0 v, f = 1 mhz, t a = 25 c 7 pf i/o capacitance c i/o v in = 0 v, f = 1 mhz, t a = 25 c 7 pf 3. these parameters are verified in device characterization and are not 100% tested. table 9. timing test conditions item value input pulse level 0.1 v cc to 0.9 v cc input rise and fall time 5 ns input and output timing reference levels 0.5 v cc output load cl = 30 pf operating temperature ? 40 to +85 c table 10. timing item symbol min max units clock frequency f clk 20 mhz clock period t clk 50 ns clock rise time t r 20 ns clock fall time t f 20 ns clock high time t hi 25 ns clock low time t lo 25 ns clock delay time t cld 25 ns cs setup time t css 25 ns cs hold time t csh 50 ns cs disable time t csd 25 ns sck to cs t scs 5 ns data setup time t su 10 ns data hold time t hd 10 ns output valid from clock low t v 25 ns output hold time t ho 0 ns output disable time t dis 20 ns hold setup time t hs 10 ns hold hold time t hh 10 ns hold low to output high-z t hz 10 ns hold high to output valid t hv 50 ns
n01s830ha, n01s830ba http://onsemi.com 11 figure 16. spi input timing cs t css msb in sck so si lsb in t f t r t cld t csh t csd t su t hd high ? z t scs figure 17. spi output timing cs t lo msb out sck si so lsb out t dis t csh t hi t v don?t care figure 18. spi hold timing cs t hs n+2 sck si so t su t hz t hh n+1 n high ? z t hs t hh t hv nn ? 1 nn ? 1 n+2 n+1 n don?t care hold
n01s830ha, n01s830ba http://onsemi.com 12 figure 19. quad input timing cs t css msb in sck si0 lsb in t f t r t cld t csh t csd t su t hd t scs figure 20. quad output timing cs t lo msb out sck sio lsb out t dis t csh t hi t v
n01s830ha, n01s830ba http://onsemi.com 13 package dimensions tssop8 3x4.4 / tssop8 (225 mil) case 948bh issue o on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 n01s830ha/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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