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ds97tad0100 p r e l i m i n a r y 1 1 p reliminary p roduct s pecification z89175 1 z89176 (r omless ) 2 v oice p rocessing c ontrollers features n watch-dog timer and power-on reset n improved low power stop mode n on-chip oscillator which accepts a crystal or external clock drive n improved global power-down mode n low power consumption - 200 mw (typical) n two comparators n ram and rom protect n on-board oscillator for 32.768 khz real-time clock n clock speeds of 20.48 or 29.49 mhz n 16-bit digital signal processor (dsp) n 8k word dsp program rom n 512 words on-chip dsp ram n 8-bit a/d converter with up to 16 khz sample rate n 10-bit pwm d/a converter n six vectored, prioritized z8 interrupts n three vectored, prioritized dsp interrupts n two dsp timers to support different a/d and d/a sampling rates n ibm pc-based development tools n developer? toolbox for t.a.m. applications general description the z89175/176 is a fully integrated, dual processor con- troller designed for voice processing applications. the i/o control processor is a z8 with 24 kb of program memory, two 8-bit counter/timers, and up to 47 i/o pins. the dsp is a 16-bit processor with a 24-bit alu and accumulator, 512x16 bits of ram, single cycle instructions, and 8k words of program rom. the chip also contains a half-flash 8-bit a/d converter with up to a 16 khz sample rate and a 10-bit pwm d/a converter. the sampling rates for the con- verters are programmable. the precision of the 8-bit a/d can be extended by resampling the data at a lower rate in software. the z8 and dsp processors are coupled by mailbox registers and an interrupt system. dsp or z8 pro- grams can be directed by events in each other? domain. the z89176 is the romless version of the z89175. how- ever, the on-chip dsp is not romless. notes: all signals with a preceding front slash, "/", are ac- tive low, e.g., b//w (word is active low); /b/w (byte is active low, only). power connections follow conventional descriptions be- low: device rom (kb) ram* (bytes) i/o lines voltage range z89175 24 256 47 4.5v to 5.5v z89176 - 256 31 4.5v to 5.5v note: *general-purpose connection circuit device power v cc v dd ground gnd v ss
z89175/z89176 voice processing controllers zilog 2 p r e l i m i n a r y ds97tad0100 general description (continued) z8 core processor the on-chip z8 is zilog? 8-bit microcontroller core with an expanded register file to allow access to register- mapped peripheral and i/o circuits. the z8 offers a flexible i/o scheme, an efficient register and address space struc- ture and a number of ancillary features which makes it ide- ally suited for high-volume processing, peripheral control- lers and consumer applications. for applications demanding powerful i/o capabilities, the z89175 provides 47 pins dedicated to input and output. these i/o lines are grouped into six ports. each port is configurable under software control to provide timing, sta- tus signals and parallel i/o with or without handshake. four basic memory resources for the z8 are available to support a wide range of configurations: program memory, register file, data memory, and expanded register file. the z8 core processor is supported by an efficient register file that allows any of 256 on-board data and control regis- ters to be either the source and/or the destination of almost any instruction. this unique architecture eliminates tradi- tional microprocessor accumulator bottlenecks and per- mits rapid content switching. the register file is composed of 236 bytes of general-pur- pose registers, four i/o port registers, and 15 control and status registers. the expanded register file consists of mailbox registers, wdt mode register, dsp control regis- ter, stop-mode recovery register, port configuration reg- ister, and the control and data registers for port 4 and port 5. some of these registers are shared with the dsp. to unburden the software from supporting real-time prob- lems such as counting/timing and data communication, the z8 offers two on-chip counter/timers with a large number of user-selectable modes. watch-dog timer and stop-mode recovery features are software driven by setting specific bits in control registers. stop and halt instructions support reduced power op- eration. the low-power stop mode allows parameter infor- mation to be stored in the register file if power fails. an ex- ternal capacitor or battery will retain device memory and power the 32 khz timer. dsp coprocessor the dsp coprocessor is a second generation, 16-bit two? complement cmos digital signal processor (dsp). most instructions, including multiply and accumulate, are ac- complished in a single clock cycle. the processor contains two on-chip data ram blocks of 256 words, a 8k word pro- gram rom, 24-bit alu, 16x16 multiplier, 24-bit accumula- tor, shifter, six-level stack, three vectored interrupts and two inputs for conditional program jumps. each ram block contains a set of four pointers which can be incremented or decremented automatically to affect hardware looping without software overhead. the data rams can be simul- taneously addressed and loaded to the multiplier for a true single-cycle scalar multiply. four external dsp registers are mapped into the expand- ed register file of the z8. communication between the z8 and the dsp occurs through those common registers which form the mailbox registers. the analog output is generated by a 10-bit resolution pulse width modulator. the pwm output is a digital signal with cmos output levels. the output signal has a resolu- tion of 1 in 1024 with a sampling rate of 16 khz (xtal = 20.48 mhz). the sampling rate can be changed under software control and can be set at 10 and 16 khz. the dy- namic range of the pwm is from 0 to 4v. an 8-bit resolution half-flash a/d converter is provided. the conversion is conducted with a sampling frequency of 16 khz. (xtal = 20.48 mhz) in order to provide oversam- pling. the input signal is 4v peak to peak. two additional timers (timer2 and timer3) have been added to support different sampling rates for the a/d and d/a converters. these timers are free-running counters that divide the crystal frequency to the appropriate sam- pling of frequency. two dsp i/o pins: dsp0, dsp1 are provided for application.
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 3 2 pin description figure 1. z89175/176 functional block diagram port 0 p00 p01 p02 p03 p04 p05 p06 p07 p10 p11 p12 p13 p14 p15 p16 p17 p20 p21 p22 p23 p24 p25 p26 p27 p31 p32 p33 p40 p41 p42 p43 p44 p45 p46 p47 p50 p51 p52 p53 p54 p55 p56 p57 rmls /as /ds r/w timer 0 capture reg. port 3 port 1 port 4 port 2 port 5 timer 1 register file 256 x 8 bit 24 kbytes program rom (z89175) z8 core register bus internal address bus internal data bus expanded register file (z8) peripheral register (dsp) expanded register bus extended bus of the dsp 8k words program rom dsp core internal address bus internal data bus dsp port pwm (10-bit) adc (8-bit) timer 2 timer 3 extended bus of the dsp ext. memory control osc power xtal1 xtal2 vdd gnd /reset int 1 int 2 dsp0 dsp1 an in an vdd an gnd vref+ vref- pwm 256 word ram 0 256 word ram 1 p34 p35 p36 p37 input output i/o (bit programmable) i/o (bit programmable) address or i/o (nibble programmable) address/data or i/o (byte programmable) i/o (bit programmable) mailbox osc1 osc2 32 khz osc
z89175/z89176 voice processing controllers zilog 4 p r e l i m i n a r y ds97tad0100 pin description (continued) figure 2. z89175 100-pin qfp pin con?uration 50 45 40 35 31 81 85 90 95 100 p06 p05 p04 p03 p02 p01 p00 gnd p17 p16 p15 p14 p13 p12 p11 p10 gnd agnd vref- anin nc nc nc vcc p51 p50 p47 p46 p45 p44 p43 p42 p41 p40 p27 p26 p25 p24 p23 p22 vref+ anvdd gnd pwm rmls dsp1 dsp0 /as /ds r//w nc p57 p56 p55 p54 vcc xtal2 xtal1 p53 p52 p37 p36 p35 p34 p33 p32 p31 /reset p20 p21 p07 nc nc vcc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc osc02 osc01 gnd nc nc 510152025 1 100-pin qfp 30 75 70 65 60 55 80 51
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 5 2 table 1. z89175 100-pin qfp pin identi?ation i/o port symbol pin number direction function gnd 3, 53, 88, 97 digital ground v cc 16, 47, 77 digital v cc = +5v vref+ 1 input/output analog voltage ref+ anv dd 2 analog v dd pwm 4 output pwm output rmls 5 input control input dsp1-0 6, 7 output dsp user output 1, 0 /as 8 output address strobe /ds 9 output data strobe r//w 10 output read/write nc 11 no connection p57-p54 12-15 input/output port 5 bit 7-4 xtal2 17 output crystal output (20.48 or 29.49 mhz) xtal1 18 input crystal input (20.48 or 29.49 mhz) p53-p52 19, 20 input/output port 5 bit 3-2 p37-p34 21-24 output port 3 bit 7-4 p33-p31 25-27 input port 3 bit 3-1 /reset 28 input/output reset p20-p27 29-36 input/output port 2, bit 0-7 p40-p47 37-44 input/output port 4, bit 0-7 p50-p51 45, 46 input/output port 5, bit 0-1 nc 48-52 no connection osc1 54 input crystal input (32.768 khz) osc2 55 output crystal output (32.768 khz) nc 56-76 no connection nc 78, 79 no connection p07-p00 80-87 input/output port 0, bit 7-0 p17-p10 89-96 input/output port 1, bit 7-0 angnd 98 analog gnd vref- 99 input analog voltage ref- anin 100 input analog input
z89175/z89176 voice processing controllers zilog 6 p r e l i m i n a r y ds97tad0100 pin description (continued) figure 3. z89175 100-pin vqfp pin con?uration 50 45 40 35 30 26 76 80 85 90 95 100 nc nc p07 p06 p05 p04 p03 p02 p01 p00 gnd p17 p16 p15 p14 p13 p12 p11 p10 gnd agnd vref- anin vref+ anvdd nc nc nc nc nc vcc p51 p50 p47 p46 p45 p44 p43 p44 p45 p46 p47 p50 p51 vcc nc nc nc nc nc gnd pwm rmls dsp1 dsp0 /as /ds r//w nc p57 p56 p55 p54 vcc xtal2 xtal1 p53 p52 p37 p36 p35 p34 p33 p32 p31 vcc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc osc2 osc1 gnd 510152025 1 70 65 60 55 51 75 100-pin vqfp
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 7 2 table 2. z89175 100-pin vqfp pin identi?ation i/o port symbol pin number direction symbol gnd 1, 51, 86, 95 digital ground v cc 14, 45, 75 digital vcc = +5v vref+ 99 input/output analog voltage ref+ anv dd 100 analog vdd pwm 2 output pwm output rmls 3 input control input dsp1-0 4, 5 output dsp user output 1, 0 /as 6 output address strobe /ds 7 output data strobe r//w 8 output read/write nc 9 no connection p57-p54 10-13 input/output port 5 bit 7-4 xtal2 15 output crystal output (20.48 or 29.49 mhz) xtal1 16 input crystal input (20.48 or 29.49 mhz) p53-p52 17, 18 input/output port 5 bit 3-2 p37-p34 19-22 output port 3 bit 7-4 p33-p31 23-25 input port 3 bit 3-1 /reset 26 input/output reset p20-p27 27-34 input/output port 2, bit 0-7 p40-p47 35-42 input/output port 4, bit 0-7 p50-p51 43, 44 input/output port 5, bit 0-1 nc 46-50 no connection osc1 52 input crystal input (32.768 khz) osc2 53 output crystal output (32.768 khz) nc 54-74 no connection nc 76, 77 no connection p07-p00 78-85 input/output port 0, bit 7-0 p17-p10 87-94 input/output port 1, bit 7-0 angnd 96 analog gnd vref- 97 input analog voltage ref- anin 98 input analog input
z89175/z89176 voice processing controllers zilog 8 p r e l i m i n a r y ds97tad0100 pin description (continued) figure 4. z89176 100-pin qfp pin con?uration 50 45 40 35 31 81 85 90 95 100 p06 p05 p04 p03 p02 p01 p00 gnd p17 p16 p15 p14 p13 p12 p11 p10 gnd agnd vref- anin nc nc nc vcc p51 p50 p47 p46 p45 p44 p43 p42 p41 p40 p27 p26 p25 p24 p23 p22 vref+ anvdd gnd pwm vcc dsp1 dsp0 /as /ds r//w nc p57 p56 p55 p54 vcc xtal2 xtal1 p53 p52 p37 p36 p35 p34 p33 p32 p31 /reset p20 p21 p07 nc nc vcc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc osc02 osc01 gnd nc nc 510152025 1 100-pin qfp 30 75 70 65 60 55 80 51
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 9 2 table 3. z89176 100-pin qfp pin identi?ation i/o port symbol pin number direction function gnd 3, 53, 88, 97 digital ground v cc 5, 16, 47, 77 digital v cc = +5v vref+ 1 input/output analog voltage ref+ anv dd 2 analog v dd pwm 4 output pwm output dsp1-0 6, 7 output dsp user output 1, 0 /as 8 output address strobe /ds 9 output data strobe r//w 10 output read/write nc 11 no connection p57-p54 12-15 input/output port 5 bit 7-4 xtal2 17 output crystal output (20.48 or 29.49 mhz) xtal1 18 input crystal input (20.48 or 29.49 mhz) p53-p52 19, 20 input/output port 5 bit 3-2 p37-p34 21-24 output port 3 bit 7-4 p33-p31 25-27 input port 3 bit 3-1 /reset 28 input/output reset p20-p27 29-36 input/output port 2, bit 0-7 p40-p47 37-44 input/output port 4, bit 0-7 p50-p51 45, 46 input/output port 5, bit 0-1 nc 48-52 no connection osc1 54 input crystal input (32.768 khz) osc2 55 output crystal output (32.768 khz) nc 56-76 no connection nc 78-79 no connection p07-p00 80-87 input/output port 0, bit 7-0 p17-p10 89-96 input/output port 1, bit 7-0 angnd 98 analog gnd vref- 99 input analog voltage ref- anin 100 input analog input
z89175/z89176 voice processing controllers zilog 10 p r e l i m i n a r y ds97tad0100 pin description (continued) figure 5. z89176 100-pin vqfp pin con?uration 50 45 40 35 30 26 76 80 85 90 95 100 nc nc p07 p06 p05 p04 p03 p02 p01 p00 gnd p17 p16 p15 p14 p13 p12 p11 p10 gnd agnd vref- anin vref+ anvdd nc nc nc nc nc vcc p51 p50 p47 p46 p45 p44 p43 p42 p41 p40 p27 p26 p25 p24 p23 p22 p21 p20 /reset gnd pwm vcc dsp1 dsp0 /as /ds r//w nc p57 p56 p55 p54 vcc xtal2 xtal1 p53 p52 p37 p36 p35 p34 p33 p32 p31 vcc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc osc2 osc1 gnd 510152025 1 70 65 60 55 51 75 100-pin vqfp
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 11 2 table 4. z89176 100-pin vqfp pin identi?ation i/o port symbol pin number direction function gnd 1, 51, 86, 95 digital ground v cc 3, 14, 45, 75 digital v cc = +5v vref+ 99 input/output analog voltage ref+ anv dd 100 analog vdd pwm 2 output pwm output dsp1-0 4, 5 output dsp user output 1, 0 /as 6 output address strobe /ds 7 output data strobe r//w 8 output read/write nc 9 no connection p57-p54 10-13 input/output port 5 bit 7-4 xtal2 15 output crystal output (20.48 or 29.49 mhz) xtal1 16 input crystal input (20.48 or 29.49 mhz) p53-p52 17, 18 input/output port 5 bit 3-2 p37-p34 19-22 output port 3 bit 7-4 p33-p31 23-25 input port 3 bit 3-1 /reset 26 input/output reset p20-p27 27-34 input/output port 2, bit 0-7 p40-p47 35-42 input/output port 4, bit 0-7 p50-p51 43, 44 input/output port 5, bit 0-1 nc 46-50 no connection osc1 52 input crystal input (32.768 khz) osc2 53 output crystal output (32.768 khz) nc 54-74 no connection nc 76, 77 no connection p07-p00 78-85 input/output port 0, bit 7-0 p17-p10 87-94 input/output port 1, bit 7-0 angnd 96 analog gnd vref- 97 input analog voltage ref- anin 98 input analog input
z89175/z89176 voice processing controllers zilog 12 p r e l i m i n a r y ds97tad0100 absolute maximum ratings stresses greater than those listed under absolute maxi- mum ratings can cause permanent damage to the device. this is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for an extended period can af- fect device reliability. standard test conditions the characteristics listed below apply for standard test conditions as noted. all voltages are referenced to gnd. positive current flows into the referenced pin (figure 6). capacitance t a = 25 c, v cc = gnd = 0v, f = 1.0 mhz, unmeasured pins returned to gnd. sym description min max units v cc supply voltage (*) ?.3 +7.0 v t stg storage temp ?5 +150 c t a oper. ambient temp. ?c notes: *voltage on all pins with respect to gnd. ?see ordering information. figure 6. test load diagram +5v from output under test 150 pf 9.1 k w 2.1 k w parameter min max input capacitance 0 12 pf output capacitance 0 12 pf i/o capacitance 0 12 pf
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 13 2 dc electrical characteristics v cc note 1 t a = 0 c to +70 c typical @ 25 c sym parameter min max units conditions i cc supply current 5.0v 65 40 ma i cc1 halt mode current 5.0v 20 6 ma i cc2 stop mode current 5.0v 20 6 m a see note 2 v max max input voltage 5.0v 7 v ch clock input high voltage 5.0v 0.9 v cc v cc +0.3 2.5 v driven by external clock generator v cl clock input low voltage 5.0v gnd ?.3 0.1 v cc 1.5 v driven by external clock generator v ih input high voltage 5.0v 0.7 v cc v cc +0.3 2.5 v v il input low voltage 5.0v gnd ?.3 0.2 v cc 1.5 v v oh output high voltage 5.0v v cc ?.4 4.8 v i oh = ?.0 ma v ol1 output low voltage 5.0v 0.4 0.1 v i ol = +4.0 ma v ol2 output low voltage 5.0v 1.2 0.3 v i ol = +12 ma, 3 pin max v rh reset input high voltage 5.0v .8 v cc v cc 2.1 v v rl reset input low voltage 5.0v gnd ?.3 0.2 v cc 1.7 v offset comparator input offset 5.0v 25 10 mv voltage i il input leakage 5.0v ?0 10 10 m a i ol output leakage 5.0v ?0 10 10 m a i ir reset input current 5.0v ?5 ?0 m a notes: 1. 5.0v 0.5v 2. when a 32 khz crystal is used, additional value must be added to the stop mode current icc2. the sum will be 200 m a/max, 150 m a/typical.
z89175/z89176 voice processing controllers zilog 14 p r e l i m i n a r y ds97tad0100 dc electrical characteristics z89175 a/d converter t a = 0 c to +70 c sym parameter v dd min max units conditions i il input leakage analog input 5.5v 1.00 m a anv dd = 5.50 v v in = 0.00 v v refh = 5.50 v v refl = 0.00 v i ih input leakage analog input 5.5v 2.00 m a anv dd = 5.50 v v in = 5.50 v v refh = 5.50 v v refl = 0.00 v i vrefh input current 5.5v 1.00 ma v in = 5.50 v v refl = 0.00 v anv dd = 5.50 v i vrefl input current 5.5v 2 m av in = 5.50 v v refl = 5.50 v anv dd = 5.50 v i vefl input current 5.5v ?.00 ma v in = 0.00 v v refh = 5.50 v anv dd = 0.00 v i vrefl input current 5.5v 2 m av in = 0.00 v v refh = 5.50 v anv dd = 5.50 v
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 15 2 dc electrical characteristics 21 other non-regular i/o t a = 0 c to +70 c sym parameter v dd min max units conditions i irh input current romless pin 5.5v 6.00 m av in = 5.50 v i ir1 input current romless pin 5.5v 6.00 m av in = 0.00 v i ir input current romless pin during reset active 5.5v 1.00 ma v in = 5.50 v i ihx2 input current xtal2 pin in stop mode 5.5v 1.00 m av in = 0.00 v i ilx2 input current xtal2 pin in stop mode 5.5v 1.00 m av in = 5.50 v i ihx1 input current xtal1 pin 5.5v 30 m av in = 0.00 v i ilx1 input current xtal1 pin 5.5v 30 m av in = 5.50 v v olxr output low voltage xtal2 reset inactive 5.5v 1.20 v i ol = 4.00 ma v olx output low voltage xtal2 reset inactive 5.5v 0.60 v i ol =1.00 ma v ohxr output high voltage xtal2 reset inactive 5.5v 4.00 v i oh = 4.00 ma i vohx output high voltage xtal2 reset inactive 5.5v 4.00 v i oh =1.00 ma i ih input current p31, p32, p33 5.5v 1.00 m av in = 5.50 v i il input current p31, p32, p33 5.5v 1.00 m av in = 0.00 v
z89175/z89176 voice processing controllers zilog 16 p r e l i m i n a r y ds97tad0100 ac characteristics external i/o or memory read and write timing diagram figure 7. external i/o or memory read/write timing r//w 9 12 19 3 16 13 4 5 8 18 11 6 17 10 15 7 14 1 port 0, /dm port 1 /as /ds (read) port1 /ds (write) a7 - a0 d7 - d0 in d7 - d0 out a7 - a0 2
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 17 2 ac characteristics external i/o or memory read and write timing table v cc t a = 0 c to +70 c no symbol parameter note 4 min max units notes 1 tda(as) address valid to /as rise delay 5.0v 25 ns 2,3 2 tdas(a) /as rise to address float delay 5.0v 35 ns 2,3 3 tdas(dr) /as rise to read data reqd valid 5.0v 150 ns 1,2,3 4 twas /as low width 5.0v 35 ns 2,3 5 tdaz(ds) address float to /ds fall 5.0v 0 ns 6 twdsr /ds (read) low width 5.0v 125 ns 1,2,3 7 twdsw /ds (write) low width 5.0v 75 ns 1,2,3 8 tddsr(dr) /ds fall to read data reqd valid 5.0v 90 ns 1,2,3 9 thdr(ds) read data to /ds rise hold time 5.0v 0 ns 2,3 10 tdds(a) /ds rise to address active delay 5.0v 40 ns 2,3 11 tdds(as) /ds rise to /as fall delay 5.0v 35 ns 2,3 12 tdr/w(as) r//w valid to /as rise delay 5.0v 25 ns 2,3 13 tdds(r/w) /ds rise to r//w not valid 5.0v 35 ns 2,3 14 tddw(dsw) write data valid to /ds fall (write) delay 5.0v 40 ns 2,3 15 tdds(dw) /ds rise to write data not valid delay 5.0v 25 ns 2,3 16 tda(dr) address valid to read data reqd valid 5.0v 180 ns 1,2,3 17 tdas(ds) /as rise to /ds fall delay 5.0v 48 ns 2,3 18 tddi(ds) data input setup to /ds rise 5.0v 50 ns 1,2,3 19 tddm(as) /dm valid to /as fall delay 5.0v 20 ns 2,3 notes: 1. when using extended memory timing add 2 tpc. 2. timing numbers given are for minimum tpc. 3. see clock cycle dependent characteristics table. 4. 5.0 v 0.5 v. standard test load all timing references use 0.9 vcc for a logic 1 and 0.1 vcc for a logic 0.
z89175/z89176 voice processing controllers zilog 18 p r e l i m i n a r y ds97tad0100 ac electrical characteristics additional timing diagram figure 8. additional timing clock 1 3 4 8 2 2 3 tin irqn 6 5 7 7 11 clock setup 10 9 stop mode recovery source
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 19 2 ac electrical characteristics additional timing table v cc t a = 0 c to +70 c no sym parameter note 5 min max units notes 1 tpc input clock period 5.0v 48.83 ns 1, 6 2 trc,tfc clock input rise & fall times 5.0v 6 ns 1 3 twc input clock width 5.0v 17 ns 1,7 4 twtinl timer input low width 5.0v 70 ns 5 twtinh timer input high width 5.0v 3tpc 1 6 tptin timer input period 5.0v 8tpc 1 7 trtin, tftin timer input rise & fall timer 5.0v 100 ns 1 8a twil int. request low time 5.0v 70 ns 1,2 8b twil int. request low time 5.0v 3tpc 1 9 twih int. request input high time 5.0v 3tpc 1 10 twsm stop-mode recovery width spec 5.0v 12 ns 1 11 tost oscillator start-up time 5.0v 5tpc 3 12 twdt watch-dog timer 5.0v 5 ms d1 = 0, d0 = 0 [4] 5.0v 15 ms d1 = 0, d0 = 1 [4] 5.0v 25 ms d1 = 1, d0 = 0 [4] 5.0v 100 ms d1 = 1, d0 = 1 [4] notes: 1. timing reference uses 0.9 vcc for a logic 1 and 0.1 vcc for a logic 0. 2. interrupt request via port 3 (p31-p33). 3. smr-d5 = 0 4. reg. wdt 5. 5.0 v 0.5 v 6. for 29.49 mhz, it will be 30.53 ns. 7. for 29.49 mhz, it will be 9 ns.
z89175/z89176 voice processing controllers zilog 20 p r e l i m i n a r y ds97tad0100 ac electrical characteristics handshake timing diagrams figure 9. input handshake timing data in 1 3 4 /dav (input) rdy (output) next data in valid delayed rdy delayed dav data in valid 5 6 2 figure 10. output handshake timing data out /dav (output) rdy (input) next data out valid delayed rdy delayed dav data out valid 7 8 9 10 11
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 21 2 ac electrical characteristics handshake timing table v cc t a = 0 c to +70 c data no symbol parameter note min max units direction 1 tsdi(dav) data in setup time 5.0v 0 ns in 2 thdi(rdy) rdy to data hold time 5.0v 0 ns in 3 twdav data available width 5.0v 40 ns in 4 tddavi(rdy) dav fall to rdy fall delay 5.0v 70 ns in 5 tddavid(rdy) dav rise to rdy rise delay 5.0v 40 ns in 6 tddo(dav) rdy rise to dav fall delay 5.0v 0 ns in 7 tcldav0(rdy) data out to dav fall delay 5.0v tpc ns out 8 tcldav0(rdy) dav fall to rdy fall delay 5.0v 0 ns out 9 tdrdy0(dav) rdy fall to dav rise delay 5.0v 70 ns out 10 twrdy rdy width 5.0v 40 ns out 11 tdrdy0d(dav) rdy rise to dav fall delay 5.0v 40 ns out note: 5.0v 0.5v
z89175/z89176 voice processing controllers zilog 22 p r e l i m i n a r y ds97tad0100 pin functions /reset (input, active low). this pin initializes the mcu. reset is accomplished either through power-on reset (por), watch-dog timer (wdt) reset, stop-mode recov- ery, or external reset. during por and wdt reset, the in- ternally generated reset signal is driving the reset pin low for the por time. any devices driving the reset line must be open-drain to avoid damage from a possible conflict during reset conditions. a /reset will reset both the z8 and the dsp. for the z8: after the por time, /reset is a schmitt-trig- gered input. to avoid asynchronous and noisy reset prob- lems, the z8 is equipped with a reset filter of four external clocks (4tpc). if the external reset signal is less than 4tpc in duration, no reset occurs. on the fifth clock after the /reset is detected, an internal rst signal is latched and held for an internal register count of 18 external clocks, or for the duration of the external reset, whichever is longer. program execution begins at location 000ch (hexadeci- mal), 5-10 tpc cycles after /reset is released. the z8 does not reset wdt, smr, p2m, and p3m registers on a stop-mode recovery operation. for the dsp: after por, the dsp is in run mode. the z8 controls the dsp commands to halt, run or reset. when the dsp is in halt mode, it cannot be woke up with wdt or smr. rmls romless (input, active high). this pin, when con- nected to vdd, disables the internal z8 rom. (note that, when pulled low to gnd, the device functions normally as the rom version.) the dsp cannot be configured as romless. this pin is only available on the z89175. r//w read/write (output, write low). the r//w signal de- fines the signal flow when the z8 is reading or writing to an external program or data memory. the z8 is reading when this pin is high and writing when this pin is low. /as address strobe (output, active low). address strobe is pulsed once at the beginning of each machine cycle. ad- dress output is through port 0/port 1 for all external pro- grams. memory address transfers are valid at the trailing edge of /as. under program control, /as is placed in the high-impedance state along with ports 0 and 1, data strobe, and read/write. /ds data strobe (output, active low). data strobe is acti- vated once for each external memory transfer. for read operations, data must be available prior to the trailing edge of /ds. for write operations, the falling edge of /ds indi- cates that output data is valid. xtal1 crystal 1 (time-based input). this pin connects a parallel-resonant crystal, ceramic resonator, lc, rc net- work, or an external single-phase clock to the on-chip os- cillator input. xtal2 crystal 2 (time-based output). this pin connects a parallel-resonant, crystal, ceramic resonant, or lc network to the on-chip oscillator output. dsp0 (output). dsp0 is a general-purpose output pin con- nected to bit 6 of the analog control register (dsp ext4). this bit has no special significance and can be used to out- put data by writing to bit 6 of the acr. dsp1 (output). dsp1 is a general-purpose output pin con- nected to bit 7 of the analog control register (dsp ext4). this bit has no special significance and can be used to out- put data by writing to bit 7 of the acr. pwm pulse width modulator (output). the pwm is a 10- bit resolution d/a converter. this output is a digital signal with cmos output levels. an in (input). analog input for the a/d converter. anv dd . analog power supply for the a/d converter. vref+ (input). reference voltage (high) for the a/d con- verter. v dd . digital power supply for the z89175. gnd . digital ground for the z89175. osc1 oscillator 1 (time-based input). this pin connects a parallel-resonant crystal, ceramic resonator, lc, rc net- work to the on-chip oscillator input. osc2 oscillator 2 (time-based output). this pin connects a parallel-resonant crystal, ceramic resonator, lc, rc net- work to the on-chip oscillator output. nc no connect. for the 100-pin qfp package, pins 63 through 76, and pins 78 and 79 should be tied to ground. other nc pins must float. port 0 (p07-p00). port 0 is an 8-bit, bidirectional, cmos compatible port. these eight i/o lines are configured un- der software control as a nibble i/o port, or as an address port for interfacing external memory. the input buffers are schmitt-triggered and the output drivers are push-pull. port 0 is placed under handshake control. in this configu- ration, port 3, lines p32 and p35 are used as the hand- shake control /dav0 and rdy0. handshake signal direc- tion is dictated by the i/o direction to port 0 of the upper nibble p07-p04. the lower nibble must have the same di- rection as the upper nibble. the auto latch on port 0 puts valid cmos levels on all cmos inputs which are not externally driven. whether this level is 0 or 1 cannot be determined. a valid cmos level, rather than a floating node, reduces excessive supply cur- rent flow in the input buffer.
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 23 2 for external memory references, port 0 provides address bits a11-a8 (lower nibble) or a15-a8 (lower and upper nib- ble) depending on the required address space. if the ad- dress range requires 12 bits or less, the upper nibble of port 0 can be programmed independently as i/o while the lower nibble is used for addressing. if one or both nibbles are needed for i/o operation, they are configured by writ- ing to the port 0 mode register. in romless mode, after a hardware reset, port 0 is config- ured as address lines a15-a8, and extended timing is set to accommodate slow memory access. the initialization routine can include reconfiguration to eliminate this ex- tended timing mode. (in rom mode, port 0 is defined as input after reset.) port 0 is set in the high-impedance mode if selected as an address output state along with port 1 and the control sig- nals /as, /ds, and r//w (figure 11). figure 11. port 0 con?uration oen out in pad auto latch port 0 (i/o or a15 - a8) handshake controls /dav0 and rdy0 (p32 and p35) z89175/176 mcu 4 4 r = 500 k w 1.5 2.3v hysteresis
z89175/z89176 voice processing controllers zilog 24 p r e l i m i n a r y ds97tad0100 pin functions (continued) port 1 (p17-p10). port 1 is an 8-bit, bidirectional, cmos compatible port (figure 12). it has multiplexed address (a7-a0) and data (d7-d0) ports. these eight i/o lines are programmed as inputs or outputs, or can be configured un- der software control as an address/data port for interfac- ing external memory. the input buffers are schmitt-trig- gered and the output drivers are push-pull. port 1 can be placed under handshake control. in this con- figuration, port 3, lines p33 and p34 are used as the hand- shake controls rdy1 and /dav1 (ready and data avail- able). memory locations greater than 24575 (z89175) (in rom mode) are referenced through port 1. to interface external memory, port 1 must be programmed for the mul- tiplexed address/data mode. if more than 256 external lo- cations are required, port 0 outputs the additional lines. port 1 can be placed in the high-impedance state along with port 0, /as, /ds, and r//w, allowing the z89175/176 to share common resources in multiprocessor and dma applications. figure 12. port 1 con?uration oen out in pad auto latch handshake controls /dav2 and rdy2 (p31 and p36) z89175/176 mcu r = 500 k w 1.5 2.3v hysteresis port 1 (i/o or ad7 - ad0) 8
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 25 2 port 2 (p27-p20). port 2 is an 8-bit, bidirectional, cmos compatible i/o port. these eight i/o lines are configured under software control independently as inputs or outputs. port 2 is always available for i/o operation. the input buff- ers are schmitt-triggered. bits programmed as outputs can be globally programmed as either push-pull or open-drain. port 2 can be placed under handshake control. in this con- figuration, port 3 lines p31 and p36 are used as the hand- shake controls lines /dav2 and rdy2. the handshake signal assignment for port 3 lines p31 and p36 is dictated by the direction (input or output) assigned to bit 7, port 2 (figure 13). the auto latch on port 2 puts valid cmos levels on all cmos inputs which are not externally driven. whether this level is 0 or 1, cannot be determined. a valid cmos level, rather than a floating node, reduces excessive supply cur- rent flow in the input buffer. figure 13. port 2 con?uration oen out in pad auto latch port 2 (i/o) handshake controls /dav2 and rdy2 (p31 and p36) z89175/176 mcu r = 500 k w 1.5 2.3v hysteresis open-drain
z89175/z89176 voice processing controllers zilog 26 p r e l i m i n a r y ds97tad0100 pin functions (continued) port 3 (p37-p31). port 3 is a 7-bit, cmos compatible port with three fixed inputs (p33-p31) and four fixed outputs (p37-p34). it is configured under software control for in- put/output, counter/timers, interrupt, and port handshakes. pins p31, p32, and p33 are standard cmos inputs; out- puts are push-pull. two on-board comparators can process analog signals on p31 and p32 with reference to the voltage on p33. the an- alog function is enabled by programming bit 1 of the port 3 mode register. port 3, pin 3 is a falling edge interrupt in- put. p31 and p32 are programmable as rising, falling or both edge-triggered interrupts (irq register bits 6 and 7). p33 is the comparator reference voltage input. access to counter/timer1 is made through p31 (t in ) and p36 (t out ). handshake lines for ports 0, 1, and 2 are available on p31 through p36. port 3 also provides the following control functions: hand- shake for ports 0, 1, and 2 (/dav and rdy); three external interrupt request signals (irq3-irq1); timer input and out- put signals (t in and t out ) (figure 14). comparator inputs. port 3, pins p31 and p32 all have a comparator front end. the comparator reference voltage, pin p33, is common to both comparators. in analog mode, p31 and p32 are the positive inputs to the comparators and p33 is the reference voltage supplied to both compar- ators. in digital mode, pin p33 can be used as a p33 reg- ister input or irq1 source. table 5. port 3 pin assignments pin i/o ctc1 an in int. p0 hs p1 hs p2 hs ext p31 in tin an1 irq2 d/r p32 in an2 irq0 d/r p33 in ref irq1 d/r p34 out r/d dm p35 out r/d p36 out tout r/d p37 out notes: hs = handshake signals d = dav r = rdy
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 27 2 figure 14. port 3 con?uration d1 r247 = p3m p31 (an1) p32 (an2) p33 (ref) from stop mode recovery source 1 = analog 0 = digital irq2, t in , p31 data latch irq0, p32 data latch irq1, p33 data latch dig. an. port 3 (i/o or control) z89175/176 mcu - + - + 1 2 3 4 5 6 7
z89175/z89176 voice processing controllers zilog 28 p r e l i m i n a r y ds97tad0100 pin functions (continued) port 4 (p47-p40). port 4 is an 8-bit, bidirectional, cmos compatible i/o port (figure 15). these eight i/o lines are configured under software control independently as inputs or outputs. port 4 is always available for i/o operation. the input buffers are schmitt-triggered. bits programmed as outputs can be globally programmed as either push-pull or open-drain. port 4 is a bit programmable general-purpose i/o port. the control registers for port 4 are mapped into the expanded register file (bank f) of the z8. auto latch. the auto latch on port 4 puts valid cmos levels on all cmos inputs which are not externally driven. whether this level is 0 or 1 cannot be determined. a valid cmos level, rather than a floating node, reduces exces- sive supply current flow in the input buffer. figure 15. port 4 con?uration oen out in pad auto latch port 4 (i/o) z89175/176 mcu r = 500 k w 1.5 2.3v hysteresis open-drain
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 29 2 port 5 (p53-p50). port 5 is a 4-bit, bidirectional, cmos compatible i/o port (figure 16). these four i/o lines are configured under software control independently as inputs or outputs. port 5 is always available for i/o operation. the input buffers are schmitt-triggered. bits programmed as outputs can be globally programmed as either push-pull or open-drain. port 5 is a bit programmable general-purpose i/o port. the control registers for port 5 are mapped into the expanded register file (bank f) of the z8. auto latch. the auto latch on port 5 puts valid cmos levels on all cmos inputs which are not externally driven. whether this level is 0 or 1 cannot be determined. a valid cmos level, rather than a floating node, reduces exces- sive supply current flow in the input buffer. figure 16. port 5 con?uration oen out in pad auto latch port 5 (i/o) z89175/176 mcu r = 500 k w 1.5 2.3v hysteresis open-drain
z89175/z89176 voice processing controllers zilog 30 p r e l i m i n a r y ds97tad0100 z8 functional description the z8 core of the z89175/176 incorporates special func- tions to enhance the z8? application in a variety of voice- processing applications. reset. the device is reset in one of the following condi- tions: n power-on reset n watch-dog timer n stop-mode recovery source n external reset program memory. the z8 addresses up to 24 kb of inter- nal program memory and 40 kb external memory (figure 17). the first 12 bytes of program memory are reserved for the interrupt vectors. these locations contain six 16-bit vectors which correspond to the five user interrupts and one dsp interrupt. byte 12 to byte 24575 consist of on- chip mask-programmed rom. at addresses 24576 and greater the z8 executes external program memory. in romless mode, the z8 will execute external program memory beginning at byte 12 and continuing through byte 65535. figure 17. program memory 12 11 10 9 8 7 6 5 4 3 2 1 0 on-chip rom in rom mode location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 irq5 24575 external rom and ram 65535
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 31 2 rom protect. the 24 kb of internal program memory for the z8 is mask programmable. a rom protect feature pre- vents ?umping?of the rom contents of program memory by inhibiting execution of ldc, ldci, lde, and ldei in- structions. the rom protect option is mask-programma- ble, to be selected by the customer at the time the rom code is submitted. data memory (/dm). in rom mode, the z8 can address up to 40 kb of external data memory beginning at location 24576 (figure 18). in romless mode, the z8 can address the full 64 kb of external data memory beginning at loca- tion 12. external data memory can be included with, or separated from, the external program memory space. /dm, an optional i/o function that can be programmed to appear on port 34, is used to distinguish between data and program memory space (table 5). the state of the /dm signal is controlled by the type of instruction being execut- ed. an ldc opcode references program (/dm inactive) memory, and an lde instruction references data (/dm ac- tive low) memory. figure 18. data memory map 65535 24575 0 external data memory not addressable (in rom mode)
z89175/z89176 voice processing controllers zilog 32 p r e l i m i n a r y ds97tad0100 z8 functional description (continued) register file. the standard z8 register file consists of four i/o port registers, 236 general-purpose registers, and 15 control and status registers (r0-r3, r4-r239, and r241-r255, respectively). the instructions access regis- ters directly or indirectly through an 8-bit address field. this allows a short, 4-bit register address using the regis- ter pointer (figure 19). in the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. the register pointer addresses the starting location of the active working register group (figure 20). note: register group e (registers ef-e0) is only access- ed through a working register and indirect addressing modes. ram protect. the upper portion of the z8? ram address spaces 80h to efh (excluding the control registers) is pro- tected from reading and writing. the ram protect bit op- tion is mask-programmable and is selected by the custom- er when the rom code is submitted. after the mask option is selected, the user activates the ram protect from the in- ternal rom code by loading a bit d6 in the imr register to either a 0 (off) or a 1 (on). a 1 in d6 indicates ram pro- tect enabled. stack. the z8? external data memory or the internal reg- ister file is used for the stack. the 16-bit stack pointer (r255-r254) is used for the external stack which can re- side only from 24576 to 65535 in rom mode or 0 to 65535 in romless mode. an 8-bit stack pointer (r255) is used for the internal stack residing within the 236 general-pur- pose registers (r239-r4). sph can be used as a general- purpose register when using internal stack only. expanded register file. the register file on the z8 has been expanded to allow for additional system control reg- isters and for mapping of additional peripheral devices along with i/o ports into the register address area. the z8 register address space has been implemented as 16 banks of 16 register groups per bank (figure 20). these register banks are known as the erf (expanded register file). bits 7-4 of register rp (register pointer) select the working register group. bits 3-0 of register rp select the expanded register bank (figure 21). the smr register, wdt register, control and data regis- ters for port 4 and port 5, and the dsp control register are located in bank f of the expanded register file. bank b of the expanded register file consists of the mailbox in- terface through which the z8 and the dsp communicate. the rest of the expanded register is not physically imple- mented and is open for future expansion. figure 19. register pointer register d7 d6 d5 d4 d3 d2 d1 d0 r253 rp expanded register file bank working register group
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 33 2 figure 20. register pointer the upper nibble of the register file address provided by the register pointer specifies the active working-register group r7 r6 r5 r4 r253 r239 i/o ports specified working register group the upper nibble of the register file address provided by the instruction points to the specified working-register group r15 r3 r255 r240 r3 r2 r1 r0 group 15 (f) control registers group 14 (e) group 13 (d) group 4 (4) group 3 (3) group 2 (2) group 1 (1) group 0 (0) r223 r79 r63 r47 r31 r0
z89175/z89176 voice processing controllers zilog 34 p r e l i m i n a r y ds97tad0100 z8 functional description (continued) figure 21. expanded register file architecture 7 654321 0 working register group pointer expanded register bank pointer ffh foh 7fh 0fh 00h z8 reg. file register pointer ffh feh fdh fch fbh fa h f9h f8h f7h f6h f5h % f4 f3h f2h f1h f0h spl sph rp flags imr irq ipr p01m p3m p2m pre0 t0 pre1 t1 tmr (f) 0fh (f) 0eh (f) 0dh (f) 0ch (f) 0bh (f) 0ah (f) 09h (f) 08h (f) 07h (f) 06h (f) 05h (f) 04h (f) 03h (f) 02h (f) 01h (f) 00h wdtmr smr uuu0 11 0 1 0010000 0 register group 0 (0) z8 expanded register bank (f) reset condition z8 standard register bank (0) register group 15(f) z8 standard control registers reserved * * * * reserved hsec reserved dsp con reserved reserved reserved reserved p45con p5m p5 p4m p4 reserved pcon register bank (0) uuu1uuuu uuu0uuu0 1111 11 1 1 uuuuuuuu 1111 11 1 1 uuuuuuuu 1111 11 1 0 0 1 2 3 4 5 6 7 8 9 a b c d e f z8 expanded register bank (b) z8-dsp mailbox interface reserved ? 1111uuuu uuuuuuuu uuuuuuuu uuuuuuuu register group 0 reset condition (0) 03h p3 (0) 02h p2 (0) 01h p1 (0) 00h p0 * * * * (r0...r15) u = unknown will not be reset with a stop-mode recovery * ? = for romless mode, reset condition 10110110 notes: u u 0 u 0 0 u 0 0 1 u u u u 0 u u 0 u u 0 u 1 0 1 u u u u 0 u u 0 u u 0 u 0 0 1 u u u u 0 u u 0 u u 0 u 0 0 1 u u u u 0 u u 0 u u 0 u 1 0 1 u u u u 0 u u 0 u u 0 u 1 0 1 u u u u 0 u u 0 u u 0 u 0 0 1 u u 0 u 0 u u 0 u u 0 u 1 0 1 0 u 0 u 0 reset condition d7 d6 d5 d4 d3 d2 d1 d0
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 35 2 interrupts. the z8 has six different interrupts from six dif- ferent sources. the interrupts are maskable and prioritized (figure 22). the six sources are divided as follows; three sources are claimed by port 3 lines p33-p31, two by counter/timers, and one by the dsp (table 6). the inter- rupt mask register globally or individually enables or dis- ables the six interrupt requests. figure 22. interrupt block diagram interrupt edge select irq register (d6, d7) irq1, 3, 4, 5 irq imr ipr priority logic 6 global interrupt enable vector select interrupt request irq0 irq2
z89175/z89176 voice processing controllers zilog 36 p r e l i m i n a r y ds97tad0100 z8 functional description (continued) when more than one interrupt is pending, priorities are re- solved by a programmable priority encoder controlled by the interrupt priority register. an interrupt machine cycle is activated when an interrupt request is granted. this dis- ables all subsequent interrupts, pushes the program counter and status flags to the stack, and then branches to the program memory vector location reserved for that in- terrupt. all z8 interrupts are vectored through locations in the pro- gram memory. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register can be polled to determine which of the interrupt requests needs service. an interrupt resulting from an1 is mapped into irq2, and an interrupt from an2 is mapped into irq0. interrupts irq2 and irq0 can be rising, falling or both edge trig- gered, and are programmable by the user. the software can poll to identify the state of the pin. programming bits for the interrupt edge select are located in the irq register (r250), bits d7 and d6 . the configu- ration is shown in table 7. clock. the z89175/176 on-chip oscillator has a high-gain, parallel-resonant amplifier for connection to a crystal, lc, ceramic resonator, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal should be at cut, 20.48 mhz maximum, with a series resistance (rs) less than or equal to 100 ohms. the system clock (sclk) is one half the crystal frequency. the crystal is connected across xtal1 and xtal2 using capacitors from each pin to ground (figure 23). table 6. interrupt types, sources, and vectors name source vector location comments irq0 /dav0, p32, an2 0, 1 external (p32), programmable rise or fall edge triggered irq1 /dav1, p33 2, 3 external (p33), fall edge triggered irq2 /dav2, p31, tin, an2 4, 5 external (p31), programmable rise or fall edge triggered irq3 irq3 6, 7 internal (dsp activated), fall edge triggered irq4 t0 8, 9 internal irq5 ti 10, 11 internal table 7. irq register irq interrupt edge d7 d6 p31 p32 00 ff 01 fr 10 rf 1 1 r/f r/f notes: f = falling edge r = rising edge
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 37 2 counter/timers. there are two 8-bit programmable counter/timers (t1,t0), each driven by its own 6-bit pro- grammable prescaler. the t1 prescaler is driven by inter- nal or external clock sources. however, the t0 prescaler is driven by the internal clock only (figure 24). the 6-bit prescalers can divide the input frequency of the clock source by any integer number from 1 to 64. each prescaler drives its counter, which decrements the value (0 to 256) that has been loaded into the counter. when the counter reaches the end of the count, a timer interrupt re- quest, irq4 (t0) or irq5 (t1), is generated. the counters can be programmed to start, stop, restart to continue, or restart from the initial value. the counters can also be programmed to stop upon reaching zero (single pass mode) or to automatically reload the initial value and continue counting (modulo-n continuous mode). the counters, but not the prescalers, are read at any time without disturbing their value or count mode. the clock source for t1 is user-definable and is either the internal mi- croprocessor clock divided by four, or an external signal in- put via port 31. the timer mode register configures the ex- ternal timer input (p31) as an external clock, a trigger input that can be retriggerable or non-retriggerable, or as a gate input for the internal clock. the counter/timers can be cascaded by connecting the t0 output to the input of t1. figure 23. oscillator con?uration xtal1 xtal2 c1 c2 c1 c2 xtal1 xtal2 xtal1 xtal2 ceramic resonator or crystal lc external clock l
z89175/z89176 voice processing controllers zilog 38 p r e l i m i n a r y ds97tad0100 z8 functional description (continued) figure 24. counter/timer block diagram pre0 initial value register t0 initial value register t0 current value register 6-bit down counter 8-bit down counter ? 16 ? 4 6-bit down counter 8-bit down counter pre1 initial value register t1 initial value register t1 current value register clock logic irq4 t p36 out irq5 internal data bus write write read internal clock gated clock triggered clock tin p31 write write read internal data bus external clock internal clock d0,d1 (smr) ? 4 ? 2 ? 2 ? 2 ? 2 osc t0, t2, t3 dsp clock d7, d6 (f) oc (dsp con)
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 39 2 port configuration register (pcon). the pcon regis- ter configures the comparator output on port 3. the pcon register (figure 25) is located in the expanded register file at bank f, location 00h. comparator output port 3 (d0). bit 0 controls the com- parator use in port 3. a 1 in this location brings the com- parator outputs to p34 and p35, and a 0 releases the port to its standard i/o configuration. port 4 and 5 configuration register (p45con). the p45con register configures port 4 and port 5, individual- ly, to open-drain or push-pull active. this register is located in the expanded register file at bank f, location 06h (fig- ure 26). port 4 open-drain (d0). port 4 can be configured as an open-drain by resetting this bit (d0 = 0) or configured as push-pull active by setting this bit (d0 = 1). the default val- ue is 1. port 5 open-drain (d4). port 5 can be configured as an open-drain by resetting this bit (d4 = 0) or configured as push-pull active by setting this bit (d4 = 1). the default val- ue is 1. power-on reset (por). a timer circuit clocked by a ded- icated on-board rc oscillator is used for the power-on re- set (por) timer function. the por time allows vcc and the oscillator circuit to stabilize before instruction execu- tion begins. the por timer circuit is a one-shot timer triggered by one of three conditions: 1. power fail to power ok status; 2. stop-mode recovery (if d5 of smr=1); 3. wdt time-out. the por time is a nominal 5 ms. bit 5 of the stop mode register determines whether the por timer is bypassed af- ter stop-mode recovery (typical for external clock, rc/lc oscillators). halt. halt turns off the internal cpu clock, but not the xtal oscillation. the counter/timers and external inter- rupts irq0, irq1, irq2, and irq3 remain active. the de- vices are recovered by interrupts, either externally or inter- nally generated. stop. this instruction turns off the internal clock and ex- ternal crystal oscillation. it reduces the standby current to 20 m a or less. the stop mode is terminated by a reset only, either by wdt time-out, por, smr, or external re- set. this causes the processor to restart the application program at address 000ch. in order to enter stop (or halt) mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. to do this, the user must execute a nop (opcode=ffh) immediately before the appropriate sleep instruction, i.e., figure 25. port con?uration register (pcon) d7 d6 d5 d4 d3 d2 d1 d0 pcon (f) %00 r always "1" w 0 p34,p37 standard output 1 p34,p37 comparator output r always "1" w no effect note: reset condition is 1 1111110 ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode
z89175/z89176 voice processing controllers zilog 40 p r e l i m i n a r y ds97tad0100 z8 functional description (continued) stop-mode recovery register (smr). this register se- lects the clock divide value and determines the mode of stop-mode recovery (figure 26). all bits are write-only except bit 7, which is read-only. bit 7 is a flag bit that is hardware set on the condition of stop recovery and reset by a power-on cycle. bit 6 controls whether a low level or a high level is required from the recovery source. bit 5 con- trols the reset delay after recovery. bits 2, 3, and 4, or the smr register, specify the source of the stop-mode recov- ery signal. bits 0 and 1 determine the time-out period of the wdt. the smr is located in bank f of the expanded reg- ister group at address 0bh. figure 26. stop-mode recovery register (smr) d7 d6 d5 d4 d3 d2 d1 d0 smr (fh) 0bh w stop delay 0 off 1 on* r always "1" w 0 low stop recovery level* 1 high stop recovery level r always "1" w no effect r 0 por* 1 stop-mode recovery * default setting after reset ? reset after stop-mode recovery w 000 por only* 001 no effect 010 p31 011 p32 100 p33 101 half second timeout from 33 khz ext. osc. 110 p2 nor 0-3 111 p2 nor 0-7 r always "1" w 0 sclk/tclk not divided by 16? 1 sclk/tclk divided by 16 r always "1" reserved
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 41 2 sclk/tclk divide-by-16 select (d0). d0 of the smr controls a divide-by-16 prescaler of sclk/tclk. the pur- pose of this control is to selectively reduce device power consumption during normal processor execution (sclk control) and/or halt mode (where tclk sources counter/timers and interrupt logic). stop-mode recovery source (d4-d2). these three bits of the smr specify the wake-up source of the stop re- covery (figure 27 and table 8). stop-mode recovery delay select (d5). when low, this bit disables the 5 ms /reset delay after stop-mode re- covery. the default configuration of this bit is 1. if the ?ast wake up is selected, the stop-mode recovery source is kept active for at least 5 tpc. stop-mode recovery edge select (d6). a 1 in this bit po- sition indicates that a high level on any one of the recovery sources wakes the z89175/176 from stop mode. a 0 in- dicates low level recovery. the default is 0 on por (table 8). cold or warm start (d7). this bit is set by the device upon entering stop mode. it is active high, and is 0 (cold) on por/wdt /reset. this bit is read-only. it is used to distinguish between a cold or warm start. dsp control register (dspcon). the dspcon register controls various aspects of the z8 and the dsp. it can con- figure the internal system clock (sclk) or the z8, /re- set, and halt of the dsp, and control the interrupt inter- face between the z8 and the dsp (table 9). figure 27. stop-mode recovery source p31 p32 p33 hsec stop mode recovery edge select (smr) p33 from pads digital/analog mode select (p3m) to p33 data latch and irq1 to por reset smr d4 d3 d2 0 0 0 vdd smr smr smr smr smr d4 d3 d2 0 1 0 0 1 1 d4 d3 d2 1 0 0 d4 d3 d2 1 0 1 d4 d3 d2 1 1 0 d4 d3 d2 1 1 1 p20 p23 p20 p27 mux table 8. stop-mode recovery source smr:432 operation description of action d4 d3 d2 0 0 0 por and/or external reset recovery 0 0 1 no effect 0 1 0 p31 transition 0 1 1 p32 transition 1 0 0 p33 transition 1 0 1 hsec 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27
z89175/z89176 voice processing controllers zilog 42 p r e l i m i n a r y ds97tad0100 z8 functional description (continued) z8 irq3 (d0). when read, this bit indicates the status of the z8 irq3. the z8 irq3 is set by the dsp by writing to d9 of dsp external register 4 (icr). by writing a 1 to this bit, z8 irq3 is reset. dsp int2 (d1). this bit is linked to dsp int2. writing a 1 to this bit sets the dsp int2. reading this bit indicates the status of the dsp int2. dsp run (d4). this bit defines the halt mode of the dsp. if this bit is set to 0, then the dsp clock is turned off to minimize power consumption. after this bit is set to 1, then the dsp will continue code execution from where it was halted. after a hardware reset, this bit is reset to 1. dsp reset (d5). setting this bit to 1 will reset the dsp. if the dsp was in halt mode, this bit is automatically pre- set to 1. writing a 0 has no effect. z8 sclk (d7-d6). these bits define the sclk frequency of the z8. the oscillator can be divided by 8, 4, or 2. after a reset, both bits default to 00. watch-dog timer mode register (wdtmr). the wdt is a retriggerable one-shot timer that resets the z8 if it reaches its terminal count. the wdt is initially enabled by executing the wdt instruction and refreshed on subse- quent executions of the wdt instruction. the wdt circuit is driven by an on-board rc oscillator or external oscillator from the xtal1 pin. the por clock source is selected with bit 4 of the wdt register (figure 29). the wdtmr register is accessible only within 64 z8 clock cycles after por. table 9. dsp control register (f) och [read/write] field dspcon (f)0ch position attrib value label z8_sclk 76------ r/w 00 01 1x (osc/8) (osc/4) (osc/2) dsp_reset --5----- r return ? w 0 no effect 1 reset dsp dsp_run ---4---- r/w 0 halt_dsp 1 run_dsp reserved ----32-- w no effect r return ? no effect dsp_int2 ------1- r fb_dsp_int2 w 1 set dsp_int2 0 no effect z8_irq3 -------0 r fb_z8_irq3 w 1 clear irq3 0 no effect
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 43 2 half-second timer status register (hsec). the half- second timer status register (figure 30) is a free-running timer clocked by the external 32.768 khz crystal. in normal operation mode, every half-second, the timer will time-out and set bit 0 (d0) of the hsec register to 1. the user can reset this bit for real timing. in stop mode, this timer can be used as a stop-mode recovery source. every half-sec- ond, the timer will recover the stop mode and bit 0 of the hsec register will be set to 1. therefore, in stop mode, the user can keep real time. figure 28. watch-dog timer mode register d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (f) 0f wdt tap int rc osc external clock 00 5 ms 256 tpc 01* 15 ms 512 tpc 10 25 ms 1024 tpc 11 100 ms 4096 tpc wdt during halt 0 off 1 on* wdt during stop 0 off 1 on* xtal1/int rc select for wdt 0 on-board rc 1 xtal w no effect r always "1" * default setting after reset figure 29. half-second timer status register d7 d6 d5 d4 d3 d2 d1 d0 hsec (f) 0e r 1 half second time-out 0 no time-out w 1 no effect 0 reset the half second timer bit reserved r "0" w no effect
z89175/z89176 voice processing controllers zilog 44 p r e l i m i n a r y ds97tad0100 z8 functional description (continued) wdt time select (d0, d1). these bits selects the wdt time period. the configuration is shown in table 10. wdt during halt (d2). this bit determines whether or not the wdt is active during halt mode. a 1 indicates ac- tive during halt. the default is 1. wdt during stop (d3). this bit determines whether or not the wdt is active during stop mode. since xtal clock is stopped during stop mode, the on-board rc must be selected as the clock source to the por counter. a 1 indicates active during stop. the default is 1. clock source for wdt (d4). this bit determines which oscillator source is used to clock the internal por and wdt counter chain. if the bit is a 1, the internal rc oscil- lator is bypassed and the por and wdt clock source is driven from the external pin, xtal1. the default configu- ration of this bit is 0 which selects the rc oscillator. table 10. wdt time select time-out of time-out of d1 d0 internal rc osc xtal clock 0 0 5 ms min 256 tpc 0 1 15 ms min 512 tpc 1 0 25 ms min 1024 tpc 1 1 100 ms min 4096 tpc notes: tpc = xtal clock cycle. tolerance = 10% figure 30. resets and wdt clk 18 clock reset generator reset clear wdt tap select rc osc. ck clr 5 ms por 5 ms 15 ms 25 ms 100 ms 2v operating voltage det. internal reset wdt select (wdtmr) ck source select (wdtmr) xtal vdd 2v ref. from stop mode recovery source wdt stop delay select (smr) 12 ns glitch filter + - 4 clock filter wdt/por counter chain m u x /reset
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 45 2 dsp registers description general. the dsp is a high-performance second genera- tion cmos digital signal processor with a modified har- vard-type architecture with separate program and data ports. the design has been optimized for processing pow- er and saving silicon space. registers. the dsp has eight internal registers and sev- en external registers. the external registers are for the a/d and d/a converters, and the mailbox and interrupt interfac- ing between dsp to the z8. external registers are access- ed in one machine cycle, the same as internal registers. dsp registers there are 15 internal and extended 16-bit registers which are defined in table 11. ext3-ext0 (external registers 3-0). these are the mail- box registers used by the dsp and z8 to communicate. these four 16-bit registers correspond to the eight outgo- ing and eight incoming 8-bit registers in bank b of the z8? expanded register file. ext4 (dsp interrupt control register (icr)). this register controls the interrupts in the dsp as well as the interrupts in common between the dsp and the z8. it is accessible by the dsp only, except for bit f and bit 9. ext5 (d/a and a/d data register). this register is used by both d/a and a/d converters. the d/a converter is loaded by writing to this register, while the a/d converter is addressed by reading from this register. the register ext5 is accessible only by the dsp. ext6 (analog control register). this register controls the d/a and a/d converters. it is a read/write register accessi- ble only by the dsp. dsp z8 mail box to receive information from the dsp, the z8 uses eight in- coming registers which are mapped in the z8 extended register file (bank b, 08 to 0f). the dsp treats these as four 16-bit registers that correspond to the eight incoming z8 registers (figure 32). table 11. dsp registers register attribute register de?ition bus read data-bus x read/write x multiplier input, 16-bit y read/write y multiplier input, 16-bit a read/write accumulator, 24-bit sr read/write status register sp read/write stack pointer pc read/write program counter p read output of mac, 24-bit ext0 read z8 erf bank b, register 00-01 (from z8) write z8 erf bank b, register 08-09 (to z8) ext1 read z8 erf bank b, register 02-03 (from z8) write z8 erf bank b, register 0a-0b (to z8) ext2 read z8 erf bank b, register 04-05 (from z8) write z8 erf bank b, register 0c-0d (to z8) ext3 read z8 erf bank b, register 06-07 (from z8) write z8 erf bank b, register 0e-0f (to z8) ext4 read/write dsp interrupt control register ext5 read a/d converter write d/a converter ext6 read/write analog control register
z89175/z89176 voice processing controllers zilog 46 p r e l i m i n a r y ds97tad0100 dsp registers description (continued) the z8 can supply the dsp with data through eight outgo- ing registers mapped into both the z8 expanded register file (bank b, registers 00 to 07) and the external register interface of the dsp. these registers are read/write and can be used as general-purpose registers of the z8. the dsp can only read information from these registers. since the dsp uses a 16-bit data format and the z8 an 8-bit data format, eight outgoing registers of the z8 correspond to four dsp registers. the dsp can only read information from the outgoing registers. both the outgoing registers and the incoming registers share the same dsp address (ext3-ext0). note: the z8 can read and write to erf bank b r00-r07, registers 08-0f are read-only from the z8. figure 31. z8-dsp interface outgoing registers incoming registers dsp interrupt control register d/a and a/d data registers analog control register (b)00, (b)01 (b)02, (b)03 (b)04, (b)05 (b)06, (b)07 (b)08, (b)09 (b)0a, (b)0b (b)0c, (b)0d (b)0e, (b)0f (f)0c ext0 ext2 ext0 ext2 ext4 ext1 ext3 ext1 ext3 ext5 ext6 d7, d1 z8 data bus dsp data bus d9 d2 table 12. z8 outgoing registers (read-only from dsp) field position attrib value label outgoing [0] (b)00 76543210 r/w %nn (b)00/dsp_ext0_hi outgoing [1] (b)01 76543210 r/w %nn (b)01/dsp_ext0_lo outgoing [2] (b)02 76543210 r/w %nn (b)02/dsp_ext1_hi outgoing [3] (b)03 76543210 r/w %nn (b)03/dsp_ext1_lo outgoing [4] (b)04 76543210 r/w %nn (b)04/dsp_ext2_hi outgoing [5] (b)05 76543210 r/w %nn (b)05/dsp_ext2_lo outgoing [6] (b)06 76543210 r/w %nn (b)06/dsp_ext3_hi outgoing [7] (b)07 76543210 r/w %nn (b)07/dsp_ext3_lo
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 47 2 table 13. z8 incoming registers (write-only from dsp) field position attrib value label incoming [8] (b)08 76543210 r %nn dsp_ext0_hi w no effect incoming [9] (b)09 76543210 r %nn dsp_ext0_lo w no effect incoming [a] (b)0a 76543210 r %nn dsp_ext1_hi w no effect incoming [b] (b)0b 76543210 r %nn dsp_ext1_lo w no effect incoming [c] (b)0c 76543210 r %nn dsp_ext2_hi w no effect incoming [d] (b)0d 76543210 r %nn dsp_ext2_lo w no effect incoming [e] (b)0e 76543210 r %nn dsp_ext3_hi w no effect incoming [f] (b)0f 76543210 r %nn dsp_ext3_lo w no effect table 14. dsp incoming registers field position attrib value label dsp_ext0 fedcba9876543210 r %nnnn (b)00, (b)01 mail box w (b)08, (b)09 dsp_ext1 fedcba9876543210 r %nnnn (b)02, (b)03 mail box w (b)0a, (b)0b dsp_ext2 fedcba9876543210 r %nnnn (b)04, (b)05 mail box w (b)0c, (b)0d dsp_ext3 fedcba9876543210 r %nnnn (b)06, (b)07 mail box w (b)0e, (b)0f
z89175/z89176 voice processing controllers zilog 48 p r e l i m i n a r y ds97tad0100 dsp interrupts the dsp processor has three interrupt sources (int2, int1, int0) (figure 33). these sources have different pri- ority levels (figure 34). the highest priority, the next lower and the lowest priority level are assigned to int2, int1 and int0, respectively (figure 35). the dsp does not al- low interrupt nesting (interrupting service routines that are currently being executed). when two interrupt requests oc- cur simultaneously the dsp starts servicing the interrupt with the highest priority level. figure 32. dsp interrupts interrupt priority logic interrupt request logic interrupt mask logic feedback z8_int mpx z8_int a/d int d/a int ipr2 ipr1 ipr0 fb dsp clear_int1 clear_int2 clear_int0 enable_int int2 int1 int0 int2 int1 int0 figure 33. dsp interrupt priority structure int0 int1 int2 dsp execution int2 int0 int1 int2
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 49 2 figure 34. interprocessor interrupts structure 4 9 after serving irq3, set d0 to clear the interrupt request. the dsp sets d9 to interrupt z8 via z8 irq3. irq3 of the z8 dsp int2 after serving int2, set d4 to clear the interrupt request. on the z8, set d1 to interrupt dsp via dsp int2. dsp side z8 side 10 dsp con icr (ext4) table 15. ext4 dsp interrupt control register (icr) de?ition field position attrib value label dsp_irq2 f--------------- r 1 set_irq2 0 reset_irq2 f--------------- w no effect dsp_irq1 -e-------------- r 1 set_irq1 0 reset_irq1 -e-------------- w no effect dsp_irq0 --d------------- r 1 set_irq0 0 reset_irq0 --d------------- w no effect dsp_maskint2 ---c------------ r/w 1 enable_int2 0 disable_int2 dsp_maskint1 ----b----------- r/w 1 enable_int1 0 disable_int1 dsp_maskint0 -----a---------- r/w 1 enable_int0 0 disable_int0 z8_irq3 ------9--------- r return "0" ------9--------- w 1 set_z8_irq3 0 reset_z8_irq3 dspintenable -------8-------- r/w 1 enable 0 disable dsp_ipr2 --------7------- r/w binary ipr2 dsp_ipr1 ---------6------ r/w binary ipr1 dsp_ipr0 ----------5----- r/w binary ipr0 clear_irq2 -----------4---- r return "0"
z89175/z89176 voice processing controllers zilog 50 p r e l i m i n a r y ds97tad0100 dsp registers description (continued) interrupt control register (icr). the icr is mapped into ext4 of the dsp (table 15). the bits are defined as fol- lows: dsp_irq2 (z8 interrupt). this bit is read by both z8 and dsp and is set only by writing to the z8 expanded register file (bank f, roc, bit 0). this bit asserts irq2 of the dsp and is cleared by writing to the clear_irq2 bit. dsp_irq1 (a/d interrupt). this bit is read by the dsp only and is set when valid data is present at the a/d output reg- ister (conversion done). this bit asserts irq1 of the dsp and is cleared by writing to the clear_irq1bit. dsp_irq0 (d/a interrupt). this bit is read by dsp only and is set by timer3. this bit assists irq0 of the dsp and is cleared by writing to the clear_irq0 bit. dsp_maskintx. these bits are accessed by the dsp only. writing a 1 to these locations allows the int to be serviced, while writing a 0 masks off the corresponding int. z8_irq3. this bit can be read by both the z8 and the dsp but can only be set by the dsp. addressing this location accesses bit d3 of the z8 irq register, hence, this bit is not implemented in the icr. during the interrupt service routine executed on the z8 side, the user must reset the z8_irq3 bit by writing a 1 to bit d0 of the dspcon. the hardware of the z89175/176 automatically resets z8_irq3 bit three instructions of the z8 after 1 is written to its location in register bank 0f. this delay provides the tim- ing synchronization between the z8 and the dsp sides during interrupts. in summary, the interrupt service routine of the z8 for irq3 should be finished by: ld ; rp,#%0f or ; r12,#%01 pop ; rp iret ; dsp enable_int. writing a 1 to this location enables glo- bal interrupts of the dsp while writing 0 disables them. a system reset globally disables all interrupts. dsp_iprx. this three-bit group defines the interrupt se- lection logic as shown in table 16. clear_irqx. these bits are accessed by the dsp only. writing a 1 to these locations resets the corresponding dsp_irqx bits to 0. clear_irqx are virtual bits and are not implemented. -----------4---- w 1 clear_irq2 0 has_no_effect clear_irq1 ------------3--- r return "0" ------------3--- w 1 clear_irq1 0 no effect clear_irq0 -------------2-- r return "0" -------------2-- w 1 clear_irq0 0 no effect reserved --------------10 w no effect "0" r table 15. ext4 dsp interrupt control register (icr) de?ition field position attrib value label table 16. dsp interrupt selection dsp_ipr[2-0] 2 1 0 z8_int is switched to a/d_int is switched to d/a_int is switched to 0 0 0 int2 int1 int0 0 0 1 int1 int2 int0 0 1 0 int2 int0 int1 0 1 1 int1 int0 int2 1 0 0 int0 int2 int1 1 0 1 int0 int1 int2 1 1 0 reserved reserved reserved 1 1 1 reserved reserved reserved
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 51 2 dsp analog data registers the d/a conversion is dsp driven by sending 10-bit data to the ext5 of the dsp. the six remaining bits of ext5 are not used (figure 36). a/d supplies 8-bit data to the dsp through the register ext5 of the dsp. from the 16 bits of ext5, only bits 2 through 9 are used by the a/d (figure 37). bits 0 and 1 are padded with zeroes. analog control register (acr) the analog control register is mapped to register ext6 of the dsp (table 17). this read/write register is accessible by the dsp only. the 16-bit field of ext6 defines modes of both the a/d and the d/a. the high byte configures the d/a while the low byte controls the a/d mode. figure 35. ext5 register d/a mode de?ition fedcba9876543210 reserved 10-bit data for d/a (write only) reserved figure 36. ext5 register a/d mode de?ition fedcba9876543210 reserved 8-bit data from a/d converter (read only) reserved table 17. ext6 analog control register (acr) field position attrib value label 20.48 mhz 29.49 mhz* mpx_dsp_int0 f--------------- r/w 1 p26 0 timer3 reserved -edcba---------- r return ? w no effect reserved ------9--------- r return ? w no effect d/a_samplingrate -------8-------- r/w 0 16 khz 8.04 khz 1 10 khz 9.6 khz
z89175/z89176 voice processing controllers zilog 52 p r e l i m i n a r y ds97tad0100 dsp registers description (continued) dsp irq0. this bit defines the source of the dsp irq0 in- terrupt. d/a_sampling rate. this field defines the sampling rate of the d/a output. it changes the period to timer3 interrupt and the maximum possible accuracy of the d/a sampling rate (table 18). dsp0. dsp0 is a general-purpose output pin connected to bit 6. this bit has no special significance and can be used to output data by writing to bit 6. dsp_port (dsp1, dsp0) --------76------ r/w user-de?ed dsp outputs enable a/d ----------5----- r/w 1 a/d enabled 0 a/d disabled conversiondone -----------4---- w no effect r 1 done 0 not done startconversion ------------3--- r/w 1 start 0 wait timer reserved -------------2-- r return ? w no effect 20/29 mhz select --------------1- r/w 1 29.49 mhz* 0 20.48 mhz? a/d_samplingrate ---------------0 r/w 1 16 khz 16 khz 0 8 khz 9.6 khz notes: * default value ? optional feature table 17. ext6 analog control register (acr) field position attrib value label 20.48 mhz 29.49 mhz* table 18. d/a data accuracy d/a_sampling rate sampling rate bit 8 20.48 mhz 29.49 mhz 0 16 khz 8.04 khz 1 10 khz 9.6 khz
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 53 2 dsp1. dsp1 is a general-purpose output pin connected to bit 7. this bit has no special significance and can be used to output data by writing to bit 7. enable a/d. writing a 0 to this location disables the a/d converter, a 1 will enable it. a hardware reset forces this bit to 0. conversion done. this read-only flag indicates that the a/d conversion is complete. upon reading ext5 (a/d da- ta), the conversion done flag is cleared. start a/d conversion. writing a 1 to this location immedi- ately starts one conversion cycle. if this bit is reset to 0 the input data is converted upon successive timer2 time-outs. a hardware reset forces this bit to 1. a/d_sampling rate. this field defines the sampling rate of the a/d. it changes the period of timer2 interrupt (table 19). dsp timers timer2 is a free running counter that divides the xtal fre- quency (20.48 mhz) to support different sampling rates for the a/d converter. the sampling rate is defined by the an- alog control register. upon reaching the end of a count, the timer generates an interrupt request to the dsp. analogous to timer2, timer3 generates the different sam- pling rates for the d/a converter. timer3 also generates an interrupt request to the dsp upon reaching its final count value (figure 37). table 19. a/d sampling rate a/d_sampling rate sampling rate bit 0 20.48 mhz 29.49 mhz 1 16 khz 16 khz 0 8 khz 9.6 khz figure 37. timer2 and timer3 osc 20.48 mhz timer2 8, 16 khz timer3 16, 10 khz a/d d/a timer2 16, 9.6 khz usc 29.49 mhz timer3 8.04, 9.6 khz a/d d/a
z89175/z89176 voice processing controllers zilog 54 p r e l i m i n a r y ds97tad0100 pulse width modulator (pwm) the pwm supports two different sampling rates (10 and 16 khz), according to the settings of bit 8 of the acr. the out- put of the pwm can be assigned to logic 1 only during the active region (which is 4/5 of the output signal period). the output will be at logic 0 for the rest of the time. an excep- tion occurs in 10 khz pwm, where the active region covers the whole output signal period (figure 39). the active re- gion is divided into 1024 time slots. in each of these time slots, the output can be set to logic 1 or logic 0. in order to increase the effective sampling rate, the pwm employs a special technique of distributing the ?ogic 1?pe- riod over the active region. the 10-bit pwm data is divided into two parts: the upper five bits (high_val) and the lower five bits (low_val). the 1024 time slots in the active region are divided into 32 equal groups, with 32 time slots in each group. the first slot of each of the 32 groups represents low_val, while high_val is represented by the remaining 31 time slots in each group. for example, a value of %13a is loaded into pwm data register ext 5: %13a = 01 0011 1010b = 314 high_val = 01001b = 9 low_val = 11010b = 26 26 out of 32 groups will then have their first slots set to log- ic 1. the remaining one slot in each group has nine time slots set to logic 1. for 10 khz pwm, the effective output frequency is 10k x 32 = 320 khz. figure 40 illustrates the waveform by using a 6-bit pwm data (3-bit high_val and 3-bit low_val). figure 38. pwm waveform (shaded area shows the active region) 10 khz 16 khz 250 m s 100 m s
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 55 2 figure 39. pwm waveform of the active region (for a 6-bit pwm data)
z89175/z89176 voice processing controllers zilog 56 p r e l i m i n a r y ds97tad0100 a/d converter (adc) analog to digital converter the a/d converter is an 8-bit half flash converter which uses two reference resistor ladders for its upper four bits (msbs) and lower four bits (lsbs) conversion (figure 41). two reference voltage pins, vref+ (high) and vref- (low), are provided for external reference voltage sup- plies. during the sampling period, the converter is auto-ze- roed before starting the conversion time depending on the external clock frequency and the selection of the a/d sam- pling rate (figure 40). the sampling rates are 10 or 16 khz (xtal = 20.48 mhz) in order to provide oversampling. the rates are software controlled by the acr (dsp external register 6). timer2 supports the adc. the maximum con- version time is 2 m s. conversion begins by writing to the appropriate bit in the analog control register (acr). the start commands are implemented in such a way as to begin a conversion at any time. if a conversion is in progress and a new start com- mand is received, then the conversion in progress is abort- ed and a new conversion initiated. this allows the pro- grammed values to be changed without affecting a conversion in progress. the new values take effect only af- ter a new start command is received. the adc can be disabled (for low power) or enabled by an analog control register bit. though the adc functions for a smaller input voltage and voltage reference, the noise and offsets remain constant over the specified electrical range. the errors of the con- verter will increase and the conversion time can also take slightly longer due to smaller input signals. figure 40. a/d converter 4-bit flash an in sample auto zero m 4-bit dac C + 4 msb 4-bit flash auto zero 4 lsb latch 4 msb latch 4 lsb bits 9-2 register 12 of dsp
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 57 2 figure 42 shows the input circuit of the adc. when con- version starts, the analog input voltage from the input is connected to the msb and lsb flash converter inputs as shown in the input impedance ckt diagram. shunting 31 parallel internal resistances of the analog switches and si- multaneously charging 31 parallel 1 pf capacitors is equiv- alent to a 400 ohms input impedance in parallel with a 31 pf capacitor. other input stray capacitance adds about 10 pf to the input load. input source resistances up to 2 ko- hms can be used under normal operating conditions with- out any degradation of the input settling time. for larger in- put source resistance, longer conversion cycle times can be required to compensate the input settling time problem. v ref is set using the v ref + pin. figure 41. adc timing diagram sclk 1234567 891011 26272829303132 p32 input sample a/d result dsp int dsp write notes: 1. sclk = 10 mhz (xtal = 20.48 mhz) 1 figure 42. input impedance of adc cmos switch on resistance 2 - 5 k w c parasitic r source v ref c .5 pf v ref c .5 pf v ref c .5 pf 31 cmos digital comparators
z89175/z89176 voice processing controllers zilog 58 p r e l i m i n a r y ds97tad0100 z8 expanded register file registers expanded register bank b figure 43. outgoing register to dsp ext0 (high byte) (b) 00h [read/write] figure 44. outgoing register to dsp ext0 (low byte) (b) 01h [read/write] figure 45. outgoing register to dsp ext1 (high byte) (b) 02h [read/write] figure 46. outgoing register to dsp ext1 (low byte) (b) 03h [read/write] d7 d6 d5 d4 d3 d2 d1 d0 (b) 00 dsp ext0, bits d15-d8 d7 d6 d5 d4 d3 d2 d1 d0 (b) 01 dsp ext0, bits d7-d0 d7 d6 d5 d4 d3 d2 d1 d0 (b) 02 dsp ext1, bits d15-d8 d7 d6 d5 d4 d3 d2 d1 d0 (b) 03 dsp ext1, bits d7-d0 figure 47. outgoing register to dsp ext2 (high byte) (b) 04h [read/write] figure 48. outgoing register to dsp ext2 (low byte) (b) 05h [read/write] figure 49. outgoing register to dsp ext3 (high byte) (b) 06h [read/write] d7 d6 d5 d4 d3 d2 d1 d0 (b) 04 dsp ext2, bits d15-d8 d7 d6 d5 d4 d3 d2 d1 d0 (b) 05 dsp ext2, bits d7-d0 d7 d6 d5 d4 d3 d2 d1 d0 (b) 06 dsp ext3, bits d15-d8
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 59 2 figure 50. outgoing register to dsp ext3 (low byte) (b) 07h [read/write] figure 51. incoming register from dsp ext0 (high byte) (b) 08h [read-only] figure 52. incoming register from dsp ext0 (low byte) (b) 09h [read-only] figure 53. incoming register from dsp ext1 (high byte) (b) 0ah [read-only] d7 d6 d5 d4 d3 d2 d1 d0 (b) 07 dsp ext3, bits d7-d0 d7 d6 d5 d4 d3 d2 d1 d0 (b) 08 dsp ext0, bits d15-d8 d7 d6 d5 d4 d3 d2 d1 d0 (b) 09 dsp ext0, bits d7-d0 d7 d6 d5 d4 d3 d2 d1 d0 (b) 0a dsp ext1, bits d15-d8 figure 54. incoming register from dsp ext1 (low byte) (b) 0bh [read-only] figure 55. incoming register from dsp ext2 (high byte) (b) 0ch [read-only] figure 56. incoming register from dsp ext2 (low byte) (b) 0dh [read-only] figure 57. incoming register from dsp ext3 (high byte) (b) 0eh [read-only] d7 d6 d5 d4 d3 d2 d1 d0 (b) 0b dsp ext1, bits d7-d0 d7 d6 d5 d4 d3 d2 d1 d0 (b) 0c dsp ext2, bits d15-d8 d7 d6 d5 d4 d3 d2 d1 d0 (b) 0d dsp ext2, bits d7-d0 d7 d6 d5 d4 d3 d2 d1 d0 (b) 0e dsp ext3, bits d15-d8
z89175/z89176 voice processing controllers zilog 60 p r e l i m i n a r y ds97tad0100 z8 expanded register file registers (continued) expanded register bank f figure 58. incoming register from dsp ext3 (low byte) (b) 0fh [read-only] figure 59. port con?uration register (pcon) (f) 00h [write-only] figure 60. port 4 data register (f) 02h [read/write] figure 61. port 4 mode register (f) 03h [write-only] d7 d6 d5 d4 d3 d2 d1 d0 (b) 0f dsp ext3, bits d7-d0 d7 d6 d5 d4 d3 d2 d1 d0 pcon (f) %00 r always "1" w 0 p34,p37 standard output 1 p34,p37 comparator output r always "1" w no effect note: reset condition is 1 1111110 d7 d6 d5 d4 d3 d2 d1 d0 p4d (fh) 02h data d7 d6 d5 d4 d3 d2 d1 d0 p40-p47 i/o definition 0 defines bit as output 1 defines bit as input returns "ff" upon read p4m (fh) 03h figure 62. port 5 data register (f) 04h [read/write] figure 63. port 5 mode register (f) 05h [write-only] figure 64. port 4 and 5 con?uration register (f) 06h [write-only] d7 d6 d5 d4 d3 d2 d1 d0 p5d (fh) 04h data d7 d6 d5 d4 d3 d2 d1 d0 p5m (fh) 05h p50-p57 i/o definition 0 defines bit as output 1 defines bit as input* returns "ff" upon read * default setting after reset p45m (fh) 06h (write only) port 4 configuration bit 0 open-drain 1 push-pull no effect port 5 configuration bit 0 open-drain 1 push-pull no effect d7 d6 d5 d4 d3 d2 d1 d0
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 61 2 figure 65. stop-mode recovery register (smr) (f) 0bh [read/write] d7 d6 d5 d4 d3 d2 d1 d0 smr (fh) 0bh w stop delay 0 off 1 on* r always "1" w 0 low stop recovery level* 1 high stop recovery level r always "1" w no effect r 0 por* 1 stop-mode recovery * default setting after reset ? reset after stop-mode recovery w 000 por only* 001 no effect 010 p31 011 p32 100 p33 101 half second timeout from 33 khz ext. osc. 110 p2 nor 0-3 111 p2 nor 0-7 r always "1" w 0 sclk/tclk not divided by 16? 1 sclk/tclk divided by 16 r always "1" reserved
z89175/z89176 voice processing controllers zilog 62 p r e l i m i n a r y ds97tad0100 z8 expanded register file registers (continued) table 20. dsp control register (f) 0ch [read/write] field dspcon (f) 0ch position attributes value label z8_sclk 76------ r/w 00 osc/8 01 osc/4 1x osc/2 dsp_reset --5----- r return ? w 0 no effect 1 reset dsp dsp_run ---4---- r/w 0 halt_dsp 1 run_dsp reserved ----32-- xx return ? no effect intfeedback ------1- r fb_dsp_int2 w 1 set dsp_int2 0 no effect -------0 r fb_z8_irq3 w 1 clear irq3 0 no effect figure 66. watch-dog timer mode register (f) 0fh [read/write] d7 d6 d5 d4 d3 d2 d1 d0 wdtmr (f) 0f wdt tap int rc osc external clock 00 5 ms 256 tpc 01* 15 ms 512 tpc 10 25 ms 1024 tpc 11 100 ms 4096 tpc wdt during halt 0 off 1 on* wdt during stop 0 off 1 on* xtal1/int rc select for wdt 0 on-board rc 1 xtal w no effect r always "1" * default setting after reset
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 63 2 z8 control registers figure 67. reserved (f0h) figure 68. timer mode register (f1h: read/write) figure 69. counter/timer 1 register (f2h: read/write) d7 d6 d5 d4 d3 d2 d1 d0 reserved r240 d7 d6 d5 d4 d3 d2 d1 d0 0 disable t0 count 1 enable t0 count 0 no function 1 load t0 0 no function 1 load t1 0 disable t1 count 1 enable t1 count tin modes 00 external clock input 01 gate input 10 trigger input (non-retriggerable) 11 trigger input (retriggerable) tout modes 00 not used 01 t0 out 10 t1 out 11 internal clock out (p36) r241 tmr d7 d6 d5 d4 d3 d2 d1 d0 t1 low byte initial value (when written) t1 low byte current value (when read) r242 t1 figure 70. prescaler 1 register (f3h: write-only) figure 71. counter/timer 0 register (f4h: read/write) figure 72. prescaler 0 register (f5h: write-only) d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 t1 single pass 1 t1 modulo n clock source 1 t1internal 0 t1external timing input (tin) mode prescaler modulo (range: 1-64 decimal 01-00 hex) r243 pre1 d7 d6 d5 d4 d3 d2 d1 d0 t0 low byte initial value (when written) t0 low byte current value (when read) r244 t0 d7 d6 d5 d4 d3 d2 d1 d0 count mode 0 t1 single pass 1 t1 modulo n clock source 1 t1internal 0 t1external timing input (tin) mode prescaler modulo (range: 1-64 decimal 01-00 hex) r243 pre1
z89175/z89176 voice processing controllers zilog 64 p r e l i m i n a r y ds97tad0100 z8 control registers (continued) figure 73. port 2 mode register (f6h: write-only) figure 74. port 3 mode register (f7h: write-only) d7 d6 d5 d4 d3 d2 d1 d0 p20 - p27 i/o definition 0 defines bit as output 1 defines bit as input * r246 p2m * default setting after reset * default setting after reset d7 d6 d5 d4 d3 d2 d1 d0 r247 p3m 0 port 2 pull-ups open drain * 1 port 2 pull-ups active 0 p31, p32 digital mode * 1 p31, p32 analog mode 0 p32 = input * p35 = output * 1 p32 = /dav0/rdy0 p35 = rdy0//dav0 00 p33 = input * p34 = output * 01 p33 = input p34 = /dm 10 p33 = input p34 = /dm 11 p33 = /dav1/rdy1 p34 = rdy1//dav1 0 p31 = input (tin) * p36 = output (tout) * 1 p31 = /dav2/rdy2 p36 = rdy2//dav2 0 p30 = input p37 = output reserved figure 75. port 0 mode register (f8h: write-only) figure 76. interrupt priority register (f9h: write-only) d7 d6 d5 d4 d3 d2 d1 d0 r248 p01m p00 - p03 mode 00 output 01 input * 1x a11 - a8 stack selection 0 external 1 internal * p10 - p17 mode 00 byte output 01 byte input * 10 ad7 - ad0 11 high-impedance ad7 - ad0, /as, /ds, /r//w, a11 - a8, a15 - a12, if selected p04 - p07 mode 00 output 01 input * 1x a15 - a12 external memory timing 0 normal * 1 extended * default setting after reset d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority 000 reserved 001 c > a > b 010 a > b > c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved irq3, irq5 priority (group a) 0 irq5 > irq3 1 irq3 > irq5 irq0, irq2 priority (group b) 0 irq2 > irq0 1 irq0 > irq2 irq1, irq4 priority (group c) 0 irq1 > irq4 1 irq4 > irq1 reserved r249 ipr
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 65 2 figure 77. interrupt request register (fah: read/write) figure 78. interrupt mask register (fbh: read/write) figure 79. flag register (fch: read/write) d7 d6 d5 d4 d3 d2 d1 d0 r250 irq inter edge p31 p32 = 00 p31 p32 - = 01 p31 - p32 = 10 p31 - p32 - = 11 irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = dsp irq4 = t0 irq5 = t1 d7 d6 d5 d4 d3 d2 d1 d0 1 enables ram protect 1 enables irq0-irq5 (d0 = irq0) 1 enables interrupts r251 imr d7 d6 d5 d4 d3 d2 d1 d0 r252 flags user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag figure 80. register pointer (fdh: read/write) figure 81. stack pointer high (feh: read/write) figure 82. stack pointer low (ffh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 r253 rp expanded register file bank working register group d7 d6 d5 d4 d3 d2 d1 d0 stack pointer upper byte (sp8 - sp15) r254 sph d7 d6 d5 d4 d3 d2 d1 d0 stack pointer lower byte (sp0 - sp7) r255 spl
z89175/z89176 voice processing controllers zilog 66 p r e l i m i n a r y ds97tad0100 package information figure 83. 100-pin qfp package diagram
z89175/z89176 zilog voice processing controllers ds97tad0100 p r e l i m i n a r y 67 2 figure 84. 100-pin vqfp package diagram
z89175/z89176 voice processing controllers zilog 68 p r e l i m i n a r y ds97tad0100 ordering information for fast results, contact your local zilog sales office for assistance in ordering the part(s) desired. codes packages f = quad flatpack (qfp) a = very small quad flatpack (vqfp) temperature s = 0 c to + 70 c speeds 20 = 20.48 mhz 29 = 29.49 mhz environmental c = plastic standard ?1997 by zilog, inc. all rights reserved. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of zilog, inc. the information in this document is subject to change without notice. devices sold by zilog, inc. are covered by warranty and patent indemnification provisions appearing in zilog, inc. terms and conditions of sale only. zilog, inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. zilog, inc. makes no warranty of merchantability or fitness for any purpose. zilog, inc. shall not be responsible for any errors that may appear in this document. zilog, inc. makes no commitment to update or keep current the information contained in this document. zilog? products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and zilog prior to use. life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. zilog, inc. 210 east hacienda ave. campbell, ca 95008-6600 telephone (408) 370-8000 fax 408 370-8056 internet: http://www.zilog.com z89175 (20 mhz) z89175 (29 mhz) 100-pin qfp 100-pin vqfp 100-pin qfp 100-pin vqfp z8917520fsc Z8917520ASC z8917529fsc z8917529asc z89176 (20 mhz) z89176 (29 mhz) 100-pin qfp 100-pin vqfp 100-pin qfp 100-pin vqfp z8917620fsc z8917620asc z8917629fsc z8917629asc example: z 89175 20 f s c environmental flow temperature package speed product number zilog prefix is a z89175, 20.48 mhz, qfp, 0 c to +70 c, plastic standard flow

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