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automotive power data sheet rev. 1.1, 2011-04-08 tle7184f system ic for b6 motor drives
data sheet 2 rev. 1.1, 2011-04-08 tle7184f table of contents table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 pin assignment tle7184f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 default state of inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 mosfet driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 inputs and dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 output stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 bootstrap principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 currents at sh pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 shunt signal conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 5 v low drop voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 interface, vdh switch and inh digital output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 pwm interface (ifma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.2 vdhs switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.3 digital output inhd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 8.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 description of modes, protection and diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 description of modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2 protection and diagnosis functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2.1 over temperature shut down (otsd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2.2 over temperature prewarning (otpw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2.3 analog temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2.4 vs under voltage lockout (vs_uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2.5 vdd under voltage diagnosis (vdd_uvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2.6 vdd under voltage shut down (vdd_uvsd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2.7 vreg under voltage diagnosis (vreg_uvd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2.8 vreg under voltage shut down (vreg_uvsd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2.9 iov and vdh over voltage shut do wn (iov_ovsd, vdh_ovsd) . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2.10 dead time and shoot through protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2.11 short circuit protection (scp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2.12 scdl pin open detection (scdl_open) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2.13 over current shut down (ocsd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2.14 vdd current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2.15 passive gxx clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.3 err pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table of contents
tle7184f table of contents data sheet 3 rev. 1.1, 2011-04-08 9.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
pg-vqfn-48 type package marking tle7184f pg-vqfn-48 tle7184f data sheet 4 rev. 1.1, 2011-04-08 system ic for b6 motor drives tle7184f 1overview features ? drives 6 n-channel power mosfets ? integrated 5v vreg-controller to power c ? integrated switch for vdh voltage ? separate control input for each mosfet ? adjustable dead time ? shoot through protection ? analog adjustable short circuit protection levels ? low quiescent current mode ? 1 bit diagnosis err ? over temperature shut down and analog temperature output ? over temperature pre-warning ? under voltage shut down ? adjustable over voltage shut down ? current sense opamp ? over current shut down based on current sense opamp, fixed shut down level ? 0 ?94% duty cycle at 25 khz pwm frequency ? green product (rohs compliant) ? aec qualified description the tle7184f is a system ic for brushless motor control. it incorporates a voltage supply for a c, a bridge driver for a b6 configuration, an application typical pwm interf ace and some other smaller features. target is to reduce the number of discrete components in typical bldc automotive applications and give enough flexibility for custom specific adaptations. it works with 3-phase motors and brush dc motors. its exposed pad package allows the usage even at high ambient temperatures.
tle7184f block diagram data sheet 5 rev. 1.1, 2011-04-08 2 block diagram figure 1 block diagram ____ rgs bh1 isp sh1 gh1 gl1 sh2 gh2 gl2 sh3 gh3 sl gl3 vreg vreg floating hs driver short circuit detection floating ls driver short circuit detection floating hs driver short circuit detection floating ls driver short circuit detection floating hs driver short circuit detection floating ls driver short circuit detection l e v e l s h i f t e r diagnostic logic under voltage over voltage overtemperature short circuit reset over current ____ err gnd iso agnd il1 ___ ih1 il2 ___ ih2 il3 ___ ih3 input control shoot through protection dead time isn scdl gnd bh2 bh3 ___ inh ____ inhd vs 5v voltage regulator vdd dt interface ifuc ifma switch octh vdh vdhs temp iov
data sheet 6 rev. 1.1, 2011-04-08 tle7184f pin configuration 3 pin configuration 3.1 pin assignment tle7184f figure 2 pin configuration 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 gnd isp iso bh2 agnd isn ___ ih3 il3 ___ ih1 il2 ___ ih2 il1 sh2 sh3 gl3 bh1 ____ i nhd gh1 sh1 gl1 gl2 bh3 gh3 ifuc gh2 nc ifma vdhs vs vreg nc gnd scdl dt gnd tle 7184 f topview n. c vdd iov n. c te m p ___ inh n. c ____ err vdh gnd ____ rgs gnd sl
tle7184f pin configuration data sheet 7 rev. 1.1, 2011-04-08 3.2 pin definitions and functions pin symbol function 5 vs supply pin 7 vreg output of supply for driver ou tput stages - conn ect to capacitor 31 vdd output of 5v supply for c - connect to capacitor 2inh input pin wake up the complete system ic 47 inhd digital output 5v for inh state (high when inh is high) 4 vdhs switched output of vdh voltage; switch open in sleep mode 33 temp output pin for analog temperature signal 36 rgs reset and go-to-sleep input pin for reset of error registers, set high to avoid to go- to-sleep 38 il1 input for low side switch 1 (active high) 37 ih1 input for high side switch 1 (active low) 40 il2 input for low side switch 2 (active high) 39 ih2 input for high side switch 2 (active low) 42 il3 input for low side switch 3(active high) 41 ih3 input for high side switch 3(active low) 11 dt input pin for adjustable dead time function, connect to gnd via resistor 9 scdl analog input pin for adjustable short cir cuit detection function, connect to voltage divider 28 iov input pin for over voltage detection. 34 err open drain error output 25 vdh voltage input common drain high side for short circuit detection 24 bh1 pin for + terminal of the bootstrap capacitor of phase 1 23 gh1 output pin for gate of high side mosfet 1 22 sh1 pin for source connection of high side mosfet 1 21 gl1 output pin for gate of low side mosfet 1 20 bh2 pin for + terminal of the bootstrap capacitor of phase 2 19 gh2 output pin for gate of high side mosfet 2 18 sh2 pin for source connection of high side mosfet 2 17 gl2 output pin for gate of low side mosfet 2 16 bh3 pin for + terminal of the bootstrap capacitor of phase 3 15 gh3 output pin for gate of high side mosfet 3 14 sh3 pin for source connection of high side mosfet 3 13 gl3 output pin for gate of low side mosfet 3 10 sl pin for common source connection of low side mosfets 44 isn input for opamp - terminal 45 isp input for opamp + terminal 46 iso output of opamp 43 agnd analog gnd for opamp and analog temperature output 3 ifma interface to master ecu (used for wake up) 48 ifuc interface to c
data sheet 8 rev. 1.1, 2011-04-08 tle7184f pin configuration exposed pad to be connected to gnd 1 gnd ground pin 12 gnd ground pin 26 gnd ground pin 32 gnd ground pin 35 gnd ground pin 6 nc connect to gnd 8 nc connect to gnd 27 nc connect to gnd 29 nc connect to gnd 30 nc connect to gnd pin symbol function
tle7184f general product characteristics data sheet 9 rev. 1.1, 2011-04-08 4 general product characteristics 4.1 absolute maximum ratings absolute maximum ratings 1) t j = -40 c to +150 c ; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max. voltages 4.1.1 voltage range at vs, ifma, inh , iov v vs1 -0.3 45 v ? 4.1.2 voltage range at ifma, inh v ifma -6.0 45 v r >= 10k 4.1.3 voltage range at vs v vs2 -3.0 45 v r vs >= 4.7 ; 60s, 5x; 4.1.4 voltage range at vs v vs3 -3.0 45 v r vs >= 2.0 ; ; 200ms, 5x; 4.1.5 voltage range at vreg output v vreg -0.3 15 v 4.1.6 voltage range at vdh, vdhs v vdhx -0.3 55 v ? 4.1.7 voltage range at vdh v vdh1 -3.0 55 v with r vdh >=10 ; 60s, 5x; t j <=150c 4.1.8 voltage range at ihx , ilx, rgs , err , ifuc, temp, dt, vdd, iso, inhd , scdl, v dp -0.3 6 v ? 4.1.9 voltage range at isp, isn v opi -5.0 5.0 v ? 4.1.10 voltage difference between isp and isn v opd -5.0 5.0 v 4.1.11 voltage range at bhx v bh -0.3 55 v ? 4.1.12 voltage range at ghx v gh -0.3 55 v ? 4.1.13 voltage range at ghx v ghp -7.0 55 v t p < 1s; f =50khz 4.1.14 voltage range at shx v sh -2.0 45 v ? 4.1.15 voltage range at shx v shp -7.0 45 v t p < 1s; f =50khz 4.1.16 voltage range at glx v gl -0.3 18 v ? 4.1.17 voltage range at glx v glp -7.0 18 v t p < 0.5s; f =50khz 4.1.18 voltage range at sl v sl -0.3 5.0 v ? 4.1.19 voltage range at sl v slp -7.0 5.0 v t p < 0.5s; f =50khz 4.1.20 voltage difference gxx-sxx v gs -0.3 15 v ? 4.1.21 voltage difference bhx-shx v bs -0.3 15 v ? 4.1.22 minimum boot strap capacitor c bs c bs 330 ? nf -10% tolerance allowed 4.1.23 minimum buffer capacitor c vreg c vreg 1?f temperatures 4.1.24 junction temperature t j -40 150 c? 4.1.25 storage temperature t stg -55 150 c?
data sheet 10 rev. 1.1, 2011-04-08 tle7184f general product characteristics note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 4.2 functional range the limitations in the pwm frequency ar e given by thermal constraints and limitations in the duty cycle (charging time of bootstrap capacitor). all maximum ratings have to be considered all basic functions will work between t j =150c and over temperature shut do wn. in this temperature range, the parameters might leave the specified range. note: within the functional range the ic operates as de scribed in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 4.1.26 case temperature 2) t case ?145c? esd susceptibility 4.1.27 esd resistivity 3) v esd -2 +2 kv ? 4.1.28 cdm v cdm ?500v? 1) not subject to production test, specified by design. 2) calculation based on tjmax, rthjc and the assumption of 1w power dissipation 3) esd susceptibility hbm according to eia/jesd 22-a 114b pos. parameter symbol limit values unit conditions min. max. 4.2.1 supply voltage at vs v vs 6.0 45 v below 7v reduced functionality 1) 2) 1) mos driver output deactivated and error pin set to low if vreg is lower uvvr 2) mos driver output stage will operate at vs=6.7v with 5ma load current at vreg 4.2.2 quiescent current ( i vs + i vdh + i ifma ) i q ?50a v s <16v; sleep mode v vs = v vdh = v ifma 4.2.3 supply current at vs (device enabled) i vs(0) ?19ma v s =8...18v; no load 3) ; f pwm =25khz; 3) no load at vdd, err, iso, ifc, vdhs, gxx, temp, dt 4.2.4 duty cycle hs d hs 094% f pwm =25khz; continuous operation 4.2.5 duty cycle ls d ls 0100% 4.2.6 junction temperature t j -40 150 c ? absolute maximum ratings (cont?d) 1) t j = -40 c to +150 c ; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max.
tle7184f general product characteristics data sheet 11 rev. 1.1, 2011-04-08 4.3 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . 4.4 default state of inputs pos. parameter symbol limit values unit conditions min. typ. max. 4.3.1 junction to case 1) 1) not subject to production test, specified by design. r thjc ??5k/w? 4.3.2 junction to ambient 1) r thja ?29?k/w 2) 2) specified r thja value is according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm boar d with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. table 1 default state of inputs characteristic state remark default state of ilx (if ilx left open -pull down) low low side mosfets off default state of ihx (if ihx left open - pull up) high high side mosfets off default state of rgs (if rgs left open - pull down) low error signal is reset and the tle7184f goes to sleep default state of inh (if inh left open - pull down) low no wake up by inh default state of scdl (if scdl left open - pull up) high error signal is set; all mosfets switched off default state of ifma (if ifma left open - pull up) 1) 1) external capacitance < 25pf high no wake up by ifma default state of iov (if iov left open - pull down) low no over voltage detection by iov default state of dt (if dt left open) max. dead time max. dead time
data sheet 12 rev. 1.1, 2011-04-08 tle7184f mosfet driver 5 mosfet driver 5.1 inputs and dead time there are 6 independent control inputs to control the 6 mo sfets individually. however, the control inputs for the high side mosfets ihx are inverted. hence, the control inputs for high side ihx and low side mosfets ilx of the same half bridge can be tight together to control one half bridge by one control signal. to avoid shoot through currents within the half bridges, a dead time is provided by the tle7184f. for more details about the dead time please see chapter 9.2.10 5.2 output stages the 3 low side and 3 high side powerful push-pull output stages of t he tle7184f are all floating blocks. all 6 output stages have the same output power and than ks to the bootstrap principle used, all mosfets can be switched up to high frequencies. each output stage has its own short circuit detection bl ock. for more details about short circuit detection see chapter 9.2.11 . 1) figure 3 block diagram of driver stages including short circuit detection 1) the high side outputs are not designed to be used for low side mosfets; the low side outputs are not designed to be used for high side mosfets ghx shx vdh v scp + - level shifter floating hs driver 3x glx sl v scp + - level shifter floating ls driver 3x vreg voltage regulator bhx vreg ___ inh vs error logic reset power on reset ____ err short ci rcui t fi l ter scd scd scd input logic shoot through protection dead time lock / unlock ___ ih1 il1 ___ ih2 il2 ___ ih3 il3 on / off on / off gnd dt short circuit detection level ____ rgs scdl vdh vreg blanking
tle7184f mosfet driver data sheet 13 rev. 1.1, 2011-04-08 5.3 bootstrap principle the tle7184f provides a bootstrap based supply for its high side output stages. the benefit of this principle is a fast switching of the high side switches - supporting active freewheeling in high side. the bootstrap capacitors are charged by switching on th e external low side mosfet s connecting the bootstrap capacitor to gnd. under this condition the bootstrap capacitor will be charged from th e vreg capacito r. if the low side mosfet is switched off and the high side mo sfet is switched on, the boot strap capacitor will float together with the shx voltage to the supply voltage of the bridge. un der this condition the supply current of the high side output stage will discharge the bootstrap capacitor. this cu rrent is specified. the size of the capa citor together with this current will determine how long the high side mosfet can be kept on without re charging the bootstrap capacitor. when all external mosfets are switched off, the shx voltage can be undefined. under this condition, the bootstrap capacitors can be discha rged, dependent on the shx voltage. 5.4 currents at sh pins the currents at the sh pins can be used for diagnostic pu rposes to check the health state of the power stage. the simplified structure related to the sh currents the tle7184f is described by figure 4 . figure 4 block diagram of shx pin configuration 5.5 electrical characteristics electrical characteristics mosfet drivers v s = 7.0 to 33 v , t j = -40 c to +150 c all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) pos. parameter symbol limit values unit conditions min. typ. max. inputs 5.5.1 low level input voltage of ilx; ihx v i_ll ??1.6v? 5.5.2 high level input voltage of ilx; ihx v i_hl 2.8??v? 5.5.3 input hysteresis of ihx ; ilx 2) d vi 100??mv? 5.5.4 ihx pull-up resistors to vdd r ih 28.5 ? 76.5 k ? 5.5.5 ilx pull-down resistors to gnd r il 178.5 ? 564 k ? vdh shx i bsh sl r shgn bhx 40a 80k
data sheet 14 rev. 1.1, 2011-04-08 tle7184f mosfet driver mosfet driver output 5.5.6 output sour ce resistance r sou 2?13.5 i load =20ma 5.5.7 output sink resistance r sink 2?9 i load =20ma 5.5.8 high level output voltage gxx vs. sxx v gxx1 ?1114v13,5v <=v vs <=45v 3) , v iov <= v oviov , v vdh <= v ovvdh i load =37,5ma 5.5.9 high level output voltage ghx vs. shx 2) v gxx2 6??v v vs =8v, c load =20nf, dc=95%; f pwm =20khz 5.5.10 high level output voltage ghx vs. shx 2)4) v gxx3 6 + v diode ??v v vs =8v, c load =20nf, dc=95%; f pwm =20khz; passive freewheeling 5.5.11 high level output voltage glx vs. gnd v gxx4 6.7??v v vs =8v, c load =20nf, dc=95%; f pwm =20khz; 5.5.12 rise time t j = -40c t j = 150c t rise 100 150 ? ? 230 350 ns c load =11nf; r load =1 v vs =7v 20-80% 5.5.13 fall time t j = -40c t j = 150c t fall 80 150 ? ? 210 290 ns 5.5.14 high level output voltage (in passive clamping) v guv ? ? 1.2 v sleep mode or vs_uvlo 2) 5) 5.5.15 pull-down resistor at bhx to gnd r bhuv ??80k 5.5.16 pull-down resistor at vreg to gnd r vruv ??30k 5.5.17 bias current into bhx i bh ??150a v bhx - v shx =5...13v; no switching 5.5.18 current between bhx and shx i bsh 15 40 60 a v bhx - v shx =5...13v; v shx = gnd 5.5.19 resistor between shx and gnd r shgn 48 80 112 k 5.5.20 bias current out of sl i sl ? ? 2 ma 0v<=vsh<=vs+1 v; no switching; v cbs >5v electrical characteristics mosfet drivers v s = 7.0 to 33 v , t j = -40 c to +150 c all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) pos. parameter symbol limit values unit conditions min. typ. max.
tle7184f mosfet driver data sheet 15 rev. 1.1, 2011-04-08 5.5.21 input propagation time (low on) t p(iln) 50 ? 200 ns c load =11nf; r load =1 5.5.22 input propagation time (low off) t p(ilf) 50 ? 200 ns 5.5.23 input propagation time (high on) t p(ihn) 50 ? 200 ns 5.5.24 input propagation time (high off) t p(ihf) 50 ? 200 ns 5.5.25 absolute input propagation time difference between above propagation times t p(diff) ??100ns vreg 5.5.26 vreg output voltage v vreg 11 12.5 14 v v vs >= 13,5v; i load =37,5ma 5.5.27 vreg over current limitation i vregocl 100 ? 500 ma no activation of error; v vreg > v vrsd 5.5.28 voltage drop between vs and vreg v vsvreg ??0.5v v vs >= 7v; i load =37,5ma; ron operation 1) r load and c load in series 2) not subject to production test; specified by design 3) values above 33v not subjected to production test; specified by design 4) v diode is the bulk diode of the external low side mosfet 5) see chapter 9.2.15 electrical characteristics mosfet drivers v s = 7.0 to 33 v , t j = -40 c to +150 c all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) pos. parameter symbol limit values unit conditions min. typ. max.
data sheet 16 rev. 1.1, 2011-04-08 tle7184f shunt signal conditioning 6 shunt signal conditioning the tle7184f incorporates a fast and precise operatio nal amplifier for conditioning and amplification of the current sense shunt signal. the gain of the opamp is adju stable by external resistors within a range higher than 5. the usage of higher gains in the application might be limited by required settling time and band width. it is recommended to apply a small offset to the opamp, to avoid operation close to the lower rail at low currents. the output of the opamp iso is not short-circuit proof. in addition to the integrated operational amplifier, the tle7184f incorporates a comparator to detect over current situations. the output voltage v iso is compared to a reference voltage v octh close to the upper rail of the 5v opamp supply (vdd). if v iso reaches this level an error is set. figure 5 shunt signal conditioning block diagram and over current limitation over current shut down see chapter 9.2.13 . 6.1 electrical characteristics electrical characteristics - current sense signal conditioning v s = 6.0 to 33 v, t j = -40 c to +150 c, gain = 5 to 75 , all voltages with respect to gr ound, positive current flowing into pin (unless otherwise specified) 1) pos. parameter symbol limit values unit conditions min. typ. max. 6.1.1 series resistors r s 100 500 1000 ? 6.1.2 feedback resistor r fb 2000 7500 ? ? 6.1.3 resistor ratio (gain ratio), max. gain limited by settling time r fb/rs 5??? r l >3k 6.1.4 input differential voltage (isp - isn) v idr -800 ? 800 mv ? 6.1.5 input voltage (both inputs - gnd) (isp - gnd) or (isn -gnd) v ll -800 ? 2000 mv ? 6.1.6 input offset voltage of the i-dc link opamp, including temperature drift v io ??+/-2mv r s =500 ; v cm =0v; v iso =1.65v; 6.1.7 input bias cu rrent (isn,isp to gnd) i ib -300 ? ? a v cm =0v; v iso =open external r s1 r s2 asic internal - + v octh err r fb2 r fb1 r shunt v dd r fb3 isn isp iso v dd - + r fb2 r fb3 = r fb1 c fc < 1 mhz 330pf
tle7184f shunt signal conditioning data sheet 17 rev. 1.1, 2011-04-08 6.1.8 high level output voltage of iso v oh v vdd - 0.2 ? v vdd v i o =-3ma 6.1.9 low level output voltage of iso v ol -0.1 ? 0.2 v i o =3ma 6.1.10 guaranteed output current capability i goc 5??ma? 6.1.11 differential input resistance 2) r i 100 ? ? k ? 6.1.12 common mode input capacitance 2) c cm ? ? 10 pf 10khz 6.1.13 common mode rejection ratio at dc cmrr = 20*log((vout_diff/vin_diff) * (vin_cm/vout_cm)) c mrr 80 100 ? db ? 6.1.14 common mode suppression 3)2) with cms = 20*log(vout_cm/vin_cm) freq =100khz freq = 1mhz freq = 10mhz c ms ? 62 43 33 ?db v in =360mv* sin(2* *freq*t); r s =500 ; r fb =7500 6.1.15 slew rate d v/dt ?10?v/sgain>= 5; r l =1.0k ; c l =500pf 6.1.16 large signal open loop voltage gain (dc) a ol 80 100 ? db ? 6.1.17 unity gain bandwidth g bw 10 20 ? mhz r l =1k ; c l =100pf 6.1.18 phase margin 2) f m ? 50 ? gain>= 5; r l =1k ; c l =100pf 6.1.19 gain margin 2) a m ?12?db r l =1k ; c l =100pf 6.1.20 bandwidth b wg 1.6 ? ? mhz gain=15; r l =1k ; c l =500pf; r s =500 6.1.21 output settle time to 98% r fb / r s =15 r fb / r s =75 t set1 ? ? 1 4.6 1.8 8 s r l =1k ; c l =500pf; 0.3< v iso < vdd-0.3v; r s =500 1) a minimum capacitance of 100pf is needed at the ou tput of the opamp (parasitic or real capacitor); r l is the total load resistance including the feedback network; in the application it is not recommended to apply a resistor from the output iso to gnd directly in addition to the feedback network. 2) not subject to production test; specified by design 3) without considering any offsets such as in put offset voltage, internal mismatch and assuming no tolerance error in external resistors. electrical characteristics - current sense signal conditioning (cont?d) v s = 6.0 to 33 v, t j = -40 c to +150 c, gain = 5 to 75 , all voltages with respect to gr ound, positive current flowing into pin (unless otherwise specified) 1) pos. parameter symbol limit values unit conditions min. typ. max.
data sheet 18 rev. 1.1, 2011-04-08 tle7184f 5 v low drop voltage regulator 7 5 v low drop voltage regulator the tle7184f incorporates a 5v ldo for c supply. the vo ltage regulator is protected against over temperature by the central temperature sensor (see chapter 9.2.1 and chapter 9.2.2 ). it has an integrat ed current limitation and under voltage detection. parameters for under voltage detection see chapter 9.2.5 . figure 6 block diagram of 5v ldo 7.1 electrical characteristics electrical characteristics - current sense signal conditioning v s = 6.0 to 45 v, t j = -40 c to +150 c, all voltages with respec t to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. 7.1.1 output voltage v dd1 4.85 ? 5.25 v 2ma <=i load <=70ma; c load = 1...22uf 1) 1) ceramic c with 100nf with esr<0.1 in parallel 7.1.2 output voltage v dd2 4.90 ? 5.20 v 5ma <= i load <=25ma; c load = 1...22uf 1) 7.1.3 ldo over current limitation i ocl 130 ? 270 ma no activation of error by current limitation 7.1.4 load regulation d vdd ?50100mv l oad step 0...20ma; c vdd =1uf 7.1.5 power supply ripple rejection 2) p srr 50 ? ? db 100hz sine wave; 0.5v pp v vs >=7v 7.1.6 power supply ripple rejection 2) p srr ? 31 ? db 100hz sine wave; 0.5v pp 6v<= v vs <7v 5v ldo vdd error logic and wake-up logic temperature sensor vs
tle7184f 5 v low drop voltage regulator data sheet 19 rev. 1.1, 2011-04-08 figure 7 typ. vdd output voltage vs. load current 2) not subject to production test; specified by design 4,950 5,000 5,050 5,100 5,150 0,000 0,010 0,020 0,030 0,040 0,050 0,060 0,070 0,080 i_vdd [a] u_vdd [v] 25c -40c +150c
data sheet 20 rev. 1.1, 2011-04-08 tle7184f 5 v low drop voltage regulator figure 8 typ. vdd output voltage vs. supply voltage 5,03 5,035 5,04 5,045 5,05 5,055 5,06 5,065 5,07 0 5 10 15 20 25 30 35 40 45 50 u_vs [v] u_vdd [v] 25c
tle7184f interface, vdh switch and inh digital output data sheet 21 rev. 1.1, 2011-04-08 8 interface, vdh switch and inh digital output 8.1 pwm interface (ifma) the tle7184f has an integrated interface supporting t he typical pwm interface between a remote master ecu and the c. the link to the external master ecu is a single wire communication based on the battery voltage and running typ. with about 10 to 400 hz. the information is encoded in the duty cycle of the signal. this communication line requires a signal co nditioning to connect to the on board c. the integrated circuit supports the incoming data path. the outgoing data path is formed by external components figure 9 structure pwm interface the integrated circuitry is described in figure 9 . the main task of this interface is level shifting and protection of the c. the ifuc signal is following the ifma signal, passin g the duty cycle information from ifma to the ifuc. the c port is used as input and is listening to the ifuc signal. the voltage at ifma is monitored. if ifma is low the ifuc open drain output is switched on - forcing the ifuc signal to low. if ifma is high, the ifuc open drain output is deactivated and the ifuc signal is pulled to high by the internal pull- up resistor. the ifma input is used as well for wake-up. see chapter 9.1 influence of serial resistor at ifma pin as shown in figure 9 a 10k resistor r1 is recommended to protect the ifma pin against negative voltage levels coming from the interface signal. the integrated pull do wn and pull up resistors at the ifma pin form a voltage divider together with the resistor r1. th is will influence the result ing switching level of th e ifma interface in the application compared to the levels specified directly at the ifma pin. in this datasheet an additional parameter is provided to calculate the influence of t he 10k resistor. the specified ifma input current divided by vs allows to calculate the drop over r1 with the following formula: uc interface_uc gnd tle 7184 f kl 30 pull up interface ecu t3 t1 vdd vcc ifuc ifma t2 wake up r1 10k vs vs 700k 340k 1 * * 1 _ _ _ r v v i r over drop voltage vs vs ifma =
data sheet 22 rev. 1.1, 2011-04-08 tle7184f interface, vdh switch and inh digital output 8.2 vdhs switch the system ic has an integrated switch connecting the vdh pin to the vdhs pin. this allows to place an external voltage divider for vdh voltage monitoring at the vdhs pi n and to disconnect this voltage divider from vdh during sleep mode to assure low current consumption. the vd hs switch is only deactiva ted when the vdd regulator is switched off. 8.3 digital output inhd the system ic provides a digital output inhd showing the logic state of inh (e.g. kl15) after a complete wake- up of the driver (approx. 1ms). the input levels of inh for the inhd output are defined separately from the levels for wake-up. voltage levels for inh wake-up function please see chapter 9.4 section wake-up and go-to-sleep. the output stage consists of an integrated lo w side switch with a pull- up resistor to vdd. 8.4 electrical characteristics electrical characterist ics - protection and diagnostic functions v s = 6.0 to 20v, t j = -40 c to +150 c, all volt ages with respect to ground, po sitive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. interface - static parameters 8.4.1 ifma input voltage high level (for ifc high) v imhl 59??%of v vs ; ic not in sleep mode 8.4.2 ifma input voltage low level (for ifc low) v imll ??46%of v vs ; ic not in sleep mode; 8.4.3 ifma input hysteresis (for ifc) v imhy 0.5?9%of v vs ; ic not in sleep mode 8.4.4 ifma wake up voltage high level = v s - v ifma v imwh 2 ? 4 v valid in sleep mode 8.4.5 ifma low time to guarantee wake- up t iflow 100??s v vs =7...20v 8.4.6 ifma internal pull-up resistor to v s r imu 210 340 495 k ? 8.4.7 ifma internal pull-down resistor to gnd r imd 420 700 980 k not active in sleep mode 8.4.8 ifma input current related to vs v ifma = 59% of v vs v ifma = 46% of v vs i ifma / v vs -2.0 -3.0 ? ? +2.0 +1.0 a/v ? 8.4.9 ifc output low voltage v iull ? ? 0.5 v no external load 8.4.10 ifc internal pull-up resistor to v dd r iu 8.5 ? 23 k ? interface - dyna mic parameters 8.4.11 ifc duty cycle d iu 0?100%? 8.4.12 propagation time rising edge ifc t pre ? ? 6 s including rise time to 80% of v vdd ; c load =100pf 8.4.13 propagation time falling edge ifc t pfe ? ? 5 s including fall time to 20% of v vdd ; c load =100pf
tle7184f interface, vdh switch and inh digital output data sheet 23 rev. 1.1, 2011-04-08 8.4.14 deviation betwe en rising and falling ifc t pd ??4s c load =100pf vdh switch 8.4.15 ron vdh switch r vdh ??150 load current = 1ma inhd digital output 8.4.16 low level input voltage inh (for inhd =low) v inhdl ??1.5v? 8.4.17 high level input voltage inh (for inhd =high) v inhdh 2.2??v? 8.4.18 input hysteresis of inh for inhd 1) d vinhd 100??mv? 8.4.19 inhd low level output voltage v inhd ? ? 0.5 v no external load 8.4.20 inhd internal pull-up resistor to v dd r inhd 42.5 ? 115 k ? 1) not subject to production test; specified by design electrical characterist ics - protection and diagnostic functions (cont?d) v s = 6.0 to 20v, t j = -40 c to +150 c, all volt ages with respect to ground, po sitive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max.
data sheet 24 rev. 1.1, 2011-04-08 tle7184f description of modes, protection and diagnostic functions 9 description of modes, protecti on and diagnostic functions 9.1 description of modes the operation of tle7184f can be described by different operation modes figure 10 state diagram tle7184f sleep mode - low quiescent current - all supplies switched off wake-up mode - ramp-up of int5v, vreg and vdd error mode - latched error is reported - mosfets switched -off - vreg and vdd on normal mode without error conditions - no error is reported - driver stages are active normal mode with ot-prewarning - latched error is reported - driver stages are active vreg shut-down mode - latched error is reported - mosfets switched -off -vreg off deadlock mode *2) - vreg and vdd off - latched error is reported - mosfets switched-off - only 5vint supply is on /inh = high ?or? ifma= low wake-up time expired reset of error /rgs = low for t > t sleep vdd <= v ddsleep vdd_uvsd ?or? (vreg_uvsd ?and? otpw) vreg_uvsd (no otpw) reset by /rgs ?and? otpw vdd_uvsd ?or? (vreg_uvsd ?and? otpw) vreg_uvsd (no otpw) otpw vdd_uvsd ?or? vreg_uvsd reset of otpw error error condition occures * 1) error condition occures *1) /rgs = low for t > t sl eep error conditions tle 7184f and used abbreviations : vreg under voltage diagnosis ( vreg_uvd ) vdd under voltage diagnosis ( vdd_uvd ) over current shut down ( ocsd ) vdh over voltage shut down ( vdh_ovsd ) iov over voltage shut down ( iov_ovsd )) short circuit detection ( scd ) scdl pin open detection ( scdlpod ) over temperature pre-warning ( otpw ) over temperature shut down ( otsd ) vdd under voltage shut down ( vdd_uvsd ) vreg under voltage shut down ( vreg_uvsd ) vs under voltage lockout ( vs_uvlo ) *1) error conditions: vreg_uvd, vdd_uvd, ocsd, vdh_ovsd, iov_ovsd , scd, scdlpod *2) only way to leave this mode is vs_uvlo vs under voltage lockout ( vs_uvlo ) leads from every mode into the sleep mode over temperature shut down ( otsd ) leads from every mode except dead lock mode into the sleep mode otpw ?or? vdd_uvsd go-to-sleep mode - vdd andvreg are switched off - latched error is reported
tle7184f description of modes, protection and diagnostic functions data sheet 25 rev. 1.1, 2011-04-08 sleep mode: the sleep mode is entered if the device is in the go-to-sleep mode and the vdd voltage is lower than v ddsleep . the complete chip is deactivated beside the wake-up fu nction (see wake-up mode). this mode is designed for lowest current consumption from the po wer net of the car. the passive clamping is active. for details see the description of pass ive clamping, see chapter 9.2.15 . the only way to leave the sleep mode is to go to the wake-up mode. wake-up mode: the tle7184f wakes up if inh (=kl15) is high or if ifma is low and v vs is higher than v vslo . in this mode all supplies are ramping up. as soon as the internal 5v is available, a so called wake-up timer starts to run. if the ic reaches this state, the wake-up will continue ev en if the wake-up signals at inh or ifma disappear. the pwm interface (ifma) is active as soon as the vdd volta ge is sufficiently high. during this time it is expected that the supplies are powered up and the c sets the rgs to high. all external mosfets are switched off actively or passively. when the wake up timer is expired the ic goes into the error mode. in this mode all errors will be ignored beside over temperat ure shut down or v s under voltage lockout. error mode the error mode can be reached in 3 different ways: 1. the device is in wake-up mode and the wake up timer expires 2. the device is in normal mode and one or more of the following errors occur: vreg under voltage shut down, vdd under voltage shut down, over current shut down, vdh over voltage shut do wn, iov over voltage shut down, short circu it detection or s cdl open detection. 3. the device is in normal mode with ot-prewarning and one or more of the following errors occur: vreg under voltage shut down, vdd under voltage shut down, over current shut down, vdh over voltage shut down, iov over voltage shut down, short circu it detection or scdl open detection. in this mode an error is set at the error pin and all external mosfets ar e actively switched off as long as the bootstrap voltages allows it. the interface is active. vdhs switch is on and the current sense functions are working. vdd and vreg are active. passive clamping is not active. the error mode can be left in the following ways: 1. if no error is present, the ic can be sent to normal mode by a reset with the rgs pin. 2. if a vreg under voltage shut down occurs and no ov er temperature prewarning is present, the device will go to vreg shut-down mode. 3. if vdd under voltage shut down occurs or a vreg under voltage shut down together with a over temperature prewarning occurs, the device will go into deadlock mode. 4. if over temperature prewarning is present, the ic can be sent to normal mode with ot-prewarning by a reset with the rgs pin. normal mode the normal mode can be reached in two different ways: 1. the device is in error mode, no error is pr esent and a reset is performed by the rgs pin. 2. the device is in normal mode with ot-prewarning, the chip temperature is below the ot-prewarning level and a reset is performed by the rgs pin. in the normal mode all functions are active and available wi th the regular limitations of the bootstrap principle. the gate drive output stages can be controlled with the input pins. the normal mode can be left in 5 ways: 1. the devices goes to the go-to-sleep mode by setting rgs to low for a time longer than t sleep . 2. if a over temperature prewarning occurs the device goes into the normal mode with ot-prewarning.
data sheet 26 rev. 1.1, 2011-04-08 tle7184f description of modes, protection and diagnostic functions 3. if a vreg under voltage shut down occurs and no ov er temperature prewarning is present, the device will go to vreg shut-down mode. 4. if vdd under voltage shut down occurs or a vreg under voltage shut down together with a over temperature prewarning occurs, the device will go into deadlock mode. 5. if one or more of the following errors occur, the device goes to the error mode: vreg under voltage shut down, vdd under voltage shut down, over current sh ut down, vdh over voltag e shut down, iov over voltage shut down, short circuit detection or scdl open detection. go-to-sleep mode the go-to-sleep mode can be reached in 2 different ways: 1. the device is in normal mode and rgs is set to low for a time longer than t sleep . 2. the device is in vreg shut-down mode and rgs is set to low for a time longer than t sleep . in this mode all external mo sfets are actively or passively switched o ff. an error is set and is shown as long as vdd is sufficient high. in this mode vdd and vreg is switched off. as soon as vdd voltage reaches the v vddsleep level the ic goes into the sleep mode. normal mode with over temperature prewarning this mode can be reached in 2 different ways: 1. the device is in error mode, the chip temperature is above the prewarning level while a reset is performed by the rgs pin. 2. the device is in normal mode and the chip temperature increases above the prewarning level. in this mode all functions are active and available. th e gate drive output stages can be controlled with the input pins with the regular limitations of the bootstrap principle. the err pin is set to low and this error is latched. there are 3 possi bilities to leave this mode: 1. this mode can be left into the normal mode by applying a reset at rgs if the temperature has dropped below the over temperature pre-warning level. 2. the device goes into error mode if one of the follo wing errors occurs: vreg un der voltage shut down, vdd under voltage shut down, over current shut down, vd h over voltage shut down, iov over voltage shut down, short circuit detectio n or scdl open detection. 3. the device goes into deadlock mode if either a vreg under voltage shut down or a vdd under voltage shut down occurs. if the temperature is still in the pre-warning range and rgs is low, the err pin gets high only during the time were rgs is low and the ic stays in the ?normal mode with over temperature prewarning?. deadlock mode this mode is intended to prevent the ic for long time toggling in over temperature if a short is present at the vdd pin. there are 4 ways to enter this mode: 1. the ic is in error mode and a vdd under voltage s hut down occurs or a vreg under voltage shut down together with a over temperature prewarning occurs 2. the ic is in normal mode with over temperature prew arning and a vdd under voltage shut down or a vreg under voltage shut down occurs. 3. the ic is in normal mode and a vdd under voltage sh ut down occurs or a vreg under voltage shut down together with a over temperature prewarning occurs. 4. the ic is in vreg shut down mode and a vdd under voltage shut down or a over temperature prewarning occurs.
tle7184f description of modes, protection and diagnostic functions data sheet 27 rev. 1.1, 2011-04-08 in this mode the vdd and vreg regu lators are switched off. the gates of the external mosfets are passively clamped. the vdhs switch is deactivated. the ic will not react to ifma or inh signals. even a over temp erature shut down detect ion will have no influence. the internal logic is supplied and prevents the ic from going into ?go to sleep mode?. the only way to leave this state is that vs is lower than v vslo , means a vs under voltage lockout occurs. in this case the ic goes to sleep mode. vreg shut down mode this mode is intended to prevent the ic from long time toggling in over temperature if a short is present at the vreg pin. there are 2 ways to enter this mode: 1. the ic is in the error mode and a vreg under voltage shut-down occurs without an over temperature prewarning. 2. the ic is in the normal mode and a vreg under vo ltage shut-down occurs witho ut an over temperature prewarning. in this mode vreg is switch ed off, but vdd is still present. the vdhs s witch is still active and the pwm interface (ifma) is working. the ic will not react to ifma or inh signals. in this situation the c is still able to provide diagnostic in formation by the interface. it can prevent the ic from go- to-sleep mode and can avoid unintended toggling as long there is no over temperature shut down. this state can be left by 2 ways: 1. the c has to set rgs to low for a time longer than t sleep . in this case the ic goes to sleep mode. 2. if a vdd under voltage shut down or an over temperature pr ewarning occurs the ic will go into the deadlock mode. 9.2 protection and diagnosis functions 9.2.1 over temperatur e shut down (otsd) if the junction temperature is exceeding the over temperat ure shut down level an error signal is set. the driver ic will pull down the gate-source voltage of all external mosfets, deactivate the vdd and vreg supply and go directly into the sleep mode. in the sleep mode the regular wake-up conditions will be used. over temperat ure cycling is possible and will lead to accelerated aging of the ic. in deadlock mode an over temperature shut down is ignored. 9.2.2 over temperatur e prewarning (otpw) the ic provides a digital over temperature pre-warning. if no other errors are present, the ic goes into ?normal mode with over temperature prewarning?. this function is not available in deadlock mode. 9.2.3 analog temperature monitoring the temp output of the tle7184f provides an analog volt age signal proportional to the chip temperature. this function is not available in deadlock mode.
data sheet 28 rev. 1.1, 2011-04-08 tle7184f description of modes, protection and diagnostic functions 9.2.4 vs under voltag e lockout (vs_uvlo) the tle7184f has an integrated vs under voltage lockout to assure that the behavior of the complete ic is predictable in all supply voltage ranges. if the supply voltage at vs reaches the under voltage shut down level v vslo for a minimum specified filter time the ic goes into go-to-sleep mode and finally into sleep mode. 9.2.5 vdd under voltag e diagnosis (vdd_uvd) the tle7184f has an integrated vdd under voltage diagnos is to assure that the behavior of the bridge driver output stages is predictable in all supply voltage ranges. if the voltage at vdd reaches th e under voltage diagnosis level v uvvdd for a minimum specified filter time, an error is set and the ic goes into error mode. figure 11 timing of vdd under voltage diagnosis 9.2.6 vdd under voltage shut down (vdd_uvsd) the tle7184f has an integrated vdd under voltage shut down to avoid operation with vdd shorted to gnd. if the supply voltage at vdd reaches the under voltage shut down level v vddsleep and the wake-up time is expired, vreg and vdd will be switched off a nd the ic will go to deadlock mode. 9.2.7 vreg under voltag e diagnosis (vreg_uvd) the tle7184f has an integrated vreg under voltage diag nosis to assure that the behavior of the bridge driver output stages is predictable in all supply voltage ranges. v vdd v rt err t rr vs < t rr ____ rgs
tle7184f description of modes, protection and diagnostic functions data sheet 29 rev. 1.1, 2011-04-08 if the voltage at vreg reaches the under voltage diagnosis level v uvvr for a minimum specified filter time, an error is set and the ic goes into error mode. as long as the vs under voltage lock out is not reached, the low side mosfets will st ay actively switched off. the status of the high side mosfet drivers is depende nt on the bootstrap voltage - which depends on the shx voltage. it is expected that the shx nodes will be pulled to vdh level by th e high side mosfets and this will switch off the high side mosfets passively. in this situation the short circuit detection of this out put stage is deactivated to avoid wrong error reporting. 9.2.8 vreg under voltage shut down (vreg_uvsd) the tle7184f has an integrated vreg under voltage sh ut down to avoid operation with vreg shorted to gnd. if the supply voltage at vreg reaches the under voltage shut down level v vrsd , ?and? no over temperature prewarning is set ?and? the wake up time is expired, vreg will be switched off and the ic will go to the vreg shut down mode. in this condition the c is still su pplied and can communicate vi a the pwm interface (ifma), the mosfets are switched off and an error is set. the on ly way to leave this mode is to go to ?sleep mode?. if the supply voltage at vreg reache s the under voltage shut down level v vrsd ?and? over temperature prewarning is set ?and? the wake-up time is expired, vr eg and vdd will be switched o ff and the ic will go to the ?dead lock mode?. the only way to leave this deadlock mode is to provoke a vs under voltage shut down, for example by removing the battery voltage. 9.2.9 iov and vdh over voltage s hut down (iov_ovsd, vdh_ovsd) the tle7184f has an integrated over voltage shut down to minimize the risk of destruction of the ic at high supply voltages caused by viol ation of the maximum ratings. the voltages are observed at the over voltage input pin io v and at the vdh pin. if t he voltage at the iov pin or at the vdh pin exceeds the over voltage shut down level fo r more than the specified f ilter time, the ic goes into error mode. the effective over voltage level can be adjusted by a vo ltage divider at the iov pin. this voltage devider is normally supplied by the vdhs pin. t he over voltage level at vdh is fix. 9.2.10 dead time and shoot through protection in bridge applications it has to be assured that the exte rnal high side and low side mosfets are not ?on? at the same time, connecting the battery voltage directly to gn d. the dead time generated in the tle7184f is set to a minimum value if the dt pin is connected to gnd. this function assures a minimum dead time if a common input signal for ilx and ihx is used. the dead time can be increased by connecting the dt pin via a dead time resistor r dt to gnd. larger dead time resistors result in a longer dead time. the typical dead time can be calc ulated with the following formula: please put in the r dt in k . if an exact dead time of the bridge is needed, t he use of the c pwm generation unit is recommended. in case of an open dt pin, the dead time is set to the internal maximum value. in addition to this dead time, the tle7184f provides a locking mechanism avoiding that both external mosfets of one half bridge can be switched on at the same time. this functionality is called shoot through protection. s t rdt deadtime + + = 4 4 . 2 02 . 0 081 . 0
data sheet 30 rev. 1.1, 2011-04-08 tle7184f description of modes, protection and diagnostic functions if the command to switch on both high and low side switches in the same half bridge is given at the input pins, the command will be ignored . the outputs will stay in the state like before the conflicting input. 9.2.11 short circuit protection (scp) the tle7184f provides a short circuit protection for th e external mosfets. it is monitoring the drain-source voltage of the external mosfets. (see figure 3 ) the drain-source voltage monitoring for a certain external mosfet is active as soon as the corresponding driver output stage is set to ?on? and the dead time and the blanking time is expired. the blanking time starts when the dead time is expired and assures that the switch on process of the mosfet is not taken into account. it is recommended to keep the s witching times of the mosfets below the blanking time. the short circuit detection level is adjustable in an analog ue way by the voltage setting at the scdl pin. there is a 1:1 translation between the voltage applied to the scdl pi n and the drain-source voltage limit. e.g. to trigger the scd circuit at 1 v drain-source voltage, the scdl pin must be set to 1 v as well. the drain-source voltage limit can be chosen between 0.3 ... 2 v. in the case that after the expiration of the blanking time the drain source voltage of the observed mosfet is still higher then the scdl leve l, the scd filter time t scp starts to run. a capacitor is charged with a current. if the capacitor voltage reaches a specific level (filter time t scp ), the error signal is set and the ic goes into error mode. if the scd condition is removed before the sc is detected, the capacitor is discharged with the same current. the discharging of the capacitor happens as well when the mosfet is switched off. it has to be considered that the high side and the low side outputs of on e phase are working with the same capacitor. 9.2.12 scdl pin open detection (scdl_open) for safety reasons a pull-up resistor at the scdl pin assu res that in case of an open pin the scdl voltage is pulled to a high level. in this case an error is set and the ic goes into error mode. 9.2.13 over current shut down (ocsd) the tle7184f is monitoring the output si gnal of the operational amplifier. if the output signal reaches a specified level close to the upper rail (vdd) for a specified time, the system ic detects an over current condition and sets an error signal. the driver output pulls down the gate-sou rce voltage of all external mosfets active ly and stays in the error mode. 9.2.14 vdd current limitation the tle7184f has an integrated voltage supply for an exte rnal c. the output current of the supply is limited to a specified value. this lim itation does not cause any error reportin g. in this situation a vdd under voltage detection is likely. if the current is limited for a lo nger time, the over temper ature protecti on will react. 9.2.15 passive gxx clamping if vs under voltage lock out is detected or the device is in sleep mode, a passive clamping is active as long as the voltage at vs or vdh is higher th an 3v. even below 3v it is assured that the mosfet driver stage will not switch on the mosfet actively. the passive clamping means that the bhx and the vreg pin are pulled to gnd with specified pull down resistors. together with the intrinsic diode of the push stage of the output stages which connec t the gate output to bhx respectively vreg, this assure s that the gate of the exte rnal mosfets are not floating. 9.3 err pin the tle7184f has a status pin to provide diagnostic feedback to the c. the logical output of this pin is an open drain output with integrated pu ll-down resistor to gnd (see figure 12 ).
tle7184f description of modes, protection and diagnostic functions data sheet 31 rev. 1.1, 2011-04-08 reset of error registers and disable the tle7184f can be reset by the enable pin rgs . if the rgs pin is pulled to low for a specified minimum time, the error registers are cleared. if the error is still existing when the rgs pin is pulled to low, no reset will be performed and the err pin stays low. the only exemption of this behavior is the over temperature prewarning. even if the junction temperature is exceeding the over temperature prewarning level, the error signal goes to high when rgs is pulled low. figure 13 describes the timing behavior during error reset: for more details see description of error mode and normal mode with over temperature pre-warning in chapter 9.1 . figure 12 structure of err output figure 13 enable / disable timing error logic uc interface_uc gnd internal internal 5v err gnd error occurs no driver reset t nres-min t res -mi n undefined tle 7184 f releases signal 5v 0v err 5v 0v rgs t sleep error reset normal operation sleep mode short glitches are ignored
data sheet 32 rev. 1.1, 2011-04-08 tle7184f description of modes, protection and diagnostic functions 9.4 electrical characteristics electrical characterist ics - protection and diagnostic functions v s = 7.0 to 33v, t j = -40 c to +150 c, all volt ages with respect to ground, po sitive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. dead time 9.4.1 programmable internal dead time t dt 0.095 0.29 0.85 1.2 2.1 0.14 0.42 1.21 1.88 3.62 0.18 0.55 1.55 2.6 5.1 s r dt =0 r dt =10 k r dt =47 k r dt =100 k r dt =1000 k 9.4.2 max. internal dead time t dt_max 2.0 4.0 6.0 s dt pin open 9.4.3 dead time deviation between channels d tdt -20 ? 20 % ? -15 ? 15 % r dt <=47 k 9.4.4 dead time deviation between channels lsoff -> hs on d tdth -14 ? 14 % ? -12 ? 12 % r dt <=47 k 9.4.5 dead time deviation between channels hsoff -> ls on d tdtl -14 ? 14 % ? -12 ? 12 % r dt <=47 k short circuit protection 9.4.6 short circuit protection detection level v scpdl 0.3 ? 2 v programmed by scdl pin 9.4.7 short circuit protection detection accuracy a scp -20 ? +20 % 0.3v<= v scdl <0.9v 9.4.8 short circuit protection detection accuracy a scp -10 ? +10 % 0.9v<= v scdl <=2.0v 9.4.9 filter time of short circuit protection t scp(off) 2.3 ? 4.3 s ixx static on 9.4.10 blanking time pl us filter time of short circuit detection t scptt 4 ? 8 s ixx switching ?off? to ?on? 9.4.11 internal pull-up resistor scdl to v dd r scdl 180 300 420 k ? 9.4.12 scdl open pin detection level v scpop 2.0 ? 2.5 v ? 9.4.13 filter time of scdl open pin t scpop 1?3.4s? 9.4.14 scdl open pin detection level hysteresis 2) v scoph ?0.3?v? over- and under voltage monitoring 9.4.15 over voltage shut down at iov v oviov 4.15 ? 4.4 v iov voltage increasing 9.4.16 pull down resistor at iov to gnd r iov 300 ? 700 k ? 9.4.17 over voltage shut down at vdh v ovvdh 33 ? 37 v vdh increasing 9.4.18 over voltage sh ut down filter time for iov or vdh t ov 13 ? 23 s ? 9.4.19 under voltage diagnosis at vreg v uvvr 5.5 ? 6.5 v vreg decreasing
tle7184f description of modes, protection and diagnostic functions data sheet 33 rev. 1.1, 2011-04-08 9.4.20 under voltage diagnosis filter time for vreg t uvvr 10 ? 30 s ? 9.4.21 under voltage shut down at vreg v vrsd 1.5 ? 2.3 v vreg decreasing 9.4.22 under voltage lockout at vs v vslo 4.4 5.0 5.5 v v vs decreasing 9.4.23 under voltage lockout filter time for vs t uvlo 1?3s? err pin 1) 9.4.24 err output voltage v err 4.4 ? ? v no external load 9.4.25 rise time err (20 - 80% of internal 5v) t f(err) ??3.5s c load =1nf; 9.4.26 internal pull-down resistor err to gnd r f(err) 21.2 ? 60 k ? reset and enable 9.4.27 low time of uc rgs signal without reset t nres ??0.5s? 9.4.28 low time of uc rgs pin necessary to trigger reset and to clear error registers t res 3??s? wake-up and go-to-sleep 9.4.29 low level input voltage of rgs v rgsll ??1.6v? 9.4.30 high level input voltage of rgs v rgshl 2.8??v? 9.4.31 input hysteresis of rgs 2) d rgs 100??mv? 9.4.32 rgs pull-down resistors to gnd r rgs 100 ? 210 k ? 9.4.33 low level input voltage of inh 3) for wake up v inhl ? ? 0.75 v ? 9.4.34 high level input voltage of inh 3) for wake up v inhh 2.1??v? 9.4.35 inh high time to guarantee wake- up t ihhigh 100??s? 9.4.36 inh pull-down resistors to gnd r inh 100 ? 210 k ? 9.4.37 wake up delay time t wake 9?17ms 9.4.38 rgs low time for go-to-sleep t sleep 20 ? 50 s 9.4.39 v dd voltage for changing from go-to-sleep mode to sleep mode v ddsleep 1.5 ? 2.3 v ? 9.4.40 v dd under voltage shut down v uvsdvdd 1.5 ? 2.3 v ? 1) err pin and reset & enable functional between v vs =6 ... 7v, but characteristics might be out of specified range 2) not subject to production test; specified by design 3) these levels are valid for wake up of the ic. the input levels for inh deciding the output state of inhd are shown in chapter 8.4 electrical characterist ics - protection and diagnostic functions (cont?d) v s = 7.0 to 33v, t j = -40 c to +150 c, all volt ages with respect to ground, po sitive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max.
data sheet 34 rev. 1.1, 2011-04-08 tle7184f description of modes, protection and diagnostic functions electrical characterist ics - protection and diagnostic functions v s = 6.0 to 33v, t j = -40 c to +150 c, all volt ages with respect to ground, po sitive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit conditions min. typ. max. temperature monitoring 9.4.41 over temperature shut down t j(sd) 160 170 180 c 1) ? 9.4.42 over temperature pre-warning t j(pw) 130 140 150 c 1) ? 9.4.43 difference between over temperature shut down level and over temperature pre-warning level d tj(sdpw) 20 30 40 c 1) ? 9.4.44 analog temperature output at 25c v atrt 1.32 ? 1.65 v c load <=1.5nf; t j =25c 9.4.45 analog temperature output coefficient k atrt 4.57 ? 5.20 mv/k c load <=1.5nf 1) 9.4.46 analog temperature output drift over lifetime 1) v atrtd 0?+6mv c load <=1.5nf 9.4.47 analog temperature range 1) 1) not subject to production test; specified by design t at -40 ? 175 c ? over current detection 9.4.48 over current detection level in% of v vdd v octh 92 ? 96.5 % ? 9.4.49 filter time for over current detection t oc 1.8 ? 4.2 s ? under voltage monitoring vdd 9.4.50 under voltage shut down at v dd 2) 2) for under voltage detection level during go-to-sleep see v ddsleep v uvvdd 3.7 ? 4.2 v v vdd decreasing 9.4.51 under voltage shut down filter time t uvvdd 15 ? 45 s ?
tle7184f application description data sheet 35 rev. 1.1, 2011-04-08 10 application description in the automotive sector there are more and more applic ations requiring high performance motor drives, such as hvac fans, engine cooling fans, pumps etc... in these applications synchronous and asynchronous 3-phase motors are used, combining high output performance, lo w space requirements and high reliability. figure 14 application circuit tle7184f note: this is a simplified example of an application circuit. the function must be verified in the real application sh1 v bat c br 4,7mf c gh1 gl1 vs il1 ___ ih1 c vs 100 nf r vs 10 gnd isp il2 ___ ih2 il3 ___ ih3 gnd vreg tle 7184 pgnd pgnd ____ err temp iso shunt r s r s r fb 1 ____ rgs ____ inhd isn bh1 c bs1 470nf r gh1 sh2 gh2 bh2 r gh2 c bs2 470nf sh3 gh3 bh3 r gh3 c bs3 470nf r gl1 gl2 r gl2 gl3 r gl3 agnd l 2,2h ifma r 1,6k l 2,2h interface r 33 ifuc dt vdd gnd agnd agnd r dt c lp sl c br 1f pgnd kl 15 r 2,2k ___ inh vdhs r fb 3 agnd gnd vdh c reg 2f r vdh + iov scdl r fb2 r 1,2k r 10k t ls2 t ls3 t ls1 t hs2 t hs3 t hs1 r sc1 r sc2 c vdd1 100nf r ov1 r ov2 r vdh1 r vdh2 r 10k c vdd2 2.2nf c vs 2f agnd c iso r lp for details of the current sense feature please see the dedicated chapter
data sheet 36 rev. 1.1, 2011-04-08 tle7184f package outlines 11 package outlines figure 15 pg-vqfn-48 green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). gvq01049 a index marking b 0.9 max. 0.08 48x 12?max. seating plane c (0.2) 0.05 max. standoff 1 12 37 48 13 24 25 36 11 x 0.65 = 7.15 0.65 11 x 0.65 = 7.15 0.65 6.8 ?.15 ?.05 0.35 ?.1 9 ?.1 8.75 0.1 48x a m b c ?.15 6.8 index marking ?.05 0.55 (0.65) ?.1 9 ?.1 8.75 you can find all of our packages, so rts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products . dimensions in mm
tle7184f revision history data sheet 37 rev. 1.1, 2011-04-08 12 revision history revision date changes rev. 1.1 2011-04-08 - voltage differen ce between isp and isn specified - minimum buffer capacitor c vreg specified - description of sh currents added - fig. 4 new - pull up and pull down resistors at ihx and ilx expanded - rise and fall times specified - propagation time tolerance reduced - limit the lower load current of vdd to 2ma - fig. 5 updated - steady state differential input voltage range across vin removed - common mode suppression, footnote added - ifma low time to guarantee wake-up added - matching of ifma pull up / pull down resistors replaced by ifma input current / vs - pull up resistor at ifuc output expanded - pull up resistor at inhd expanded - high level input voltage inh (for inhd =high) adapted - dead time description improved - short circuit detection accuracy improved - scdl open pin detection level hysteresis, footnote added - rise time err adapted - pull down resistor at err output expanded - inh high time to guarantee wake-up added - analog temperature output tolerance at 25c improved rev.1.0 2008-12-04 - test conditions of bias current into bhx modified - current between bhx and shx adapted - ifma internal pull-up resistor to vs modified - matching of internal pull-up / pull-down resistor expanded - filter time of short circuit protection test conditions improved - blanking time plus filter time of shor t circuit detection test conditions added - filter time for over current detection expanded
edition 2011-04-08 published by infineon technologies ag 81726 munich, germany ? 2011 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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