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hc05j5agrs/h rev 2.1 68hc05j5a 68hrc05j5a 68hc705j5a 68hrc705j5a specification (general release) july 16, 1999 semiconductor products sector f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification rev 2.1 i table of contents section page section 1 general description 1.1 features ...................................................................................................... 1-1 1.2 mask options.............................................................................................. 1-2 1.3 mcu structure.......................................................................................... 1-2 1.4 pin assignments ........................................................................................ 1-4 1.5 functional pin description.................................................................. 1-4 1.5.1 v dd and v ss .............................................................................................. 1-4 1.5.2 osc1, osc2/r............................................................................................ 1-4 1.5.3 reset ......................................................................................................... 1-6 1.5.4 irq (maskable interrupt request)................................................ 1-6 1.5.5 pa0-pa7 ...................................................................................................... 1-6 1.5.6 pb0-pb5 ...................................................................................................... 1-7 section 2 memory 2.1 i/o and control registers ................................................................... 2-2 2.2 ram ................................................................................................................. 2-2 2.3 rom................................................................................................................. 2-2 2.4 i/o registers summary ........................................................................... 2-3 section 3 central processing unit 3.1 registers .................................................................................................... 3-1 3.2 accumulator (a)........................................................................................ 3-2 3.3 index register (x) ..................................................................................... 3-2 3.4 stack pointer (sp) .................................................................................... 3-2 3.5 program counter (pc) ........................................................................... 3-2 3.6 condition code register (ccr) ........................................................... 3-3 3.6.1 half carry bit (h-bit) .................................................................................... 3-3 3.6.2 interrupt mask (i-bit) .................................................................................... 3-3 3.6.3 negative bit (n-bit) ...................................................................................... 3-3 3.6.4 zero bit (z-bit) ............................................................................................. 3-3 3.6.5 carry/borrow bit (c-bit) ............................................................................... 3-4 section 4 interrupts 4.1 cpu interrupt processing ................................................................... 4-1 4.2 reset interrupt sequence .................................................................. 4-2 4.3 software interrupt (swi) ..................................................................... 4-3 4.4 hardware interrupts ............................................................................ 4-3 4.5 external interrupt (irq)....................................................................... 4-3 4.5.1 irq control/status register (icsr) $0a...................................... 4-5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 MC68HC05J5A ii rev 2.1 table of contents section page 4.5.2 optional external interrupts (pa0-pa3) .................................... 4-6 4.5.3 timer interrupt (mft) ......................................................................... 4-7 4.5.4 timer1 interrupt (16-bit timer)........................................................ 4-7 section 5 resets 5.1 external reset (reset).......................................................................... 5-2 5.2 internal resets ........................................................................................ 5-2 5.2.1 power-on reset (por) ........................................................................ 5-2 5.2.2 computer operating properly reset (copr)........................... 5-2 5.2.3 low voltage reset (lvr) ................................................................... 5-3 5.2.4 illegal address reset (iladr)......................................................... 5-3 section 6 low power modes 6.1 stop instruction...................................................................................... 6-2 6.1.1 stop mode ................................................................................................. 6-3 6.1.2 halt mode.................................................................................................. 6-3 6.2 wait instruction....................................................................................... 6-4 6.3 data-retention mode.............................................................................. 6-4 6.4 cop watchdog timer considerations ............................................. 6-4 section 7 input/output ports 7.1 slow output falling-edge transition............................................. 7-1 7.2 port a............................................................................................................ 7-1 7.2.1 port a data register.................................................................................... 7-2 7.2.2 port a data direction register..................................................................... 7-2 7.2.3 port a pulldown/up register........................................................................ 7-3 7.2.4 port a drive capability................................................................................. 7-3 7.2.5 port a i/o pin interrupts............................................................................... 7-3 7.3 port b............................................................................................................ 7-4 7.3.1 port b data register.................................................................................... 7-4 7.3.2 port b data direction register..................................................................... 7-5 7.3.3 port b pulldown/up register........................................................................ 7-5 7.4 i/o port programming ............................................................................ 7-6 7.4.1 pin data direction........................................................................................ 7-6 7.4.2 output pin.................................................................................................... 7-6 7.4.3 input pin....................................................................................................... 7-6 7.4.4 i/o pin transitions ....................................................................................... 7-7 7.4.5 i/o pin truth tables..................................................................................... 7-7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification rev 2.1 iii table of contents section page section 8 multi-function timer 8.1 overview...................................................................................................... 8-2 8.2 computer operating properly (cop) watchdog ........................ 8-2 8.3 mft registers ............................................................................................ 8-2 8.3.1 timer counter register (tcr) $09.............................................................. 8-3 8.3.2 timer control/status register (tcsr) $08 ................................................. 8-3 8.4 operation during stop mode .............................................................. 8-5 8.5 operation during wait/halt mode..................................................... 8-5 section 9 16-bit timer 9.1 timer1 counter registers (tcnth, tcntl) ...................................... 9-2 9.2 alternate counter registers (acnth, acntl).............................. 9-3 9.3 input capture registers ...................................................................... 9-5 9.4 timer1 control register (t1cr) ......................................................... 9-8 9.5 timer1 status register (t1sr)............................................................. 9-9 9.6 timer1 operation during wait mode................................................. 9-9 9.7 timer1 operation during stop mode ................................................ 9-9 section 10 instruction set 10.1 addressing modes ................................................................................. 10-1 10.1.1 inherent...................................................................................................... 10-1 10.1.2 immediate .................................................................................................. 10-1 10.1.3 direct ......................................................................................................... 10-2 10.1.4 extended.................................................................................................... 10-2 10.1.5 indexed, no offset..................................................................................... 10-2 10.1.6 indexed, 8-bit offset .................................................................................. 10-2 10.1.7 indexed, 16-bit offset ................................................................................ 10-3 10.1.8 relative...................................................................................................... 10-3 10.1.9 instruction types ....................................................................................... 10-3 10.1.10 register/memory instructions .................................................................... 10-4 10.1.11 read-modify-write instructions ................................................................. 10-5 10.1.12 jump/branch instructions .......................................................................... 10-5 10.1.13 bit manipulation instructions...................................................................... 10-7 10.1.14 control instructions.................................................................................... 10-7 10.1.15 instruction set summary ........................................................................... 10-8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 MC68HC05J5A iv rev 2.1 table of contents section page section 11 electrical specifications 11.1 maximum ratings..................................................................................... 11-1 11.2 thermal characteristics ................................................................... 11-1 11.3 functional operating range ............................................................ 11-1 11.4 dc electrical characteristics........................................................ 11-2 11.5 control timing ........................................................................................ 11-5 section 12 mechanical specifications 12.1 16-pin pdip (case #648) ............................................................................ 12-1 12.2 16-pin soic (case #751g) ......................................................................... 12-1 12.3 20-pin pdip (case #738) ............................................................................ 12-2 12.4 20-pin soic (case #751d) ......................................................................... 12-2 appendix a mc68hrc05j5a a.1 introduction..............................................................................................a-1 a.2 rc oscillator connections.................................................................a-1 a.3 electrical characteristics ................................................................a-2 appendix b mc68hc705j5a b.1 introduction..............................................................................................b-1 b.2 memory .........................................................................................................b-1 b.3 mask option registers (mor)...............................................................b-1 b.4 bootstrap mode .......................................................................................b-4 b.5 eprom programming ...............................................................................b-4 b.5.1 eprom program control register (pcr)...................................................b-4 b.5.2 programming sequence ..............................................................................b-5 b.6 electrical characteristics ................................................................b-6 appendix c mc68hrc705j5a c.1 introduction..............................................................................................c-1 c.2 rc oscillator connections.................................................................c-1 c.3 electrical characteristics ................................................................c-2 appendix d ordering information d.1 mc order numbers...................................................................................d-1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification rev 2.1 v list of figures figure title page 1-1 MC68HC05J5A block diagram........................................................................ 1-3 1-2 pin assignments for 16-pin and 20-pin packages........................................... 1-4 1-3 oscillator connections ..................................................................................... 1-5 2-1 MC68HC05J5A memory map .......................................................................... 2-1 2-2 i/o registers memory map .............................................................................. 2-2 2-3 i/o registers $0000-$000f.............................................................................. 2-3 2-4 i/o registers $0010-$001f.............................................................................. 2-4 3-1 mc68hc05 programming model ..................................................................... 3-1 4-1 interrupt processing flowchart ........................................................................ 4-2 4-2 irq function block diagram............................................................................ 4-3 4-3 irq status & control register ......................................................................... 4-5 5-1 reset block diagram ....................................................................................... 5-1 6-1 stop/halt/wait flowcharts......................................................................... 6-2 7-1 port b data direction register ......................................................................... 7-1 7-2 port a i/o circuitry ........................................................................................... 7-2 7-3 port b i/o circuitry ........................................................................................... 7-4 8-1 multi-function timer block diagram ................................................................ 8-1 8-2 cop watchdog timer location ....................................................................... 8-2 8-3 timer counter register.................................................................................... 8-3 8-4 timer control/status register (tcsr)............................................................. 8-3 9-1 16-bit timer block diagram ............................................................................. 9-1 9-2 16-bit timer counter block diagram ............................................................... 9-2 9-3 16-bit timer counter registers (tcnth, tcntl) .......................................... 9-3 9-4 alternate counter block diagram..................................................................... 9-4 9-5 alternate counter registers (acnth, acntl) ............................................... 9-4 9-6 timer input capture block diagram................................................................. 9-5 9-7 timer1 capture control register ..................................................................... 9-6 9-8 tcap input signal conditioning....................................................................... 9-6 9-9 tcap input comparator output....................................................................... 9-7 9-10 input capture registers (ich, icl) .................................................................. 9-7 9-11 timer control register (t1cr) ........................................................................ 9-8 9-12 timer status registers (t1sr) ........................................................................ 9-9 12-1 16-pin pdip mechanical dimensions ............................................................ 12-1 12-2 16-pin soic mechanical dimensions ............................................................ 12-1 12-3 20-pin pdip mechanical dimensions ............................................................ 12-2 12-4 20-pin soic mechanical dimensions ............................................................ 12-2 a-1 rc oscillator connections ...............................................................................a-1 a-2 typical internal operating frequency for rc oscillator connections..............a-2 b-1 mc68hc705j5a memory map ........................................................................b-3 b-2 eprom programming sequence ....................................................................b-5 c-1 rc oscillator connections ...............................................................................c-1 c-2 typical internal operating frequency for rc oscillator connections..............c-2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 MC68HC05J5A vi rev 2.1 list of figures figure title page f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification rev 2.1 vii list of tables table title page 4-1 vector address for interrupts and reset.......................................................... 4-1 6-1 cop watchdog timer recommendations ....................................................... 6-5 7-1 port a i/o pin functions................................................................................... 7-7 7-2 port b i/o pin functions................................................................................... 7-7 8-1 rti rates and cop reset times .................................................................... 8-5 10-1 register/memory instructions ........................................................................ 10-4 10-2 read-modify-write instructions ..................................................................... 10-5 10-3 jump and branch instructions........................................................................ 10-6 10-4 bit manipulation instructions .......................................................................... 10-7 10-5 control instructions ........................................................................................ 10-7 10-6 instruction set summary ............................................................................... 10-8 10-7 opcode map................................................................................................. 10-14 11-1 dc electrical characteristics, vdd=5 v ........................................................ 11-2 11-2 dc electrical characteristics, vd d=2.2v ..................................................... 11-3 11-3 control timing, vd d=5v ............................................................................... 11-5 11-4 control timing, vdd=2.2v............................................................................ 11-5 a-1 functional operating range ............................................................................a-2 a-2 dc electrical characteristics, vd d=5v ...........................................................a-2 b-1 functional operating range ............................................................................b-6 b-2 eprom programming electrical characteristics .............................................b-6 b-3 dc electrical characteristics, vdd=5 v ..........................................................b-6 c-1 functional operating range ............................................................................c-2 c-2 dc electrical characteristics, vdd=5 v ..........................................................c-2 d-1 mc order numbers..........................................................................................d-1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 MC68HC05J5A viii rev 2.1 list of tables table title page f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification general description rev 2.1 1-1 section 1 general description the MC68HC05J5A is a member of the low-cost high-performance m68hc05 family of 8-bit microcontroller units (mcus). the m68hc05 family is based on the customer-speci?d integrated circuit design strategy. all mcus in the family use the popular m68hc05 central processing unit (cpu) and are available with a variety of subsystems, memory sizes and types, and package types. the MC68HC05J5A is an enhanced version of the mc68hc05j5, with expanded ram, rom sizes, and an additional 16-bit timer with tcap. this mcu is available in 20-pin pdip, 20-pin soic, 16-pin pdip, and 16-pin soic packages. the 16-pin version has four less i/o lines. three variation on the MC68HC05J5A device are available; a summary of their differences are listed in the following table: 1.1 features the features of the MC68HC05J5A include the following: industry standard m68hc05 cpu core fully static operation with no minimum clock speed power-saving stop and wait modes memory-mapped input/output (i/o) registers 2560 bytes of user rom with security feature 128 bytes of user ram on-chip oscillator: crystal/resonator oscillator external clock oscillator 15-bit multi-function timer 16-bit programmable timer with input capture device rom type oscillator option reference MC68HC05J5A 2560 bytes rom crystal/resonator or external clock oscillator mc68hrc05j5a 2560 bytes rom rc oscillator appendix a mc68hc705j5a 2560 bytes eprom crystal/resonator or external clock oscillator appendix b mc68hrc705j5a 2560 bytes eprom rc oscillator appendix c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 general description MC68HC05J5A 1-2 rev 2.1 14 bidirectional i/o pins (10 i/o pins on 16-pin package) pa0-pa5, pb0, and pb3-pb5: with software programmable input pull- down devices pb1, pb2, pa6 and pa7: open-drained i/o pins with software programmable pull-up devices pa6, pa7, and pb1: with slow output falling transition feature pa7: with falling-edge interrupt capability pa0-pa3: with maskable rising-edge only or rising-edge and high level interrupt capability 20-pin package: pb1 and pb2, each with 25ma current sink capability 16-pin package: pb1 with 50ma current sink capability computer operation properly (cop) watchdog low voltage reset circuit illegal address reset 20-pin pdip, 20-pin soic, 16-pin pdip, and 16-pin soic packages 1.2 mask options the following mask options are available on the MC68HC05J5A: 1.3 mcu structure figure 1-1 shows the structure of MC68HC05J5A mcu. mask option stop instruction convert to wait [enabled] or [disabled] external interrupt pins (irq , pa0-pa3) [edge-triggered] or [edge and level triggered] port a and port b pull-down/pull-up resistors [enabled] or [disabled] pa0-pa3 external interrupt capability [enabled] or [disabled] oscillator delay option (internal clock cycles) [224] or [4064] low voltage reset [enabled] or [disabled] cop watchdog timer [enabled] or [disabled] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification general description rev 2.1 1-3 figure 1-1. MC68HC05J5A block diagram oscillator and divide by 2 osc1 128 bytes ram 2560 bytes rom pa0 ? pa1 ? pa2 ? pa3 ? pa4 - pa5 - pa6 ? pa7 data dir reg port a reg irq vdd vss stk ptr cond code reg 1 1 1 i n z c h index reg cpu control 0 0 0 1 1 0 0 0 0 0 alu 68hc05 cpu accum program counter cpu regisers osc2/r reset core timer (cop) low voltage reset pb0 pb1 pb2 2 pb3 2 pb4 2 pb5 2 data dir reg port b reg - : 8 ma current sink : shared pin: pb0/tcap ? : external edge interrupt capability ? : open-drained with internal pull-up and 8 ma current sink : external interrupt capability, open-drained with internal pull-up and 8 ma current sink 2 : not bonded out in 16-pin package : 25 ma current sink open-drained with internal pull-up 16-bit timer tcap f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 general description MC68HC05J5A 1-4 rev 2.1 1.4 pin assignments figure 1-2. pin assignments for 16-pin and 20-pin packages 1.5 functional pin description the following paragraphs give a description of the general function of each pin assigned in figure 1-2 . 1.5.1 v dd and v ss power is supplied to the mcu through v dd and v ss . v dd is the positive supply, and v ss is ground. the mcu operates from a single power supply. very fast signal transitions occur on the mcu pins. the short rise and fall times place very high short-duration current demands on the power supply. to prevent noise problems, special care should be taken to provide good power supply bypassing at the mcu by using bypass capacitors with good high-frequency char- acteristics that are positioned as close to the mcu as possible. bypassing requirements vary, depending on how heavily the mcu pins are loaded. 1.5.2 osc1, osc2/r the osc1 and osc2/r pins are the connections for the on-chip oscillator. the osc1 and osc2/r pins can accept the following sets of components: osc2/r osc1 reset pa7 pa6 pa5 pa4 pb0/tcap pb1 vdd vss irq /vpp pa0 pa1 pa2 pa3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 osc2/r osc1 reset pa7 pa6 pa5 pa4 pb0/tcap pb1 vdd vss irq /vpp pa0 pa1 pa2 pa3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 20 19 18 17 pb3 pb4 pb2 pb5 irq /vpp: vpp is only available on eprom parts f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification general description rev 2.1 1-5 1. a crystal as shown in figure 1-3 (a) 2. a ceramic resonator as shown in figure 1-3 (a) 3. an external clock signal as shown in figure 1-3 (b) the frequency, f osc , of the oscillator or external clock source is divided by two to produce the internal operating frequency, f op . crystal oscillator the circuit in figure 1-3 (a) shows a typical oscillator circuit for an at-cut, parallel resonant crystal. the crystal manufacturers recommendations should be fol- lowed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. the load capacitance values used in the oscillator circuit design should include all stray capacitances. the crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. an internal start-up resistor is provided between osc1 and osc2/r for the crystal type oscillator. figure 1-3. oscillator connections ceramic resonator oscillator in cost-sensitive applications, a ceramic resonator can be used in place of the crystal. the circuit in figure 1-3 (a) can be used for a ceramic resonator. the res- onator manufacturers recommendations should be followed, as the resonator parameters determine the external component values required for maximum sta- bility and reliable starting. the load capacitance values used in the oscillator cir- cuit design should include all stray capacitances. the ceramic resonator and components should be mounted as close as possible to the pins for start-up stabi- lization and to minimize output distortion. an internal start-up resistor is provided between osc1 and osc2/r for the ceramic resonator type oscillator. external clock an external clock from another cmos-compatible device can be connected to the osc1 input, with the osc2/r input not connected, as shown in figure 1-3 (b). mcu 37pf osc1 osc2/r 37 pf r osc unconnected external clock osc1 osc2/r mcu (a) crystal or ceramic resonator connection (b) external clock source connection r osc : see section 11. electrical specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 general description MC68HC05J5A 1-6 rev 2.1 1.5.3 reset this is an i/o pin. this pin can be used as an input to reset the mcu to a known start-up state by pulling it to the low state. the reset pin contains a steering diode to discharge any voltage on the pin to v dd , when the power is removed. an internal pull-up is also connected between this pin and v dd . the reset pin con- tains an internal schmitt trigger to improve its noise immunity as an input. this pin is an output pin if lvr triggers an internal reset. 1.5.4 irq (maskable interrupt request) this input pin drives the asynchronous irq interrupt function of the cpu. the irq interrupt function has a mask option to provide either only negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. if the option is selected to include level-sensitive triggering, the irq input requires an external resistor to v dd for "wired-or" operation, if desired. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. each of the pa0 through pa3 i/o pins may be connected as an or function with the irq interrupt function by a mask option. this capability allows keyboard scan applications where the transitions or levels on the i/o pins will behave the same as the irq pin, except for the inverted phase. the edge or level sensitivity selected by a separate mask option for the irq pin also applies to the i/o pins or?d to create the irq signal. besides, pa7 also has falling-edge only interrupt capability whose functionality is controlled by another set of register bits. 1.5.5 pa0-pa7 these eight i/o lines comprise port a. pa6 and pa7 are open-drained pins with pull-up devices whereas pa0 to pa5 are push-pull pins with pull-down devices. pa4 to pa7 are also capable of sinking 8ma. the state of any pin is software programmable and all port a lines are con?ured as inputs during power-on or reset. the lower four i/o pins (pa0 to pa3) can be connected via an internal or gate to the irq interrupt function enabled by a mask option. another independent interrupt source comes from the falling-edge on pa7. pa7 interrupt source is associated with a second set of interrupt control/status bits. all port a pins except pa6 and pa7 have software programmable pull-down devices also provided by a mask option. pa6 and pa7 pins have software programmable pull-up devices also provided by the same mask option. pull-up devices on pa6 and pa7 once enabled are always enabled regardless of pin direction con?uration, unlike pull-down devices on pa0 to pa5 which are activated only when these pins are con?ured as input pins. pa6 and pa7 pins, when con?ured as output pins, also have slow output falling- edge transition feature to reduce emi. the falling-edge transition time is set at 250ns typical at a speci?d load of 500pf, assuming the bus rate is 2mhz. the slow transition output feature of pa6 and pa7, along with that of pb1 and pb2, f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification general description rev 2.1 1-7 can be enabled or disabled by software. both pa6 and pa7 pins have schmitt trigger input for better noise immunity. v ih and v il are speci?d at 2.4v and 0.8v, respectively. the slow transition feature of pa6 and pa7 pins can be enabled or disabled by software. once enabled, slow transition feature is applied to both pins while in output mode. 1.5.6 pb0-pb5 note i/o lines pb2 to pb5 are not available on the 16-pin package. these six i/o lines comprise port b. pb0, pb3 to pb5 are push-pull i/o lines with pull-down resistor. pb1 and pb2 are open-drain i/o lines with pull-up resistor. the state of any line is software programmable and is con?ured as an input during power-on or reset. i/o lines pb1 and pb2 have software programmable pull-up device, whereas pb0, pb3 to pb5 have software programmable pull-down device, provided by mask option. pull-up devices on pb1 and pb2 lines once enabled are always enabled regardless of pin direction con?uration; unlike pull- down devices on pb0, pb3-pb5 lines, which are activated only when the pin is con?ured as input pin. similar to pa6 and pa7, pb1 also has a slow output falling transition feature when con?ured as an output line. pb1 has 25ma sink capability at 0.5v v ol . pb2 output is one clock cycle (250ns if bus rate is 2mhz) late than other i/o pins if slow output transition feature is enabled. pb2 has 25ma sink capability at 0.5v v ol . note for the 16-pin package, pb1 and pb2 are bonded to the same pin and is labelled pb1. this pb1 pin has 50ma sink capability if pb1 and pb2 data register bits they are written with the same value at the same write cycle. the falling transition time of pb1 is set at 250ns typical at a speci?d load of 50pf, assuming that the bus rate is 2mhz. the slow transition feature on this pb1 pin is longer than pb1 pin for the 20-pin package. note if port data register pb1 and pb2 are not written with the same value, pb1 pin on the 16-pin package will sink 25ma only and the output transition time will be shorter. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 general description MC68HC05J5A 1-8 rev 2.1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification memory rev 2.1 2-1 section 2 memory the MC68HC05J5A has 4k-bytes of addressable memory consisting 32 bytes of i/o, 128 bytes of user ram, and 2560 bytes of user rom, as shown in figure 2-1 . figure 2-1. MC68HC05J5A memory map rom reserved 6 bytes user vectors rom 10 bytes unimplemented 96 bytes 3327 3328 4095 4086 3583 stack user ram 128 bytes reset vector (low byte) reset vector (high byte) swi vector (low byte) swi vector (high byte) irq vector (low byte) irq vector (high byte) mft vector (low byte) mft vector (high byte) $0ff7 $0ff8 $0ff9 $0ffa $0ffb $0ffc $0ffd $0ffe $0fff $001f $0000 $0100 $00ff 0255 0256 i/o 32 bytes 0032 0031 0000 $0fff $0ff0 $0fef $0d00 $0cff $0080 $007f $0020 $001f $0000 user rom 2560 bytes i/o registers 32 bytes (see figure 2-2 ) 0128 0127 unimplemented 512 bytes $0ff6 $0ff3 $0ff4 $0ff5 $0ff2 $0ff1 $0ff0 cop watchdog timer* $0dff $0e00 3584 4079 internal test & vectors 496 bytes rom * writing a 0 to bit 0 of $0ff0 clears the cop timer. reading $0ff0 returns rom data. timer1 vector (low byte) reserved timer1 vector (high byte) reserved reserved reserved reserved $0ff6 $0ff5 4080 4085 unimplemented 256 bytes 0767 0768 $0300 $02ff 0192 $00c0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 memory MC68HC05J5A 2-2 rev 2.1 2.1 i/o and control registers the i/o and control registers reside in locations $0000-$001f. the overall orga- nization of these registers is shown in figure 2-2 . the bit assignments for each register are shown in figure 2-3 and figure 2-4 . reading from unimplemented bits will return unknown states, and writing to unimplemented bits will be ignored. figure 2-2. i/o registers memory map 2.2 ram the total ram consists of 128 bytes (including the stack) at locations $0080 through $00ff. the stack begins at address $00ff and proceeds down to $00c0. using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. 2.3 rom there are a total of 2570 bytes of user rom on-chip. this includes 2560 bytes of user rom from locations $0300 to $0cff for user program storage and 10 bytes for user vectors from locations $0ff6 to $0fff. port a data register $0000 port b data register $0001 port a data direction register $0004 port b data direction register $0005 mft control & status register $0008 mft counter register $0009 reserved for test $001f unimplemented (2) unimplemented (5) irq control & status register $000a port a pulldown/up register $0010 port b pulldown/up register $0011 unimplemented (1) $0002 $0003 unimplemented (2) timer1 registers (4) $0012 $0015 unimplemented (3) timer1 registers (4) $0018 $001b $001e reserved timer1 capture control register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification memory rev 2.1 2-3 2.4 i/o registers summary addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0000 port a data r pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 porta w $0001 port b data r 0 0 pb5 pb4 pb3 pb2 pb1 pb0 portb w $0002 timer1 capture control r tcaps t1cc w $0003 unimplemented r w $0004 port a data direction r ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 ddra w $0005 port b data direction r slowe 0 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 ddrb w $0006 unimplemented r w $0007 unimplemented r w $0008 mft ctrl/status r tof rtif tofe rtie 00 rt1 rt0 tcsr w tofr rtifr $0009 mft counter r tmr7 tmr6 tmr5 tmr4 tmr3 tmr2 tmr1 tmr0 tcr w $000a irq control/status r irqe irqe1 0 0 irqf irqf1 0 0 icsr w r irqr irqr1 $000b unimplemented r w $000c unimplemented r w $000d unimplemented r w $000e unimplemented r w $000f unimplemented r w unimplemented bits reserved bits r figure 2-3. i/o registers $0000-$000f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 memory MC68HC05J5A 2-4 rev 2.1 addr register r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 $0010 port a pull-down/up r pdura w pura7 pura6 pdra5 pdra4 pdra3 pdra2 pdra1 pdra0 $0011 port b pull-down/up r pdurb w pdrb5 pdrb4 pdrb3 purb2 purb1 pdrb0 $0012 timer1 control r icie 0 t1oie 000 iedge 0 t1cr w $0013 timer1 status r icf 0 t1of 00000 t1sr w $0014 input capture high r bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 ich w $0015 input capture low r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 icl w $0016 unimplemented r w $0017 unimplemented r w $0018 timer1 counter high r bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 tcnth w $0019 timer1 counter low r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tcntl w $001a alt. counter high r bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 acnth w $001b alt. counter low r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 acntl w $001c unimplemented r w $001d unimplemented r w $001e reserved r r r r r r r r r w $001f reserved r r r r r r r r r w unimplemented bits reserved bits r figure 2-4. i/o registers $0010-$001f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification central processing unit rev 2.1 3-1 section 3 central processing unit the MC68HC05J5A has an 4k-bytes memory map. the stack has only 64 bytes. therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00c0 and then wrap-around to $00ff. all other instructions and registers behave as described in this chapter. 3.1 registers the mcu contains ?e registers which are hard-wired within the cpu and are not part of the memory map. these ?e registers are shown in figure 3-1 and are described in the following paragraphs. figure 3-1. mc68hc05 programming model condition code register i accumulator 60 a index register 71 x 4 52 3 stack pointer sp 14 8 15 9 12 13 10 11 pc cc 111 11 0 0 0 0 0 0 0 0 program counter h nzc half-carry bit (from bit 3) interrupt mask negative bit zero bit carry bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 central processing unit MC68HC05J5A 3-2 rev 2.1 3.2 accumulator (a) the accumulator is a general purpose 8-bit register as shown in figure 3-1 . the cpu uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. the accumulator is not affected by a reset of the device. 3.3 index register (x) the index register shown in figure 3-1 is an 8-bit register that can perform two functions: indexed addressing temporary storage in indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. in indexed addressing with an 8-bit offset, the cpu ?ds the operand address by adding the index register content to an 8-bit immediate value. in indexed addressing with a 16-bit offset, the cpu ?ds the operand address by adding the index register content to a 16-bit immediate value. the index register can also serve as an auxiliary accumulator for temporary storage. the index register is not affected by a reset of the device. 3.4 stack pointer (sp) the stack pointer shown in figure 3-1 is a 16-bit register. in mcu devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. the stack pointer contains the address of the next free location on the stack. during a reset or the reset stack pointer (rsp) instruction, the stack pointer is set to $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled off the stack. when accessing memory, the ten most signi?ant bits are permanently set to 0000000011. the six least signi?ant register bits are appended to these ten ?ed bits to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64($c0) locations. if 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. a subroutine call occupies two locations on the stack and an interrupt uses ?e locations. 3.5 program counter (pc) the program counter shown in figure 3-1 is a 16-bit register. in mcu devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. the program counter contains the address of the next instruction or operand to be fetched. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification central processing unit rev 2.1 3-3 normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.6 condition code register (ccr) the ccr shown in figure 3-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. the ?th bit is the interrupt mask. these bits can be individually tested by a program, and speci? actions can be taken as a result of their states. the condition code register should be thought of as having three additional upper bits that are always ones. only the interrupt mask is affected by a reset of the device. the following paragraphs explain the functions of the lower ?e bits of the condition code register. 3.6.1 half carry bit (h-bit) when the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last add or adc (add with carry) operation. the half-carry bit is required for binary-coded decimal (bcd) arithmetic operations. 3.6.2 interrupt mask (i-bit) when the interrupt mask is set, the internal and external interrupts are disabled. interrupts are enabled when the interrupt mask is cleared. when an interrupt occurs, the interrupt mask is automatically set after the cpu registers are saved on the stack, but before the interrupt vector is fetched. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. normally, the interrupt is processed as soon as the interrupt mask is cleared. a return from interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. after any reset, the interrupt mask is set and can only be cleared by the clear i-bit (cli), or wait instructions. 3.6.3 negative bit (n-bit) the negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (bit 7 of the result was a logical one.) the negative bit can also be used to check an often tested ?g by assigning the ?g to bit 7 of a register or memory location. loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the ?g. 3.6.4 zero bit (z-bit) the zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 central processing unit MC68HC05J5A 3-4 rev 2.1 3.6.5 carry/borrow bit (c-bit) the carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. the carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. this bit is neither set by an inc nor by a dec instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification interrupts rev 2.1 4-1 section 4 interrupts the mcu can be interrupted in six different ways: non-maskable software interrupt instruction (swi) external asynchronous interrupt (irq ) optional external interrupt via irq on pa0-pa3 (by a mask option) external interrupt via irq on pa7 multi-function timer (mft) 16-bit timer interrupt (timer1) 4.1 cpu interrupt processing interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i-bit) to prevent additional interrupts. unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are con- sidered pending until the current instruction is complete. if interrupts are not masked (i-bit in the ccr is clear) and the corresponding inter- rupt enable bit is set the processor will proceed with interrupt processing. other- wise, the next instruction is fetched and executed. if an interrupt occurs the processor completes the current instruction, then stacks the current cpu register states, sets the i-bit to inhibit further interrupts, and ?ally checks the pending hardware interrupts. if more than one interrupt is pending following the stacking operation, the interrupt with the highest vector location shown in table 4-1 will be serviced ?st. the swi is executed the same as any other instruction, regardless of the i-bit state. when an interrupt is to be processed the cpu fetches the address of the appro- priate interrupt software service routine from the vector table at locations $0ff6 thru $0fff as de?ed in table 4-1 . table 4-1. vector address for interrupts and reset n/a n/a irqf/irqf1 tof rtif t1of, icf register n/a n/a icsr tcsr tcsr t1sr flag name interrupts reset software external interrupt mft overflow real time interrupt timer1 interrupt cpu interrupt reset swi irq mft mft timer1 vector address $0ffe-$0fff $0ffc-$0ffd $0ffa-$0ffb $0ff8-$0ff9 $0ff8-$0ff9 $0ff6-$0ff7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 interrupts MC68HC05J5A 4-2 rev 2.1 an rti instruction is used to signify when the interrupt software service routine is completed. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. figure 4-1 shows the sequence of events that occur during interrupt processing. figure 4-1. interrupt processing flowchart 4.2 reset interrupt sequence the reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in figure 4-1 . a low level input on the reset pin or an internally generated rst signal causes the program to vector to its start- ing address which is speci?d by the contents of memory locations $0ffe and $0fff. the i-bit in the condition code register is also set. execute instruction from reset is i-bit set? load pc from: swi: $0ffc, $0ffd irq: $0ffa-$0ffb timer: $0ff8-$0ff9 timer1: $0ff6-$0ff7 set i-bit in ccr stack pc, x, a, cc clear irq request latch if irqe1 is cleared restore registers from stack cc, a, x, pc y n irq external interrupt? y n timer internal interrupt? y n fetch next instruction rti instruction ? y n swi instruction ? y n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification interrupts rev 2.1 4-3 4.3 software interrupt (swi) the swi is an executable instruction and a non-maskable interrupt since it is exe- cuted regardless of the state of the i-bit in the ccr. as with any instruction, inter- rupts pending during the previous instruction will be serviced before the swi opcode is fetched. the interrupt service routine address is speci?d by the con- tents of memory locations $0ffc and $0ffd. 4.4 hardware interrupts all hardware interrupts except reset are maskable by the i-bit in the ccr. if the i-bit is set, all hardware interrupts (internal and external) are disabled. clearing the i-bit enables the hardware interrupts. there are two types of hardware inter- rupts which are explained in the following sections. 4.5 external interrupt (irq ) the irq pin provides an asynchronous interrupt to the cpu. a block diagram of the irq function is shown in figure 4-2 . figure 4-2. irq function block diagram irq latch r v dd irq pin irqe mask option (irq level) irqf to irq processing in cpu irqr to bih & bil instruction sensing rst mask option (port a external int.) pa0 pa1 pa2 pa3 irq fetch vector irqe1 irq1 latch r v dd irqr1 rst irqf1 irqe1 pa7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 interrupts MC68HC05J5A 4-4 rev 2.1 the irq pin is a source of irq interrupts and a mask option can also enable the other four lower port a pins (pa0 thru pa3) to act as other irq interrupt sources. the last source of irq interrupt comes from pa7 whenever there is a falling edge on pa7 and irqe1 is enabled. there is no mask option associated with pa7 inter- rupt. refer to figure 4-2 for the following descriptions. irq interrupt source comes from irq and irq1 latches. the irq latch will be set on the falling edge of the irq pin or on any rising edge of pa0-3 pins if pa0-3 interrupts have been enabled. the irq1 latch will be set on the falling edge of pa7 if pa7 interrupt has been enabled. if "edge-only" sensitivity is chosen by a mask option, only the irq latch output can activate an irqf ?g which creates a request to the cpu to generate the irq interrupt sequence. this makes the irq interrupt sensitive to the following cases: 1. falling edge on the irq pin. 2. rising edge on any pa0-pa3 pin with irq enabled (via mask option). if level sensitivity is chosen, the rising edge signal on the clock input of the irq latch can also activate an irqf ?g which creates an irq request to the cpu to generate the irq interrupt sequence. this makes the irq interrupt sensitive to the following cases: 1. low level on the irq pin. 2. falling edge on the irq pin. 3. high level on any pa0- pa3 pin with irq enabled (via mask option). 4. rising edge on any pa0- pa3 pin with irq enabled (via mask option). the irqe enable bit controls whether an active irqf ?g can generate an irq interrupt sequence. this interrupt is serviced by the interrupt service routine located at the address speci?d by the contents of $0ffa and $0ffb. the irq latch is automatically cleared by entering the interrupt service routine if irqe1 enable bit is cleared. if irqe1 enable bit is also set, the only way of clear- ing irqf is by writing a logic one to the irqr acknowledge bit. writing a logic one to the irqr acknowledge bit in the icsr is the other way of clearing irqf ?g, regardless of the status of the irqe1 bit, besides irq vector fetch. this condi- tional reset of irqf ?g provides a way for the user to differentiate the interrupt sources from irq and irq1 latches and also to make it j1a compatible if pa7 interrupt is not used. as long as the output state of the irqf ?g bit is active the cpu will continuously re-enter the irq interrupt sequence until the active state is removed or the irqe enable bit is cleared. pa7 interrupt source, if enabled by irqe1 enable bit, triggers irq interrupt on pa7 falling edge only. the irq1 latch (irqf1 ?g) can only be cleared by writing a logic one to the irqr1 acknowledge bit in the icsr. irq vector fetch can not clear irqf1 ?g. irq interrupt caused by pa7 falling edge also vectors to $0ffa and $0ffb. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification interrupts rev 2.1 4-5 4.5.1 irq control/status register (icsr) $0a the irq interrupt function is controlled by the icsr located at $000a. all unused bits in the icsr will read as logic zeros. the irqf, irqf1, irqe1 bits are cleared and irqe bit is set by reset. figure 4-3. irq status & control register irqr 1 - pa7 interrupt acknowledge the irqr1 acknowledge bit clears an irq interrupt triggered by a falling edge on pa7 by clearing the irq1 latch. the irqr1 acknowledge bit will always read as a logic zero. 1 = writing a logic one to the irqr1 acknowledge bit will clear the irq1 latch. 0 = writing a logic zero to the irqr1 acknowledge bit will have no effect on the irq1 latch. irqr - irq interrupt acknowledge the irqr acknowledge bit clears an irq interrupt by clearing the irq latch. the irqr acknowledge bit will always read as a logic zero. 1 = writing a logic one to the irqr acknowledge bit will clear the irq latch. 0 = writing a logic zero to the irqr acknowledge bit will have no effect on the irq latch. irqf1 - pa7 interrupt request flag writing to the irqf1 ?g bit will have no effect on it. if the additional setting of irqf1 ?g bit is not cleared in the irq service routine and the irqe1 enable bit remains set the cpu will re-enter the irq interrupt sequence continuously until either the irqf1 ?g bit or the irqe1 enable bit is cleared. the irqf1 latch is cleared by reset. 1 = indicates that an irq request triggered by a falling edge on pa7 is pending. 0 = indicates that no irq request triggered by a falling edge on pa7 is pending. the irqf1 ?g bit can only be cleared by writing a logic one to the irqr1 acknowledge bit. doing so before exiting the service routine will mask out additional occurrences of the irqf1. 0 irqr1 icsr $000a 1 7 w r 0000000 reset t 6543210 irqe irqf 0 irqr 0 irqf1 irqe1 0 reserved for test r r unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 interrupts MC68HC05J5A 4-6 rev 2.1 irqf - irq interrupt request flag writing to the irqf ?g bit will have no effect on it. if the additional setting of irqf ?g bit is not cleared in the irq service routine and the irqe enable bit remains set the cpu will re-enter the irq interrupt sequence continuously until either the irqf ?g bit or the irqe enable bit is clear. the irqf latch is cleared by reset. 1 = indicates that an irq request is pending. 0 = indicates that no irq request triggered by pins pa0-3 or irq is pending. the irqf ?g bit is cleared once the irq vector is fetched and if irqe1 is also cleared. if irqe1 is set, then the only way of clearing irqf ?g is by writing a logic one to irqr bit. the irqf ?g bit can be cleared, regardless of the status of the irqe1 bit, by writing a logic one to the irqr acknowledge bit to clear the irq latch and also conditioning the external irq sources to be inactive (if the level sensitive interrupts are enabled via mask option). doing so before exiting the service routine will mask out additional occurrences of the irqf. irqe1 - pa7 interrupt enable the irqe1 bit enables/disables the irqf1 ?g bit to initiate an irq interrupt sequence. 1 = enables irqf1 interrupt, that is, the irqf1 ?g bit can generate an interrupt sequence. execution of the stop or wait instructions will leave the irqe1 bit to be unaffected. 0 = the irqf1 ?g bit cannot generate an interrupt sequence. reset clears the irqe1 enable bit, thereby disabling pa7 interrupts. irqe - irq interrupt enable the irqe bit enables/disables the irqf ?g bit to initiate an irq interrupt sequence. 1 = enables irqf interrupt, that is, the irqf ?g bit can generate an interrupt sequence. reset sets the irqe enable bit, thereby enabling irq interrupts once the i-bit is cleared. execution of the stop or wait instructions causes the irqe bit to be set in order to allow the external irq to exit these modes. 0 = the irqf ?g bit cannot generate an interrupt sequence. 4.5.2 optional external interrupts (pa0-pa3) the irq interrupt can also be triggered by the inputs on the pa0 thru pa3 port pins if enabled by a single mask option. if enabled, the lower four bits of port a can activate the irq interrupt function, and the interrupt operation will be the same as for inputs to the irq pin. this mask option of pa0-3 interrupt allow all of these input pins to be or?d with the input present on the irq pin. all pa0 thru pa3 pins must be selected as a group as an additional irq interrupt. all the pa0-3 interrupt sources are also controlled by the irqe enable bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification interrupts rev 2.1 4-7 note the bih and bil instructions will only apply to the level on the irq pin itself, and not to the output of the logic or function with the pa0 thru pa3 pins. the state of the individual port a pins can be checked by reading the appropriate port a pins as inputs. note if enabled, the pa0 thru pa3 and pa7 pins will cause an irq interrupt regardless of whether these pins are con?ured as inputs or outputs. 4.5.3 timer interrupt (mft) the timer interrupt is generated by the multi-function timer when either a timer over?w or a real time interrupt has occurred as described in section 8 . the inter- rupt ?gs and enable bits for the timer interrupts are located in the timer control & status register (tcsr) located at $0008. the i-bit in the ccr must be clear in order for the timer interrupt to be enabled. either of these two interrupts will vec- tor to the same interrupt service routine located at the address speci?d by the contents of memory locations $0ff8 and $0ff9. 4.5.4 timer1 interrupt (16-bit timer) the timer1 interrupt is generated by the 16-bit timer when either a timer1 over- ?w or a input capture has occurred as described in section 9 . the interrupt flags and enable bits for the timer1 interrupt are located in the timer1 control & status register (t1cr & t1sr) located at $0012, $0013. the i-bit in the ccr must be cleared in order to enable the timer1. either of these two interrupts will vector to the same interrupt service routine located at the address specified by the contents of memory locations $0ff6 and $0ff7. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 interrupts MC68HC05J5A 4-8 rev 2.1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification resets rev 2.1 5-1 section 5 resets the mcu can be reset from ?e sources: one external input and four internal restart conditions. initial power up of device (power on reset) a logic zero applied to the reset pin (external reset) timeout of the cop watchdog (cop reset) low voltage applied to the device (lvr reset) fetch of an opcode from an address not in the memory map (illegal address reset) figure 5-1 shows a block diagram of the reset sources and their interaction. figure 5-1. reset block diagram illegal address (iladr) cpu latch reset cop watchdog (copr) rst osc data address address ph2 to other peripherals s irq mode select to interrupt logic latch r power-on reset (por) v dd low voltage reset (lvr) v dd r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 resets MC68HC05J5A 5-2 rev 2.1 5.1 external reset (reset ) the reset pin is the only external source of a reset. this pin is connected to a schmitt trigger input gate to provide an upper and lower threshold voltage sepa- rated by a minimum amount of hysteresis. this external reset occurs whenever the reset pin is pulled below the lower threshold and remains in reset until the reset pin rises above the upper threshold. this active low input will generate the rst signal and reset the cpu and peripherals. this pin is also an output pin whenever the lvr triggers an internal reset. termination of the external reset input or the internal cop watchdog reset or lvr are the only reset sources that can alter the operating mode of the mcu. note activation of the rst signal is generally referred to as reset of the device, unless otherwise speci?d. 5.2 internal resets the four internally generated resets are the initial power-on reset function, the cop watchdog timer reset, the illegal address detector reset and the low voltage reset (lvr). termination of the external reset input or the internal cop watch- dog timer or lvr are the only reset sources that can alter the operating mode of the mcu. the other internal resets will not have any effect on the mode of opera- tion when their reset state ends. 5.2.1 power-on reset (por) the internal por is generated on power-up to allow the clock oscillator to stabi- lize. the por is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). there is an oscillator stabilizing delay after the oscillator becomes active. the delay time could be 224 or 4064 of internal processor bus clock cycles (ph2) which is a mask option. the por will generate the rst signal which will reset the cpu. if any other reset function is active at the end of this delay time, the rst signal will remain in the reset condition until the other reset condition(s) end. 5.2.2 computer operating properly reset (copr) the internal copr reset is generated automatically (if the cop is enabled) by a time-out of the cop watchdog timer. this time-out occurs if the counter in the cop watchdog timer is not reset (cleared) within a speci? time by a software reset sequence. the cop watchdog timer can be disabled by a mask option. refer to section 8.2 for more information on this time-out feature. cop reset also forces the reset pin low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification resets rev 2.1 5-3 the copr will generate the rst signal which will reset the cpu and other peripherals. also, the copr will establish the mode of operation based on the state of the irq pin at the time the copr signal ends. if the voltage on the irq pin is at the v tst level, the state of the pb0 pin during the last rising edge of the reset pin will determine which test mode (internal or expanded) the mcu will be in. if the voltage at the irq pin is in the normal operating range (v ss to v dd ), the mcu will enter single-chip mode when the copr signal ends. if any other reset function is active at the end of the copr reset signal, the rst signal will remain in the reset condition until the other reset condition(s) end. 5.2.3 low voltage reset (lvr) the internal lvr reset is generated when v dd falls below the speci?d lvr trig- ger value v lv r for at least one t cyc . in typical applications, the power supply de- coupling circuit will eliminate negative-going voltage glitches of less than one t cyc . this reset will hold the mcu in the reset state until v dd rises above v lv r . whenever v dd is above v lvr and below 4.5v, the mcu is guaranteed to operate although not within speci?ation. the output from the lvr is connected directly to the internal reset circuitry and also forces the reset pin low. the internal reset will be removed once the power supply voltage rises above v lv r , at which time a normal power-on-reset sequence occurs. 5.2.4 illegal address reset (iladr) the internal iladr reset is generated when an instruction opcode fetch occurs from an address which is not implemented in the ram ($0080 - $00ff) nor rom ($0300-$0cff, $0e00-$0fff). the iladr will generate the rst signal which will reset the cpu and other peripherals. if any other reset function is active at the end of the iladr reset signal, the rst signal will remain in the reset condition until the other reset condition(s) end. notice that iladr also forces the reset pin low. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 resets MC68HC05J5A 5-4 rev 2.1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification low power modes rev 2.1 6-1 section 6 low power modes there are three modes of operation that reduce power consumption: stop mode wait mode halt mode the wait and stop instructions provide two power saving modes by stopping various internal modules and/or the on-chip oscillator. the stop and wait instructions are not normally used if the cop watchdog timer is enabled. a mask option is provided to convert the stop instruction to a halt, which is a wait-like instruction that does not halt the cop watchdog timer but has a recovery delay. the ?w of the stop, halt, and wait modes are shown in figure 6-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 low power modes MC68HC05J5A 6-2 rev 2.1 figure 6-1. stop/halt/wait flowcharts 6.1 stop instruction the stop instruction can result in one of two modes of operation depending on the stop mask option chosen. one option is for the stop instruction to operate like the stop in normal mc68hc05 family members and place the device in the 1. fetch reset vector or 2. service interrupt a. stack b. set i-bit c. vector to interrupt routine wait stop conversion to halt? y n external reset? y n irq external interrupt? y n stop external oscillator, stop internal timer clock, reset startup delay restart external oscillator, start stabilization delay stop internal processor clock, clear i-bit in ccr, and set irqe in icsr end of stabilization delay? y n irq external interrupt? y n external oscillator active and internal timer clock active restart internal processor clock timer internal interrupt? y n external reset? y n stop halt external reset? y n irq external interrupt? y n external oscillator active and internal timer clock active timer internal interrupt? y n cop internal reset? y n cop internal reset? y n stop internal processor clock, clear i-bit in ccr, and set irqe in icsr stop internal processor clock, clear i-bit in ccr, and set irqe in icsr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification low power modes rev 2.1 6-3 stop mode. the other option is for the stop instruction to behave like a wait instruction (except that the restart time will involve a delay) and place the device in the halt mode. 6.1.1 stop mode execution of the stop instruction in this mode (selected by a mask option) places the mcu in its lowest power consumption mode. in the stop mode the internal oscillator is turned off, halting all internal processing, including the cop watchdog timer. when the cpu enters stop mode the interrupt ?gs (tof and rtif) and the interrupt enable bits (tofe and rtie) in the tcsr are cleared by internal hard- ware to remove any pending timer interrupt requests and to disable any further timer interrupts. execution of the stop instruction automatically clears the i-bit in the condition code register and sets the irqe enable bit in the irq control/sta- tus register so that the irq external interrupt is enabled. all other registers, including the other bits in the tcsr, and memory remain unaltered. all input/out- put lines remain unchanged. the mcu can be brought out of the stop mode only by an irq external interrupt or an externally generated reset or an lvr reset. when exiting the stop mode the internal oscillator will resume after a 224 or 4064 internal processor clock cycle oscillator stabilizing delay which is selected by a mask option. note execution of the stop instruction with the stop mode mask option will cause the oscillator to stop and therefore disable the cop watchdog timer. if the cop watchdog timer is to be used, the stop mode should be changed to the halt mode by choosing the appropriate mask option. see section 6.4 for more details. 6.1.2 halt mode execution of the stop instruction in this mode (selected by a mask option) places the mcu in a low-power mode, which consumes more power than the stop mode. in the halt mode the internal processor clock is halted, suspending all processor and internal bus activity. internal timer clocks remain active, permitting interrupts to be generated from the timer (mft or timer 1) or a reset to be gener- ated from the cop watchdog timer. execution of the stop instruction automati- cally clears the i-bit in the condition code register and sets the irqe enable bit in the irq control/status register so that the irq external interrupt is enabled. all other registers, memory, and input/output lines remain in their previous states. the halt mode may be terminated by a timer interrupt, an external irq, an lvr reset, or external reset occurs. since the internal timer is still running in the halt mode, the wake up delay timer (oscillator stabilizing delay timer) may start counting from an unknown value. so, the internal processor clock will resume f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 low power modes MC68HC05J5A 6-4 rev 2.1 after a varied delay time which is from one to 224 or 4064 internal processor clock cycles (the por delay time). the halt mode is not intended for normal use, but is provided to keep the cop watchdog timer active should the stop instruction opcode be inadvertently executed. 6.2 wait instruction the wait instruction places the mcu in a low-power mode, which consumes more power than the stop mode. in the wait mode the internal processor clock is halted, suspending all processor and internal bus activity. internal timer clocks remain active, permitting interrupts to be generated from the timer or a reset to be generated from the cop watchdog timer. execution of the wait instruction auto- matically clears the i-bit in the condition code register and sets the irqe enable bit in the irq control/status register so that the irq external interrupt is enabled. all other registers, memory, and input/output lines remain in their previous states. if timer (mft or timer 1) interrupts are enabled, a timer interrupt will cause the processor to exit the wait mode and resume normal operation. the timer may be used to generate a periodic exit from the wait mode. the wait mode may also be exited when an external irq or an lvr reset or an external reset occurs. 6.3 data-retention mode if the lvr mask option is selected and since lvr kicks in whenever v dd is below the speci?d lvr trigger voltage which is higher than that required of the data retention mode, the data retention mode will not exist. data retention mode is only meaningful if lvr mask option is not selected. the contents of ram and cpu registers are retained at supply voltage as low as 2.0 vdc. this is called the data-retention mode where the data is held, but the device is not guaranteed to operate. the reset pin must be held low during data-retention mode. 6.4 cop watchdog timer considerations the cop watchdog timer is active in all modes of operation if enabled by a mask option. thus, emulation of applications that do not service the cop should only be done with devices that have the cop mask option disabled. if the cop watchdog timer is selected by the mask option, any execution of the stop instruction (either intentional or inadvertent due to the cpu being dis- turbed) will cause the oscillator to halt and prevent the cop watchdog timer from timing out unless the stop to halt conversion feature is enabled. therefore, it is recommended that the stop instruction should be converted to a halt instruc- tion if the cop watchdog timer is enabled. if the cop watchdog timer is selected by the mask option, the cop will reset the mcu when it times out. therefore, it is recommended that the cop watchdog should be disabled for a system that must have intentional uses of the wait mode for periods longer than the cop time-out period. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification low power modes rev 2.1 6-5 the recommended interactions and considerations for the cop watchdog timer, stop instruction, and wait instruction are summarized in table 6-1 . table 6-1. cop watchdog timer recommendations wait time less than cop time-out stop instruction wait time then the cop watchdog timer should be as follows: disable cop by mask option converted to halt by mask option enable or disable cop by mask option wait time more than cop time-out any length wait time acts as stop disable cop by mask option converted to halt by mask option if the following conditions exist: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 low power modes MC68HC05J5A 6-6 rev 2.1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification input/output ports rev 2.1 7-1 section 7 input/output ports in the normal operating mode there are 14 usable bidirectional i/o lines arranged as one 8-bit i/o port (port a), and one 6-bit i/o port (port b). the individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (ddrs). also, if enabled by a single mask option all port a and port b i/o pins may have individual software programmable pull-down or pull-up devices. also, pa4-pa7 and pb1-pb2 pins have high current sink capa- bility; pa0-pa3 may function as additional irq interrupt input sources. note that both pa6 and pa7 pins have schmitt trigger input for better noise immunity. v ih and v il speci?d at 2.4v and 0.8v, respectively. the four port pins, pb2-pb5 are only available on the 20-pin version of the device. 7.1 slow output falling-edge transition figure 7-1. port b data direction register slowe - slow transition enable the slow transition feature is controlled by the slowe bit of ddrb (port b data direction register). 1 = enables the slow falling-edge output transition feature on the four i/ o lines: pa6, pa7, pb1, and pb2. if the pin is con?ured as an output pin. 0 = disables slow falling-edge output transition feature on the four i/o lines: pa6, pa7, pb1, and pb2. default value of slowe bit is cleared. 7.2 port a port a is a 8-bit bidirectional port which shares ?e of its pins with the irq inter- rupt system as shown in figure 7-2 . note that both pa6 and pa7 pins have schmitt trigger input for better noise immunity. only the pa6 and pa7 pins are open-drained type with slow output transition feature. 0 ddrb0 ddrb $0005 0 7 w r 0000000 reset t 6543210 slowe ddrb1 ddrb2 ddrb3 ddrb4 ddrb5 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 input/output ports MC68HC05J5A 7-2 rev 2.1 each port a pin is controlled by the corresponding bits in a data direction register, a data register and a pulldown/up register. the port a data register is located at address $0000. the port a data direction register (ddra) is located at address $0004. the port a pulldown/up register (pdura) is located at address $0010. reset operation will clear the ddra and the pdura. the port a data register is unaffected by reset. figure 7-2. port a i/o circuitry 7.2.1 port a data register each port a i/o pin has a corresponding bit in the port a data register. when a port a pin is programmed as output, the corresponding data register bit deter- mines the logic state of that pin. when a port a pin is programmed as input, any read from the port a data register will return the logic state of the corresponding i/o pin. the port a data register is unaffected by reset. 7.2.2 port a data direction register each port a i/o pin may be programmed as input by clearing the corresponding bit in the ddra, or programmed as output by setting the corresponding bit in the ddra. the ddra can be accessed at address $0004. the ddra is cleared by reset. if con?ured as output pins, pa6 and pa7 have slow output falling-edge transition feature. the slow transition feature is controlled by the slowe bit of ddrb. slowe bit, if set and if the pin is con?ured as an output pin, enables the slow falling-edge output transition feature of all four i/o lines, pa6, pa7, pb1, and pb2. write $0010 100 m a pulldown read $0000 write $0000 read $0004 data register bit pa0-pa3 and pa7 only: to irq interrupt system 8 ma sink capability (bits 4-7 only) i/o pin output mask option (software pulldown/up inhibit) internal hc05 data bus reset (rst) write $0004 data direction register bit pulldown/up register bit vdd 5k pullup note1: all the i/o port pins may have either pullup or pulldown device. note2: pa6 and pa7 output drivers are the open-drained type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification input/output ports rev 2.1 7-3 7.2.3 port a pulldown/up register all port a i/o pins may have software programmable pulldown/up devices enabled by the applicable mask option. if the pulldown/up mask option is selected, the pull- down/up is activated whenever the corresponding bit in the pdura is clear. if the corresponding bit in the pdura bit is set or the mask option for pulldown/up is not chosen, the pulldown/up will be disabled. a pulldown on an i/o pin is activated only if the i/o pin is programmed as an input whereas a pullup device on an i/o pin is always activated whenever enabled, regardless of port direction. the pdura is a write-only register. any reads of location $0010 will return unde- ?ed results. since reset clears both the ddra and the pdura, all pins will ini- tialize as inputs with the pulldown active and pullup devices active (if enabled by mask option). typical value of port a pullup is 5k w . 7.2.4 port a drive capability the outputs for the upper four bits of port a (pa4, pa5, pa6 and pa7) are capable of sinking approximately 8ma of current to v ss . 7.2.5 port a i/o pin interrupts the inputs to pa0, pa1, pa2, pa3 may be connected to the irq input of the cpu if enabled by a mask option. the input to pa7 is also connected to the irq input of the cpu, yet it is only enabled or disabled by software, not by mask option. pa7 interrupt capability is controlled by a set of control and status bits (irqe1, irqf1, irqr1), different from the set of control and status bits for that of pa0-pa3 and irq pin (irqe, irqf, irqr) in the same icsr (interrupt control and status reg- ister). when connected as an alternate source of an irq interrupt, pa0-3 input pins will behave the same as the irq pin itself, except that their active state is a logical one or a rising edge. the irq pin has an active state that is a logical zero or a falling edge. pa7 interrupt occurs, if enabled, only upon the falling edge at the input. if mask options for both level and edge sensitivity interrupts are chosen, the pres- ence of a logic one or occurrence of a rising edge on any one of the lower four port a pins will cause an irq interrupt request. if the edge-only sensitivity is selected, the occurrence of a rising edge on any one of the lower four port a pins will cause an irq interrupt request. as long as any one of the lower four port a irq inputs remains at a logic one level, the other of the lower four port a irq inputs are effectively ignored. note the bih and bil instructions will only apply to the level on the irq pin itself, and not to the internal irq input to the cpu. therefore bih and bil cannot be used to test the state of the lower four port a input pins as a group nor that of pa7. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 input/output ports MC68HC05J5A 7-4 rev 2.1 7.3 port b port b is a 6-bit bidirectional port which functions as shown in figure 7-3 . only pb1 and pb2 are of open-drained type. each port b pin is controlled by the corre- sponding bits in a data direction register, a data register and a pulldown/up regis- ter. the port b data register is located at address $0001. the port b data direction register (ddrb) is located at address $0005. the port b pulldown/up register (pdurb) is located at address $0011. reset clears the ddrb and the pdurb. the port b data register is unaffected by reset. please note that only pb0 and pb1 pins are bonded out in the 16-pin package type. actually, the pb1 and pb2 i/o port lines are short and bonded to the pb1 on the 16-pin package. both pb1 and pb2 are of open-drained type, capable of typi- cally sinking 25ma current at v ol 0.5v max. in order to constitute a single pin capable of typically sinking 50ma, both pb1 and pb2 have to be written with the same value at the same write cycle. figure 7-3. port b i/o circuitry port pin pb0 is shared with tcap input of the 16-timer input capture function. the input capture function can be programmed for a positive edge or the negative edge tcap input. when an expected edge is generated on this pin, the counter value at that moment will be captured into a capture register. for the details about this feature please refer to the section 9 . 7.3.1 port b data register all port b i/o pins have a corresponding bit in the port b data register. when a port b pin is programmed as output the corresponding data register bit determines the logic state of the output pin. when a port b pin is programmed as input, any read from the port b data register will return the logic state of the write $0011 read $0001 write $0001 read $0005 write $0005 internal hc05 data bus 100 m a pulldown data register bit i/o pin output mask option (software pulldown/up inhibit) reset (rst) data direction register bit pulldown/up register bit vdd 30k pullup note1: all the i/o port pins may have either pullup or pulldown device. note2: pb1 and pb2 output drivers are the open-drained type f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification input/output ports rev 2.1 7-5 corresponding i/o pin. the port b data register is unaffected by reset. unused bits 6 and 7 will always read as logic zeros, and any write to these bits will be ignored. the port b data register is unaffected by reset. 7.3.2 port b data direction register port b i/o pins may be programmed as an input by clearing the corresponding bit in the ddrb, or programmed as an output by setting the corresponding bit in the ddrb. the ddrb can be accessed at address $0005. unused bits 6 and 7 will always read as logic zeros, and any write to these bits will be ignored.the ddrb is cleared by reset. if con?ured as output pins, pb1 and pb2 have slow output falling-edge transition feature. the slow transition feature is controlled by the slowe bit of ddrb. slowe bit, if set and if the pin is con?ured as an output pin, enables the slow falling-edge output transition feature of all four i/o lines, pa6, pa7, pb1 and pb2. for the 16-pin package type, care should be taken in using pb1 pin, which is bonded to two internal port b i/o lines pb1 and pb2, to constitute a 50ma current sinking driver. both pb1 and pb2 i/o lines are capable of sinking 25ma. if they are written with the same logic 0 value in the same write cycle, pb1 pin will sink 50 ma. if they are written with different values in the same write cycle, pb1 pin will sink only 25ma. for the 20-pin package type, i/o lines pb1 and pb2 are not bonded to the same pin. hence, to constitute a 50ma current sinking driver, pb1 and pb2 pins have to be tied together externally and controlled in the same way as in the16-pin pack- age type case. also, if the slow transition feature of pin pb1 is enabled, a combination of i/o lines pb1 and pb2, is also a combination of slow transition features of i/o lines pb1 and pb2. pb2 line falling-edge output transition occurs t cyc /2 after the write cycle, with a standard i/o edge transition time. whereas for pb1 line, the falling- edge transition occurring immediately after the write cycle, but with an edge tran- sition time slower than standard i/os, similar to pa6 and pa7 pins. the net result is, for the 16-pin package type, since both pb1 and pb2 i/o lines are bonded to the same pb1 pin, the combination of delayed pb1 line sharp-edge output and the non-delayed slow transition output yields the desired slow output falling-edge transition. for the 20-pin package, pb1 and pb2 pins should be tied externally to create a driver with the desired slow output falling-edge transition feature. if slowe is set and pb2 pin is not tied to pb1 pin, be advised that the output at pb2 changes state t cyc /2 after the write cycle. 7.3.3 port b pulldown/up register all port b i/o pins may have software programmable pulldown/up devices enabled by a mask option. if the pulldown/up mask option is selected, the pulldown/up is activated whenever the corresponding bit in the pdurb is clear. a pulldown on an f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 input/output ports MC68HC05J5A 7-6 rev 2.1 i/o pin is activated only if the i/o pin is programmed as an input whereas a pullup device on an i/o pin is always activated whenever enabled, regardless of port direction. the pdurb is a write-only register. any reads of location $0011 will return unde- ?ed results. since reset clears both the ddrb and the pdurb, all pins will ini- tialize as inputs with the pulldown devices active and pullup devices active (if chosen via mask option). typical value of port b pullup is 30k w . 7.4 i/o port programming all i/o pins can be programmed as inputs or outputs, with or without pulldown/up devices. 7.4.1 pin data direction the direction of a pin is determined by the state of its corresponding bit in the associated port data direction register (ddr). a pin is con?ured as an output if its corresponding ddr bit is set to a logic one. a pin is con?ured as an input if its corresponding ddr bit is cleared to a logic zero. the data direction bits ddrb0-ddrb5 and ddra0-ddra7 are read/write bits which can be manipulated with read-modify-write instructions. at power-on or reset, all ddrs are cleared which con?ures all port pins as inputs. if the pull- down/up mask option is chosen, all pins will initially power-up with their software programmable pulldowns/ups enabled. 7.4.2 output pin when an i/o pin is programmed as an output pin, the state of the corresponding data register bit will determine the state of the pin. the state of the data register bits can be altered by writing to address $0000 for port a and address $0001 for port b. reads of the corresponding data register bit at address $0000 or $0001 will return the state of the data register bit (not the state of the i/o pin itself). therefore bit manipulation is possible on all pins programmed as outputs. if the corresponding bit in the pulldown/up register is clear (and the pulldown/up mask option is chosen), only output pins with pullups have an activated pullup device connected to the pin. for those pins with pulldowns and con?ured as out- put pins, the pulldowns will be inactivated regardless of the state of the corre- sponding pulldown/up register bit. since the pulldown/up register bits are write- only, bit manipulation should not be used on these register bits. 7.4.3 input pin when an i/o pin is programmed as an input pin, the state of the pin can be deter- mined by reading the corresponding data register bit. any writes to the corre- sponding data register bit for an input pin will be ignored in the sense that the written value will not be re?cted on the pin, rather it is only re?cted in the port data register. please refer to table 7-1 and table 7-2 for details. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification input/output ports rev 2.1 7-7 if the corresponding bit in the pulldown/up register is clear (and the pulldown/up mask option is chosen) the input pin will also have an activated pulldown/up device. since the pulldown/up register bits are write-only, bit manipulation should not be used on these register bits. 7.4.4 i/o pin transitions a "glitch" can be generated on an i/o pin when changing it from an input to an out- put unless the data register is ?st preconditioned to the desired state before changing the corresponding ddr bit from a zero to a one. if pulldowns are enabled by mask option, a ?ating input can be avoided by clear- ing the pulldown/up register bit before changing the corresponding ddr from a one to a zero. this will insure that the pulldown device will be activated before the i/o pin changes from a driven output to a pulled low/high input. 7.4.5 i/o pin truth tables every pin on port a and port b may be programmed as an input or an output under software control as shown in table 7-1 and table 7-2 . all port i/o pins may also have software programmable pulldown/up devices if selected by the appropri- ate mask option. table 7-1. port a i/o pin functions table 7-2. port b i/o pin functions accesses to pdura at $0010 accesses to data register @ $0000 0 1 in, hi-z out pdura0-7 pdura0-7 ddra0-7 ddra0-7 i/o pin pa0-7 * pa0-7 u u i/o pin mode ddra read/write accesses to ddra @ $0004 read write read write * does not affect input, but stored to data register u is undefined accesses to pdurb at $0011 accesses to data register @ $0001 0 1 in, hi-z out pdurb0-2 pdurb0-2 ddrb0-2 ddrb0-2 i/o pin pb0-5 * pb0-5 u u i/o pin mode ddra read/write accesses to ddrb @ $0005 read write read write * does not affect input, but stored to data register u is undefined f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 input/output ports MC68HC05J5A 7-8 rev 2.1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification multi-function timer rev 2.1 8-1 section 8 multi-function timer the multi-function timer module is a 15-stage ripple counter with timer over flow (tof), real time interrupt (rti), cop watchdog, and the power-on reset delay function. figure 8-1. multi-function timer block diagram to reset logic cop clear mc68hc05 internal bus $09 tcr 7-bit counter interrupt circuit $08 tcsr rti select circuit overflow circuit detect cop watchdog resetable timer to interrupt logic 8 8 f op /2 2 f op /2 10 por tcbp tcsr tcr internal timer clock (ntf1) tof rtif tofe rtie rt1 rt0 rtifr tofr timer control & status register timer counter register (tcr) ? 4 f op /2 8 mux f op /2 12 ? 14 ? 15 ? 17 ? 16 (8) oscdly (mask option) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 multi-function timer MC68HC05J5A 8-2 rev 2.1 8.1 overview as shown in figure 8-1 , the timer is driven by the timer clock, ntf1, divided by four. ntf1 has the same phase and frequency as the processor bus clock, ph2, but is not stopped by the wait or halt modes. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the timer counter register (tcr) at address $09. a timer over?w function is implemented on the last stage of this counter, giving a possible inter- rupt at the rate of f op /1024. the por function is generated at f op /224 stage or at f op /4064 stage, which is selected by a mask option. the last stage of the 8-bit counter also drives a further 7-bit counter. the ?al four stages is used by the rti circuit, giving possible rti rates of f op /2 14 , f op /2 15 , f op /2 16 or f op /2 17 , selected by rt1 and rt0 (see table 8-1 ). the rti rate selec- tor bits, and the rti and tof enable bits and ?gs are located in the timer con- trol and status register at location $08. the power-on cycle clears the entire counter chain and begins clocking the counter. after 224 or 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and nor- mal device operation will begin. if reset is asserted at any time during operation the counter chain will be cleared. 8.2 computer operating properly (cop) watchdog the cop watchdog is enabled by a mask option. the cop watchdog timer function is implemented by using the output of the rti circuit and further dividing it by eight. the minimum cop reset rates are listed in table 8-1 . if the cop circuit times out, an internal reset is generated and the nor- mal reset vector is fetched. preventing a cop time-out is done by writing a ? to bit-0 of address $0ff0. when the cop is cleared, only the ?al divide by eight stage (output of the rti) is cleared. figure 8-2. cop watchdog timer location 8.3 mft registers the 15-stage multi-function timer contains two registers: a timer counter regis- ter and a timer control/status register. 7 w r 6543210 cop $0ff0 copr reading $0ff0 returns the contents of test rom. unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification multi-function timer rev 2.1 8-3 8.3.1 timer counter register (tcr) $09 the timer counter register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked at f op divided by 4 and can be used for various functions including a soft- ware input capture. extended time periods can be attained using the tof function to increment a temporary ram storage location thereby simulating a 16-bit (or more) counter. the value of each bit of the tcr is shown in figure 8-3 . this reg- ister is cleared by reset. figure 8-3. timer counter register 8.3.2 timer control/status register (tcsr) $08 the tcsr contains the timer interrupt ?g bits, the timer interrupt enable bits, and the real time interrupt rate select bits. bit 2 and bit 3 are write-only bits which will read as logical zeros. figure 8-4 shows the value of each bit in the tcsr follow- ing reset. figure 8-4. timer control/status register (tcsr) tof - timer over?w flag the tof is a read-only ?g bit. 1 = set when the 8-bit ripple counter rolls over from $ff to $00. a timer interrupt request will be generated if tofe is also set. 0 = reset by writing a logical one to the tof acknowledge bit, tofr. writing to the tof ?g bit has no effect on its value. this bit is cleared by reset. tcr $09 0 7 w r 0000000 reset t 6543210 tmr0 tmr2 tmr1 tmr3 tmr4 tmr5 tmr6 tmr7 rtif tofe 0 7 tof rt1 w r 0000011 6543210 tcsr $08 reset t 0 rtifr 0 tofr rtie rt0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 multi-function timer MC68HC05J5A 8-4 rev 2.1 rtif - real time interrupt flag the rtif is a read-only ?g bit. 1 = set when the output of the chosen (1 of 4 selections) real time interrupt stage goes active. a timer interrupt request will be generated if rtie is also set. 0 = reset by writing a logical one to the rtif acknowledge bit, rtifr. writing to the rtif ?g bit has no effect on its value. this bit is cleared by reset. tofe - timer over?w enable the tofe is an enable bit that allows generation of a timer interrupt upon over?w of the timer counter register. 1 = when set, the timer interrupt is generated when the tof ?g bit is set. 0 = when cleared, no timer interrupt caused by tof bit set will be generated. this bit is cleared by reset. rtie - real time interrupt enable the rtie is an enable bit that allows generation of a timer interrupt by the rtif bit. 1 = when set, the timer interrupt is generated when the rtif ?g bit is set. 0 = when cleared, no timer interrupt caused by rtif bit set will be generated. this bit is cleared by reset. tofr - timer over?w acknowledge the tofr is an acknowledge bit that resets the tof ?g bit. this bit is unaf- fected by reset. reading the tofr will always return a logical zero. 1 = clears the tof ?g bit. 0 = does not clear the tof ?g bit. rtifr - real time interrupt acknowledge the rtifr is an acknowledge bit that resets the rtif ?g bit. this bit is unaf- fected by reset. reading the rtifr will always return a logical zero. 1 = clears the rtif ?g bit. 0 = does not clear the rtif ?g bit. rt1, rt0 - real time interrupt rate select the rt0 and rt1 control bits select one of four taps for the real time interrupt circuit. table 8-1 shows the available interrupt rates for two f op values. both the rt0 and rt1 control bits are set by reset, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. care should be taken when altering rt0 and rt1 if the time-out period is imminent or uncertain. if the selected tap is modi?d during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. to avoid problems, the cop should be cleared just prior to changing rti taps. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification multi-function timer rev 2.1 8-5 8.4 operation during stop mode the timer system is cleared when going into stop mode. when stop is exited by an external interrupt or an lvr reset or an external reset , the internal oscilla- tor will resume, followed by a 224 (or 4064) internal processor oscillator stabilizing delay. the timer system counter is then cleared and operation resumes. if chosen by a mask option, the stop instruction will initiate halt mode and the effects on the timer are as described in section 8.5 . 8.5 operation during wait/halt mode the cpu clock halts during the wait/halt mode, but the timer remains active. if interrupts are enabled, a timer interrupt or custom periodic interrupt will cause the processor to exit the wait/halt mode. table 8-1. rti rates and cop reset times rt1 rt0 rti rates at f op freq. specified: min. cop reset at f op freq. specified: divider 1mhz 2mhz divider 1mhz 2mhz 00 16384 16.384ms 8.192ms 131072 131ms 66ms 01 32768 32.768ms 16.384ms 262144 262ms 131ms 10 65536 65.536ms 32.768ms 524288 524ms 262ms 11 131072 131.072ms 65.536ms 1048576 1059ms 524ms f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 multi-function timer MC68HC05J5A 8-6 rev 2.1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification 16-bit timer rev 2.1 9-1 section 9 16-bit timer this 16-bit timer (timer1) is a programmable timer with an input capture function. figure 9-1 shows a block diagram of the 16-bit programmable timer. figure 9-1. 16-bit timer block diagram iedg icie t1oie tcnth ($18) tcntl ($19) 16-bit counter ? 4 internal (f osc ? 2) timer1 control register timer1 request overflow (t1of) reset clock interrupt acnth ($1a) acntl ($1b) edge select & detect icf t1of timer1 status register iedg icf $12 $13 internal data bus logic ich ($14) icl ($15) pb0/ tcap signal conditioning tcaps (bit 7 at $02) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 16-bit timer MC68HC05J5A 9-2 rev 2.1 the basis of the 16-bit timer is a 16-bit free-running counter which increases in count with each internal bus clock cycle. the counter is the timing reference for the input capture and output compare functions. the input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. software can read the value in the 16-bit free-running counter at any time without affect the counter sequence. because of the 16-bit timer architecture, the i/o registers are pairs of 8-bit regis- ters. each register pair contains the high and low byte of that function. generally, accessing the low byte of a speci? timer function allows full control of that func- tion; however, an access of the high byte inhibits that speci? timer function until the low byte is also accessed. because the counter is 16 bits long and preceded by a ?ed divide-by-four pres- caler, the counter rolls over every 262,144 internal clock cycles. timer resolution with a 4mhz crystal oscillator is 2 microsecond/count. the interrupt capability and the input capture edge are controlled by the timer con- trol register (t1cr) located at $0012 and the status of the interrupt ?gs can be read from the timer status register (t1sr) located at $0013. 9.1 timer1 counter registers (tcnth, tcntl) the functional block diagram of the 16-bit free-running timer counter and timer registers is shown in figure 9-2 . the timer registers include a transparent buffer latch on the lsb of the 16-bit timer counter. figure 9-2. 16-bit timer counter block diagram t1oie tcnth ($18) tcntl lsb 16-bit counter ? 4 internal (f osc ? 2) timer1 control reg. timer1 request overflow (t1of) reset clock interrupt tcntl ($19) t1of timer1 status reg. $12 $13 internal ($fffc) data read tcnth read tcntl read latch bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification 16-bit timer rev 2.1 9-3 the timer counter registers (tcnth, tcntl) shown in figure 9-3 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. writing to the timer registers has no effect. reset of the device presets the timer counter to $fffc. the tcntl latch is a transparent read of the lsb until the a read of the tcnth takes place. a read of the tcnth latches the lsb into the tcntl location until the tcntl is again read. the latched value remains ?ed even if multiple reads of the tcnth take place before the next read of the tcntl. therefore, when read- ing the msb of the timer at tcnth the lsb of the timer at tcntl must also be read to complete the read sequence. during power-on-reset (por), the counter is initialized to $fffc and begins counting after the oscillator start-up delay. because the counter is 16 bits and pre- ceded by a ?ed divide-by-four prescaler, the value in the counter repeats every 262, 144 internal bus clock cycles (524, 288 oscillator cycles). when the free-running counter rolls over from $ffff to $0000, the timer over?w ?g bit (t1of) is set in the t1sr. when the t1of is set, it can generate an inter- rupt if the timer over?w interrupt enable bit (t1oie) is also set in the t1cr. the t1of ?g bit can only be reset by reading the tcntl after reading the t1sr. other than clearing any possible t1of ?gs, reading the tcnth and tcntl in any order or any number of times does not have any effect on the 16-bit free-run- ning counter. note to prevent interrupts from occurring between readings of the tcnth and tcntl, set the i bit in the condition code register (ccr) before reading tcnth and clear the i bit after reading tcntl. 9.2 alternate counter registers (acnth, acntl) the functional block diagram of the 16-bit free-running timer counter and alternate counter registers is shown in figure 9-4 . the alternate counter registers behave the same as the timer counter registers, except that any reads of the alternate bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcnth r bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 $0018 w reset: 11111111 tcntl r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0019 w reset: 11111100 figure 9-3. 16-bit timer counter registers (tcnth, tcntl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 16-bit timer MC68HC05J5A 9-4 rev 2.1 counter will not have any effect on the t1of ?g bit and timer interrupts. the alternate counter registers include a transparent buffer latch on the lsb of the 16- bit timer counter. figure 9-4. alternate counter block diagram the alternate counter registers (acnth, acntl) shown in figure 9-5 are read- only locations which contain the current high and low bytes of the 16-bit free-run- ning counter. writing to the alternate counter registers has no effect. reset of the device presets the timer counter to $fffc. the acntl latch is a transparent read of the lsb until the a read of the acnth takes place. a read of the acnth latches the lsb into the acntl location until the acntl is again read. the latched value remains ?ed even if multiple reads of the acnth take place before the next read of the acntl. therefore, when read- ing the msb of the timer at acnth the lsb of the timer at acntl must also be read to complete the read sequence. during power-on-reset (por), the counter is initialized to $fffc and begins counting after the oscillator start-up delay. because the counter is 16 bits and pre- ceded by a ?ed divide-by-four prescaler, the value in the counter repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles). reading the acnth and acntl in any order or any number of times does not have any effect on the 16-bit free-running counter or the t1of ?g bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 acnth r bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 $001a w reset: 11111111 acntl r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $001b w reset: 11111100 figure 9-5. alternate counter registers (acnth, acntl) acnth ($1a) tmr lsb 16-bit counter ? 4 internal (f osc ? 2) reset clock acntl ($1b) internal ($fffc) data read acnth read acntl read latch bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification 16-bit timer rev 2.1 9-5 note to prevent interrupts from occurring between readings of the acnth and acntl, set the i bit in the condition code register (ccr) before reading acnth and clear the i bit after reading acntl. 9.3 input capture registers figure 9-6. timer input capture block diagram the input capture function is a technique whereby an external signal (connected to pb0/tcap pin) is used to trigger the 16-bit timer counter. in this way it is possi- ble to relate the timing of an external signal to the internal counter value, and hence to elapsed time. note since the tcap pin is shared with the pb0 i/o pin, changing the state of the pb0 ddr or data register can cause an unwanted tcap interrupt. this can be avoided by clearing the icie bit before changing the con?uration of pb0, and clearing any pending interrupts before enabling icie. the signal on the tcap pin is ?st directed to a schmitt trigger or a voltage comparator as shown in figure 9-8 . setting the tcaps bit to ? will enable the comparator and the v dd /2 reference voltage. icie ich ($14) 16-bit counter ? 4 internal (f osc ? 2) timer1 control reg. timer1 request input capture (icf) reset clock interrupt icl ($15) icf timer1 status reg. $12 $13 internal ($fffc) data read ich read icl latch bus iedg edge select & detect logic iedg internal data bus signal conditioning pb0/ tcap tcaps (bit7 at $02) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 16-bit timer MC68HC05J5A 9-6 rev 2.1 figure 9-7. timer1 capture control register tcaps ?timer input capture comparator enable 1 = timer input capture comparator is selected. 0 = timer input capture comparator schmitt trigger is selected. note when the comparator and v dd /2 reference are enabled, pb0 pin will automatically becomes an input pin, irrespective of ddr setting. however, it is recommended to set pb0 as an input ?st (via ddr), before enabling the comparator. a read of pb0 will re?ct the tcap pin status, not the pb0 register bit. the comparator uses the v dd /2 reference as the compare voltage, resulting in a typical output as shown in figure 9-9 . switching off the v dd /2 voltage reference by clearing tcaps=0 will further save power when the mcu is in a low power mode. figure 9-8. tcap input signal conditioning bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1cc r tcaps $0002 w reset: 00000000 + mux pb0/ tcap voltage reference v ref en pb0 i/o port logic tcaps bit v dd ?2 schmitt trigger comparator to edge select and detect logic f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification 16-bit timer rev 2.1 9-7 figure 9-9. tcap input comparator output when the input capture circuitry detects an active edge on the tcap pin, it latches the contents of the free-running timer counter registers into the input cap- ture registers as shown in figure 9-6 . latching values into the input capture registers at successive edges of the same polarity measures the period of the selected input signal. latching the counter val- ues at successive edges of opposite polarity measures the pulse width of the sig- nal. the input capture registers are made up of two 8-bit read-only registers (ich, icl) as shown in figure 9-10 . the input capture edge detector contains a schmitt trig- ger to improve noise immunity. the edge that triggers the counter transfer is de?ed by the input edge bit (iedg) in the t1cr. reset does not affect the con- tents of the input capture registers. the result obtained by an input capture will be one count higher than the value of the free-running timer counter preceding the external transition. this delay is required for internal synchronization. resolution is affected by the prescaler, allowing the free-running timer counter to increment once every four internal clock cycles (eight oscillator clock cycles). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ich r bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 $0014 w reset: uuuuuuuu icl r bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0015 w reset: uuuuuuuu u = unaffected by reset figure 9-10. input capture registers (ich, icl) v dd ?2 v dd output of comparator signal on tcap pin time f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 16-bit timer MC68HC05J5A 9-8 rev 2.1 reading the ich inhibits further captures until the icl is also read. reading the icl after reading the timer status register (t1sr) clears the icf ?g bit. does not inhibit transfer of the free-running counter. there is no con?ct between reading the icl and transfers from the free-running timer counters. the input capture reg- isters always contain the free-running timer counter value which corresponds to the most recent input capture. note to prevent interrupts from occurring between readings of the ich and icl, set the i bit in the condition code register (ccr) before reading ich and clear the i bit after reading icl. 9.4 timer1 control register (t1cr) the timer control register is shown in figure 9-11 performs the following func- tions: enables input capture interrupts enables output compare interrupts enables timer over?w interrupts control the active edge polarity of the tcap signal on pin pb0/tcap reset clears all the bits in the t1cr with the exception of the iedg bit which is unaffected. icie - input capture interrupt enable this read/write bit enables interrupts caused by an active signal on the pb0/ tcap pin. reset clears the icie bit. 1 = input capture interrupts enabled. 0 = input capture interrupts disabled. t1oie - timer overflow interrupt enable this read/write bit enables interrupts caused by a timer1 over?w. reset clears the t1oie bit. 1 = timer1 over?w interrupts enabled. 0 = timer1 over?w interrupts disabled. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1cr r icie 0 t1oie 000 iedg 0 $0012 w reset: 000000u0 u = unaffected by reset figure 9-11. timer control register (t1cr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification 16-bit timer rev 2.1 9-9 iedg - input capture edge select the state of this read/write bit determines whether a positive or negative transi- tion on the tcap pin triggers a transfer of the contents of the timer register to the input capture register. reset has no effect on the iedg bit. 1 = positive edge (low to high transition) triggers input capture. 0 = negative edge (high to low transition) triggers input capture. 9.5 timer1 status register (t1sr) the timer status register (t1sr) shown in figure 9-12 contains ?gs for the fol- lowing events: an active signal on the pb0/tcap pin, transferring the contents of the timer registers to the input capture registers. an over?w of the timer registers from $ffff to $0000. writing to any of the bits in the t1sr has no effect. reset does not change the state of any of the ?g bits in the t1sr. icf - input capture flag the icf bit is automatically set when an edge of the selected polarity occurs on the pb0/tcap pin. clear the icf bit by reading the timer status register with the icf set, and then reading the low byte (icl, $0015) of the input capture registers. reset has no effect on icf. t1of - timer1 overflow flag the t1of bit is automatically set when the 16-bit timer counter rolls over from $ffff to $0000. clear the t1of bit by reading the timer status register with the t1of set, and then accessing the low byte (tcntl, $0019) of the timer registers. reset has no effect on t1of. 9.6 timer1 operation during wait mode during wait mode the 16-bit timer continues to operate normally and may gener- ate an interrupt to trigger the mcu out of the wait mode. 9.7 timer1 operation during stop mode when the mcu enters the stop mode the free-running counter stops counting (the internal processor clock is stopped). it remains at that particular count value until the stop mode is exited by applying a low signal to the irq pin, at which bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1sr r icf 0 t1of 00000 $0013 w reset: u u u 00000 u = unaffected by reset figure 9-12. timer status registers (t1sr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 16-bit timer MC68HC05J5A 9-10 rev 2.1 time the counter resumes from its stopped value as if nothing had happened. if stop mode is exited via an external reset (logic low applied to the reset pin) the counter is forced to $fffc. if a valid input capture edge occurs at the pb0/tcap pin during the stop mode the input capture detect circuitry will be armed. this action does not set any ?gs or ?ake up the mcu, but when the mcu does ?ake up there will be an active input capture ?g (and data) from the ?st valid edge. if the stop mode is exited by an external reset, no input capture ?g or data will be present even if a valid input capture edge was detected during the stop mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification instruction set rev 2.1 10-1 section 10 instruction set this section describes the addressing modes and instruction types. 10.1 addressing modes the cpu uses eight addressing modes for ?xibility in accessing data. the addressing modes de?e the manner in which the cpu ?ds the data required to execute an instruction. the eight addressing modes are the following: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative 10.1.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry ?g (sec) and increment accumulator (inca). inherent instructions require no memory address and are one byte long. 10.1.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no memory address and are two bytes long. the opcode is the ?st byte, and the immediate data value is the second byte. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 instruction set MC68HC05J5A 10-2 rev 2.1 10.1.3 direct direct instructions can access any of the ?st 256 memory addresses with two bytes. the ?st byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. brset and brclr are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. 10.1.4 extended extended instructions use only three bytes to access any address in memory. the ?st byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. 10.1.5 indexed, no offset indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the ?st 256 memory locations. the index register contains the low byte of the conditional address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000?00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 10.1.6 indexed, 8-bit offset indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the ?st 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the conditional address of the operand. these instructions can access locations $0000?01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the ?st 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification instruction set rev 2.1 10-3 10.1.7 indexed, 16-bit offset indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the conditional address of the operand. the ?st byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. these instructions can address any location in memory. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. 10.1.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu ?ds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, twos complement byte that gives a branching range of ?28 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and veri?s that it is within the span of the branch. 10.1.9 instruction types the mcu instructions fall into the following ?e categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 instruction set MC68HC05J5A 10-4 rev 2.1 10.1.10 register/memory instructions most of these instructions use two operands. one operand is in either the accumulator or the index register. the cpu ?ds the other operand in memory. table 10-1 lists the register/memory instructions. table 10-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification instruction set rev 2.1 10-5 10.1.11 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modi?d value back to the memory location or to the register. the test for negative or zero instruction (tst) is an exception to the read-modify-write sequence because it does not write a replacement value. table 10-2 lists the read-modify-write instructions. 10.1.12 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump to subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. all branch instructions use relative addressing. bit test and branch instructions cause a branch based on the state of any readable bit in the ?st 256 memory locations. these three-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu ?ds the conditional branch destination by adding the table 10-2. read-modify-write instructions instruction mnemonic arithmetic shift left asl arithmetic shift right asr clear bit in memory bclr set bit in memory bset clear clr complement (one? complement) com decrement dec increment inc logical shift left lsl logical shift right lsr negate (two? complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 instruction set MC68HC05J5A 10-6 rev 2.1 third byte to the program counter if the speci?d bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from ?28 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. table 10-3 lists the jump and branch instructions. table 10-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification instruction set rev 2.1 10-7 10.1.13 bit manipulation instructions the cpu can set or clear any writable bit in the ?st 256 bytes of memory. port registers, port data direction registers, timer registers, and on-chip ram locations are in the ?st 256 bytes of memory. the cpu can also test and branch based on the state of any bit in any of the ?st 256 memory locations. bit manipulation instructions use direct addressing. table 10-4 lists these instructions. 10.1.14 control instructions these register reference instructions control cpu operation during program execution. control instructions, listed in table 10-5 , use inherent addressing. table 10-4. bit manipulation instructions instruction mnemonic clear bit bclr branch if bit clear brclr branch if bit set brset set bit bset table 10-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 instruction set MC68HC05J5A 10-8 rev 2.1 10.1.15 instruction set summary table 10-6 is an alphabetical list of all m68hc05 instructions and shows the effect of each instruction on the condition code register. table 10-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles h i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification instruction set rev 2.1 10-9 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff p 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 table 10-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 instruction set MC68HC05J5A 10-10 rev 2.1 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 cli clear interrupt mask i ? 0 0 inh 9a 2 clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ?(m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one? complement) m ? ( ) = $ff ?(m) a ? ( ) = $ff ?(m) x ? ( ) = $ff ?(m) m ? ( ) = $ff ?(m) m ? ( ) = $ff ?(m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ?(m) imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) ?1 a ? (a) ?1 x ? (x) ?1 m ? (m) ?1 m ? (m) ?1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 table 10-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc m a x m m f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification instruction set rev 2.1 10-11 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) ?1 push (pch); sp ? (sp) ?1 pc ? conditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (two? complement) m ? ?m) = $00 ?(m) a ? ?a) = $00 ?(a) x ? ?x) = $00 ?(x) m ? ?m) = $00 ?(m) m ? ?m) = $00 ?(m) dir inh inh ix1 ix 30 40 50 60 70 ii ff 5 3 3 6 5 nop no operation inh 9d 2 table 10-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc c b0 b7 0 b0 b7 c 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 instruction set MC68HC05J5A 10-12 rev 2.1 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) ?(m) ?(c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 table 10-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc c b0 b7 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification instruction set rev 2.1 10-13 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) ?(m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) ?1; push (pch) sp ? (sp) ?1; push (x) sp ? (sp) ?1; push (a) sp ? (sp) ?1; push (ccr) sp ? (sp) ?1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x ? (a) inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ?$00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts 0 inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ? ) negation (two? complement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag set or cleared n any bit not affected table 10-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles h i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola instruction set MC68HC05J5A 10-14 rev 2.1 table 10-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 tax 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb m s b lsb msb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification electrical specifications rev 2.1 11-1 section 11 electrical specifications this section provides the electrical and timing speci?ations for the MC68HC05J5A. 11.1 maximum ratings note maximum ratings are the extreme limits the device can be exposed to without causing permanent damage to the chip. the device is not intended to operate at these conditions. the mcu contains circuitry that protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. keep v in and v out within the range from v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . 11.2 thermal characteristics 11.3 functional operating range (voltages referenced to v ss ) rating symbol value unit supply voltage v dd 0.3 to +7.0 v test mode (irq pin only) v in v ss ?0.3 to 2v dd + 0.3 v current drain per pin excluding pb1, pb2, v dd and v ss i25ma operating junction temperature t j +150 c storage temperature range t stg 65 to +150 c characteristic symbol value unit thermal resistance pdip soic q ja q ja 60 60 c/w c/w characteristic symbol value unit operating temperature range t a 0 to +70 c operating voltage range v dd 5.0 10% 2.2 10% v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 electrical specifications MC68HC05J5A 11-2 rev 2.1 11.4 dc electrical characteristics table 11-1. dc electrical characteristics, v dd =5v characteristic 1 symbol min typ 2 max unit output voltage i load = 10.0 m a v ol v oh v dd ?0.1 0.1 v output high voltage (i load =0.8 ma) pa0-5, pb0, pb3-5 v oh v dd ?0.8 v output low voltage (i load = 1.6ma) pa0-3, pb0, pb3-5 (i load = 8ma) pa4-7 (i load = 25ma) pb1, pb2 (see note 8) v ol 0.4 0.4 0.5 v input high voltage pa0-5, pb0-5, irq , reset , osc1 v ih 0.7 v dd ? dd v input low voltage pa0-5, pb0-5, i rq , reset , osc1 v il v ss 0.2 v dd v positive-going input threshold voltage pa6, pa7 v t+ 1.7 v negative-going input threshold voltage pa6, pa7 v t 1.15 v supply current run 3 wait 4 stop 5 lvr on lvr off i dd 6 2 40 20 8 4 80 40 ma ma m a m a i/o ports hi-z leakage current pa0-7, pb0-5 (without individual pull-down/up activated) i z 10 m a input pull-down current pa0-5, pb0, pb3-5 (with individual pull-down activated) i il 50 100 200 m a input pull-up current reset ?40 ?80 ?40 m a input current i rq , osc1 i in 1 m a capacitance ports (as input or output) rese t , irq , osc1, osc2/r c out c in 12 8 pf pf crystal/ceramic resonator oscillator mode internal resistor osc1 to osc2/r r osc 3 m w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification electrical specifications rev 2.1 11-3 pull-up resistor pa6, pa7 6 pb1, pb2 r pullup 2 15 5 30 10 60 k w k w lvr trigger voltage v lvri 2.52 2.8 v tcap input threshold voltage v tcap ? dd /2 v 1. v dd = 5.0vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted. 2. typical values re?ct average measurements at midpoint of voltage range, 25 c only. 3. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc = 2.0 mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l = 20 pf on osc2/r. 4. wait i dd : only mft and timer1 active. wait i dd is affected linearly by the osc2/r capacitance. 5. stop i dd measured with osc1 = v ss . 6. input voltage level on pa6 or pa7 higher than 2.4v is guaranteed to be recognized as logical one and as logic zero if lower than 0.8v. pa6 and pa7 pull-up resistor values are speci?d under the condition that pin voltage ranges from 0v to 2.4v. table 11-2. dc electrical characteristics, v dd =2.2v characteristic 1 symbol min typ 2 max unit output voltage i load = 10.0 m a v ol v oh v dd ?0.1 0.1 v output high voltage (i load =0.4 ma) pa0-5, pb0, pb3-5 v oh v dd ?0.3 v output low voltage (i load = 0.8ma) pa0-3, pb0, pb3-5 (i load = 2ma) pa4-7 (i load = 8ma) pb1, pb2 (see note 8) v ol 0.3 0.3 0.4 v input high voltage pa0-5, pb0-5, irq , reset , osc1 v ih 0.7 v dd ? dd v input low voltage pa0-5, pb0-5, i rq , reset , osc1 v il v ss 0.2 v dd v positive-going input threshold voltage pa6, pa7 v t+ 0.7 v negative-going input threshold voltage pa6, pa7 v t 0.5 v supply current run 3 wait 4 stop 5 (lvr off) i dd 1 0.2 6 2 0.4 15 ma ma m a table 11-1. dc electrical characteristics, v dd =5v characteristic 1 symbol min typ 2 max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 electrical specifications MC68HC05J5A 11-4 rev 2.1 i/o ports hi-z leakage current pa0-7, pb0-5 (without individual pull-down/up activated) i z 10 m a input pull-down current pa0-5, pb0, pb3-5 (with individual pull-down activated) i il 50 100 200 m a input pull-up current reset ?0 ?0 ?5 m a input current i rq , osc1 i in 1 m a capacitance ports (as input or output) rese t , irq , osc1, osc2/r c out c in 12 8 pf pf crystal/ceramic resonator oscillator mode internal resistor osc1 to osc2/r r osc 3 m w pull-up resistor pa6, pa7 6 pb1, pb2 r pullup 2 15 5 30 10 60 k w k w lvr trigger voltage lvr must be disabled (mask option) for v dd =2.2v tcap input threshold voltage v tcap ? dd /2 v 1. v dd = 2.2vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted. 2. typical values re?ct average measurements at midpoint of voltage range, 25 c only. 3. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc = 2.0 mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l = 20 pf on osc2/r. 4. wait i dd : only mft and timer1 active. wait i dd is affected linearly by the osc2/r capacitance. 5. stop i dd measured with osc1 = v ss . 6. input voltage level on pa6 or pa7 higher than 2.4v is guaranteed to be recognized as logical one and as logic zero if lower than 0.8v. pa6 and pa7 pull-up resistor values are speci?d under the condition that pin voltage ranges from 0v to 2.4v. table 11-2. dc electrical characteristics, v dd =2.2v characteristic 1 symbol min typ 2 max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification electrical specifications rev 2.1 11-5 11.5 control timing table 11-3. control timing, v dd =5v characteristic 1 1. v dd = 5.0vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted. symbol min max units frequency of operation crystal oscillator option external clock source f osc f osc dc 4.2 4.2 mhz mhz internal operating frequency crystal oscillator (f osc ? 2) external clock (f osc ? 2) f op f op dc 2.1 2.1 mhz mhz cycle time (1/f op )t cyc 415 ns reset pulse width low t rl 1.5 t cyc irq interrupt pulse width low (edge-triggered) t ilih 0.5 t cyc irq interrupt pulse period t ilil see note 2 2. the minimum period t ilil or t ihih should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 t cyc . ? cyc pa0 to pa3 interrupt pulse width high (edge-triggered) t ihil 0.5 t cyc pa0 to pa3 interrupt pulse period t ihih see note 3 t cyc pa7 interrupt pulse width low t ilih 0.5 t cyc osc1 pulse width t oh , t ol 200 ns output high to low transition period on pa6, pa7, pb1 3 3. t slow is a parameter dependent on f osc and loading. t slow 0.5 (typical) t cyc table 11-4. control timing, v dd =2.2v characteristic 1 1. v dd = 2.2vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted. symbol min max units frequency of operation crystal oscillator option external clock source f osc f osc dc 2.1 2.1 mhz mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 electrical specifications MC68HC05J5A 11-6 rev 2.1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification mechanical specifications rev 2.1 12-1 section 12 mechanical specifications this section provides the mechanical dimensions for the four available packages for MC68HC05J5A. 12.1 16-pin pdip (case #648) figure 12-1. 16-pin pdip mechanical dimensions 12.2 16-pin soic (case #751g) figure 12-2. 16-pin soic mechanical dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 dim min max min max inches millimeters a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 8x g 14x d 16x seating plane t s a m 0.010 (0.25) b s t 16 9 8 1 f j r x 45 m c k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 mechanical specifications MC68HC05J5A 12-2 rev 2.1 12.3 20-pin pdip (case #738) figure 12-3. 20-pin pdip mechanical dimensions 12.4 20-pin soic (case #751d) figure 12-4. 20-pin soic mechanical dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 a seating plane k n f g d 20 pl t m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c t seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification rev 2.1 a-1 appendix a mc68hrc05j5a this appendix describes the mc68hrc05j5a, a resistor-capacitor (rc) oscillator mask option version of the MC68HC05J5A. the entire MC68HC05J5A data sheet applies to the mc68hrc05j5a, with exceptions outlined in this appendix. a.1 introduction the mc68hrc05j5a is a resistor-capacitor (rc) oscillator mask option version of the MC68HC05J5A. the mc68hrc05j5a is functionally identical to the MC68HC05J5A with the exception that the mc68hrc05j5a supports the rc oscillator only, as outlined in appendix a.2 . a.2 rc oscillator connections this is the only oscillator option supported by the mc68hrc05j5a device. on the mc68hrc05j5a device, an external resistor is connected between osc2/r pin and the v ss pin as shown in figure a-1 . the typical operating fre- quency f osc is set at 4mhz with the external r tied to v ss . use the graph in figure a-2 to select the value of r for the required oscillator frequency. the tolerance of this rc oscillator is guaranteed to be no greater than 15% at the speci?d conditions of 0 c to 40 c and 5v 10% v dd providing that the toler- ance of the external resistor r is at most 1% and the center frequency range is from 3.8mhz to 4.2mhz. the center frequency is the nominal operating frequency of the rc oscillator and can be adjusted by adjusting the external r value to change the internal vco charging current. in order to obtain an oscillator clock with the best possible tolerance, the external resistor connected to the osc2/r pin should be grounded as close to the vss pin as possible and the other terminal of this external resistor should be connected as close to the osc2/r pin as possible. figure a-1. rc oscillator connections mcu osc2/r osc1 r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 MC68HC05J5A a-2 rev 2.1 figure a-2. typical internal operating frequency for rc oscillator connections a.3 electrical characteristics table a-1. functional operating range characteristic symbol value unit operating temperature range t a 0 to +70 c operating voltage range v dd 5.0 10% v table a-2. dc electrical characteristics, v dd =5v characteristic 1 1. v dd = 5.0vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted. symbol min typ 2 2. typical values re?ct average measurements at midpoint of voltage range, 25 c only. max unit supply current run 3 wait 4 stop lvr on lvr off 3. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc = 2.0 mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l = 20 pf on osc2/r. 4. wait i dd : only mft and timer1 active. wait i dd is affected linearly by the osc2/r capacitance. i dd 6 2 40 20 8 4 80 40 ma ma m a m a 51015202530 6 5 4 3 2 1 resistance r (k w ) frequency (mhz) vdd = 5v ?0% at 25 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification rev 2.1 b-1 appendix b mc68hc705j5a this appendix describes the mc68hc705j5a, the emulation part for MC68HC05J5A. the entire MC68HC05J5A data sheet applies to the mc68hc705j5a, with exceptions outlined in this appendix. b.1 introduction the mc68hc705j5a is an eprom version of the MC68HC05J5A, and is avail- able for user system evaluation and debugging. the mc68hc705j5a is function- ally identical to the MC68HC05J5A with the exception of the 2560 bytes user rom is replaced by 2560 bytes user eprom. also, the mask options available on the MC68HC05J5A are implemented using the mask option register (mor) in the mc68hc705j5a. the mc68hc705j5a is not available in the 16-pin soic package. b.2 memory the mc68hc705j5a memory map is shown in figure b-1 . b.3 mask option registers (mor) the mask option register (mor) consists of two bytes of eprom used to select the features controlled by mask options on the MC68HC05J5A. in order to pro- gram this register the moron bit in pcr need to be set to ? before doing the eprom programming process. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mor1 r stopmd irqtrig pullren painten oscdly lvren $0200 w erased: x x 111111 reset: unaffected by reset bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mor2 r cop_en $0201 w erased: 00000001 reset: unaffected by reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 MC68HC05J5A b-2 rev 2.1 stopmd ?stop mode option 1 = stop mode is selected. 0 = stop mode is converted to halt mode. irqtrig ?irq, pa0-pa3 interrupt option 1 = edge-triggered only. 0 = edge-and-level-triggered. pullren ?port a and b pull-up/down option 1 = connected. 0 = disconnected painten ?pa0-pa3 external interrupt option 1 = external interrupt capability on pa0-pa3 disabled. 0 = external interrupt capability on pa0-pa3 enabled. oscdly ?oscillator delay option 1 = 224 internal clock cycles. 0 = 4064 internal clock cycles. lvren ?lvr option 1 = low voltage reset circuit enabled. 0 = low voltage reset circuit disabled. cop_en ?cop watchdog timer option 1 = disabled. 0 = enabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification rev 2.1 b-3 figure b-1. mc68hc705j5a memory map rom reserved 6 bytes user vectors eprom 10 bytes unimplemented 96 bytes 3327 3328 4095 4086 3583 stack user ram 128 bytes reset vector (low byte) reset vector (high byte) swi vector (low byte) swi vector (high byte) irq vector (low byte) irq vector (high byte) mft vector (low byte) mft vector (high byte) $0ff7 $0ff8 $0ff9 $0ffa $0ffb $0ffc $0ffd $0ffe $0fff $001f $0000 $0100 $00ff 0255 0256 i/o 32 bytes 0032 0031 0000 $0fff $0ff0 $0fef $0d00 $0cff $0080 $007f $0020 $001f $0000 user eprom 2560 bytes i/o registers 32 bytes (see figure 2-2 ) 0128 0127 $0ff6 $0ff3 $0ff4 $0ff5 $0ff2 $0ff1 $0ff0 cop watchdog timer* $0dff $0e00 3584 4079 bootloader rom 496 bytes * writing a 0 to bit 0 of $0ff0 clears the cop timer. reading $0ff0 returns rom data. timer1 vector (low byte) reserved timer1 vector (high byte) reserved reserved reserved reserved $0ff6 $0ff5 4080 4085 unimplemented 256 bytes 0767 0768 $0300 $02ff 0192 $00c0 $001e program control register $0200 $0201 unimplemented 256 bytes unimplemented 254 bytes mask option registers 1 & 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 MC68HC05J5A b-4 rev 2.1 b.4 bootstrap mode bootloader mode is entered upon the rising edge of reset if the irq /v pp pin is at v tst and the pb0 pin is at logic zero. the bootloader program is masked in the rom area from $0e00 to $0fef. this program handles copying of user code from an external eprom into the on-chip eprom. the bootload function has to be done from an external eprom. the bootloader performs one programming pass at 1ms per byte then does a verify pass. the user code must be a one-to-one correspondence with the internal eprom addresses. b.5 eprom programming programming the on-chip eprom is achieved by using the program control reg- ister located at address $3e. please contact motorola for programming board availability. b.5.1 eprom program control register (pcr) this register is provided for programming the on-chip eprom in the mc68hc705j5a. moron ?mask option register on 0 = disable programming to mask option register ($0200 & $0201) 1 = enable programming to mask option register ($0200 & $0201) elat ?eprom latch control 0 = eprom address and data bus con?ured for normal reads 1 = eprom address and data bus con?ured for programming (writes to eprom cause address and data to be latched). eprom is in programming mode and cannot be read if elat is 1. this bit should not be set when no programming voltage is applied to the v pp pin. pgm ?eprom program command 0 = programming power is switched off from eprom array. 1 = programming power is switched on to eprom array. if elat 1 1, then pgm = 0. bits [7:3] ?reserved these are reserved bits and should remain zero. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pcrr00000 moron elat pgm $001e w r r r r r reset: 00000000 r = reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification rev 2.1 b-5 b.5.2 programming sequence the eprom programming sequence is: 1. set the elat bit 2. write the data to the address to be programmed 3. set the pgm bit 4. delay for a time t pgmr 5. clear the pgm bit 6. clear the elat bit the last two steps must be performed with separate cpu writes. caution it is important to remember that an external programming voltage must be applied to the v pp pin while programming, but it should be equal to v dd during normal operations. figure b-2 shows the ?w required to successfully program the eprom. figure b-2. eprom programming sequence start elat=1 write eprom byte pgm=1 wait 1ms pgm=0 elat=0 write additional byte? n y end f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 MC68HC05J5A b-6 rev 2.1 b.6 electrical characteristics table b-1. functional operating range characteristic symbol value unit operating temperature range t a ?0 to +85 c operating voltage range v dd 5.0 10% v table b-2. eprom programming electrical characteristics characteristic symbol min typ max unit programming voltage irq /v pp v pp 10 12 15 v programming current irq /v pp i pp ?ma programming time per byte t epgm 1 4 ?s table b-3. dc electrical characteristics, v dd =5v characteristic 1 symbol min typ 2 max unit output voltage i load = 10.0 m a v ol v oh v dd ?0.1 0.1 v output high voltage (i load =0.8 ma) pa0-5, pb0, pb3-5 v oh v dd ?0.8 v output low voltage (i load = 1.6ma) pa0-3, pb0, pb3-5 (i load = 8ma) pa4, pa5 (i load = 6ma) pa6, pa7 (i load = 25ma) pb1, pb2 (see note 8) v ol 0.4 0.4 0.4 0.5 v input high voltage pa0-5, pb0-5, irq , reset , osc1 v ih 0.7 v dd ? dd v input low voltage pa0-5, pb0-5, i rq , reset , osc1 v il v ss 0.2 v dd v positive-going input threshold voltage pa6, pa7 v t+ 1.7 v negative-going input threshold voltage pa6, pa7 v t 1.15 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification rev 2.1 b-7 supply current run 3 wait 4 stop 5 lvr on lvr off i dd 6 2 40 10 10 4 80 30 ma ma m a m a i/o ports hi-z leakage current pa0-7, pb0-5 (without individual pull-down/up activated) i z 10 m a input pull-down current pa0-5, pb0, pb3-5 (with individual pull-down activated) i il 50 100 200 m a input pull-up current reset ?0 ?00 ?00 m a input current i rq , osc1 i in 1 m a capacitance ports (as input or output) rese t , irq , osc1, osc2/r c out c in 12 8 pf pf crystal/ceramic resonator oscillator mode internal resistor osc1 to osc2/r r osc 2 m w pull-up resistor pa6, pa7 6 pb1, pb2 r pullup 2 10 5 30 10 60 k w k w lvr trigger voltage v lvri 2.7 3.0 v tcap input threshold voltage v tcap ? dd /2 v 1. v dd = 5.0vdc 10%, v ss = 0 vdc, t a = ?0 c to +85 c, unless otherwise noted. 2. typical values re?ct average measurements at midpoint of voltage range, 25 c only. 3. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc = 2.0 mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l = 20 pf on osc2/r. 4. wait i dd : only mft and timer1 active. wait i dd is affected linearly by the osc2/r capacitance. 5. stop i dd measured with osc1 = v ss . 6. input voltage level on pa6 or pa7 higher than 2.4v is guaranteed to be recognized as logical one and as logic zero if lower than 0.8v. pa6 and pa7 pull-up resistor values are speci?d under the condition that pin voltage ranges from 0v to 2.4v. table b-3. dc electrical characteristics, v dd =5v characteristic 1 symbol min typ 2 max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 MC68HC05J5A b-8 rev 2.1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification rev 2.1 c-1 appendix c mc68hrc705j5a this appendix describes the mc68hrc705j5a, the emulation part for mc68hrc05j5a, and a resistor-capacitor (rc) oscillator mask option version of the mc68hc705j5a. the entire MC68HC05J5A data sheet and appendix b applies to the mc68hrc705j5a, with exceptions outlined in this appendix. c.1 introduction the mc68hrc705j5a is a resistor-capacitor (rc) oscillator mask option version of the mc68hc705j5a (see appendix b ). the mc68hrc705j5a is functionally identical to the mc68hc705j5a with the exception that the mc68hrc705j5a supports the rc oscillator only, as outlined in appendix c.2 . the mc68hrc705j5a is not available in the 16-pin soic package. c.2 rc oscillator connections this is the only oscillator option supported by the mc68hrc705j5a device. on the mc68hrc705j5a device, an external resistor is connected between osc2/r pin and the v ss pin as shown in figure c-1 . the typical operating fre- quency f osc is set at 4mhz with the external r tied to v ss . use the graph in figure c-2 to select the value of r for the required oscillator frequency. the tolerance of this rc oscillator is guaranteed to be no greater than 15% at the speci?d conditions of 0 c to 40 c and 5v 10% v dd providing that the toler- ance of the external resistor r is at most 1% and the center frequency range is from 3.8mhz to 4.2mhz. the center frequency is the nominal operating frequency of the rc oscillator and can be adjusted by adjusting the external r value to change the internal vco charging current. in order to obtain an oscillator clock with the best possible tolerance, the external resistor connected to the osc2/r pin should be grounded as close to the vss pin as possible and the other terminal of this external resistor should be connected as close to the osc2/r pin as possible. figure c-1. rc oscillator connections mcu osc2/r osc1 r f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 MC68HC05J5A c-2 rev 2.1 figure c-2. typical internal operating frequency for rc oscillator connections c.3 electrical characteristics table c-1. functional operating range characteristic symbol value unit operating temperature range t a ?0 to +85 c operating voltage range v dd 5.0 10% v table c-2. dc electrical characteristics, v dd =5v characteristic 1 1. v dd = 5.0vdc 10%, v ss = 0 vdc, t a = ?0 c to +85 c, unless otherwise noted. symbol min typ 2 2. typical values re?ct average measurements at midpoint of voltage range, 25 c only. max unit supply current run 3 wait 4 stop 5 lvr on lvr off 3. run (operating) i dd , wait i dd : measured using external square wave clock source to osc1 (f osc = 2.0 mhz), all inputs 0.2 vdc from rail; no dc loads, less than 50pf on all outputs, c l = 20 pf on osc2/r. 4. wait i dd : only mft and timer1 active. wait i dd is affected linearly by the osc2/r capacitance. 5. stop i dd measured with osc1 = v ss . i dd 6 2 40 10 10 4 80 30 ma ma m a m a 51015202530 6 5 4 3 2 1 resistance r (k w ) frequency (mhz) vdd = 5v ?0% at 25 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
july 16, 1999 general release specification rev 2.1 d-1 appendix d ordering inform a tion this section contains orde r ing numbers f or the MC68HC05J5A, mc68hrc05j5a, mc68hc705j5a, and mc68hrc705j5a. d .1 mc o r der numbe r s t able d-1 . m c o r de r numbe r s mc order number pin count package type operating temperature device type MC68HC05J5Ajp 16 pdip 0 c to +70 c 2560 bytes rom, crystal/resonator or external oscillator option MC68HC05J5Ajdw 16 soic MC68HC05J5Ap 20 pdip MC68HC05J5Adw 20 soic mc68hrc05j5ajp 16 pdip 0 c to +70 c 2560 bytes rom, rc oscillator option mc68hrc05j5ajdw 16 soic mc68hrc05j5ap 20 pdip mc68hrc05j5adw 20 soic mc68hc705j5acjp 16 pdip ?0 c to +85 c 2560 bytes otprom, crystal/resonator or external oscillator option mc68hc705j5acp 20 pdip mc68hc705j5acdw 20 soic mc68hrc705j5acjp 16 pdip ?0 c to +85 c 2560 bytes otprom, rc oscillator option mc68hrc705j5acp 20 pdip mc68hrc705j5acdw 20 soic notes: c = extended temperature p = plastic dual-in-line package (pdip) dw = small outline integrated circuit (soic) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
general release specification july 16, 1999 MC68HC05J5A d-2 re v 2.1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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