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1. general description the 74avch1t45-q100 is a single bit, dual supply transceiver that enables bidirectional level translation. it features two 1-bit input-output ports (a and b), a direction control input (dir) and dual supply pins (v cc(a) and v cc(b) ). both v cc(a) and v cc(b) can be supplied with any voltage between 0.8 v and 3.6 v maki ng the device suitable for translating between any of the low voltage nodes (0.8 v, 1.2 v, 1.5 v, 1.8 v, 2.5 v and 3.3 v). pins a and dir are referenced to v cc(a) and pin b is referenced to v cc(b) . a high on dir allows transmission from a to b and a low on dir allows transmission from b to a. the device is fully specified for pa rtial power-down applications using i off . the i off circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. in suspend mode when either v cc(a) or v cc(b) are at gnd level, both a and b are in the high-impedance off-state. the 74avch1t45-q100 has active bus hold circui try which is provided to hold unused or floating data inputs at a valid logic level. this feature eliminates the need for external pull-up or pull- down resistors. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? wide supply voltage range: ? v cc(a) : 0.8 v to 3.6 v ? v cc(b) : 0.8 v to 3.6 v ? high noise immunity ? complies with jedec standards: ? jesd8-12 (0.8 v to 1.3 v) ? jesd8-11 (0.9 v to 1.65 v) ? jesd8-7 (1.2 v to 1.95 v) ? jesd8-5 (1.8 v to 2.7 v) ? jesd8-b (2.7 v to 3.6 v) ? esd protection: ? mil-std-883, method 3015 class 3b exceeds 8000 v ? hbm jesd22-a114e class 3b exceeds 8000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) 74avch1t45-q100 dual-supply voltage level tran slator/transceiver; 3-state rev. 2 ? 9 april 2013 product data sheet
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 2 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state ? maximum data rates: ? 500 mbit/s (1.8 v to 3.3 v translation) ? 320 mbit/s (< 1.8 v to 3.3 v translation) ? 320 mbit/s (translate to 2.5 v or 1.8 v) ? 280 mbit/s (translate to 1.5 v) ? 240 mbit/s (translate to 1.2 v) ? suspend mode ? bus hold on data inputs ? latch-up performance exceeds 100 ma per jesd 78 class ii ? inputs accept voltages up to 3.6 v ? low noise overshoot and undershoot < 10 % of v cc ? i off circuitry provides partial power-down mode operation 3. ordering information 4. marking [1] the pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. functional diagram table 1. ordering information type number package temperature range name description version 74AVCH1T45GW-Q100 ? 40 ? c to +125 ? c sc-88 plastic surface-mounted package; 6 leads sot363 table 2. marking type number marking code [1] 74AVCH1T45GW-Q100 k5 fig 1. logic symbol fig 2. logic diagram 001aag885 v cc(b) v cc(a) 5 dir 3 a b 4 001aag886 v cc(b) v cc(a) dir a b
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 3 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state 6. pinning information 6.1 pinning 6.2 pin description 7. functional description [1] h = high voltage level; l = low voltage level; x = don?t care; z = high-impedance off-state. [2] the input circuit of the data i/o is always active. [3] the dir input circuit is referenced to v cc(a) . [4] if at least one of v cc(a) or v cc(b) is at gnd level, the device goes into suspend mode. fig 3. pin configuration sot363

table 3. pin description symbol pin description v cc(a) 1 supply voltage port a and dir gnd 2 ground (0 v) a 3 data input or output b 4 data input or output dir 5 direction control v cc(b) 6 supply voltage port b table 4. function table [1] supply voltage input input/output [2] v cc(a) , v cc(b) dir [3] a b 0.8 v to 3.6 v l a = b input 0.8 v to 3.6 v h input b = a gnd [4] xzz
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 4 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state 8. limiting values [1] the minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are obs erved. [2] v cco is the supply voltage associated with the output port. [3] v cco + 0.5 v should not exceed 4.6 v. [4] for sc-88 packages: above 87.5 ? c the value of p tot derates linearly with 4.0 mw/k. table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc(a) supply voltage a ? 0.5 +4.6 v v cc(b) supply voltage b ? 0.5 +4.6 v i ik input clamping current v i <0v ? 50 - ma v i input voltage [1] ? 0.5 +4.6 v i ok output clamping current v o <0v ? 50 - ma v o output voltage active mode [1] [2] [3] ? 0.5 v cco +0.5 v suspend or 3-state mode [1] ? 0.5 +4.6 v i o output current v o =0vtov cco - ? 50 ma i cc supply current i cc(a) or i cc(b) -1 0 0m a i gnd ground current ? 100 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = ? 40 ? c to +125 ?c [4] -2 5 0m w
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 5 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state 9. recommended operating conditions [1] v cco is the supply voltage associated with the output port. [2] v cci is the supply voltage associated with the input port. 10. static characteristics table 6. recommended operating conditions symbol parameter conditions min max unit v cc(a) supply voltage a 0.8 3.6 v v cc(b) supply voltage b 0.8 3.6 v v i input voltage 0 3.6 v v o output voltage active mode [1] 0v cco v suspend or 3-state mode 0 3.6 v t amb ambient temperature ? 40 +125 ?c ? t/ ? v input transition rise and fall rate v cci = 0.8 v to 3.6 v [2] -5n s / v table 7. typical static characteristics at t amb = 25 ?c [1] [2] at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit v oh high-level output voltage v i = v ih or v il i o = ? 1.5 ma; v cc(a) =v cc(b) = 0.8 v - 0.69 - v v ol low-level output voltage v i = v ih or v il i o = 1.5 ma; v cc(a) =v cc(b) = 0.8 v - 0.07 - v i i input leakage current dir input; v i = 0 v or 3.6 v; v cc(a) =v cc(b) = 0.8 v to 3.6 v - ? 0.025 ? 0.25 ? a i bhl bus hold low current v i = 0.42 v; v cc(a) = v cc(b) = 1.2 v [3] -26- ? a i bhh bus hold high current v i = 0.78 v; v cc(a) = v cc(b) = 1.2 v [4] - ? 24 - ? a i bhlo bus hold low overdrive current v i = gnd to v cci ; v cc(a) =v cc(b) =1.2v [5] -28- ? a i bhho bus hold high overdrive current v i = gnd to v cci ; v cc(a) =v cc(b) =1.2v [6] - ? 26 - ? a i oz off-state output current a or b port; v o =0 vor v cco ; v cc(a) =v cc(b) = 0.8 v to 3.6 v [7] - ? 0.5 ? 2.5 ? a i off power-off leakage current a port; v i or v o = 0 v to 3.6 v; v cc(a) =0v;v cc(b) = 0.8 v to 3.6 v - ? 0.1 ? 1 ? a b port; v i or v o = 0 v to 3.6 v; v cc(b) =0v;v cc(a) = 0.8 v to 3.6 v - ? 0.1 ? 1 ? a c i input capacitance dir input; v i = 0 v or 3.3 v; v cc(a) =v cc(b) =3.3v -1.0-pf
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 6 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state [1] v cco is the supply voltage associated with the output port. [2] v cci is the supply voltage associated with the data input port. [3] the bus hold circuit can sink at least the minimum low sustaining current at v il max. measure i bhl after lowering v i to gnd and then raising it to v il max. [4] the bus hold circuit can source at leas t the minimum high sustaining current at v ih min. measure i bhh after raising v i to v cc and then lowering it to v ih min. [5] an external driver must source at least i bhlo to switch this node from low to high. [6] an external driver must sink at least i bhho to switch this node from high to low. [7] for i/o ports, the parameter i oz includes the input leakage current. c i/o input/output capacitance a and b port; suspend mode; v o =v cco or gnd; v cc(a) =v cc(b) =3.3v -4.0-pf table 7. typical static characteristics at t amb = 25 ?c [1] [2] ?continued at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions min typ max unit table 8. static characteristics [1] [2] at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min max min max v ih high-level input voltage data input v cci = 0.8 v 0.70v cci - 0.70v cci -v v cci = 1.1 v to 1.95 v 0.65v cci - 0.65v cci -v v cci = 2.3 v to 2.7 v 1.6 - 1.6 - v v cci = 3.0 v to 3.6 v 2 - 2 - v dir input v cc(a) = 0.8 v 0.70v cc(a) -0.70v cc(a) -v v cc(a) = 1.1 v to 1.95 v 0.65v cc(a) -0.65v cc(a) -v v cc(a) = 2.3 v to 2.7 v 1.6 - 1.6 - v v cc(a) = 3.0 v to 3.6 v 2 - 2 - v v il low-level input voltage data input v cci = 0.8 v - 0.30v cci - 0.30v cci v v cci = 1.1 v to 1.95 v - 0.35v cci - 0.35v cci v v cci = 2.3 v to 2.7 v - 0.7 - 0.7 v v cci = 3.0 v to 3.6 v - 0.9 - 0.9 v dir input v cc(a) = 0.8 v - 0.30v cc(a) - 0.30v cc(a) v v cc(a) = 1.1 v to 1.95 v - 0.35v cc(a) - 0.35v cc(a) v v cc(a) = 2.3 v to 2.7 v - 0.7 - 0.7 v v cc(a) = 3.0 v to 3.6 v - 0.9 - 0.9 v
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 7 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state v oh high-level output voltage v i = v ih or v il i o = ? 100 ? a; v cc(a) =v cc(b) = 0.8 v to 3.6 v v cco ? 0.1 - v cco ? 0.1 - v i o = ? 3ma; v cc(a) =v cc(b) =1.1v 0.85 - 0.85 - v i o = ? 6ma; v cc(a) =v cc(b) =1.4v 1.05 - 1.05 - v i o = ? 8ma; v cc(a) =v cc(b) =1.65v 1.2 - 1.2 - v i o = ? 9ma; v cc(a) =v cc(b) =2.3v 1.75 - 1.75 - v i o = ? 12 ma; v cc(a) =v cc(b) =3.0v 2.3 - 2.3 - v v ol low-level output voltage v i = v ih or v il i o = 100 ? a; v cc(a) =v cc(b) = 0.8 v to 3.6 v -0.1-0.1v i o = 3 ma; v cc(a) =v cc(b) = 1.1 v - 0.25 - 0.25 v i o = 6 ma; v cc(a) =v cc(b) = 1.4 v - 0.35 - 0.35 v i o = 8 ma; v cc(a) =v cc(b) =1.65v - 0.45 - 0.45 v i o = 9 ma; v cc(a) =v cc(b) = 2.3 v - 0.55 - 0.55 v i o = 12 ma; v cc(a) =v cc(b) =3.0v -0.7-0.7v i i input leakage current dir input; v i = 0 v or 3.6 v; v cc(a) =v cc(b) = 0.8 v to 3.6 v - ? 1- ? 1.5 ? a i bhl bus hold low current a or b port [3] v i = 0.49 v; v cc(a) =v cc(b) =1.4v 15 - 15 - ? a v i = 0.58 v; v cc(a) =v cc(b) =1.65v 25 - 25 - ? a v i = 0.70 v; v cc(a) =v cc(b) =2.3v 45 - 45 - ? a v i = 0.80 v; v cc(a) =v cc(b) =3.0v 100 - 90 - ? a i bhh bus hold high current a or b port [4] v i = 0.91 v; v cc(a) =v cc(b) =1.4v ? 15 - ? 15 - ? a v i = 1.07 v; v cc(a) =v cc(b) =1.65v ? 25 - ? 25 - ? a v i = 1.60 v; v cc(a) =v cc(b) =2.3v ? 45 - ? 45 - ? a v i = 2.00 v; v cc(a) =v cc(b) =3.0v ? 100 - ? 100 - ? a table 8. static characteristics ?continued [1] [2] at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min max min max
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 8 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state [1] v cco is the supply voltage associated with the output port. [2] v cci is the supply voltage associated with the data input port. [3] the bus hold circuit can sink at least the minimum low sustaining current at v il max. measure i bhl after lowering v i to gnd and then raising it to v il max. [4] the bus hold circuit can source at leas t the minimum high sustaining current at v ih min. measure i bhh after raising v i to v cc and then lowering it to v ih min. [5] an external driver must source at least i bhlo to switch this node from low to high. [6] an external driver must sink at least i bhho to switch this node from high to low. [7] for i/o ports, the parameter i oz includes the input leakage current. i bhlo bus hold low overdrive current a or b port [5] v cc(a) = v cc(b) = 1.6 v 125 - 125 - ? a v cc(a) = v cc(b) = 1.95 v 200 - 200 - ? a v cc(a) = v cc(b) = 2.7 v 300 - 300 - ? a v cc(a) = v cc(b) = 3.6 v 500 - 500 - ? a i bhho bus hold high overdrive current a or b port [6] v cc(a) = v cc(b) = 1.6 v ? 125 - ? 125 - ? a v cc(a) = v cc(b) = 1.95 v ? 200 - ? 200 - ? a v cc(a) = v cc(b) = 2.7 v ? 300 - ? 300 - ? a v cc(a) = v cc(b) = 3.6 v ? 500 - ? 500 - ? a i oz off-state output current a or b port; v o =0 vor v cco ; v cc(a) =v cc(b) = 0.8 v to 3.6 v [7] - ? 5- ? 7.5 ? a i off power-off leakage current a port; v i or v o = 0 v to 3.6 v; v cc(a) =0v; v cc(b) = 0.8 v to 3.6 v - ? 5- ? 35 ? a b port; v i or v o = 0 v to 3.6 v; v cc(b) =0v; v cc(a) = 0.8 v to 3.6 v - ? 5- ? 35 ? a i cc supply current a port; v i = 0 v or v cci ; i o = 0 a v cc(a) = 0.8 v to 3.6 v; v cc(b) = 0.8 v to 3.6 v -8-12 ? a v cc(a) = 3.6 v; v cc(b) = 0 v - 8 - 12 ? a v cc(a) = 0 v; v cc(b) = 3.6 v ? 2- ? 8- ? a b port; v i = 0 v or v cci ; i o = 0 a v cc(a) = 0.8 v to 3.6 v; v cc(b) = 0.8 v to 3.6 v -8-1 2 ? a v cc(a) = 3.6 v; v cc(b) = 0 v ? 2- ? 8- ? a v cc(a) = 0 v; v cc(b) = 3.6 v - 8 - 12 ? a a plus b port (i cc(a) + i cc(b) ); i o =0a; v i =0 vor v cci ; v cc(a) = 0.8 v to 3.6 v; v cc(b) = 0.8 v to 3.6 v -16-24 ? a table 8. static characteristics ?continued [1] [2] at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min max min max
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 9 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state 11. dynamic characteristics [1] t pd is the same as t plh and t phl ; t dis is the same as t plz and t phz ; t en is the same as t pzl and t pzh . t en is a calculated value using the formula shown in section 13.4 ? enable times ? [1] t pd is the same as t plh and t phl ; t dis is the same as t plz and t phz ; t en is the same as t pzl and t pzh . t en is a calculated value using the formula shown in section 13.4 ? enable times ? [1] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l ? v cc 2 ? f o ) = sum of the outputs. [2] f i = 10 mhz; v i =gndtov cc ; t r = t f = 1 ns; c l = 0 pf; r l = ? ? . table 9. typical dynamic characteristics at v cc(a) = 0.8 v and t amb = 25 ?c [1] voltages are referenced to gnd (ground = 0 v); for test circuit see figure 6 ; for wave forms see figure 4 and figure 5 symbol parameter conditions v cc(b) unit 0.8 v 1.2 v 1.5 v 1.8 v 2.5 v 3.3 v t pd propagation delay a to b 15.8 8.4 8.0 8.0 8.7 9.5 ns b to a 15.8 12.7 12.4 12.2 12.0 11.8 ns t dis disable time dir to a 12.2 12.2 12.2 12.2 12.2 12.2 ns dir to b 11.7 7.9 7.6 8.2 8.7 10.2 ns t en enable time dir to a 27.5 20.6 20.0 20.4 20.7 22.0 ns dir to b 28.0 20.6 20.2 20.2 20.9 21.7 ns table 10. typical dynamic characteristics at v cc(b) = 0.8 v and t amb = 25 ?c [1] voltages are referenced to gnd (ground = 0 v); for test circuit see figure 6 ; for wave forms see figure 4 and figure 5 symbol parameter conditions v cc(a) unit 0.8 v 1.2 v 1.5 v 1.8 v 2.5 v 3.3 v t pd propagation delay a to b 15.8 12.7 12.4 12.2 12.0 11.8 ns b to a 15.8 8.4 8.0 8.0 8.7 9.5 ns t dis disable time dir to a 12.2 4.9 3.8 3.7 2.8 3.4 ns dir to b 11.7 9.2 9.0 8.8 8.7 8.6 ns t en enable time dir to a 27.5 17.6 17.0 16.8 17.4 18.1 ns dir to b 28.0 17.6 16.2 15.9 14.8 15.2 ns table 11. typical power dissipation capacitance at v cc(a) = v cc(b) and t amb = 25 ?c [1] [2] voltages are referenced to gnd (ground = 0 v). symbol parameter conditions v cc(a) and v cc(b) unit 0.8 v 1.2 v 1.5 v 1.8 v 2.5 v 3.3 v c pd power dissipation capacitance a port: (direction a to b); b port: (direction b to a) 122222pf a port: (direction b to a); b port: (direction a to b) 91111121417pf
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 10 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state [1] t pd is the same as t plh and t phl ; t dis is the same as t plz and t phz ; t en is the same as t pzl and t pzh . t en is a calculated value using the formula shown in section 13.4 ? enable times ? table 12. dynamic characteristics for temperature range ? 40 ? c to +85 ?c [1] voltages are referenced to gnd (ground = 0 v); for test circuit see figure 6 ; for wave forms see figure 4 and figure 5 . symbol parameter conditions v cc(b) unit 1.2 v ? 0.1 v 1.5 v ? 0.1 v 1.8 v ? 0.15 v 2.5 v ? 0.2 v 3.3 v ? 0.3 v min max min max min max min max min max v cc(a) = 1.1 v to 1.3 v t pd propagation delay a to b 1.0 9.0 0.7 6.8 0.6 6.1 0.5 5.7 0.5 6.1 ns b to a 1.0 9.0 0.8 8.0 0.7 7.7 0.6 7.2 0.5 7.1 ns t dis disable time dir to a 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 2.2 8.8 ns dir to b 2.2 8.4 1.8 6.7 2.0 6.9 1.7 6.2 2.4 7.2 ns t en enable time dir to a - 17.4 - 14.7 - 14.6 - 13.4 - 14.3 ns dir to b - 17.8 - 15.6 - 14.9 - 14.5 - 14.9 ns v cc(a) = 1.4 v to 1.6 v t pd propagation delay a to b 1.0 8.0 0.7 5.4 0.6 4.6 0.5 3.7 0.5 3.5 ns b to a 1.0 6.8 0.8 5.4 0.7 5.1 0.6 4.7 0.5 4.5 ns t dis disable time dir to a 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 1.6 6.3 ns dir to b 2.0 7.6 1.8 5.9 1.6 6.0 1.2 4.8 1.7 5.5 ns t en enable time dir to a - 14.4 - 11.3 - 11.1 - 9.5 - 10.0 ns dirtob -14.3-11.7-10.9-10.0- 9.8ns v cc(a) = 1.65 v to 1.95 v t pd propagation delay a to b 1.0 7.7 0.6 5.1 0.5 4.3 0.5 3.4 0.5 3.1 ns b to a 1.0 6.1 0.7 4.6 0.5 4.4 0.5 3.9 0.5 3.7 ns t dis disable time dir to a 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 1.6 5.5 ns dir to b 1.8 7.8 1.8 5.7 1.4 5.8 1.0 4.5 1.5 5.2 ns t en enable time dir to a - 13.9 - 10.3 - 10.2 - 8.4 - 8.9 ns dir to b - 13.2 - 10.6 - 9.8 - 8.9 - 8.6 ns v cc(a) = 2.3v to 2.7v t pd propagation delay a to b 1.0 7.2 0.5 4.7 0.5 3.9 0.5 3.0 0.5 2.6 ns b to a 1.0 5.7 0.6 3.8 0.5 3.4 0.5 3.0 0.5 2.8 ns t dis disable time dir to a 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 1.5 4.2 ns dir to b 1.7 7.3 2.0 5.2 1.5 5.1 0.6 4.2 1.1 4.8 ns t en enable time dir to a - 13.0 - 9.0 - 8.5 - 7.2 - 7.6 ns dir to b - 11.4 - 8.9 - 8.1 - 7.2 - 6.8 ns v cc(a) = 3.0v to 3.6v t pd propagation delay a to b 1.0 7.1 0.5 4.5 0.5 3.7 0.5 2.8 0.5 2.4 ns b to a 1.0 6.1 0.6 3.6 0.5 3.1 0.5 2.6 0.5 2.4 ns t dis disable time dir to a 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns dir to b 1.7 7.2 0.7 5.5 0.6 5.5 0.7 4.1 1.7 4.7 ns t en enable time dir to a - 13.3 - 9.1 - 8.6 - 6.7 - 7.1 ns dir to b - 11.8 - 9.2 - 8.4 - 7.5 - 7.1 ns
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 11 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state [1] t pd is the same as t plh and t phl ; t dis is the same as t plz and t phz ; t en is the same as t pzl and t pzh . t en is a calculated value using the formula shown in section 13.4 ? enable times ? table 13. dynamic characteristics for temperature range ? 40 ? c to +125 ?c [1] voltages are referenced to gnd (ground = 0 v); for test circuit see figure 6 ; for wave forms see figure 4 and figure 5 symbol parameter conditions v cc(b) unit 1.2 v ? 0.1 v 1.5 v ? 0.1 v 1.8 v ? 0.15 v 2.5 v ? 0.2 v 3.3 v ? 0.3 v min max min max min max min max min max v cc(a) = 1.1 v to 1.3 v t pd propagation delay a to b 1.0 9.9 0.7 7.5 0.6 6.8 0.5 6.3 0.5 6.8 ns b to a 1.0 9.9 0.8 8.8 0.7 8.5 0.6 8.0 0.5 7.9 ns t dis disable time dir to a 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 ns dir to b 2.2 9.2 1.8 7.4 2.0 7.6 1.7 6.9 2.4 8.0 ns t en enable time dir to a - 19.1 - 16.2 - 16.1 - 14.9 - 15.9 ns dir to b - 19.6 - 17.2 - 16.5 - 16.0 - 16.5 ns v cc(a) = 1.4 v to 1.6 v t pd propagation delay a to b 1.0 8.8 0.7 6.0 0.6 5.1 0.5 4.1 0.5 3.9 ns b to a 1.0 7.5 0.8 6.0 0.7 5.7 0.6 5.2 0.5 5.0 ns t dis disable time dir to a 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 ns dir to b 2.0 8.3 1.8 6.5 1.6 6.6 1.2 5.3 1.7 6.1 ns t en enable time dir to a - 15.8 - 12.5 - 12.3 - 10.5 - 11.1 ns dir to b - 15.8 - 13.0 - 12.7 - 11.1 - 10.9 ns v cc(a) = 1.65 v to 1.95 v t pd propagation delay a to b 1.0 8.5 0.6 5.7 0.5 4.8 0.5 3.8 0.5 3.5 ns b to a 1.0 6.8 0.7 5.1 0.5 4.9 0.5 4.3 0.5 4.1 ns t dis disable time dir to a 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 ns dir to b 1.8 8.6 1.8 6.3 1.4 6.4 1.0 5.0 1.5 5.8 ns t en enable time dir to a - 15.4 - 11.4 - 11.3 - 9.3 - 9.9 ns dir to b - 14.6 - 11.8 - 10.9 - 9.9 - 9.6 ns v cc(a) = 2.3v to 2.7v t pd propagation delay a to b 1.0 8.0 0.5 5.2 0.5 4.3 0.5 3.3 0.5 2.9 ns b to a 1.0 6.3 0.6 4.2 0.5 3.8 0.5 3.3 0.5 3.1 ns t dis disable time dir to a 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns dir to b 1.7 8.0 2.0 5.8 1.5 5.7 0.6 4.7 1.1 5.3 ns t en enable time dir to a - 14.3 - 10.0 - 9.5 - 8.0 - 8.4 ns dir to b - 12.7 - 9.9 - 9.0 - 8.0 - 7.6 ns v cc(a) = 3.0v to 3.6v t pd propagation delay a to b 1.0 7.9 0.5 5.0 0.5 4.1 0.5 3.1 0.5 2.7 ns b to a 1.0 6.8 0.6 4.0 0.5 3.5 0.5 2.9 0.5 2.7 ns t dis disable time dir to a 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 ns dir to b 1.7 7.9 0.7 6.0 0.6 6.1 0.7 4.6 1.7 5.2 ns t en enable time dir to a - 14.7 - 10.1 - 9.6 - 7.5 - 7.9 ns dir to b - 13.1 - 10.2 - 9.3 - 8.3 - 7.9 ns
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 12 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state 12. waveforms [1] v cci is the supply voltage associated with the data input port. [2] v cco is the supply voltage associated with the output port. measurement points are given in table 14 . v ol and v oh are typical output voltage levels that occur with the output load. fig 4. the data input (a, b) to output (b, a) propagation delay times 001aae967 a, b input b, a output t plh t phl gnd v i v oh v m v m v ol measurement points are given in table 14 . v ol and v oh are typical output voltage levels that occur with the output load. fig 5. enable and disable times 001aae968 t pzl t pzh t phz t plz gnd gnd v i v cco v ol v oh v m v m v m v x v y outputs disabled outputs enabled outputs enabled output low-to-off off-to-low output high-to-off off-to-high dir input table 14. measurement points supply voltage input [1] output [2] v cc(a) , v cc(b) v m v m v x v y 1.1 v to 1.6 v 0.5v cci 0.5v cco v ol +0.1v v oh ? 0.1 v 1.65 v to 2.7 v 0.5v cci 0.5v cco v ol +0.15v v oh ? 0.15 v 3.0 v to 3.6 v 0.5v cci 0.5v cco v ol +0.3v v oh ? 0.3 v
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 13 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state [1] v cci is the supply voltage associated with the data input port. [2] v cco is the supply voltage associated with the output port. test data is given in table 15 . r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance. v ext = external voltage for measuring switching times. fig 6. test circuit for measuring switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aae331 v ext v cc v i v o dut c l r t r l r l g table 15. test data supply voltage input load v ext v cc(a) , v cc(b) v i [1] ? t/ ? v c l r l t plh , t phl t pzh , t phz t pzl , t plz [2] 1.1 v to 1.6 v v cci ?? 1.0ns/v 15pf 2k ? open gnd 2v cco 1.65 v to 2.7 v v cci ? 1.0ns/v 15pf 2k ? open gnd 2v cco 3.0 v to 3.6 v v cci ? 1.0ns/v 15pf 2k ? open gnd 2v cco
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 14 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state 13. application information 13.1 unidirectional logic l evel-shifting application the circuit given in figure 7 is an example of the 74avch1t45-q100 being used in a unidirectional logic level-shifting application. fig 7. unidirectional logic level-shifting application table 16. description unidirectional logic level-shifting application pin name function description 1v cc(a) v cc1 supply voltage of system-1 (0.8 v to 3.6 v) 2 gnd gnd device gnd 3 a out output level depends on v cc1 voltage 4 dir dir the gnd (low level) determ ines b port to a port direction 5 b in input threshold value depends on v cc2 voltage 6v cc(b) v cc2 supply voltage of system-2 (0.8 v to 3.6 v)

74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 15 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state 13.2 bidirectional logic l evel-shifting application figure 8 shows the 74avch1t45-q100 being used in a bidirectional logic level-shifting application. since the device does not have an output enable pin, the system designer should take precautions to avoid bus contention between system-1 and system-2 when changing directions. ta b l e 1 7 provides a sequence that illustrates data transmis sion from system-1 to system-2 and then from system-2 to system-1. [1] h = high voltage level; l = low voltage level; z = high-impedance off-state. fig 8. bidirectional logic l evel-shifting application table 17. description bidirectional logic level-shifting application [1] state dir ctrl i/o-1 i/o-2 description 1 h output input system-1 data to system-2 2 h z z system-2 is getting ready to send data to system-1. i/o-1 and i/o-2 are disabled. the bus-line state depends on bus hold. 3 l z z dir bit is set low. i/o-1 and i/o-2 are still disabled. the bus-line state depends on bus hold. 4 l input output system-2 data to system-1

74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 16 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state 13.3 power-up considerations the device is designed such that no special power-up sequence is required other than gnd being applied first. 13.4 enable times the enable times for the 74avch1t45-q100 are calculated from the following formulas: ? t en (dir to a) = t dis (dir to b) + t pd (b to a) ? t en (dir to b) = t dis (dir to a) + t pd (a to b) in a bidirectional application, these enable times provide the maximum delay from the time the dir bit is switched until an out put is expected. for example, if the 74avch1t45-q100 is initially tran smitting from a to b, then the dir bit is switched, the b port of the device must be disabled before presenting it with an input. after the b port has been disabled, an input signal applied to it appears on the corresponding a port after the specified propagation delay. table 18. typical total supply current (i cc(a) + i cc(b) ) v cc(a) v cc(b) unit 0 v 0.8 v 1.2 v 1.5 v 1.8 v 2.5 v 3.3 v 0 v 0 0.1 0.1 0.1 0.1 0.1 0.1 ? a 0.8 v 0.1 0.1 0.1 0.1 0.1 0.7 2.3 ? a 1.2 v 0.1 0.1 0.1 0.1 0.1 0.3 1.4 ? a 1.5 v 0.1 0.1 0.1 0.1 0.1 0.1 0.9 ? a 1.8 v 0.1 0.1 0.1 0.1 0.1 0.1 0.5 ? a 2.5 v 0.1 0.7 0.3 0.1 0.1 0.1 0.1 ? a 3.3 v 0.1 2.3 1.4 0.9 0.5 0.1 0.1 ? a
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 17 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state 14. package outline fig 9. package outline sot363 (sc-88) references outline version european projection issue date iec jedec jeita sot363 sc-88 wb m b p d e 1 e pin 1 index a a 1 l p q detail x h e e v m a a b y 0 1 2 mm scale c x 13 2 45 6 plastic surface-mounted package; 6 leads sot363 unit a 1 max b p cd e e 1 h e l p qy wv mm 0.1 0.30 0.20 2.2 1.8 0.25 0.10 1.35 1.15 0.65 e 1.3 2.2 2.0 0.2 0.1 0.2 dimensions (mm are the original dimensions) 0.45 0.15 0.25 0.15 a 1.1 0.8 04-11-08 06-03-16
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 18 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state 15. abbreviations 16. revision history table 19. abbreviations acronym description cdm charged device model cmos complementary metal oxide semiconductor dut device under test esd electrostatic discharge hbm human body model mm machine model mil military table 20. revision history document id release date data sheet status change notice supersedes 74avch1t45_q100 v.2 20130409 product data sheet - 74avch1t45_q100 v.1 modifications: ? type number 74avch1t45gm-q100 has been removed. 74avch1t45_q100 v.1 20120807 product data sheet - -
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 19 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74avch1t45_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 9 april 2013 20 of 21 nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74avch1t45-q100 dual-supply voltage level translator/transceiver; 3-state ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 9 april 2013 document identifier: 74avch1t45_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 3 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 recommended operating conditions. . . . . . . . 5 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 5 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 9 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 13 application information. . . . . . . . . . . . . . . . . . 14 13.1 unidirectional logic level-shifting application . 14 13.2 bidirectional logic level-shifting application. . . 15 13.3 power-up considerations . . . . . . . . . . . . . . . . 16 13.4 enable times . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 19 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 17.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 18 contact information. . . . . . . . . . . . . . . . . . . . . 20 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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