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buffered 2:1 tmds switch with equalization AD8194 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features 2 inputs, 1 output hdmi/dvi high speed signal switch pin-to-pin compatible with the ad8193 enables hdmi 1.3-compliant receiver 4 tmds channels per input/output supports 250 mbps to 2.25 gbps data rates supports 25 mhz to 225 mhz pixel clocks fully buffered unidirectional inputs/outputs equalized inputs for operatio n with long hdmi cables (20 m at 2.25 gbps) matched 50 input and output on-chip terminations low added jitter single-supply operation (3.3 v) standards compliant: hdmi receiver, dvi 32-lead, 5 mm 5 mm, rohs-compliant lfcsp applications advanced television (hdtv) sets multiple input displays projectors a/v receivers set-top boxes functional block diagram 07004-001 AD8194 control logic +4 4 ? + ? + ? 4 4 4 4 tx switch core high speed buffered vtto vtti ip_a[3:0] in_a[3:0] ip_b[3:0] in_b[3:0] vtti s_sel op[3:0] on[3:0] a v c c a v ee eq figure 1. typical application hdmi receiver AD8194 hdtv set dvd player set-top box 07004-002 figure 2. typical AD8194 application for hdtv sets general description the AD8194 is a low cost quad 2:1 tmds? switch for high speed hdmi?/dvi video applications. the AD8194 features equalized inputs, ideal for systems with long cable runs. its primary function is to switch the high speed signals from one of two single-link (hdmi or dvi) sources to the single-link output. the AD8194 is a fully buffered switch solution with 50 input and output terminations, providing full-swing output signal recovery and minimizing reflections for improved system signal integrity. the AD8194 is provided in a space-saving, 32-lead, lfcsp, surface-mount, rohs-compliant, plastic package and is specified to operate over the ?40c to +85c temperature range. product highlights 1. data supports rates up to 2.25 gbps, enabling greater than 1080p deep color (12-bit color) hdmi formats and greater than uxga (1600 2300) dvi resolutions. 2. fully buffered inputs and outputs. 3. input cable equalizer enables use of long cables at the input. for a typical 24 awg cable, the AD8194 compen- sates for more than 20 m at data rates up to 2.25 gbps. 4. matched 50 on-chip input and output terminations improve system signal integrity. 5. single-pin source select bit. 6. low added jitter.
AD8194 rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 typical application........................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 4 thermal resistance ...................................................................... 4 maximum power dissipation ..................................................... 4 esd caution.................................................................................. 4 pin configuration and function descriptions............................. 5 typical performance characteristics ..............................................6 theory of operation .........................................................................9 introduction...................................................................................9 input channels ..............................................................................9 output channels ...........................................................................9 switching mode .......................................................................... 10 application notes ........................................................................... 11 switching high speed signals................................................... 11 switching low speed signals.................................................... 11 pcb layout guidelines.............................................................. 11 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 11/07revision 0: initial version
AD8194 rev. 0 | page 3 of 16 specifications t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, avee = 0 v, differential input swing = 1000 mv, pattern = prbs 2 7 ? 1, data rate = 2.25 gbps, tmds outputs terminated with external 50 resistors to 3.3 v, unless otherwise noted. table 1. parameter conditions/comments min typ max unit dynamic performance maximum data rate (dr) per channel nrz 2.25 gbps bit error rate (ber) 10 ?9 added deterministic jitter 10 ps (p-p) added random jitter 1 ps (rms) differential intrapair sk ew at output 1 ps differential interpair skew 1 at output 30 ps equalization performance receiver boost frequency = 1.125 ghz 12 db input characteristics input voltage swing differential 150 1200 mv input common-mode voltage (v icm ) avcc ? 800 avcc mv output characteristics high voltage level single-ended high speed channel avcc mv low voltage level single-ended high speed channel avcc ? 600 avcc ? 400 mv rise/fall time (20% to 80%) 75 178 ps termination input resistance single-ended 50 output resistance single-ended 50 power supply avcc operating range 3 3.3 3.6 v quiescent current 2 avcc 50 70 ma vtti 40 54 ma vtto 40 65 ma power dissipation 3 429 mw source select interface input high voltage (v ih ) s_sel 2 v input low voltage (v il ) s_sel 0.8 v 1 differential interpair skew is measured between the tmds pairs of a single link. 2 typical value assumes only the selected hdmi/dvi link is active with nominal signal swings and that the unselected hdmi/dvi li nk is deactivated. minimum and maximum limits are measured at the respective extremes of input termination resistan ce and input voltage swing. 3 the total power dissipation excludes power dissipated in the 50 off-chip loads.
AD8194 rev. 0 | page 4 of 16 absolute maximum ratings table 2. parameter rating avcc to avee 3.7 v vtti avcc + 0.6 v vtto avcc + 0.6 v internal power dissipation 1.2 w high speed input voltage avcc ? 1.4 v < v in < avcc + 0.6 v high speed differential input voltage 2.0 v source select (s_sel) avee ? 0.3 v < v in < avcc + 0.6 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions: a device soldered in a 4-layer jedec circuit board for surface-mount packages. jc is specified for the exposed pad soldered to the circuit board with no airflow. table 3. thermal resistance package type ja jc unit 32-lead lfcsp 47 6.8 c/w maximum power dissipation the maximum power that can be safely dissipated by the AD8194 is limited by the associated rise in junction tempera- ture. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175c for an extended period can result in device failure. to ensure proper operation, it is necessary to observe the maximum power derating as determined by the coefficients in table 3 . esd caution
AD8194 rev. 0 | page 5 of 16 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 in_a2 ip_a2 vtti in_a3 ip_a3 avcc op3 on3 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 op2 on2 avee op1 on1 vtto op0 on0 ip_b2 in_b2 avcc ip_b1 in_b1 vtti ip_b0 in_b0 24 23 22 21 20 19 18 17 pin 1 indicator ip_a1 in_a1 s_sel ip_a0 in_a0 avee ip_b3 in_b3 AD8194 top view (not to scale) 07004-003 notes 1. the AD8194 lfcsp has an exposed paddle (epad) on the underside of the package, which aids in heat dissipation. the epad must be electrically connected to the avee supply plane to meet thermal specifications. figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic type 1 description 1 in_a2 hs i high speed input complement. 2 ip_a2 hs i high speed input. 3, 19 vtti power input termination supply. nominally connected to avcc. 4 in_a3 hs i high speed input complement. 5 ip_a3 hs i high speed input. 6, 22 avcc power positive power supply. 3.3 v nominal. 7 op3 hs o high speed output. 8 on3 hs o high speed output complement. 9 op2 hs o high speed output. 10 on2 hs o high speed output complement. 11, 27, epad avee power negative power supply. 0 v nominal. 12 op1 hs o high speed output. 13 on1 hs o high speed output complement. 14 vtto power output termination supply. nominally connected to avcc. 15 op0 hs o high speed output. 16 on0 hs o high speed output complement. 17 in_b0 hs i high speed input complement. 18 ip_b0 hs i high speed input. 20 in_b1 hs i high speed input complement. 21 ip_b1 hs i high speed input. 23 in_b2 hs i high speed input complement. 24 ip_b2 hs i high speed input. 25 in_b3 hs i high speed input complement. 26 ip_b3 hs i high speed input. 28 in_a0 hs i high speed input complement. 29 ip_a0 hs i high speed input. 30 s_sel control source selector pin. 31 in_a1 hs i high speed input complement. 32 ip_a1 hs i high speed input. 1 hs = high speed, i = input, o = output.
AD8194 rev. 0 | page 6 of 16 typical performance characteristics t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, avee = 0 v, differential input swing = 1000 mv, pattern = prbs 2 7 ? 1, data rate = 2.25 gbps, tmds outputs terminated with external 50 resistors to 3.3 v, unless otherwise noted. reference eye diagram at tp1 digital pattern generator AD8194 evaluation board serial data analyzer sma coax cable hdmi cable tp1 tp2 tp3 0 7004-004 figure 4. test circuit diagram for rx eye diagrams 0.125ui/div at 2.25gbps 250mv/di v 07004-005 figure 5. rx eye diagram at tp2 (cable = 2 m, 30 awg) 0.125ui/div at 2.25gbps 250mv/di v 07004-006 figure 6. rx eye diagram at tp2 (cable = 20 m, 24 awg) 0.125ui/div at 2.25gbps 250mv/di v 07004-007 figure 7. rx eye diagram at tp3, eq = 12 db (cable = 2 m, 30 awg) 0.125ui/div at 2.25gbps 250mv/di v 07004-008 figure 8. rx eye diagram at tp3, eq = 12 db (cable = 20 m, 24 awg)
AD8194 rev. 0 | page 7 of 16 t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, avee = 0 v, differential input swing = 1000 mv, pattern = prbs 2 7 ? 1, data rate = 2.25 gbps, tmds outputs terminated with external 50 resistors to 3.3 v, unless otherwise noted. 0 0.1 0.2 0.3 0.4 0.5 0.6 0 5 10 15 20 25 480p 1080i/720p 07004-028 hdmi cable length (meters) deterministic jitter (ui) 2m to 5m = 30awg 10m = 28awg 20m = 24awg 1080p 8-bit 1080p 12-bit figure 9. jitter vs. input cable length (see figure 4 for test setup) 0 0.2 0.4 0.6 0.8 1.0 1.2 07004-029 data rate (gbps) eye height (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 figure 10. eye height vs. data rate 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 07004-030 supply voltage (v) eye height (v) figure 11. eye height vs. supply voltage 0 10 20 30 40 50 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 07004-031 data rate (gbps) jitter (ps) dj (p-p) rj (rms) 1080p 12-bit 1.65gbps 1080p 8-bit 1080i/720p 480i 480p figure 12. jitter vs. data rate 3.0 3.2 3.4 3.6 0 10 20 30 40 50 07004-032 supply voltage (v) jitter (ps) dj (p-p) rj (rms) figure 13. jitter vs. supply voltage 0.5 1.0 1.5 02 0 10 20 30 40 50 07004-033 differential input swing (v) jitter (ps) . 0 dj (p-p) rj (rms) figure 14. jitter vs. differential input swing
AD8194 rev. 0 | page 8 of 16 t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, avee = 0 v, differential input swing = 1000 mv, pattern = prbs 2 7 ? 1, data rate = 2.25 gbps, tmds outputs terminated with external 50 resistors to 3.3 v, unless otherwise noted. 2.5 2.7 2.9 3.1 3.3 3.5 3.7 0 10 20 30 40 50 07004-034 input common-mode voltage (v) jitter (ps) dj (p-p) rj (rms) figure 15. jitter vs. input common-mode voltage 40 42 44 46 48 50 52 54 56 58 60 ?40 ?15 10 35 60 85 07004-035 temperature (c) single-ended input resistance ( ? ) figure 16. single-ended input resistance vs. temperature ?40 ?15 10 35 60 85 0 10 20 30 40 50 07004-036 temperature (c) jitter (ps) dj (p-p) rj (rms) figure 17. jitter vs. temperature 0 20 40 60 80 100 120 140 160 0 20406080100 ?40 ?20 07004-037 temperature (c) rise/fall time 20% to 80% (ps) rise time fall time figure 18. rise and fall time vs. temperature
AD8194 rev. 0 | page 9 of 16 theory of operation introduction the primary function of the AD8194 is to switch the high speed signals from one of two (hdmi or dvi) single-link sources to one output. each source group consists of four differential, high speed channels. the four high speed channels include a data- word clock and three transition minimized differential signaling (tmds) data channels running at 10 the data-word clock frequency for data rates up to 2.25 gbps. all four high speed channels of the AD8194 are identical; that is, the pixel clock can be run on any of the four tmds channels. the AD8194 does not provide switching of the low speed ddc and cec signals. the AD8194 is an equalized, buffered tmds switch with low added jitter. the output pins are electrically isolated from the inputs and the input equalizer recovers and transmits an open, full-swing data eye at the output, even for heavily attenuated input signals. because the AD8194 is a tmds-only switch, a complete hdmi switch solution requires another component to switch the low speed ddc channels. several low cost cmos switches can be used along with the AD8194 to make an hdmi 1.3-compliant 2:1 link switch. the requirements for such a switch are as follows: ? low input capacitance. the hdmi 1.3 specification limits the total ddc link capacitance for an hdmi sink to less than 50 pf. this 50 pf limit includes the hdmi connector, the pcb, the capacitance of the cmos switch, and what- ever capacitance is seen at the input of the hdmi receiver. ? low channel on resistance (r on ). switches with high on resistance degrade the quality of the ddc signals. ? an appropriate form factor to switch the ddc and hpd signals as necessary. a reference design that incorporates the AD8194 and a low cost cmos switch is described in more detail in the evaluation board section. in addition to the AD8194, analog devices, inc., offers several hdmi switches with integrated ddc, in a variety of form factors. input channels each high speed input differential pair terminates to the 3.3 v vtti power supply through a pair of single-ended 50 on-chip resistors, as shown in figure 19 . these matched on- chip terminations absorb reflections on the input tmds channels, properly terminating the inputs and improving overall system signal integrity. the input termination resistors all have series switches, as shown in figure 19 . the state of these switches is determined by the s_sel signal, which also controls the input selection. the termination switches for the selected input channel are closed (terminations present), whereas the termination switches for the unselected input are open (high-z inputs). the input equalizer of the AD8194 provides 12 db of high frequency boost. no specific cable length is suggested for use with the AD8194 because cable performance varies widely between manufacturers; however, in general, the equalization of the AD8194 does not degrade the system signal integrity, even for short input cables. for a 24 awg reference cable, the AD8194 can equalize more than 20 m at data rates up to 2.25 gbps. cable eq 50? 50? ip_xx in_xx avee v tti 0 7004-019 figure 19. high speed input simplified schematic output channels each high speed output differential pair is terminated to the 3.3 v vtto power supply through two single-ended 50 on-chip resistors, as shown in figure 20 . these matched on- chip back terminations absorb reflections on the output tmds channels and improve the overall system signal integrity. these termination resistors are always present in the outputs and they cannot be switched out. v tto 50? 50? opx onx avee i out 07004-020 figure 20. high speed output simplified schematic in a typical application, the AD8194 output is connected to the input of an hdmi/dvi receiver, which provides a second set of matched terminations in accordance with the hdmi 1.3 specification. if no receiver is connected, each of the AD8194 output pins should be tied to 3.3 v through a 50 on-board termination resistor.
AD8194 rev. 0 | page 10 of 16 switching mode the source selector pin, s_sel, is used to select which of the two input groups is routed to the output. source a is selected when s_sel is pulled up to logic high, and source b is selected when s_sel is pulled down to logic low. logic levels for this pin are set in accordance with the specifications listed in table 5 . the AD8194 can be used as a single-link tmds buffer by setting s_sel to one fixed logic value. s_sel also controls the switch status of the input termination resistors. the termination resistors for the selected input are always connected, whereas the termination resistors for the unselected input are always switched out (high-z inputs). table 5. s_sel description s_sel selected input input termination status 0 input b input b terminations enabled, input a terminations disabled 1 input a input a terminations enabled, input b terminations disabled
AD8194 rev. 0 | page 11 of 16 application notes switching high speed signals the AD8194 is a quad 2:1 tmds switch that is used to switch the high speed signals of two input hdmi links to a single hdmi output. switching low speed signals because the AD8194 is a tmds-only switch, a complete hdmi switch solution requires another component to switch the low speed ddc channels. the hdmi 1.3 specification places a number of restrictions on the low speed signal path that limit the selection of a suitable low cost ddc switch. the first requirement is that the switch must be bidirectional to convey the i 2 c? protocol signals that pass through it. a cmos device is the simplest switch with this capability. the second hdmi requirement for the ddc signals is that the total ddc signal path capacitance be less than 50 pf. the total capacitance comprises the hdmi connector, the pc board traces, the ddc switch, and the input capacitance of the hdmi receiver. as a practical design consideration, a suitable ddc switch has a total channel capacitance of less than 10 pf. finally, the channel on-resistance (r on ) of the ddc switch must not be too high; otherwise, the voltage drop across it violates the maximum v ol of the i 2 c signals. any switch with an on resistance of approximately 100 is sufficient in a typical application, assuming that the end application includes an i 2 c-compliant receiver device. switches with lower channel on resistance have improved v ol performance. for the AD8194 evaluation board, the mc74lvx4053 was chosen to switch the low speed signals. this part has a maximum r on of 108 and a maximum parasitic capacitance of 10 pf. refer to the evaluation board section for details on how to use the mc74lvx4053 with the AD8194 in an application. pcb layout guidelines the AD8194 is used to switch hdmi/dvi video signals, which are differential, unidirectional, and high speed (up to 2.25 gbps). the channels that carry the video data must be controlled impedance, terminated at the receiver, and capable of operating up to at least 2.25 gbps. it is especially important to note that the differential traces that carry the tmds signals should be designed with a controlled diff erential impedance of 100 . the AD8194 provides single-ended 50 terminations on chip for both its inputs and outputs. transmitter termination is not fully specified by the hdmi standard, but the inclusion of the 50 output terminations improves the overall system signal integrity. tmds signals the audiovisual (av) data carried on these high speed channels is encoded by a technique called transition minimized differ- ential signaling (tmds) and, in the case of hdmi, is also encrypted according to the high bandwidth digital content protection (hdcp) standard. in the hdmi/dvi standard, four differential pairs carry the tmds signals. for dvi, three of these pairs are dedicated to carrying rgb video and sync data. for hdmi, audio data is also interleaved with the video data; the dvi standard does not incorporate audio information. the fourth high speed differential pair is used for the av data-word clock and runs at one-tenth the speed of the tmds data channels. the four high speed channels of the AD8194 are identical. no concession was made to lower the bandwidth of the fourth channel for the pixel clock, so any channel can be used for any tmds signal. the user chooses which signal is routed over which channel. additionally, the tmds channels are symmetrical; therefore, the p and n of a given differential pair are inter- changeable, provided the inversion is consistent across all inputs and outputs of the AD8194. however, the routing between inputs and outputs through the AD8194 is fixed. for example, output channel 0 always switches between input a0 and input b0, and so forth. the AD8194 buffers the tmds signals, and the input traces can be considered electrically independent of the output traces. in most applications, the quality of the signal on the input tmds traces is more sensitive to the pcb layout. regardless of the data being carried on a specific tmds channel, or whether the tmds line is at the input or the output of the AD8194, all four high speed signals should be routed on a pcb in accordance with the same rf layout guidelines. layout for the tmds signals the tmds differential pairs can be either microstrip traces, routed on the outer layer of a board, or stripline traces, routed on an internal layer of the board. if microstrip traces are used, there should be a continuous reference plane on the pcb layer directly below the traces. if stripline traces are used, they must be sandwiched between two continuous reference planes in the pcb stackup. additionally, the p and n of each differential pair must have a controlled differential impedance of 100 . the characteristic impedance of a differential pair is a function of several variables, including the trace width, the distance separating the two traces, the spacing between the traces and the reference plane, and the dielectric constant of the pc board binder material. interlayer vias introduce impedance discontinuities that can cause reflections and jitter on the signal path; therefore, it is preferable to route the tmds lines exclusively on one layer of the board, particularly for the input traces. additionally, to prevent unwanted signal coupling and interference, route the tmds signals away from other signals and noise sources on the pcb.
AD8194 rev. 0 | page 12 of 16 both traces of a given differential pair must be equal in length to minimize intrapair skew. maintaining the physical symmetry of a differential pair is integral to ensuring its signal integrity; excessive intrapair skew can introduce jitter through duty cycle distortion (dcd). the p and n of a given differential pair should always be routed together to establish the required 100 differential impedance. enough space should be left between the differential pairs of a given group so that the n of one pair does not couple to the p of another pair. for example, one tech- nique is to make the interpair distance 4 to 10 times wider than the intrapair spacing. any group of four tmds channels (input a, input b, or the output) should have closely matched trace lengths to minimize interpair skew. severe interpair skew can cause the data on the four different channels of a group to arrive out of alignment with one another. a good practice is to match the trace lengths for a given group of four channels to within 0.05 inches on fr4 material. the length of the tmds traces should be minimized to reduce overall signal degradation. commonly used pc board material such as fr4 is lossy at high frequencies; therefore, long traces on the circuit board increase signal attenuation, resulting in decreased signal swing and increased jitter through intersymbol interference (isi). controlling the characterist ic impedance of a tmds differential pair the characteristic impedance of a differential pair depends on a number of variables, including the trace width, the distance between the two traces, the height of the dielectric material between the trace and the reference plane below it, and the dielectric constant of the pcb binder material. to a lesser extent, the characteristic impedance also depends upon the trace thickness and the presence of solder mask. there are many combinations that can produce the correct characteristic impedance. it is generally required to work with the pc board fabricator to obtain a set of parameters to produce the desired results. to guarantee a differential pair with a differential impedance of 100 over the entire length of the trace, change the width of the traces in a differential pair based on how closely one trace is coupled to the other. when the two traces of a differential pair are close and strongly coupled, they should have a width that produces a 100 differential impedance. when the traces split apart to go into a connector, for example, and are no longer so strongly coupled, the width of the traces should be increased to yield a differential impedance of 100 in the new configuration. ground current return in some applications, it may be necessary to invert the output pin order of the AD8194. this requires routing the tmds traces on multiple layers of the pcb. when routing differential pairs on multiple layers, it is also necessary to reroute the corresponding reference plane to provide one continuous ground current return path for the differential signals. standard plated through-hole vias are acceptable for both the tmds traces and the reference plane. an example of this is illustrated in figure 21 . pcb dielectric silkscreen silkscreen pcb dielectric pcb dielectric layer 2: gnd (reference plane) layer 4: signal (microstrip) through-hole vias layer 1: signal (microstrip) keep reference plane adjacent to signal on all layers to provide continuous ground current return path. layer 3: pwr (reference plane) 07004-012 figure 21. example routing of reference plane tmds terminations the AD8194 provides internal 50 single-ended terminations for all of its high speed inputs and outputs. the termination resistors back-terminate the output tmds transmission lines. these back-terminations act to absorb reflections from imped- ance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. for example, interlayer vias can be used to route the AD8194 tmds outputs on multiple layers of the pcb without severely degrading the quality of the output signal. in a typical application, the AD8194 output is connected to an hdmi/dvi receiver or to another device with a 50 single-ended input termination. it is recommended that the outputs be terminated with external 50 on-board resistors when the AD8194 is not connected to another device.
AD8194 rev. 0 | page 13 of 16 auxiliary control signals there are four single-ended control signals associated with each source or sink in an hdmi/dvi application. these are hot plug detect (hpd), consumer electronics control (cec), and two display data channel (ddc) lines. the two signals on the ddc bus are sda and scl (serial data and serial clock, respectively). the AD8194, which is a low cost part, does not have any addi- tional capability to switch these signals; other means are required to switch these signals if required. in general, it is sufficient to route each auxiliary signal as a single-ended trace. these signals are not sensitive to impedance discontinuities, do not require a reference plane, and can be routed on multiple layers of the pcb. however, it is best to follow strict layout practices whenever possible to prevent the pcb design from affecting the overall application. the specific routing of the hpd, cec, and ddc lines depends upon the application in which the AD8194 is being used. for example, the maximum speed of signals present on the auxiliary lines is 100 khz i 2 c data on the ddc lines; therefore, any layout that enables 100 khz i 2 c to be passed over the ddc bus should suffice. the hdmi 1.3 specification, however, places a strict 50 pf limit on the amount of capacitance that can be measured on either sda or scl at the hdmi input connector. this 50 pf limit includes the hdmi connector, the pcb, the capacitance of the cmos switch, and whatever capacitance is seen at the input of the hdmi receiver. there is a similar limit of 100 pf of input capacitance for the cec line. the parasitic capacitance of traces on a pcb increases with trace length. to help ensure that a design satisfies the hdmi specification, the length of the cec and ddc lines on the pcb should be made as short as possible. additionally, if there is a reference plane in the layer adjacent to the auxiliary traces in the pcb stackup, relieving or clearing out this reference plane immediately under the auxiliary traces significantly decreases the amount of parasitic trace capacitance. an example of the board stackup is shown in figure 22 . pcb dielectric layer 1: signal (microstrip) silkscreen silkscreen pcb dielectric pcb dielectric layer 2: gnd (reference plane) layer 3: pwr (reference plane) layer 4: signal (microstrip) w 3w 3w reference layer relieved underneath microstrip 07004-013 figure 22. example board stackup hpd is a dc signal presented by a sink to a source to indicate that the source edid is available for reading. the placement of this signal is not critical, but it should be routed as directly as possible. power supplies the AD8194 has three separate power supplies referenced to a single ground. the supply/ground pairs are ? avc c /avee ? vtti/avee ? vtto/avee the avcc/avee (3.3 v) supply powers the core of the AD8194. the vtti/avee supply (3.3 v) powers the input termination (see figure 19 ). similarly, the vtto/avee supply (3.3 v) powers the output termination (see figure 20 ). in a typical application, all pins labeled avee should be con- nected directly to ground. all pins labeled avcc, vtti, or vtto should be connected to 3.3 v. the supplies can also be powered individually, but care must be taken to ensure that each stage of the AD8194 is powered correctly. power supply bypassing the AD8194 requires minimal supply bypassing. when powering the supplies individually, place a 0.01 f capacitor between each 3.3 v supply pin (avcc, vtti, and vtto) and ground to filter out supply noise. generally, bypass capacitors should be placed near the power pins and should connect directly to the relevant supplies (without long intervening traces). for example, to minimize the parasitic inductance of the power supply decoupling capacitors, minimize the trace length between capacitor landing pads and the vias as shown in figure 23 . extra added inductance recommended not recommended 07004-014 figure 23. recommended pad outline for bypass capacitors in applications where the AD8194 is powered by a single 3.3 v supply, it is recommended to use two reference supply planes and bypass the 3.3 v reference plane to the ground reference plane with one 220 pf, one 1000 pf, two 0.01 f, and one 4.7 f capacitors. the capacitors should via down directly to the supply planes and be placed within a few centimeters of the AD8194.
AD8194 rev. 0 | page 14 of 16 evaluation board the AD8194 evaluation board illustrates one way to implement a 2:1 hdmi link switch with an AD8194 and a cmos switch. the AD8194 evaluation board deviates from a typical application in that it uses an hdmi connector for the output as well as for the inputs. this setup makes it easy to connect equipment to the AD8194 evaluation board with standard hdmi cables. however, this arrangement requires crossing over the tmds signals on the output side (see figure 24 ). in a typical application, the output of the AD8194 is routed directly into an hdmi receiver. because a receiver is generally designed to interface directly to an hdmi input connector, it is not necessary to cross over the tmds signals in a typical application (see figure 25 ). crossover required hdmi connector 1 19 19 AD8194 hdmi connector 1 1 19 hdmi connector 07004-027 figure 24. block diagram of AD8194 evaluation board showing output crossover hdmi connector hdmi receiver 1 19 AD8194 07004-026 figure 25. hdmi signals to hdmi receiver, no crossover required
AD8194 rev. 0 | page 15 of 16 figure 26 shows the layout of the tmds traces. these are 100 differential, controlled-impedance traces. serpentine traces are used for some of the paths to match the lengths within a group of four. the gray traces are routed on the top layer and the black traces on the bottom layer. the low speed switching is performed by an mc74lvx4053. this part contributes a maximum on resistance of 108 and a maximum capacitive load of 10 pf. the same select signal (s_sel) controls both the AD8194 and the mc74lvx4053. 07004-015 figure 26. layout of tmds traces
AD8194 rev. 0 | page 16 of 16 outline dimensions 092007-a compliant to jedec standards mo-220-vhhd-2 1 32 8 9 25 24 17 16 2.85 2.70 sq 2.55 top view coplanarity 0.08 3.50 ref 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.20 min * exposed pad (bot tom view) pin 1 indicator 0.30 0.25 0.18 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom seating plane 0.50 0.40 0.30 5.00 bsc sq 4.75 bsc sq * the AD8194 has a conductive heat slug to help dissipate heat and ensure reliable operation of the device over the full hdmi/dvi temperature range. the slug is exposed on the bottom of the package and electrically connected to avee. it is recommended that no pcb signal traces or vias be located under the package that could come in contact with the conductive slug. attaching the slug to an avee plane reduces the junction temperature of the device which may be beneficial in high temperature environments. figure 27. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-8) dimensions shown in millimeters ordering guide model temperature range package description package option ordering quantity AD8194acpz 1 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-8 AD8194acpz-r7 1 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq], reel cp-32-8 1,500 AD8194-evalz 1 evaluation board 1 z = rohs compliant part. ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07004-0-1 1/07(0)

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