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lt8582 1 8582f typical application features description dual 3a boost/inverting/sepic dc/dc converter with fault protection the lt ? 8582 is a dual independent channel pwm dc/dc converter with a power good pin and built-in fault protection to help guard against input overvoltage and overtempera- ture conditions. each channel consists of a 42v master switch and a 42v slave switch that can be tied together for a total current limit of 3a. the lt8582 is ideal for many local power supply designs. each channel can be easily configured in boost, sepic, inverting, or flyback configurations. together, the two chan- nels can produce a 12v and a C12v output with 14.4w of combined output power from a 5v input. in addition, the lt8582s slave switch allows the part to be configured in high voltage, high power charge pump topologies that are more efficient and require fewer components than traditional circuits. the lt8582 also features innovative shdn pin circuitry that allows for slowly varying input signals and an adjustable undervoltage lockout function. additional features such as output short protection, frequency foldback and soft-start are integrated. the lt8582 is available in a 24-pin 7mm 4mm dfn package. 1.5mhz, 5v to 12v efficiency and power loss (load between 12v and C12v outputs) applications n local power supply n vacuum fluorescent display (vfd) bias supplies n tft-lcd bias supplies n automotive engine control unit (ecu) power l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 7579816. n dual 42v, 3a combined power switch n master/slave (1.7a/1.3a) switch design n wide input range: 2.5v to 22v operating, 40v maximum transient n power good pin for event based sequencing n switching frequency up to 2.5mhz n each channel easily configurable as a boost, sepic, inverting or flyback converter n low v cesat switch: 270mv at 2.75a (typical) n can be synchronized to an external clock n output short-circuit protection n high gain shdn pin accepts slowly varying input signals n 24-pin 7mm 4mm dfn package load current (a) 0 20 efficiency (%) power loss (w) 30 80 70 60 50 90 0.2 0.3 0.6 8582 ta01b 40 0.1 0.4 0.5 100 0 0.4 2.4 2.0 1.6 1.2 2.8 0.8 3.2 swb2 swa2 swb1 swa1 lt8582 8582 ta01a pg1 sync1 clkout1 clkout2 215k sync2 pg2 v in2 shdn2 v in1 shdn1 v c1 ss1 rt1 gnd rt2 ss2 gate2 v c2 fbx2 fbx1 gate1 v out1 12v 550ma v out2 C12v 550ma 4.7f 2.2f v in 5v 0.1f 6.04k 0.1f 53.6k 53.6k 4.7nf 47pf 47pf 14.7k 6.49k 100k 100k 143k 215k 4.7h s 4.7h s 2.2nf 10f 10f 130k 4.7f 10f 4.7h
lt8582 2 8582f pin configuration absolute maximum ratings v in1 voltage ............................................... C0.3v to 40v swa1/swb1 voltage .................................. C0.4v to 42v rt1 voltage ................................................. C0.3v to 5v ss1 voltage .............................................. C0.3v to 2.5v fbx1 voltage ................................................ C0.3v to 5v v c1 voltage .................................................. C0.3v to 2v shdn1 voltage .........................................................40v shdn1 current ...................................................... C1ma sync1 voltage .......................................... C0.3v to 5.5v gate1 voltage ........................................... C0.3v to 60v pg1 voltage ............................................... C0.3v to 40v pg1 current ........................................................0.5ma clkout1 ........................................................... (note 5) operating junction temperature range lt8582e ............................................ C40c to 125c lt8582i ............................................. C40c to 125c storage temperature range .................. C65c to 150c note: absolute maximum ratings are shown for channel 1 only. channel 2 ratings are identical. top view 25 gnd dkd package 24-lead (7mm 4mm) plastic dfn swa1 v in1 pg1 gate1 v c1 fbx1 fbx2 v c2 gate2 pg2 v in2 swa2 swb1 clkout1 shdn1 rt1 ss1 sync1 sync2 ss2 rt2 shdn2 clkout2 swb2 12 11 10 13 14 15 16 17 18 19 20 21 22 23 24 9 8 7 6 5 4 3 2 1 t jmax = 125c, ja = 34c/w, jc = 7c/w exposed pad (pin 25) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt8582edkd#pbf lt8582edkd#trpbf 8582 24-pin (7mm 4mm) plastic dfn C40c to 125c lt8582idkd#pbf lt8582idkd#trpbf 8582 24-pin (7mm 4mm) plastic dfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a la bel on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ (note 1) lt8582 3 8582f electrical characteristics parameter conditions min typ max units minimum input voltage v in l 2.3 2.5 v v in overvoltage lockout 22.2 24.5 27 v positive feedback voltage l 1.185 1.204 1.220 v negative feedback voltage l 2 7 16 mv positive fbx pin bias current v fbx = positive feedback voltage, current into pin l 81 83.3 85 a negative fbx pin bias current v fbx = negative feedback voltage, current out of pin l 81 83.3 85.5 a error amp transconductance i = 10a 280 mhos error amp voltage gain 80 v/v quiescent current v shdn = 2.5v, not switching 2.1 2.5 ma quiescent current in shutdown v shdn = 0 0 1 a reference line regulation 2.5v v in 20v 0.01 0.05 %/v switching frequency, f osc r t = 31.6k r t = 407k l l 2.125 170 2.5 200 2.875 230 mhz khz switching frequency in foldback compared to normal f osc 1/6 ratio switching frequency range free-running or synchronizing l 200 2500 khz sync high level for sync l 1.3 v sync low level for sync l 0.4 v sync clock pulse duty cycle v sync = 0v to 2v 20 80 % recommended min sync ratio f sync /f osc 3/4 ratio minimum off-time 45 ns minimum on-time 55 ns swa current limit minimum duty cycle maximum duty cycle l l 1.8 1.3 2.4 1.8 3 2.5 a a swa fault current limit minimum duty cycle maximum duty cycle l l 2.2 1.6 2.8 2.3 3.5 3.0 a a sw current sharing, i swb /i swa swa and swb tied together 0.79 a/a swa + swb current limit minimum duty cycle, i swb /i swa = 0.79 maximum duty cycle, i swb /i swa = 0.79 l l 3.3 2.3 4.3 4.1 5.4 4.5 a a swa + swb fault current limit minimum duty cycle, i swb /i swa = 0.79 maximum duty cycle, i swb /i swa = 0.79 l l 4 2.8 5 4 6.3 5.4 a a switch v cesat i swa + i swb = 2.75a 270 mv swa leakage current v swa = 5v, v shdn = 0 0.01 1 a swb leakage current v swb = 5v, v shdn = 0 0.01 1 a ss charge current v ss = 30mv, current flows out of ss pin l 5.7 8.8 11.7 a ss discharge current part in fault, v ss = 2.1v, current flows into ss pin l 5.7 8.8 11.7 a ss high detection voltage part in fault l 1.65 1.84 2 v ss low detection voltage part exiting fault l 15 55 100 mv shdn minimum input voltage high active mode, shdn rising active mode, shdn falling l l 1.26 1.21 1.31 1.27 1.4 1.35 v v shdn input voltage low shutdown mode l 0.3 v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 5v, v shdn = v in , unless otherwise noted (note 2). specifications are identical for both channels unless noted otherwise. lt8582 4 8582f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt8582e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating temperature range are assured by design, characterization and correlation with statistical process controls. the lt8582i is guaranteed over the full C40c to 125c operating junction temperature range. parameter conditions min typ max units shdn pin bias current v shdn = 3v v shdn = 1.3v v shdn = 0v 10.1 45 12.1 0 65 14.1 0.1 a a a clkout output voltage high 1ma out of clkout pin 1.9 2.1 2.3 v clkout output voltage low 1ma into clkout pin 30 200 mv clkout1 duty cycle all t j 50 % clkout2 duty cycle t j = C40c t j = 25c t j = 125c 22.5 42 72 % % % clkout rise time c clkout = 120pf 25 ns clkout fall time c clkout = 120pf 15 ns gate pull-down current v gate = 3v v gate = 20v l l 0.8 0.8 1 1 1.2 1.2 ma ma gate leakage current v gate = 50v, gate off 0.01 1 a pg threshold for positive feedback voltage v fbx rising 1.09 1.15 1.20 v pg threshold for negative feedback voltage v fbx falling 20 65 120 mv pg hysteresis for feedback voltage 4mv pg output voltage low 100a into pg pin, v fbx = 1v l 70 150 mv pg leakage current v pg = 40v, v fbx = 1.204v 0.01 1 a electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 5v, v shdn = v in , unless otherwise noted (note 2). specifications are identical for both channels unless noted otherwise. note 3: current limit guaranteed by design and/or correlation to static test. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation over the specified maximum operating junction temperature may impair device reliability. note 5: do not apply a positive or negative voltage or current source to clkout, otherwise permanent damage may occur. lt8582 5 8582f typical performance characteristics switch current limit at minimum duty cycle clkout duty cycle oscillator frequency switching frequency during soft-start gate pin current (v ss = 2.1v) switch current limit vs duty cycle switch saturation voltage switch current sharing t a = 25c, unless otherwise noted. swa current (a) 0 0 i swb /i swa (a/a) 0.4 0.3 0.2 0.1 0.6 0.8 0.7 0.9 1 1.5 3.5 8582 g03 0.5 0.5 2 2.5 3 1.0 temperature (c) C50 0 swa + swb current (a) 2 1 3 4 0 25 150 8582 g04 C25 50 75 100 125 5 temperature (c) C50 0 clkout duty cycle (%) 40 20 60 80 0 150 8582 g06 C25 25 50 75 100 125 100 channel 1 channel 2 gate pin voltage (v) 0 gate pin current (a) 60 8582 g09 10 20 30 40 50 1100 1000 900 800 700 600 500 400 300 200 100 0 t a = C40c t a = 25c t a = 125c ss voltage (v) 0 0 swa + swb current (a) 2 1 3 4 0.4 1.2 8582 g05 0.2 0.6 0.8 1 5 commanded current limit vs ss voltage temperature (c) C50 0.2 frequency (mhz) 0.6 0.4 0.0 0.8 1.0 1.2 1.4 1.6 2.4 2.2 2.0 1.8 0 150 8582 g07 C25 25 50 75 100 125 2.8 2.6 3.0 r t = 31.6k r t = 402k duty cycle (%) 10 0 swa + swb current (a) 1 3 4 40 50 90 8582 g01 2 20 30 60 70 80 5 swa + swb current (a) 0 0 saturation voltage (mv) 50 150 250 200 300 1 1.5 3.5 8582 g02 100 0.5 2 2.5 3 350 v sw1 = v sw2 fbx voltage (v) 0 normalized oscillator frequency (f sw /f nom ) 1/4 1/5 1/3 1/2 1.2 8582 g08 0.2 0.4 0.6 0.8 1 1 inverting configurations noninverting configurations lt8582 6 8582f typical performance characteristics shdn pin current shdn pin current internal uvlo clkout rise and fall times at 1mhz v in overvoltage lockout pg threshold gate pin current (v gate = 5v) active/lockout threshold t a = 25c, unless otherwise noted. ss voltage (v) 0 gate pin current (a) 1.5 8582 g10 0.25 0.5 0.75 1 1.25 1000 900 800 700 600 500 400 300 200 100 0 shdn voltage (v) 0 shdn pin current (a) 2 8582 g13 0.25 0.50 0.75 1 1.75 1.25 1.50 30 25 20 15 10 5 0 t a = C40c t a = 25c t a = 125c shdn voltage (v) 0 shdn pin current (a) 40 8582 g14 5 10 15 20 35 25 30 300 250 200 150 100 50 0 t a = C40c t a = 25c t a = 125c temperature (c) C50 v in voltage (v) 150 8582 g15 C25 0 25 50 125 75 100 2.50 2.45 2.40 2.35 2.30 2.25 2.20 2.15 2.10 clkout capacitive load (pf) clkout transition time (ns) 150 8582 g16 0 25 50 125 75 100 40 35 30 25 20 15 10 5 0 rise time fall time temperature (c) v in voltage (v) 150 8582 g17 C50 C25 0 100 125 50 25 75 28 27 26 25 24 23 22 20 19 21 18 positive feedback voltage temperature (c) C50 fbx voltage (v) 150 8582 g11 C25 0 25 50 75 100 125 1.220 1.215 1.210 1.205 1.200 1.195 1.190 temperature (c) fbx voltage (v) 150 8582 g18 C50 C25 0 100 125 50 25 75 1.50 1.25 1.00 0.75 0.25 0.50 0 temperature (c) C50 shdn voltage (v) 150 8582 g12 C25 0 25 50 75 100 125 1.40 1.38 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 1.20 shdn rising shdn falling lt8582 7 8582f pin functions fbx1, fbx2 (pin 6/pin 7): positive and negative feedback pins. for an inverting or noninverting output converter, tie a resistor from the fbx pin to v out according to the following equations: r ; noninverting converter fbx = v out C 1.204v 83.3a ? ? ? ? ? ? r fbx = | | v out | | + 7mv 83.3a ; inverting converter ? ? ? ? ? ? vc1, vc2 (pin 5/pin 8): error amplifier output pins. tie external compensation network to these pins. gate1, gate2 (pin 4/pin 9): pmos gate drive pins. the gate pin is a pull-down current source and can be used to drive the gate of an external pmos transistor for output short-circuit protection or output disconnect. the gate pin current increases linearly with the ss pin voltage, with a maximum pull-down current of 1ma at ss voltages exceeding 550mv. note that if the ss voltage is greater than 550mv and the gate pin voltage is less than 2v, the gate pin looks like a 2k impedance to ground. see the appendix for more information. pg1, pg2 (pin 3/pin 10): power good indication pins. this active high pin indicates that the fbx pin voltage for the corresponding channel is within 4% of its regulation voltage (v fbx > 1.15v for noninverting outputs or v fbx < 65mv for inverting outputs). for most applications, a 4% change in v fbx corresponds to an 8% change in v out . this open drain output requires a pull-up resistor to indicate power good. also, the status is valid only when shdn > 1.31v and v in > 2.3v. vin1, vin2 (pin 2/pin 11): input supply pins. must be locally bypassed. swa1, swa2 (pin 1/pin 12): master switch pins. this is the collector of the internal master npn power switch for each channel. swa is designed to handle a peak collector current of 1.7a (minimum). minimize the metal trace area connected to this pin to minimize emi. swb1, swb2 (pin 24/pin 13): slave switch pins. this is the collector of the internal slave npn power switch for each channel. swb is designed to handle a peak collector current of 1.3a (minimum). minimize the metal trace area connected to this pin to minimize emi. clkout1, clkout2 (pin 23/pin 14): clock output pins. use these pins to synchronize one or more other ics to either channel of the lt8582. can also be used to syn- chronize channel 1 or channel 2 of the lt8582 with the other channel of the lt8582. this pin oscillates at the same frequency as the internal oscillator of the part or, if active, the sync pin. the clkout pin signal on ch1 is 180 out of phase with the internal oscillator or sync pin and the duty cycle is fixed at ~50%. the clkout pin signal on ch2 is in phase with the internal oscillator or sync pin and the duty cycle varies linearly with the parts junction temperature. note that clkout of either channel is only meant to drive capacitive loads up to 120pf. shdn1 , shdn2 (pin 22/pin 15): shutdown pins. in conjunction with the uvlo (undervoltage lockout) circuit, these pins are used to enable/disable the channel and restart the soft-start sequence. drive below 0.3v to dis- able the channel with very low quiescent current. drive above 1.31v (typical) to activate the channel and restart the soft-start sequence. do not float these pins. rt1, rt2 (pin 21/pin 16): timing resistor pins. adjusts the switching frequency of the corresponding channel. place a resistor from these pins to ground to set the frequency to a fixed free running level. do not float these pins. ss1, ss2 (pin 20/pin 17): soft-start pins. place a soft- start capacitor here. upon start-up, the ss pins will be charged by a (nominally) 250k resistor to ~2.1v. during a fault, the ss pin for the corresponding channel will be slowly charged up and discharged as part of a timeout sequence (see the state diagram for more information). sync1, sync2 (pin 19/pin 18): use to synchronize the switching frequency of a channel to an outside clock. the high voltage level of the clock must exceed 1.3v and the low level must be less than 0.4v. drive these pins to less than 0.4v to revert to the internal free running clock for the corresponding channel. see the applications information section for more information. gnd (exposed pad pin 25): ground. exposed pad must be soldered directly to local ground plane. (ch1/ch2) lt8582 8 8582f block diagram figure 1. block diagram C + 250k 1.84v 1.31v 50k v in1 2.1v vc1 55mv driver disable i swa1 comparator die temp 165c v in1 22.2v (min) 2a (min) gnd swa1 swb1 8582 bd start-up and fault logic soft-start rq s sr1 driver C + C + C + C + C + C + C + fbx1 1.15v 65mv fbx1 C + C + 7 # & |