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this is information on a product in full production. february 2015 docid023010 rev 4 1/18 STL7DN6LF3 automotive-grade dual n-channel 60 v, 35 m ? typ., 6.5 a stripfet? f3 power mosfet in powerflat? 5x6 double island datasheet - production data figure 1. internal schematic diagram features ? designed for automotive application and aec-q101 qualified ? logic level v gs(th) ? 175 c junction temperature ? 100% avalanche rated ? wettable flank package applications ? switching applications description this device is a dual n-channel power mosfet developed using stripfet? f3 technology. it is designed to minimize on-resistance and gate charge to provide superior switching performance. powerflat? 5x6 double island 1 2 3 4 top view order code v ds r ds(on) max i d STL7DN6LF3 60 v 43 m 6.5 a table 1. device summary order code marking package packaging STL7DN6LF3 7dn6lf3 powerflat? 5x6 double island (1) tape and reel 1. for wettable flank option, please contact st sale offices. www.st.com
contents STL7DN6LF3 2/18 docid023010 rev 4 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
docid023010 rev 4 3/18 STL7DN6LF3 electrical ratings 18 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v ds drain-source voltage 60 v v gs gate-source voltage 20 v i d (1),(2) 1. specified by design. not subject to production test. 2. current is limited by bonding, with an r thjc = 2.9 c/w the chip is able to carry 22 a at 25 c. drain current (continuous) at t c = 25 c 20 a i d (1) drain current (continuous) at t c = 100 c 16 a i d (4) drain current (continuous) at t pcb = 25 c 6.5 a i d (4) drain current (continuous) at t pcb =100 c 4.6 a i dm (3),(4) 3. pulse width limited by safe operating area 4. when mounted on fr-4 board of 1inch2, 2oz cu, t < 10 sec drain current (pulsed) 26 a p tot total dissipation at t c = 25c 52 w p tot (4) total dissipation at t pcb = 25c 4.3 w i av not-repetitive avalanche current 6.5 a e as (5) 5. starting t j = 25 c, i d = 8 a, v dd = 25 v single pulse avalanche energy 190 mj t j t stg operating junction temperature storage temperature -55 to 175 c table 3. thermal resistance symbol parameter value unit r thj-case thermal resistance junction-case 2.9 c/w r thj-pcb (1) 1. when mounted on fr-4 board of 1inch2, 2oz cu, t < 10 sec thermal resistance junction-pcb 35 c/w
electrical characteristics STL7DN6LF3 4/18 docid023010 rev 4 2 electrical characteristics (t case = 25 c unless otherwise specified) table 4. on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage (v gs = 0) i d = 250 a 60 v i dss zero gate voltage drain current (v gs = 0) v ds = 60 v 1 a i gss gate body leakage current (v ds = 0) v gs = 20 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 1 2.5 v r ds(on) static drain-source on- resistance v gs = 10 v, i d = 3 a v gs = 5 v, i d = 3 a 35 48 43 60 m m table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds =25 v, f=1 mhz, v gs =0 -432 - pf c oss output capacitance - 93 - pf c rss reverse transfer capacitance - 10.5 - pf q g total gate charge v dd =30 v, i d = 6.5 a v gs =10 v, figure 13 -8.7 - nc q gs gate-source charge - 1.9 - nc q gd gate-drain charge - 1.9 - nc r g intrinsic gate resistance f=1 mhz open drain - 6.3 - table 6. switching times symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time v dd =30 v, i d = 3 a, r g =4.7 , v gs =10 v figure 12 -6.7-ns t r rise time - 10.4 - ns t d(off) turn-off delay time - 32.4 - ns t f fall time - 5.4 - ns
docid023010 rev 4 5/18 STL7DN6LF3 electrical characteristics 18 table 7. source drain diode symbol parameter test conditions min typ. max unit i sd source-drain current - 6.5 a i sdm (1) 1. pulse width limited by safe operating area source-drain current (pulsed) - 26 a v sd (2) 2. pulsed: pulse duration= 300 s, duty cycle 1.5% forward on voltage i sd = 6.5 a, v gs =0 - 1.3 v t rr reverse recovery time i sd = 6.5 a, di/dt = 100 a/s, v dd =48 v, tj=150 c -24-ns q rr reverse recovery charge - 23.3 - nc i rrm reverse recovery current - 1.94 - a
electrical characteristics STL7DN6LF3 6/18 docid023010 rev 4 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance figure 4. output characteristics figure 5. transfer characteristics figure 6. normalized v (br)dss vs temperature figure 7. static drain-source on-resistance i d 10 1 0.1 0.1 1 v ds (v) 10 (a) operation in this area is limited by max r ds(on) 1s 100ms 10ms tj=175c tc=25c single pulse am13023v1 10 -4 10 -3 10 -2 10 -1 t p (s) 10 -2 10 -1 k 0.2 0.05 0.02 0.01 0.1 single pulse =0.5 10 0 10 1 10 -3 zth_am13007v1 i d 15 10 5 0 0 2 v ds (v) 4 (a) 1 3 20 25 4v 5v v gs =6, 7, 8, 9, 10v am13024v1 i d 15 10 5 0 0 2 v gs (v) 4 (a) 1 3 20 25 v ds =5v am13025v1 v (br)dss -75 t j (c) (norm) -25 75 25 125 0.90 0.94 0.98 1.02 1.06 i d =250a 1.10 am13010v1 r ds(on) 35.0 34.8 34.6 34.4 3 i d (a) (m ) 2 4 35.2 35.4 5 v gs =10v am13026v1
docid023010 rev 4 7/18 STL7DN6LF3 electrical characteristics 18 figure 8. gate charge vs gate-source voltage figure 9. capacitance variations figure 10. normalized gate threshold voltage vs temperature figure 11. normalized on-resistance vs temperature v gs 6 4 2 0 0 2 q g (nc) (v) 8 8 4 6 10 v dd =30v i d =6.5a 10 am13027v1 c 100 10 0 10 v ds (v) (pf) 20 ciss coss crss 30 40 50 am13028v1 v gs(th) 1.0 0.8 0.6 0.4 -75 t j (c) (norm) -25 1.2 75 25 125 i d =250a am13014v1 r ds(on) 1.2 0.8 0.4 0 -75 t j (c) (norm) -25 75 25 125 1.6 2.0 v gs =10v am13015v1
test circuits STL7DN6LF3 8/18 docid023010 rev 4 3 test circuits figure 12. switching times test circuit for resistive load figure 13. gate charge test circuit figure 14. test circuit for inductive load switching and diode recovery times figure 15. unclamped inductive load test circuit figure 16. unclamped inductive waveform figure 17. switching time waveform am01468v1 v gs p w v d r g r l d.u.t. 2200 f 3.3 f v dd am01469v1 v dd 47k 1k 47k 2.7k 1k 12v v i =20v=v gmax 2200 f p w i g =const 100 100nf d.u.t. v g am01470v1 a d d.u.t. s b g 25 a a b b r g g fast diode d s l=100 h f 3.3 1000 f v dd am01471v1 v i p w v d i d d.u.t. l 2200 f 3.3 f v dd am01472v1 v (br)dss v dd v dd v d i dm i d am01473v1 v ds t on td on td off t off t f t r 90% 10% 10% 0 0 90% 90% 10% v gs
docid023010 rev 4 9/18 STL7DN6LF3 package information 18 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark.
package information STL7DN6LF3 10/18 docid023010 rev 4 figure 18. powerflat 5x6 double island type r outline %rwwrpylhz 6lghylhz 7rsylhz 3lq lghqwlilfdwlrq 3lq lghqwlilfdwlrq b5hybw\shb5
docid023010 rev 4 11/18 STL7DN6LF3 package information 18 table 8. powerflat 5x6 double island type r mechanical data ref. dimensions (mm) min. typ. max. a 0.80 1.00 a1 0.02 0.05 a2 0.25 b 0.30 0.50 d 5.00 5.20 5.40 d2 1.68 1.88 e 5.95 6.15 6.35 e2 3.50 3.70 e4 0.55 0.75 e5 0.08 0.28 e6 2.35 2.55 e7 0.40 0.60 e1.27 l 0.60 0.80 k 1.275 1.575
package information STL7DN6LF3 12/18 docid023010 rev 4 figure 19. powerflat 5x6 double island wf type r outline %rwwrpylhz 3lq lghqwlilfdwlrq 6lghylhz 7rsylhz 3lq lghqwlilfdwlrq b5hyb7\shb5:)
docid023010 rev 4 13/18 STL7DN6LF3 package information 18 table 9. powerflat 5x6 double island wf type r mechanical data ref. dimensions (mm) min. typ. max. a 0.80 1.00 a1 0.02 0.05 a2 0.25 b 0.30 0.50 d 5.00 5.20 5.40 d2 1.68 1.88 e 6.20 6.40 6.60 e2 3.50 3.70 e4 0.55 0.75 e5 0.08 0.28 e6 2.35 2.55 e7 0.40 0.60 e1.27 l 0.70 0.90 l1 0.275 k 1.275 1.575
package information STL7DN6LF3 14/18 docid023010 rev 4 figure 20. powerflat 5x6 double island recommended footprint (dimensions are in mm) b5hyb7\shb5:)b)rrwsulqw
docid023010 rev 4 15/18 STL7DN6LF3 packaging information 18 5 packaging information figure 21. powerflat? 5x6 tape (a) figure 22. powerflat 5x6 wf tape (a) a. all dimensions are in millimeters. measured from centerline of sprocket hole to centerline of pocket. cumulative tolerance of 10 sprocket holes is 0.20 . measured from centerline of sprocket hole to centerline of pocket. (i) (ii) (iii) 2 2.00.1 (i) bo (5.300.1) ko (1.200.1) 0.05) ?1.5 min. ?1.550.05 p ao(6.300.1) f(5.500.1)(iii) w(12.000.3) 1.750.1 4.00.1 (ii) p 0 y y section y-y c l p1(8.000.1) do d1 e 1 (0.30 t ref.r0.50 ref 0.20 base and bulk quantity 3000 pcs 8234350_tape_rev_c 1.50 0.0 + 0.1 do 4.0 0.1(ii) po 1.75 0.1 e1 1.50 min d1 2.0 0.05(i) p2 y y r0.30 max 0.30 0.05 t section y-y measured from centreline of sprocket hole to centreline of pocket. cumulative tolerance of 10 sprocket holes is 0.20 . measured from centreline of sprocket hole to centreline of pocket. (i) (ii) (iii) base and bulk quantity 3000 pcs p1(8.000.1) ao(6.700.1) f(5.500.0.05)(iii) w(12.000.1) bo (5.350.05) ko (1.200.1) 8234350_tapewf_rev_c
packaging information STL7DN6LF3 16/18 docid023010 rev 4 figure 23. powerflat? 5x6 package orientation in carrier tape figure 24. powerflat? 5x6 reel pin 1 identification 2.20 ?21.2 13.00 core detail 2.50 1.90 r0.60 77 128 ?a r1.10 2.50 4.00 r25.00 part no. w1 w2 18.4 (max) w3 06 ps esd logo attention observe precautions for handling electrostatic sensitive devices 11.9/15.4 12.4 (+2/-0) a 330 (+0/-4.0) all dimensions are in millimeters ?n 178(2.0) 8234350_reel_rev_c
docid023010 rev 4 17/18 STL7DN6LF3 revision history 18 6 revision history table 10. document revision history date revision changes 28-mar-2012 1 first release. 19-jun-2012 2 section 2.1: electrical characteristics (curves) has been added. updated section 4: package information and tile on the coverpage. 26-jun-2012 3 document status promoted from preliminary to production data. 23-feb-2015 4 updated title, features and description in cover page. updated table 5: dynamic , table 6: switching times and section 2.1: electrical characteristics (curves) . updated section 4: package information . added section 5: packaging information . minor text changes.
STL7DN6LF3 18/18 docid023010 rev 4 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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