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april 2007 rev 1 1/38 AN2512 application note three-phase meter based stpm01, viper12a introduction this application note describes how to design a three-phase meter using stpm01 as the measuring device and a viper12a based smps (switch mode power supply). stpm01 is a metering assp impl emented in an advanced 0.35 m bcd6 technology. it is designed for the effective measurement of active, reactive and apparent energies, vrms, irms, instantaneous voltage and current, frequency in power line systems that use the current transformer, rogowski coil and/or shunt principle. this device can be used as a standalone on-boa rd metering device in single-phase energy meter applications or as a peripheral in a microprocessor based single- or three-phase meter. in a standalone configuration stpm01 outputs a pulse train signal having a frequency proportional to the active power used, while in peripheral mode stpm01 is used in a microprocessor based application. in this case, measured data are read at a fixed time interval from the device internal registers by means of spi interface processed by a microcontroller. in the following paragraphs a circuit description is explained, with particular focus on the power supply section, the three-phase design, and the clock management network. then, the power calculation algorithm is discussed and finally some layout hints and experimental results are shown. this application note should be used in conjunction with the stpm01 and viper12a datasheet. three phase block diagram www.st.com
contents AN2512 2/38 contents 1 application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 power supply circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 phase circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4.1 current sensing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4.2 anti-aliasing filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4.3 voltage sensing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4.4 crosstalk cancellation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 clock management network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 communication with microproc essor . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 power calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 stpm01 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 stpm01 initialization (latching) and readi ng (shifting) . . . . . . . . . . . . . . . 14 3.3 data record structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 data integrity checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 unpacking of data records . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 processing of phase energy values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 three-phase energy calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 pulse generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 layout rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 phase one results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 phase two results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 phase three results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4 voltage and frequency influence on phase three . . . . . . . . . . . . . . . . . . . 24 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
AN2512 list of figures 3/38 list of figures figure 1. top layer circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. smps circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. phase circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. clock management network schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. connectors schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. flow chart of phase reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. timing for data records reading in 3 phase system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. data records reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. stpm01 data register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. typical profile of output of an energy integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. graph of experimental results of phase n.1 tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. graph of experimental results of phase n.2 tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. graph of experimental results of phase n.3 tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. graph of voltage and frequency influence on phase n.3 . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. instantaneous vo ltage (or current) in one voltage cycle of a three-phase system . . . . . . . 25 figure 16. per-phase powers in (a) delta-connected load and (b) wye-connected load . . . . . . . . . . . 26 figure 17. two-wattmeter method in star- or delta-connected load. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 18. the wattmeter connections in the three-phase four-wire loads . . . . . . . . . . . . . . . . . . . . . 28
application description AN2512 4/38 1 application description three-phase meters (which derive as particular cases from poly-phase systems), are most commonly used in practical industrial applicatio ns, and in a few cases also for domestic use. this three-phase meter can be used as a refe rence board to build a class 0,5 three-phase microprocessor based meter for power line systems 3-wire delta service, 4-wires delta and wye service. it uses a multi-chip topolo gy, in which each phase is monitored using a single-phase device. in this way, three stpm01 have been used with a common clock network. the power supply is implemented in fly-back topology using a viper12a. the meter cannot be used in standalone mode and a management/supervisory board must be used for energy integration and data displaying. such a control board should be plugged in the connector j2 (referring to board schematics below), while the connector j1 is used for calibration purposes in association (o r conjunction) with the stpmxx parallel programmer/reader released with the application. 1.1 operating conditions 1.2 circuit description the meter consists of one board divided into the following sections: power supply management circuit phase circuit clock management network connectors. the schematic of the board is shown in figure 1 . table 1. operating conditions value min max unit v nom 80 480 v rms i nom /i max 530a rms f lin 45 65 hz t amb - 40 +85 c
AN2512 application description 5/38 figure 1. top layer circuit schematic 1.3 power supply circuit a 3-phase 4-wire bridge is used for mains rectif ication because the neutral rectification is needed to ensure proper operation in case of missing neutral connection or neutral miss- wiring. a varistor is connected between each line and neutral to guarantee pulse voltage test immunity according to the en62052-11 standard. the input emi filter is a simple, undamped lc-filter for both differential and common mode noise suppression. the circuit for input voltage limiting is connected between the input emi filter and the bulk capacitor c4. such a circuitry includes a power mosfet and a self driven control section. the mosfet q1 is a standard n-channel 500 v 3.3 ? in d-pak package, mounted on a small copper area to improve thermal performance. the self driven control section consists of a voltage divider and zener diodes. the resistors r1, r2 and r3 ensure the gate-source charge for the switch, while the zener diodes d3 and d4 set the maximum voltage value (360 v) across the bulk capacitor. an ntc limits the inrush current and ensures q1 operation inside its safe operating area. the flyback converter is based on viper12a, a product in the viperx2a family, which combines a dedicated current mode off-line pwm controller with a high voltage power mosfet on the same silicon chip. the switching frequency is fixed at 60 khz by the ic internal oscillator in order to optimize the transformer si ze and cost. the transformer reflected voltage has been set to 60 v, providing enough margin for the leakage inductance voltage spike and no snubber circuit is needed which allows consequent cost savings. as soon as the voltage is applied on the input of the converter, the high voltage start-up current source connected to the drain pin is activated and starts to charge the v dd capacitor c8 through a constant current of 1 ma. when th e voltage across this capacitor reaches the v dd on threshold (about 14 v), the viper12a starts to switch. during normal operation the phase_2 phase sda scs scl syn n p gnd vdd led votp clki n clkou t smps smps p1 p2 n p3 5v gnd 3.3v phase_3 phase sda scs scl syn n p gnd vdd led votp clki n clkou t phase_1 phase sda scs scl syn n p gnd vdd led votp clki n clkou t vdd vdd vdd 5v vdd 5v vdd vdd p3 votpl1 scsl1 scsl1 p1 p1 n n votpl3 ledl3 scsl3 ledl3 p3 scsl3 ledl1 ledl1 n sda scl sda n scl clki n syn ledl2 syn scl syn syn p2 votpl2 ledl2 p2 scsl2 sda sda scl scsl2 scsl1 scsl2 scsl3 votpl1 votpl2 votpl3 scs votp sda scl syn j13 scsjumper 1 2 3 4 5 6 j1 1 2 3 4 5 6 7 8 9 10 j14 jumper3 1 2 3 4 5 6 u8b 74hc14a/so 3 4 j7 1 j11 1 j8 1 c2 15pf c1 15pf j2 con20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 j12 1 y1 4.194304mhz r1 1m j9 1 j5 1 j10 1 u8a 74hc14a/so 1 2
application description AN2512 6/38 smart power ic is powered by the auxiliary wi nding of the transformer via the diode d7. no spike killer for the auxiliary voltage fluctuatio ns is needed thanks to the wide range of the v dd pin (9-38 v). the primary current is measured using the integrated current sensing for current mode operation. the output rectifier d6 has been chosen in accordance with the maximum reverse voltage and power dissipation. in particular a 0.5a-80 v schottky diode, type tmbat49, has been selected. the output voltage regulation is performed by secondary feedback on the 5 v output dedicated to the display, while the 3.3 v output, dedicated to the logic part and the microcontroller, is linearly post-regulated from the 5 v output. this operation is performed by a very low drop voltage regulator, l4931abd33, in so-8 package. the voltage regulator delivers up to 100 ma, ensuring good reliab ility with no heat sink. the feedback network ensures the required insulation between the primary and secondary sections. the optotransistor directly drives the viper12a feedback pin which controls the ic operation. a small lc filter has been added to the 5 v output in order reduce the high frequency ripple with reasonable output capacitors value. the flyback transformer is a layer type based on e13 core and n27 ferrite, manufactured by pulse eldor, and ensures safety insulation in accordance with the en60950. for more info on the power supply, please refer to an2264, "three-phase smps for low power applications with viper12a". the schematic of the power supply section is shown in figure 2 .
AN2512 application description 7/38 figure 2. smps circuit schematic r62 22e 1w r58 330k r63 22e 1w c17 100nf smd + c15 22uf 16v q1 std5nk40z 1 4 3 c19 220nf 630v d4 zmm 15/sod-80 r59 330k so5k275/275v rv3 d9 180v so5k275/275v rv1 so5k275/275v rv2 t1 1 2 10 6 4 5 + c14 330uf 25v d7 180v c16 220nf 630v l3 10uh 125ma smd u4 ts2431 3 1 2 c23 100nf 50v smd r25 4.7k 1% smd d5 tm bat49 ntc1 120e l2 1mh + c21 10uf 50v r23 4.7k 1% smd r64 22e 1w r21 220e smd c24 47nf 50v smd u3 pc817 1 2 4 3 r24 5.6k d10 ll4148 u5 viper12as/so-8 8 4 3 1 2 7 6 5 d vdd fb s s d d d r22 1k smd r20 10e smd r60 330k + c20 1000uf 50v -+ d8 bridge 2 3 1 4 -+ d3 bridge 2 3 1 4 + c18 2.2uf450v c22 2nf/2kv (y1) u2 l4931abd33 1 8 2 3 6 7 5 vout vin gnd gnd gnd gnd inhib r61 22e 1w p1 p2 n p3 5v gnd 3.3v 3.3v@100ma 5v@10ma
application description AN2512 8/38 1.4 phase circuit this paragraph explains the implementation of the phase network which performs the power calculation. the three phases are identical. figure 3 shows the implementation of the stpm01 used for energy calculation of each phase. the schematic can be divided into the following subsets: current sensing circuit (1) anti-aliasing filter (2) voltage sensing circuit (3) crosstalk cancellation network (4). figure 3. phase circuit schematic vdd vdd p led votp sda scl led n syn votp scs gnd r13 0 l1 ct r10 2,2k r7 150k r5 1k c4 1nf c9 10nf c3 1nf c8 1my c5 1my r8 1k c6 1nf c7 1nf r6 3.4 d2 ll4148 r9 2.2m r16 200k d1 1 2 r15 270k r14 270k u1 stpm01_tssop20 20 1 2 4 5 6 8 7 9 10 11 12 13 14 16 17 15 3 18 19 led mon mop vddd vss vcc vdda votp ilp1 iln1 ilp2 iln2 vip vin clkin clkout syn scs scl sda r2 750 c12 33nf r17 470 c11 4.7u sda scs scl syn n p vdd led votp clki n clkou t gnd 3 1 2 4
AN2512 application description 9/38 1.4.1 current sensing circuit the stpm01 has two external current sensing circuits, primary and secondary current channels. normally, the second current circuit is used in single-phase meter implementation when the anti-tamper feature is required. in this way it is possible to read also the current flowing into the neutral wire to have a comparison with the current flowing into the line wire and detect possible tampers. in this application only the primary channel has been used. as a consequence, the configuration of stpm01 is: pst= 2 if a current transformer is used (this is the case of this meter); pst= 0 (or 1) if a rogowski coil is used in the latter case addg bit can be used to have a further gain of x8. the current channel uses a current transformer to sense mains current. the burden resistor is used to produce a voltage between vin1 and vip1 proportional to the current measured. 1.4.2 anti-aliasing filter the anti-aliasing filter is a low-pass filter. it has a negligible influence on the voltage drop between iin1 and iip1. its aim is to reduce the distortion caused by the sampling, also called aliasing, by removing the out-of-band frequencies of the input signal before sampling it with the analog-to-digital converter. filtering is easily implemented with a resist or-capacitor (rc) single-pole circuit which obtains an attenuation of -20db/dec. 1.4.3 voltage sensing circuit a resistor divider is used as voltage sensor. the 740 k ? resistor is separated into three, 2x270 k ? and 1x200 k ? , in-series resistors, which ensure that a high voltage transient does not bypass the resistor. this also reduces the potential across the resistor s, thereby decreasing the possib ility of arcing. the following resistors are used to implement resistor divider: r=r14+r15+r16=740 k ? , r5=470 ? . capacitor c11 and resistance (r19+ r15) create a filter which prevents electromagnetic interference (emi). 1.4.4 crosstalk cancel lation network the voltage front-end handles voltages of considerable amplitude, which makes it a potential source of noise. disturbances are readily emitted into current measurement circuitry where they interfere with the actual si gnal to be measured. typically, this produces a non-linear error at small signal amplitudes and non-unity power factors. at unity power factor, voltage and current signals are in phase and crosstalk between voltage and current channels merely appears as a gain error, which can be calibrated. when voltage and current are not in phase, crosstalk has a non-linear effect on the measurements, which cannot be calibrated.
application description AN2512 10/38 crosstalk is minimized by means of good pcb planning and the proper use of filter components in the crosstalk network. recommended filter components are shown in figure 3 . the network subtracts a signal proportional to the voltage input from the current input. this prevents cross talking within the stpm01. 1.5 clock management network 4.194 mhz quartz is used to supply the clock to the three stpm01 devices. figure 4 shows the schematic of the enhanced clock network which prevents emi influences. a discrete inverter network is used to change the impedance of the common node of the three blocks. the output of the inverter prevents the second order antenna effect of the node. the clkout pins are grounded to guarantee the current loop. to select the measurement frequency range , mdiv must be set to 0 in the configuration register of stpm01. if an 8 mhz quartz is used , this bit must be changed to 1. figure 4. clock management network schematic phase_2 phase sda scs scl syn n p gnd vdd led votp clki n clkou t phase_3 phase sda scs scl syn n p gnd vdd led votp clki n clkou t phase_1 phase sda scs scl syn n p gnd vdd led votp clki n clkou t vdd vdd vdd votpl1 scsl1 p1 n n votpl3 ledl3 p3 scsl3 ledl1 scl sda n scl clki n syn ledl2 syn syn p2 votpl2 sda sda scl scsl2 u8b 74hc14a/ so 3 4 c2 15pf c1 15pf y1 4.194304mhz r1 1m u8a 74hc14a/so 1 2
AN2512 communication with microprocessor 11/38 2 communication with microprocessor a control board with embedded microprocessor should be connected to connector j2 of module using 20-wire flat cable. ta b l e 2 below describes the pin-out of the connector. each stpm01 has an spi communication port implemented by four multi-purpose pins. through the j2 connector, the control board can read data records or it can access the mode or configuration signals of each meteri ng device by means of dedicated protocol. each pin can draw up to 4 ma at +3.0 v from the control module. the selection of the device to be read is done acting on one of the three scslx (stpm01 device select) pins. by default, the stpm01 is configured in peripheral mode by setting configuration bits apl = 0. this implies also the fo llowing output settings: watchdog reset signal on mon pin; zero-crossing (zcr) on mop pin; a pulse train with frequency proportional to the power consumption on led pin. to display the information on the power consumption, it is either possible to feed three leds, each one showing the information on one phase, from the led pins of the three measurement devices, or the control board can generate an led signal to show the global power consumption by reading and manipulating energy information from the three stpm01 registers. in this case, the control board may also recalibrate any result read from the module through appropriate software. figure 5. connectors schematic vdd 5v vdd scsl1 ledl3 scsl3 ledl1 sda syn scl ledl2 scsl2 scsl1 scsl2 scsl3 votpl1 votpl2 votpl3 scs votp sda scl syn j13 scsjumper 1 2 3 4 5 6 j1 1 2 3 4 5 6 7 8 9 10 j14 jumper3 1 2 3 4 5 6 j2 con20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
communication with microprocessor AN2512 12/38 a host system can communicate with each measurement module (actually, with the stpm01) using spi interface, through connector j2. the stpm01 always acts as an spi slave while the host system acts as an spi master. an application control board or an external system can be considered as host. connector j1 is used in the evaluation phase to connect the measurement module to a pc through the stpm01 parallel programmer/reader hardware interface. this allows the user to set temporarily or pe rmanently the internal stpm01 registers using a dedicated gui. jumpers j13 and j14 select which of the three devices will be accessed. the votp pin on the connector j1 is used when a host wants to permanently write some configuration bits in the metering device. in this case, a +15 v power level must be present on the votp. this level must be delivered from the host itself because the module does not have an on-board charge pump. ta bl e 3 shows the pin description of the connector j1. table 2. j2 connector pin description pin no. pin name functional description 1. 5 v power out of +5.0 v up to 25 ma can be drawn from this pin 2. scl spi interface pin 3. sda spi interface data pin 4. syn spi interface pin 5. scsl1 phase n.1 spi enable signal 6. scsl2 phase n.2 spi enable signal 7. scsl3 phase n.3 spi enable signal 8. ledl1 led output of phase n.1 9. ledl2 led output of phase n.2 10. ledl3 led output of phase n.3 11. gnd signal reference level 0 v and power supply return 12. vdd power out of +3.3 v up to 100 ma can be drawn from this pin 13. --- nc 14. --- nc 15. --- nc 16. --- nc 17. --- nc 18. --- nc 19. --- nc 20. --- nc
AN2512 power calculation algorithm 13/38 3 power calculation algorithm 3.1 stpm01 spi interface the stpm01 spi interface supports a simple serial protocol, which is implemented in order to enable communication between a host system (microcontroller or pc) and the device. three tasks can be performed with this interface: remote resetting the device reading data records writing the mode bits and the configuration bits (temporarily or permanently). four pins of the device are dedicated to this purpose: scs, syn, scl, and sda. scs, syn and scl are all input pins while sda can be input or output according to whether the spi is in write or read mode. the condition under which scs, syn and scl i nputs are set to high level determines the idle state of the spi interface and no data transfer occurs. scs: enables spi operation when low. the microcontroller uses this pin to multiplex the reading of the three devices. syn: when scs is low, the syn pin status se lects whether the spi is in read (syn=1) or write mode (syn=0). when scs is high and syn is also high, the results of the input or output data are transferred to the transmission latches. scl: is the clock pin of the spi interface. th is pin function is also controlled by the scs status. if scs is low, scl is the input of se rial bit synchronization clock signal. when scs is high, scl is also high determining the idle state of the spi. sda: is the data pin. if scs is low, the operation of sda is dependent on the status of syn pin. if syn is high, sda is the output of serial bit data (read mode). if syn is low, sda is the input of serial bit data signal (write mode). if scs is high, sda is idle. table 3. j1 connector pin description pin no. pin name functional description 1. votp power supply input of +15.0 v during permanent write to otp cells 2. --- nc 3. gnd signal reference level 0v and power supply return 4. sda spi interface data signal 5. scs spi enable signal 6. scl spi interface clock signal 7. --- nc 8. syn spi interface signal 9. --- nc 10. vdd power out of +3.3 v up to 100 ma can be drawn from this pin
power calculation algorithm AN2512 14/38 in this chapter the readings of data records will be treated in case of 3 ph ase usage of stpm01, in particular we will refer to the flow chart in figure 6 . figure 6. flow chart of phase reading 3.2 stpm01 initialization (lat ching) and reading (shifting) there are two phases of reading the stpm01 data called latching and shifting. latching is used to sample results into transmis sion latches by initiating an active pulse on syn while scs is idle. the pulse length of syn must be longer than 2 periods of the measurement clock (that is, t 2 - t 1 more than 500 ns). the latching phase has to be done at the same time for all the stpm01 devices keeping the scslx lines in idle state in order to read the information coming from each phase at the same moment. shifting starts when scs becomes active (low). at the beginning of this phase, another, much shorter pulse (t 5 - t 4 = 30 ns) should be applied to syn. an alternative way to read shifted data is to extend the pulse on syn into the second phase of reading (from t 1 to t 5 ). latching and shifting finish at the last rise of syn (shown by the t 5 line in figure 7 ). after these readings are completed, the stpm01 is reset. it is possible to read data, by applying 32 serial clocks per data record. up to 8 data records can be read this way from each device. switching to another device is possible enabling the corresponding scs line. note that, enabling multiple scs lines corrupts the information received causing parity error. so, in any case, two or more devices cannot be enabled at the same time. in order to maximize the reliability of the read ings, each data structure can be read twice and compared. this is possible just by restarting the shifting procedure, then applying the clock signal on the scl pin one more time, keeping the corresponding scs pin in active state (low).
AN2512 power calculation algorithm 15/38 figure 7. timing for data records reading in 3 phase system t 1 t 2 : latching phase. interval value>2/f clk t 2 t 3 : data latched, spi idle. interval value>30 ns t 3 t 4 : enable spi for read operation. interval value > 30 ns t 4 t 5 : serial clock counter is reset. interval value > 30 ns t 5 t 6 : spi reset and enabled for read operation. interval value > 30 ns t 7 : internal data transferred to sda t 8 : sda data is stable and can be read t 9 : end of phase 1 reading, begin of phase 2 reading t 10 : end of phase 2 reading, begin of phase 3 reading t 11 : end of phase 3 reading, stop of stpm01 shifting 3.3 data record structure every data record is 4 bytes long. the 1st readout byte of data record is the least significant byte (lsb). each byte can be further divided into a most and least significant nibble (msn, lsn). the msn of the 4th byte of data value holds the parity code rather than useful data. in fact, every data record consists of 4-bit parity code and 28-bit data value where the parity code is computed from the data value which makes total of 32 bits or 4 bytes. the figure 8 below shows top down how bytes of data record are output from the sda and how they should be re-organized by the host to retrieve useful information.
power calculation algorithm AN2512 16/38 figure 8. data records reconstruction the data records have a fixed position of reading and no addressing of records is needed. it is up to the host to decide how many records should be read out from the device. figure 9 shows the records position within the default sequence of reading, their name and information contained. figure 9. stpm01 data register structure 7 0 7 0 7 0 7 0 7 0 7 0 15 8 15 8 23 16 23 16 0 0 24 24 8 bit spi reading order 32 bits register assembling 1 st byte - lsb msb lsb 4 th byte - msb 7 0 7 0 7 0 7 0 parity nibble msb lsb parity nibble 28 bit data
AN2512 power calculation algorithm 17/38 3.4 data integrity checks each bit of parity nibble is defined as odd parity of all seven corresponding bits of data nibbles. in order to check the data record integrity, the application might execute the following c code, given as an example: in t badpari t y (un s igned char *bp) { regi st er un s igned char pr t y; /* t emporary regi st er */ pr t y = *bp, /* t ake t he 1 st by t e of da t a */ pr t y ^= *(bp+1), /* xor i t wi t h t he 2nd by t e*/ pr t y ^= *(bp+2), /*and wi t h t he 3rd by t e */ pr t y ^= *(bp+3), /*and wi t h t he 4 t h by t e */ pr t y ^= pr t y<<4, pr t y &= 0xf0; /* combine and remove t he lower nibble */ re t urn (pr t y != 0xf0); /*re t urn s 1, if bad pari t y */ } if (badpari t y(dap) || badpari t y(drp) || /* dap and drp. da t a record*/ badpari t y(d s p) || badpari t y(dfp) || /* dsp and dfp da t a record */ badpari t y(dev) || badpari t y(dmv) || /* de v and dm v da t a record */ badpari t y(cfl) || badpari t y(cfh)) /* c fl and c fh da t a record */ /* code for repea t of reading s equence s hould be en t ered here */ ; if the parity nibble check fails, the reading task should be repeated but, this time, without request of latching, otherwise a new data is la tched and the previous reading is incorrectly lost. in a very harsh emi environment, it would be good practice to read the data records twice and then compare both readings. this way the probab ility of detecting bad readings is significantly improved. a single bad data reading can be discarded because no meaningful information is lost as long the reading frequency is about 30 ms. 3.5 unpacking of data records after each data record is read correctly, its parity nibble and possible padding bits should be masked out and then it should be unpacked to retrieve each information as indicated in figure 9 . the momentary values of current and voltage should be considered as signed integers, while all the other values as unsigned integers. below an example of readings and unpacking of the data is given (msbf is cleared, that is, the device reads most significant bit first). dap 65 7a 7c 82: parity = 8, type0 energy=27c7a, status = 65 drp 52 7a 0c 90: parity = 9, reactive energy=00c7a, frequency high byte = 52 dsp 25 00 8c e2: parity = e, apparent energy=28c00, frequency low byte = 25
power calculation algorithm AN2512 18/38 dfp 00 06 6e 22: parity = 2, type1 energy = 26e06, mode signals = 00 dev bb b3 07 dd: parity = d, i rms = 1b3bb, u rms = 638 dmv 3f af aa ca: parity = c, i mom = af3f, u mom = aaa cfl 01 00 00 e0: parity = e, configuration bits low part = 0000001 cfh 00 00 00 f0: parity = f, configuration bits high part = 0000000 the metering device computes wide-band active energy which is type0 by default and fundamental harmonic active energy which is type1 by default. the configuration bit fund can be used to select which becomes type0 or type1, by default fund = 0. ta bl e 4 shows the meaning of "status" byte in the dap data record. normally, a host reads the dap data record first but, if a "precharge" command is sent to the module before the beginning of the reading task, the dev data record is read first. this way, faster reading of rms and momentary values is possible. table 4. stpm01 status bit description bit no. bit name functional description condition 0. bil no load condition bil = 0: no load condition not detected bil = 1: no load detected 1. bcf ? signal status bcf= 0: ? signals alive bcf= 1: one or both ? signals are stacked 2. bfr line frequency range bfr = 0: line frequency inside the 45 hz-65 hz range bfr = 1: line frequency out of range 3. bit tamper condition bit = 0: tamper not detected bit = 1: tamper detected 4. mux current channel selection mux = 0: primary current chann els selected by the tamper module mux = 1: secondary current channels selected by the tamper module 5. lin trend of the line voltage lin = 0: line voltage is going from the minimum to the maximum value ( ? v/ ? t >0) lin = 1: line voltage is going from the maximum to the minimum value ( ? v/ ? t < 0) 6. pin output pin check pin = 0: the output pins ar e consistent with the data pin = 1: the output pins are different with the data, this means some output pin is forced to 1 or 0 7. hlt data validity hlt = 0: the data records reading are valid hlt = 1: the data records are not valid. a reset occurred and a restart is in progress.
AN2512 power calculation algorithm 19/38 3.6 processing of phase energy values within each stpm01 metering device the sources of energy values are implemented as 20- bit up/down counters. the value of such counters eventually rolls over if the direction of power is not changing too often, which is normally the case. for example, if the maximal possible positive power (360 v * 33 a = 12 kw) is measured by one of the phases, the internal counter would count up and reach its maximal value (0xfffff) in about 1.2 seconds then the value rolls over to zero (0x00000) at once and starts to count up again. a sawtooth shape of values is produced, see figure 10 . for the negative power, the counter counts down, showing the same behavior. the slope of the shape is proportional to measured power which may change its value and direction at any moment. also, if power is absolutely less than no-load cond ition limit, selected by ltch, the counter stops. for the calculation of the value of the least significan t bit of counters, please refer to the stpm01 datasheet. an application should recognize rollovers. a rollover from high to low should be recognized . if the msn of the energy value of two consecutive readings changes from 0xf to 0x0 or, if change from 0x0 to 0xf is detected, a low to high rollover is recognized. to ensure detection of change, an application should successfully read the energy values at least every 0.1 second but, for security reasons, at least 30 readings per second should be performed. figure 10. typical profile of output of an energy integrator using an msn of energy value as a rollover code is convenient because it is stored in the msb of data record accompanied with the parity code. therefore it is easily unpacked and checked for the characteristic values. when rollover is detected, a 0x00100000 should be added to the energy reading with rollover code 0x0. to compute a single phase energy it is recommended to use the following procedure. the software should implement a 32-bit integrator. the integrator is divided into two stages: frac 32-bit signed integer variable; integ 32-bit signed integer variable. the other variables to be used are: old 32-bit signed integer variable; new 32-bit signed integer variable; quot 16-bit unsigned integer variable; quant 16-bit signed integer variable. each time the host receives a new reading, the 20-bit energy value is stored in the new variable, and the difference between the new and old energy values is stored in the quant variable. the value of frac is derived by adding to itself the quant value. before the next
power calculation algorithm AN2512 20/38 reading, the old variable should be updated with the new value for the next quant computation. when frac collects a preset amount of energy (that is, 10 wh, absolute, with the corresponding integer value stored as a threshold variable), the integ value should be changed by 1 bit and the frac value changed according to the threshold value. the preset threshold value must be set according to the value of the least significant bit of the internal energy counter (for more detail, please refer to the stpm01 datasheet). if the time difference of two consecutive readings is known, an applied power can be computed easily as: p = quant/ ? t. this procedure should be repeated for each energy type (active, reactive, apparent and fundamental active). if an led output from mcu is required, the resolution of the energy count must be increased by dividing the value of quant by 16 and adding it in 16 times to frac. a reminder of such division can be added to the frac value immediat ely, while the quotient quot (quant/16) can be added later 16 times but faster. a timer interrupt service routine is the best place to implement these calls. this way, output pulse generation of signal leds, which is used for meter accuracy check, with 2 ms resolution is possible (given that 2 consecutive readings occur every 32 ms). this calculation should be done for each type of energy (active wide band, reactive, apparent and active fundamental). for more details on single phase energy calculation , please refer to an2159 "spi communication for comprehensive energy reading of the stpm01". 3.7 three-phase energy calculation the above procedure refers to one of the phases of a three-phase meter. to calculate the global amount of energy in a three-phase system, it is necessary to define an array of the above variables structure, where the number of elements is four, one for each phase energy and one for the total energy, which is given by the sum of the three-phase energies. in appendix a an example of the definition of the variables used in a practical application is shown. 3.8 pulse generation from the first stage of integration of total active energy counter (referred to as frac), and according to the number of pulses per kwh de sired as output, a pulse train is generated to feed an led. three more leds are fed from the led pins of stpm01 devices to display power consumption of the respective phase.
AN2512 layout rules 21/38 4 layout rules noise rejection is the main is sue to work on when a three - phase multi - chip approach has been chosen. in this case layout plays a crucial role. here some rules to follow in layout phase: components positioning the components of measuring section (stpm01, current transformers, passive components) are placed using the same layout for each phase. the phases are placed in a symmetrical scheme. in this way reduction of the cross talking can be achieved. the current transformer is placed very close to the correspondent stpm01 to minimize the captured noise. components routing the passive components belonging to the analogue input channels must be placed between the sensor and the stpm01 always respecting a symmetrical scheme. particular care should be given for the voltage channel path because the voltage inputs are normally relatively further from the corresponding stpm01. quartz the crystal network has been placed in the middle of the board ensuring a completely symmetrical path between the devices. a copper plate has been used under the crystal both on the top and on the bottom side of pcb. copper plate the copper plate area should be extended under the entire digital section and under the crystal oscillator which provides the clock for the three stpm01.
experimental results AN2512 22/38 5 experimental results the tests have been conducted considering in =10 a, vn = 220 v, f = 52 hz, where in is the nominal current and vn is the nominal voltage. 5.1 phase one results figure 11. graph of experimental results of phase n.1 tests table 5. experimental results of phase n.1 tests i (a) e%min e%av e%max pf 0,5c pf 0,5l stmin stmax 0,05 -1,841 -1,257 -0,724 0,1 -0,259 -0,119 0,123 -1 1 0,25 0,277 0,282 0,336 -1 1 0,5 0,114 0,152 0,177 -0,5 0,5 5 0,038 0,047 0,052 0,04 0,03 -0,5 0,5 10 0,032 0,036 0,041 -0,5 0,5 20 0,016 0,019 0,022 -0,5 0,5 30 0,045 -0,5 0,5 45 0,06 -0,5 0,5 -1,5 -1 -0,5 0 0,5 1 1,5 0,05 0,1 0,25 0,5 5 10 20 30 45 i[a] p[%]
AN2512 experimental results 23/38 5.2 phase two results figure 12. graph of experimental results of phase n.2 tests 5.3 phase three results table 6. experimental results of phase n.2 tests i (a) e%min e%av e%max pf 0,5c pf 0,5l stmin stmax 0,05 -1,841 -1,257 -0,724 0,1 -0,259 -0,119 0,123 -1 1 0,25 0,277 0,282 0,336 -1 1 0,5 0,114 0,152 0,177 -0,5 0,5 5 0,038 0,047 0,052 0,04 0,03 -0,5 0,5 10 0,032 0,036 0,041 -0,5 0,5 20 0,016 0,019 0,022 -0,5 0,5 30 0,045 -0,5 0,5 45 0,06 -0,5 0,5 -1,5 -1 -0,5 0 0,5 1 1,5 0,05 0,1 0,25 0,5 5 10 20 30 45 i[a] p[%] table 7. experimental results of phase n.3 tests i (a) e%min e%av e%max pf 0,5c pf 0,5l stmin stmax 0,05 2,14 0,1 -0,45 -1 1 0,25 -0,04 -1 1 0,5 0,09 -0,5 0,5 5 0 0,03 0,04 -0,5 0,5 10 -0,5 0,5 20 -0,5 0,5
experimental results AN2512 24/38 figure 13. graph of experimental results of phase n.3 tests 5.4 voltage and frequency influence on phase three 30 -0,5 0,5 45 -0,5 0,5 table 7. experimental results of phase n.3 tests (continued) i (a) e%min e%av e%max pf 0,5c pf 0,5l stmin stmax table 8. voltage influence on phase n.3 i = 0,1 a f = 52 hz ve%stmin 240 -0,22 -0,65 220 -0,45 -0,65 180 -0,47 -0,65 120 -0,58 -0,65 table 9. frequency influence on phase n.3 i = 5 a v = 220 v fe%stmin 45 -0,41 -0,4 52 0 -0,4 65 -0,41 -0,4 i = 5 a v = 220 v
AN2512 three-phase systems 25/38 figure 14. graph of voltage and frequency influence on phase n.3 appendix a three-phase systems three-phase is a common method of electric po wer transmission. it is a type of polyphase system used to power motors and many other devices. the currents are sinusoidal functions of time, all at the same frequency but with different phases. in a three-phase system the phases are spac ed equally, giving a phase separation of 120. the frequency is typically 50 hz in europe and 60 hz in the us and canada. figure 15. instantaneous voltage (or current) in one voltage cycle of a three-phase system the three phases could be supplied over six wires, with two wires reserved for the exclusive use of each phase. however, they are generally supplied over three or four wires: three phases, 3-wire delta service which has no neutral and 220 v between phases -0,7 -0,5 -0,3 -0,1 0,1 240 220 180 120 i[a] p[%] -0,5 -0,3 -0,1 0,1 45 52 65 i[a] p[%]
three-phase systems AN2512 26/38 three phases, 4-wires delta and wye service which has 220 v between phase- neutral and 380 v phase-phase. a.1 power in three-phase ac circuits let's assume that the angle between the phase voltage and the phase current is , which is equal to the angle of the load impedance. considering the load configurations given in figure 16 , the phase power and the total power can be estimated easily. figure 16. per-phase powers in (a) delta-connected load and (b) wye-connected load in the case of figure 16 (a) , the total active power is equal to three times the power of one phase: equation 1 equation 2 since the line current in the balanced delta-connected loads is: equation 3 if this equation is substituted into equation 2 , the total active load becomes: equation 4 in figure 16 (b) , however, the impedances contain the line currents i line (equal to the phase current, i phase ) and the phase voltages. equation 5 (a) (b) p 1 p 2 p 3 pv line i phase ? cos ? ==== p total 3p 3v line i phase ? cos ? == i line 3i phase ? = p total 3v line ? i line ? cos ? = v phase v line 3 ------------ =
AN2512 three-phase systems 27/38 therefore, the phase active power and the total active power are: equation 6 equation 7 if the relationship between the phase voltage and the line voltage is used, the total active power becomes identical to the equation 4 developed. this means that the total power in any balanced three-phase load ( ? - or y-connected) is given by equation 4 . similarly, the total reactive and the total apparent power in the three-phase balanced ac circuits can be given by: equation 8 equation 9 a.2 power measurement techniques in the three-phase power systems, one, two, or three wattmeters can be used to measure the total power. a wattmeter may be considered to be a voltmeter and an ammeter combined in the same box, which has a deflection proportional to v rms i rms cos , where is the angle between the voltage and current. a wattmeter has two voltage and two current terminals, which have + or - polarity signs . three power measuremen t methods utilizing the wattmeters are described next, and are applied to the balanced three-phase ac load. a.2.1 two-wattmeter method this method can be used in a three-phase th ree-wire balanced or unbalanced load system that may be connected ? or y. to perform the measurement, two wattmeters are connected as shown in figure 17 . figure 17. two-wattmeter method in star- or delta-connected load p 1 p 2 p 3 pv phase i line ? cos ? ==== p total 3p 3v phase i line cos ? ? == q total 3v line i line sin ? ? = s total 3v line i line ? =
three-phase systems AN2512 28/38 in the balanced loads, the sum of the two wattmeter readings gives the total power. this can be proven in a star-connected load mathematically using the power reading of each meter as: equation 10 equation 11 equation 12 if the difference of the readings is computed, equation 13 which is 1/ 3 times the total three-phase reactive power. this means that the two-wattmeter method can also indicate the total reactive power in the three-phase loads and also the power factor. a.3 three-wattmeter method this method is used in a three-phase four-wire balanced or unbalanced load. the connections are made with one meter in each line as shown in figure 18 . in this configuration, the total active power supplied to the load is equal to the sum of the three wattmeter readings. equation 14 figure 18. the wattmeter connections in the three-phase four-wire loads p 1 v 12 i 1 ? 30 ? () cos ? v line i line ? 30 ? () cos ? = = p 2 v 32 i 3 ? 30 ? () cos ? v line i line ? 30 ? () cos ? = = p total p 1 p 2 3v line i line cos ? ? = + = p 2 p 1 ? v line i line ? 30 ? () cos ? v line i line ? 30 ? () v line i line ? sin = cos ? ? = p total p 1 p 2 ? p 3 ? =
AN2512 example of source code 29/38 a.4 one-wattmeter method this method is suitable only in three-phase four-wire balanced loads. the connection of the wattmeter is similar to the drawing given in figure 18 . the total power is equal to three times the reading of only one wattmeter that is connected between one phase and the neutral. appendix b example of source code the c code below shows an example of handling energy value (either active type 0, type1, reactive or apparent) after it has been read, unpacked and stored into register new. for signed wide-band active energy as an example, a pointer named e should be loaded with &actwb then, energyquant() should be called. this function checks for rollover and computes a quant of energy. later, energyupdate() is called. this function updates the fractional part of integrator first (frac). if the fractional part reaches a certain limit, it is subtracted from the fractional part and the integer part (integ) of integrator increments. the value of the limit and the direction of subtraction and increment depends on the sign of quant. some applications may have positive and negative energy integrators or quadrant integrators for apparent energy. all this influences an implementation of both functions. with a proper limit value for the fractional part, one can prescribe a suitable bit weight of the integer part of the integrator. for example if the limit is set to 0x00140000 (with a device calibrated to provide 128000 pulses/kwh) then the lsb of the integer part represents exactly 0.01 kwh. below is an example of source code. /* defini t ion of stpm01 regi st er s st ruc t ure */ t ypedef st ruc t stpm { long in t dap[3]; long in t drp[3]; long in t dsp[3]; long in t dfp[3]; long in t de v [3]; long in t dm v [3]; long in t c fl[3]; long in t c fh[3]; } stpm_s t ruc t ; /* defini t ion of energy in t egra t or st ruc t ure */ t ypedef st ruc t energ { long in t old[4]; /* previou s energy value */ in t quo t [4]; /* quan t /16 */ in t quan t [4]; /* new - old, mea s ure of power */
example of source code AN2512 30/38 long in t frac[4]; /* frac t ion par t of energy in t egra t or */ long in t in t eg[4]; /* in t eger par t of energy in t egra t or */ } energ; /* defini t ion of variable s for in t ernal regi st er s value s */ char st a t u s [3]; char mode[3]; in t freq[3]; in t urms[3]; in t irms[3]; in t umom[3]; in t imom[3]; long in t ac t ive0[4]; long in t ac t ive1[4]; long in t reac t ive[4]; long in t apparen t [4]; /* alloca t ion for all t ype s of energie s */ long in t new; /* energy value t o be handled */ energ *e; /* -> energy in t egra t or */ energ ac t wb; /* ac t ive wide band energy */ energ reac t ive; /* reac t ive energy */ energ ac t fund; /* ac t ive fundamen t al energy */ energ apparen t ; /* apparen t energy */ /* defini t ion of con st an t */ #define elimit 0x140000 /* produce s 0.01 kwh re s olu t ion in ca s e of 128000 pul s e s per kwh */ /*---------------------------------------------------------------------------------- routine name : energyquan t input/output : none/none des c ription : energy quan t compu t ing func t ion (ver s ion for s igned energy in t egra t ion). c heck s for rollover s and compu t e quan t a s difference be t ween new and old value. re t urn s a nega t ive s ign of quan t . ----------------------------------------------------------------------------------*/ in t energyquan t (long in t *new) { long in t newtemp; char i,temp;
AN2512 example of source code 31/38 if (readstpm01falg == 0){ for (i = 0; i < 3; i ++){ newtemp = * new; e->old[i] = newtemp;// s ave t he value for t he fir st t ime reading new ++; //nex t da t a } e->quo t [0] = 0; e->quo t [1] = 0; e->quo t [2] = 0; } el s e{ e->quan t [3] = 0; for (i = 0; i <3; i++ ){ newtemp = *new; // rollover high t o low occur s when msb goe s from f t o 0 if (newtemp >= e->old[i]){ if ((newtemp - e->old[i]) >= 0x80000){ //roll over, nega t ive energy e->quan t [i] = 0x100000 + e->old[i] -newtemp; e->quan t [3] -= e->quan t [i];// t o t al ernergy minu s t he nega t ive energy } el s e{ e->quan t [i] = newtemp - e->old[i]; //po s i t ive energy e->quan t [3] += e->quan t [i]; //add t he po s i t ive energy t o t he t o t al energy } } el s e{ if ((e->old[i] - newtemp) >= 0x80000) { //roll over, po s i t ive energy e->quan t [i] = 0x100000 + newtemp - e->old[i]; e->quan t [3] += e->quan t [i]; // t o t al ernergy plu s t he po s i t ive energy } el s e{ e->quan t [i] = e->old[i] - newtemp; //nega t ive energy e->quan t [3] -= e->quan t [i]; // t o t al energy minu s t he nega t ive energy } } e->old[i] = newtemp;// s ave t he value for nex t t ime new ++; //nex t da t a } }
example of source code AN2512 32/38 if (e->quan t [3] > 0xf0000000) //for t e st purpo s e e->quan t [3] = 0; e->quo t [3] = e->quan t [3] >> 4; temp = e->quan t [3] & 0x0f;// s ave t he re s idue e->frac[3] += temp; accuracy_error_ c oun t ++; if (accuracy_error_ c oun t == 3){ accuracy_error_ c oun t = 0; if (e->quan t [0] >= 2) e->quan t [0] -= 2; } led_frac += e->quan t [0] & 0x0f; e->quo t [2] = e->quo t [1]; e->quo t [1] = e->quo t [0]; e->quo t [0] = e->quan t [0] >> 4; } /*-------------------------------------------------------------------------------- routine name : energyupda t e input/output : none/none des c ription : energy upda t e func t ion (ver s ion for s igned energy in t egra t ion)if quan t i s nega t ive, s ub t rac t o t herwi s e add i ts value from t he in t egra t or. re t urn s t rue when frac reache s elimit ---------------------------------------------------------------------------------*/ in t energyupda t e(void) { pm_u8 i; e = &ac t wb; // ac t ive wb energy calcula t ion for (i = 0; i < 3; i++){ e->frac[i] += (long in t )e->quo t [i];// add quo t t o frac if (e->quan t [i] < 0){ // i s quan t nega t ive? if (e->frac[i] > (-elimit)) re t urn(0); // ye s , i s wi t hin t he limi t ? el s e { e->frac[i] += elimit; (e->in t eg[i])--; // no, s ub t rac t i t and incremen t
AN2512 example of source code 33/38 } } el s e { if (e->frac[i] < elimit) re t urn(0); // no, i s wi t hin t he limi t ? el s e { e->frac[i] -= elimit; (e->in t eg[i])++; // no, s ub t rac t i t and incremen t } } } e->frac[3] += (long in t )e->quo t [3]; // add quo t t o frac led_frac += (long in t )e->quo t [0]; if (led_frac >= me t er c on st an t ) { //me t er c on st an t = 0x1f400 //128000 0x4000) gpio0->pd ^= 0x1000; //gpio0.12 ac t ive engergy ou t pu t led_frac -= me t er c on st an t ; //0x4000; } if (e->frac[3] >= elimit) { e->frac[3] -= elimit; (e->in t eg[3])++; // no, s ub t rac t i t and incremen t lto t al[0] ++; } /*cacula t e t he 3 pha s e t o t al energy, and genera t e t he ou t pu t pul s e*/ re t urn(1); // re t urn limi t ha s been reached }
bom list AN2512 34/38 appendix c bom list table 10. bom list index qty ref. value / generic part number package manufacture?s ordering code/ orderable part number supplier sup- plier?s order- ing code 12 c1,c2 smt c0g ceramic capacitor,15 pf 50 v 0805 212 c3, c4, c6, c7, c13, c14, c16, c17, c23, c24, c26, c27 smt x7r ceramic capacitor,1000 pf 50 v 0805 36 c5, c8, c15, c18, c25, c28 x7r smt ceramic capacitor, 1 f 16 vdc 0805 46 c9, c12, c19, c22, c29, c32 smt x7r ceramic capacitor,10 nf 50 v 0805 5 3 c11, c21, c31 4.7 f no mounted 61 c34 rubycon aluminium radial lead electrolytic capacitor zl series 56 mr 995 ma 20% 330 f 25 v rubycon 71 c35 rubycon aluminium radial lead electrolytic capacitor za series 270 mr 350 ma 20% 22uf 16 v rubycon 8 2 c36, c39 smd ceramic capacitor 220 nf 630 v 20% 220nf 630 v 2220 tdk 9 2 c37, c43 smt x7r ceramic capacitor,100 nf 50 v 0805 10 1 c38 radyal electrolytic capacitor 2.2 f 400 v diameter: 10 mm lead s p a c i n g : 5 mm 11 1 c40 radyal electrolytic capacitor 1000 f 25 v diameter: 13 mm lead s p a c i n g : 5 mm 12 1 c41 radyal electrolytic capacitor 10 f 50 v diameter:4 mm lead spacing: 2.5 mm 13 1 c42 y1 suppression ceramic cap, 2.2 nf 250 vac ceramite rs 214-5903
AN2512 bom list 35/38 14 1 c44 smt x7r ceramic capacitor 47nf 50 v 0805 15 3 d1,d3,d5 smd led low current superred p-lcc-2 osram distrelec 631039 16 4 d2,d4,d6,d14 small signal smd diode ll4148 1206 17 2 d7,d12 smt diode bridge 1000 v 1 a general semiconductor rs 269-344 18 1 d8 mini-melf zener diode 15 v 0.5 w 5% smd mini- melf 1206 19 1 d9 small signal schottky diode 80 v 0.5 a tmbat49 melf glass stmicroelectronics 20 2 d11,d13 do-41 zener diode 180 v 2 w 5% do41 21 1 j1 5 way 2 row header, 0.1 in pitch 7 mm pin (10 pin connector) tht 22 1 j2 10 way 2 row header, 0.1 in pitch 7 mm pin (20 pin connector) tht 23 7 j5,j7,j8,j9,j10,j11, j12 1 way header, 7 mm pin (1 pin connector) tht 24 2 j13, j14 3 way 2 row header, 0.1in pitch 7 mm pin (6 pin connector for jumper) tht 25 3 l1,l2,l3 current transformer for indirect connection without dc-tolerance ct 1:2000 tht vac www.vacuumschm elze.de 26 1 l4 axial bc inductor, 1000 h 130 ma tht axial epcos rs 191-0712 27 1 l5 signal-use smd inductor 10 h 125 ma 0805 tdk 28 1 ntc1 ntc inrush current suppressor, 50 r 2 a tht rs 210-673 29 1 q1 n-channel 500 v - 2.8 ? - 2.3 a zener- protected supermesh?power mosfet std3nk50z dpak stmicroelectronics table 10. bom list (continued) index qty ref. value / generic part number package manufacture?s ordering code/ orderable part number supplier sup- plier?s order- ing code
bom list AN2512 36/38 30 3 rv1,rv2,rv3 so5k275/275 v epcos distrelec 730096 31 1 r1 s m t c h i p r e s i s t o r 1 mohm 1% 0.125 w 0805 32 3 r2,r18,r34 smt chip resistor, 750 ohm 1% 0.125 w 0805 33 7 r5,r8,r21,r24,r37, r40,r54 s m t c h i p r e s i s t o r 1 kohm 1% 0.125 w 0805 34 3 r6,r22,r38 mma 0204 professional melf resistors 3.3 ohm 1% 1206 beyschlag distrelec 713014 35 3 r7,r23,r39 smt chip resistor 150 kohm 1% 0.125 w 0805 36 3 r9,r25,r41 mma 0204 professional m e l f r e s is t or s 2.2 mohm 1% 1206 beyschlag distrelec 713154 37 3 r10,r26,r42 smt chip resistor 2,2 kohm 1% 0.125 w 0805 38 3 r13,r29,r45 s m t c h i p r e s i s t o r, 0 ohm 0.125 w 0805 39 6 r14,r15,r30,r31,r 46,r47 mma 0204 professional melf resistors 270 kohm 1% smd 1206 beyschlag distrelec 713132 40 3 r16,r32,r48 mma 0204 professional melf resistors 200 kohm 1% smd 1206 beyschlag distrelec 713129 41 3 r17,r33,r49 mma 0204 professional melf resistors 470 ohm 1% smd 1206 beyschlag distrelec 713066 42 1 r52 smt chip resistor 10 ohm 1% 0.125 w 0805 43 1 r53 smt chip resistor 220 ohm 1% 0.125 w 0805 44 2 r55,r57 smt chip resistor 4.7 kohm 1% 0.125 w 0805 45 1 r56 smt chip resistor 5.6 kohm 1% 0.125 w 0805 46 3 r58,r59,r60 smt chip resistor 330 kohm 5% 0.25 w 1206 47 4 r61,r62,r63,r64 rox1s metal oxide film resistor 22 ohm 1 w axial neohm rs 214-0920 table 10. bom list (continued) index qty ref. value / generic part number package manufacture?s ordering code/ orderable part number supplier sup- plier?s order- ing code
AN2512 revision history 37/38 6 revision history 48 1 t1 e13 tiw switch mode transformer tht pulse (www.pulseeng. com) 49 3 u1,u2,u3 programmable single phase energy metering ic with tamper detection stpm01ftr_tssop20 tssop20 stmicroelectronics 50 1 u4 very low drop voltage regulators 3.3 v with inhibit 300 ma 1% l4931abd33 so-8 stmicroelectronics 51 1 u5 opto-isolator pc817 dip6 52 1 u6 programmable shunt voltage reference 1% ts2431 sot23-3 stmicroelectronics 53 1 u7 low power off-line smps primary switcher viper12as-e so-8 stmicroelectronics 54 1 u8 hex schmitt inverter m74hc14 sop stmicroelectronics 55 1 y1 crystal 4.194304 mhz auris distrelec 335026 table 10. bom list (continued) index qty ref. value / generic part number package manufacture?s ordering code/ orderable part number supplier sup- plier?s order- ing code table 11. revision history date revision changes 17-apr-2007 1 first issue
AN2512 38/38 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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