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july 2007 rev 1 1/33 AN2555 application note porting an application from th e st10f269zx to the st10f276z5 introduction the st10f276z5 is a member of the stmicroelectronics st10 family of 16-bit single-chip cmos microcontrollers. it is functionally upward compatible with the st10f269zx. the goal of this document is to highli ght the differences between st10f269zx and st10f276z5 devices. it is intended for hardware or software designers who are adapting an existing application based on the st10f269zx to the st10f276z5. this document presents the st10f276z5?s modified functionalities and the new ones then it describes the modified registers and the new registers. for each part, the differences with the st10f269zx that may have an impact when replacing the st10f269zx by the st10f276z5 are stressed and some advice is given on the way they can be handled. this document applies from the second silicon version of the st10f276z5, that is from the ba step where a new sectorizatio n of the flash memory was in troduced. the silicon version can be verified by reading the idchip register at location 00?f07ch. the values for these silicon versions are 114xh with x > 1. www.st.com
AN2555 - application note contents 2/33 contents 1 modified features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 xram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 flash eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.6 can modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.7 port input control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.8 port output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.9 pll and main on-chip oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 new features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1 additional xperipherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 new multiplexer for x-interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 programmable divider on clkout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 additional port input control: xpicon register . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 modified registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 xpercon register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 idchip register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 new registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 xadrs3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2 xperemu register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 emulation-dedicated registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4 xmisc register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 ac characteristics at 40 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AN2555 - application note modified features 3/33 1 modified features 1.1 pinout 1.1.1 pinout modification summary ta b l e 1 summarizes the modifications made in the pinout. 1.1.2 pin 17 on the st10f269zx, a decoupling capacitor of 330nf minimum has to be connected between the pin 17 (named dc2) and the nearest v ss pin. this is no longer the case for the st10f276z5 device where pin 17 is a v dd pin. hardware impact pcb must be adapted. software impact none. table 1. pinout modifications pin number st10f269zx name and func tion st10f276z5 name and function 17 dc: internal voltage regulator decoupling. connect to nearest v ss via a 330 nf capacitor. v dd : 5 v power supply pin 56 dc1: internal voltage regulator decoupling. connect to nearest v ss via a 330nf capacitor. v18: internal voltage regulator decoupling. connect to nearest v ss via a 10-100nf capacitor. 99 ea : selects code execution out of internal flash memory or external memory according to level during reset. ea -v stby : selects code execution out of internal flash memory or external memory according to level during reset. power supply input for standby mode. 143 v ss : ground pin xtal3: input to the 32 khz oscillator amplifier circuit. when not used shall be tied to ground to avoid consumption. besides, bit off32 in rtccon register must be set. 144 v dd : 5v power supply pin xtal4: output of the 32 khz oscillator amplifier circuit. when not used must be left open to avoid spurious consumption.
AN2555 - application note modified features 4/33 1.1.3 pin 56 on the st10f269zx, a decoupling capacitor of 330nf minimum has to be connected between the pin 56 (named dc1) and the nearest v ss pin. on the st10f276z5, pin 56 is named v 18 and a capacitor of value between 10nf minimum to 100nf maximum must be connected between it and the nearest v ss pin. hardware impact change on the capacitor value. as the value is much lower, the footprint of the capacitor might be smaller and a modification of the pcb might be needed. software impact none. 1.1.4 pin 99 on the st10f269zx, pin 99 is ea and used upon reset to select the start from the internal flash memory or the external memory. on the st10f276z5, pin 99 has the additional function of providing the 5v power supply to the device in standby mode (new power-saving mode), it is called ea -v stby . hardware impact the modification depends on the previous use of the st10f269zx and on whether the standby mode is used or not. for an application where the standby mode is not used, no change to the pcb is required. if the new application uses the standby mode, the ea -v stby pin must be separated from the common 5v and have a specific supply path. software impact none. 1.1.5 pins 143 and 144 these pins are v ss and v dd , respectively, in the st10f269zx. on the st10f276z5 they are used as xtal3 and xtal4 for connection to an optional 32 khz crystal to clock the real time clock during power-down. hardware impact pcb must be redesigned. if the optional 32 khz is not used: pin 143 (xtal3) must be linked to ground like on the st10f269zx pin 144 (xtal4) must be left open. it can also be connected to ground via a capacitor to reduce the potential rf noise that might be propagated inside the device if the pin is left floating.
AN2555 - application note modified features 5/33 software impact in case the optional 32 khz is not used, the off32 bit of the rtccon register must be set. prior to setting the off32 bit in rtccon register, the rtc must be enabled by setting rtcen, bit 4 of xpercon, and xpen, bit 3 of syscon. 1.2 xram the st10f269zx has 10 kbytes of extension ram whereas the st10f276z5 has 66 kbytes. the xram of the st10f269zx is divided into 2 ranges, xram1 of 2 kbytes and xram2 of 8 kbytes: the xram1 address range is 00?e000h - 00?e7ffh if enabled (xpen and xram1en, bit 2 of syscon register and of xper con register, respectively , must both be set). the xram2 address range is 00?c000h - 00?dfffh if enabled (xpen and xram2en, bit 2 of syscon register and bit 3 of xpercon register, respectively, must both be set). the xram of the st10f276z5 is divided into 2 ranges, xram1 of 2 kbytes and xram2 of 64 kbytes: the xram1 address range is 00?e000h - 00?e7ffh if enabled (xpen and xram1en, bit 2 of syscon register and bit 2 of xpercon register, respectively, must both be set). the xram2 address range is 0f?0000h - 0f?ffffh if enabled ( xpen and xram2en, bit 2 of syscon register and bit 3 of xpercon register, respectively, must both be set). 1.2.1 hardware impacts none. 1.2.2 software impacts there is no change in the enabling of the xram blocks: xpercon register bits, xram1en and xram2en, and syscon register bit, xpen, are used to enable them. the memory mapping of the application is impacted by the different xram size and the different location of xram2 in segment 15. in the st10f269zx the whole xram is in page 3 of segment 0. variables and pec transfers for architecture reasons, the pec destination and source pointers must be in segment 0. therefore all ram variables and arrays that will be pec addresse d must be located with in either the dpram (00?f600h - 00?fdffh) or xram1 (00?e000h - 00?e7ffh). about toolchain memory model a change in the toolchain configuration is needed to take into account the new xram2 location. in the st10f269zx, the entire xram is in page 3 and is th en automatically addressed using dpp3 that points to page 3 (in order to access the dpram and the sfr/esfr). for the st10f276z5, it is necessary to dedicate a dpp to access some of xram2. example in case of small memory model with tasking toolchain the small memory model makes it possible to have a total code size up to 16 mbytes, up to 64 kbytes of fast accessible 'normal user data' in three different memory configurations and the possibility to access far/huge data, if more than 64 kbytes of data is needed.
AN2555 - application note modified features 6/33 the three memory configurations possible for this 64 kbytes of 'normal user data' are: default the four dpp registers are assume d to contain their system startup value (0-3), prov iding one linear data area of 64 kbytes in the first segment (00?0000h - 00?ffffh). addresses linear dpp3 contains page number 3, allowing access to st10 registers and bit-addressable memory. dpp0 - dpp2 provide a linear data area of 48 kbytes anywhere in memory. paged dpp3 contains page number 3, allowing access to st10 registers and bit-addressable memory. dpp0, dpp1 and dpp2 contain the page numbers of data areas of 16 kbytes anywhere in memory. the default configuration can no longe r be used. the other configurati ons offer the following possibilities: with the addresses linear configuration the xram2 block is almost entirely covered with dpps but then accesses to constants must be made via extp instructions. in the paged configuration up to two dpps ca n be assigned to xram2 and one dpp for constants. 1.3 flash eeprom table 3: flash memory mapping shows the flash memory address ranges of the 2 devices. table 2. flash memory key characteristics st10f269zx st10f276z5 flash size 256 kbytes 832 kbytes flash organization 7 blocks 4 banks, 17 blocks programming voltage 5 volts 5 volts programming method write/erase controller write/erase controller program/erase cycles 100000 cycles 100000 cycles
AN2555 - application note modified features 7/33 1.3.1 hardware impacts none. 1.3.2 software impacts the mapping of the application, the programming and erasing routines are impacted. 1.4 a/d converter in the st10f276z5, the analog digital converter has been re-designed (compared to the a/d converter in the st10f269zx). the st 10f276z5 still provides an analog / digital converter with 10-bit resolution and an on-chip sample & hold circuit. 1.4.1 hardware / software impact: conversion timing control the a/d converter in the st10f276z5 is not fully compatible to that in the st10f269zx (timing and programming model). table 3. flash memory mapping segment number st10f269zx flash mapping s t10f276z5 flash mapping 14 05?0000 - 0e?ffff 0e?0000 - 0e?ffff flash registers 13 0d?0000 - 0d?ffff x-bank3, block1: 64kb 12 0c?0000 - 0c?ffff x-bank3, block0: 64kb 11 0b?0000 - 0b?ffff x-bank2, block2: 64kb 10 external memory 0a?0000 - 0a?ffff x-bank2, block1: 64kb 9 09?0000 - 09?ffff x-bank2, block0: 64kb 8 08?0000 - 08?ffff i-bank1, block1: 64kb 7 07?0000 - 07?ffff i-bank1, block0: 64kb 6 06?0000 - 06?ffff i-bank0, block9: 64kb 5 05?0000 - 05?ffff i-bank0, block8: 64kb 4 04?0000 - 04?ffff block6: 64kb 04?0000 - 04?ffff i-bank0, block7: 64kb 3 03?0000 - 03?ffff block 5: 64kb 03?0000 - 03?ffff i-bank0, block6: 64kb 2 02?0000 - 02?ffff block 4: 64kb 02?0000 - 02?ffff i-bank0, block5: 64kb 1 01?8000 - 01?ffff block 3: 32kb 01?8000 - 01?ffff i-bank0, block4: 32kb 01?0000 - 01?7fff external memory 01?0000 - 01?7fff external memory 00?8000 - 00?ffff external memory internal ram 00?8000 - 00?ffff external memory internal ram 0 00?6000 - 00?7fff block 2: 8kb 00?6000 - 00?7fff i-bank0, block3: 8kb 00?4000 - 00?5fff block 1: 8kb 00?4000 - 00?5fff i-bank0, block2: 8kb 00?0000 - 00?3fff block 0: 16kb 00?2000 - 00?3fff i-bank0, block1:8kb 00?0000 - 00?1fff i-bank0, block0: 8kb
AN2555 - application note modified features 8/33 in the st10f269zx, the sample time (to charge the capacitors) and the conversion time are programmable and can be adjusted to the external circuitry. the total conversion time is compatible with the formula used for st10f269zx, while the meanings of the adctc and adstc bit fields are no longer compatible. the parameter to take care of is the sample time: this is the time during which the capacitances of the converter are charged via the respective analog input pins. table 5: st10f276z5 vs. st10f269zx sample time comparison table shows the respective samp le times of the 2 devices. table 4. st10f276z5 conversion timing table adctc adstc sample comparison extra total conversion 00 00 tcl * 120 tcl * 240 tcl * 28 tcl * 388 00 01 tcl * 140 tcl * 280 tcl * 16 tcl * 436 00 10 tcl * 200 tcl * 280 tcl * 52 tcl * 532 00 11 tcl * 400 tcl * 280 tcl * 44 tcl * 724 11 00 tcl * 240 tcl * 120 tcl * 52 tcl * 772 11 01 tcl * 280 tcl * 560 tcl * 28 tcl * 868 11 10 tcl * 400 tcl * 560 tcl * 100 tcl * 1060 11 11 tcl * 800 tcl * 560 tcl * 52 tcl * 1444 10 00 tcl * 480 tcl * 960 tcl * 100 tcl * 1540 10 01 tcl * 560 tcl * 1120 tcl * 52 tcl * 1732 10 10 tcl * 800 tcl * 1120 tcl * 196 tcl * 2116 10 11 tcl * 1600 tcl * 1120 tcl * 164 tcl * 2884
AN2555 - application note modified features 9/33 in the default configuration the sample time of the st10f276z5 is 2.5 times longer compared to that of the st10f269zx. this has an impact on the frequency of the input signal that can be applied to the st10f276z5. 1.4.2 hardware impacts electrical characteristics ta b l e 6 lists the differences in the dc characteristics of the two devices. the main points are: i aref is 10 times higher on the st10f276z5. the v aref pad must therefore be directly connected to the power supply: connecting a resistor would create a voltage shift in the analog reference. c ain , input pin capacitances are different. dnl, inl and ofs are different: the adc conversion curves for the 2 devices are different. table 5. st10f276z5 vs. st10f269zx sample time comparison table adctc adstc st10f269zx sample time st10f276z5 sample time ratio f276z5 / f269zx 00 00 tcl * 48 tcl * 120 2.5 00 01 tcl * 96 tcl * 140 1.46 00 10 tcl * 192 tcl * 200 1.04 00 11 tcl * 384 tcl * 400 1.04 11 00 tcl * 96 tcl * 240 2.5 11 01 tcl * 192 tcl * 280 1.46 11 10 tcl * 384 tcl * 400 1.04 11 11 tcl * 768 tcl * 800 1.04 10 00 tcl * 192 tcl * 480 2.08 10 01 tcl * 384 tcl * 560 1.46 10 10 tcl * 768 tcl * 800 1.04 10 11 tcl * 1538 tcl * 1600 1.04
AN2555 - application note modified features 10/33 note: the v aref pin is also used as a supply pin for t he adc module. as there is a higher current sink on this pin on the st10f276z5 compared to the st10f269zx, it is recommended not to connect a resistor (for example because of an rc filter), to prevent creating an offset in the reference. 1.4.3 software impacts self-calibration and adc initialization routine an automatic self-calibration adjusts the adc module to process parameter variations at each reset event. after reset, the busy flag (read-only) adbsy is set because the self-calibration is ongoing. the table 6. adc differences parameter symbol limit values for st10f269zx limit values for st10f276z5 unit min. max. min. max. analog reference voltage v aref 4.0 v dd + 0.1 4.5 v dd v analog input voltage v ain v agnd v aref v agnd v aref v adc input capacitance port5, not sampling port5, sampling port1, not sampling port1, sampling c ain - - - - 10 15 n.a. n.a. - - - - c p1 + c p2 +c s 7 10.5 9 12.5 pf sample time t s 48tcl 1536tcl 1s 120tcl 1600tcl conversion time t c 388tcl 2884tcl 388tcl 2884tcl total unadjusted error port5 port1 - no overload port1 - overload tue -2.0 - - +2.0 - - -2.0 -5.0 -7.0 +2.0 +5.0 +7.0 lsb internal resistance of analog source r asrc t s [ns]/150 - 0.25 k ? analog switch resistance r sw port5 port1 n.a. n.a. - - 600 1000 ? r ad n.a. n.a. - 1300 ? reference supply current running mode power-down mode i aref - - 500 1 - - 5000 1 a differential nonlinearity dnl -0.5 +0.5 1 1 lsb integral nonlinearity inl -1.5 +1.5 -1.5 1.5 lsb offset error ofs -1.0 +1.0 -1.5 1.5 lsb
AN2555 - application note modified features 11/33 duration of self-calibration depends on the cpu clock: it may take up to 40.629 1 clock pulses. the user must poll this bit to know wh en self-calibration is complete in order to initializ e the adc module. this self-calibration is seen by th e st10f276z5 as a conversion and thus bit adcir is set. the software must perform a dummy read of the addat register and clear the adcir and adceir flags before configuring the adc module and starting the first conversion. new bit adoff, bit 6 of adcon register adcon (ffa0h / a0h) sfr reset value: 0000h the bit 6 of the adcon register, reserved in previous st10 devices, is now used to enable or disable the adc. by default this bit is cleared and the st10f276z5 is compatible with the st10f269zx. therefore there is no impact on the software, provided that the software does not write to this bit. additional analog channels on port1 a new multiplexer selects one out of up to 16+8 analog input channels (alternate functions of port 5 and port1). the selection of port1 or port5 as input of the adc is made via adcmux, bit 0 of xmisc register. by default the multiplexer selects port5, so there is no impact on the software as compared to an st10f269zx implementation. note that xmiscen, bit 10 of the xpercon register, must be set to ha ve access to the xmisc register. xmisc (eb46h) xreg reset value: --00h 15 14 13 12 11 10 9 8 7 6 543210 adctc adstc adctc adcin adwr adbsy adst adoff adm adch rw rw rw rw rw r rw rw rw rw bit function comment adoff adc disable ?0?: analog circuitry of a/d converter is on ?1?: analog circuitry of a/d converter is turned off (no consumption) new bit only for the st10f276z5. reserved for the st10f269zx. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------vregoffcanck2canparadcmux rw rw rw rw bit function adcmux ?0? default configuration, analog inputs on port p5.y can be converted ?1? analog inputs on port p1.z can be converted, only 8 channel can be managed
AN2555 - application note modified features 12/33 1.5 real time clock the rtc module can be clocked by two different source s: the main osc illator ( pins xtal1 and xtal2) or the 32 khz low power oscilla tor (pins xtal3 and xtal4) . the selection of the cl ock source can be made via an additional bit in the rtccon register. 1.5.1 hardware impacts check the usage of xtal3 and xtal4 (respectively pins 143 and 144). 1.5.2 software impacts the address range of the rtc registers has been modified from 00?ec00h - 00?ecffh on the st10f269zx to 00?ed00h - 00?edffh on the st10f276z5. this change had no impact if the software uses the register names defined by the toolchains and if the target cpu selection is changed to st10f276z5. if the software was directly using the address of the rtc register, it must be modified according to new mapping. in the st10f269zx, both byte and word accesses were allowed for the rtc module. in the st10f276z5, only word accesses are possible. check that the code is not doing byte accesses to the rtc module. in addition, new bits have been added into the rtccon register (osc, off32). there is no impact if the code was not writing to the upper part of the rtccon register, which was reserved. the handling of the rtcair and rtcsir flags (respect ively, bit 2 and bit 0 of the rtccon register) is also changed: in the st10f276z5, these flags are cleared by writing them to 1 in the st10f269zx, these flags are cleared by writing them to 0 as these flags must be cleared by software when ente ring the corresponding interrupt service routine, a change in the application code is needed. example for the rtcsir flag replace st10f269zx code: rtccon &= 0xfffe;// clear rtcsir flag by the following code for st10f276z5: rtccon |= 0x0001;// write 1 into rtcsir flag to clear it st10f269zx: rtccon (f1c4h / e2h) esfr reset value: --00h st10f276z5: rtccon (f1c4h / e2h) esfr reset value: 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -------- rtc off --- rtc aen rtc air rtc sen rtc sir rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------off32oscrtcoff---rtcaenrtcairrtcsenrtcsir rw r rw rw rw rw rw
AN2555 - application note modified features 13/33 1.6 can modules the st10f269zx has two can modules of the b-can type. the st10f276z5 has two can modules of the c-can type. these modules are functionally compatible with the modules of the st10f269zx. the c-can cells provide additiona l message objects and new functi onalities like time triggered protocol capability. the main differ ence is that the message objects are no longer direct ly accessed as memory but are available through a message interface. this changes the programming model of the modules. in the st10f269zx, byte and word accesses are authorized for the can modules. in the st10f276z5 only word accesses are possible. 1.6.1 hardware impacts none. 1.6.2 software impacts re-write the can drivers. table 7. rtccon register bits bit function reset value rtcsir rtc second interrupt request flag (every basic clock unit) ?0?: the bit was reset less than a basic clock unit ago. ?1?: the interrupt was triggered. 0 rtcsen rtc second interrupt enable ?0?: rtc_secit is disabled. ?1?: rtc_secit is enabled, it is generated every basic clock unit. 0 rtcair rtc alarm interrupt request flag (when the alarm is triggered) ?0?: the bit was reset less th an n basic clock units ago. ?1?: the interrupt was triggered. 0 rtcaen rtc alarm interrupt enable ?0?: rtc_alarmit is disabled. ?1?: rtc_alarmit is enabled. 0 rtcoff rtc switch off bit ?0?: clock oscillator and rtc run even if st10 is in power down mode. ?1?: clock oscillator is off when st10 enters power down mode. besides, setting this bit stop rtc dividers an d counters, and regi sters can be written. 0 osc oscillator selection flag ?0?: the clock oscillator used by the rtc is the main oscillator. ?1?: the clock oscillator used by the rtc is the low power 32 khz oscillator. u off32 32 khz oscillator switch off bit ?0?: the 32 khz oscillator is enabled. rtc clocked by 32 khz oscillator (if there is a valid signal). ?1?: the 32 khz oscillator is disabled. rtc clocked by the main oscillator. 0
AN2555 - application note modified features 14/33 1.7 port input control the port input control register picon is used to select between ttl and cmos-like input thresholds. the cmos-like input thresholds are defined above the ttl levels and feature a hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds. on the st10f269zx this feature is available for all pins of port 2, port 3, port4, port 7 and port 8 and the hysteresis level is 250mv for cmos levels. in the st10f276z5, port 6 has been added. moreover the default hysteresis is now 500mv for ttl levels and 800mv for cmos levels. st10f269zx: picon (f1c4 h / e2 h ) esfr reset value: --00h st10f276z5: picon (f1c4 h / e2 h ) esfr reset value: --00h 1.7.1 hardware impacts the cmos levels of the 2 devices are slightly differen t, therefore the circuitry must be checked to verify that the new levels can still matc h the requirements. re fer to the st10f276z5 datasheet an d to the section 5.1: dc characteristics for more details. 1.7.2 software impacts the initialization of the picon register should be checked to control that it is not writing to the new bit p6lin. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 --------p8linp7lin-p4linp3hinp3linp2hinp2lin rwrw - rwrwrwrwrw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 --------p8linp7linp6linp4l in p3hin p3lin p2hin p2lin rw rw rw rw rw rw rw rw bit function reset value pxlin port x low byte input level selection ?0?: pins px.7..0 switch on standard ttl input levels 1: pins px.7..0 switch on cmos input levels 0 pxhin port x high byte input level selection ?0?: pins px.15..8 switch on standard ttl input levels ?1?: pins px.15..8 switch on cmos input levels 0
AN2555 - application note modified features 15/33 1.8 port output control in the st10f269zx, the port output control registers poconx are used to select the output driver characteristics of a port. in this way, the output drivers can be adapted to the application?s requirements, and eventually, the emi behavior of the device can be improved. two characteristics may be selected: edge characteristic defines the rise/fall time for the respective outputs, that is, the transition time. slow edge reduces the peak currents that are sunk/sourced when changing the voltage level of an external capacitive load. driver characteristic defines either the general driving capabilit y of the respective drivers, or if the driver strength is reduced after the target output level has been reached or not. reducing the driver strength increases the output?s internal resistance, which attenuates noise that is imported via the output line. this feature is not available on the st10f276z5. 1.8.1 hardware impacts depending on the usage of this functionality, some modifications might be needed. 1.8.2 software impacts parts related to the initia lization of the poconx registers should be suppressed.
AN2555 - application note modified features 16/33 1.9 pll and main on-chip oscillator compared to the st10f269zx, several modifications have been introduced: pll multiplication factors have been adapted in order to match the new frequency range. on-chip main oscillator input fre quency range has been res haped, reducing it to a range from 4 to 12 mhz: this allows the power consumption to be r educed when the real time clock is running in power down mode and the on-chip main os cillator clock is used as the reference. when the pll is used, the cpu frequency range is 16 to 64 mhz. figure 1: st10f276z5 clock generation diagram gives a simplified description of the cpu clock generation. depending on the multiplication factor selected via port 0 at reset, values are set for each stage. the cpu clock is in fact generated mainly from a vco (voltage contro lled oscillato r) with the following characteristics: input range: 1 to 3.5 mhz, which is delivered from xtal divided by a prescaler. output range: 64 to 128 mhz that is then divided through divider1 to generate the cpu clock figure 1. st10f276z5 clock generation diagram table 8: st10f269zx vs. st10f276z5 pll ratio lists the new pll multiplication factors and the corresponding frequency ranges for the st10f276z5. all configurations need a crystal (or ceramic resonator) to generate the cpu clock through the internal oscillator amplifier, except for the direct drive mode (oscillator am plifier disabled, so no crystal or resonator can be used). vice versa, the clock can be forced through an external clock source only in direct drive mode. table 8. st10f269zx vs. st10f276z5 pll ratio p0.15-13 (p0h.7-5) st10f269zx st10f276z5 notes pll factor f cpu = f xtal * f pll factor f cpu = f xtal * f input frequency range (mhz) 111 f xtal * 4 f xtal * 4 4 to 8 default configuration 110 f xtal * 3 f xtal * 3 5.3 to 10.6 101 f xtal * 8 f xtal * 8 4 to 8 100 f xtal * 5 f xtal * 5 6.4 to 12 011 f xtal * 1 f xtal * 1 1 to 64 direct drive 010 f xtal * 1.5 f xtal * 10 4 to 6.4 001 f xtal / 2 f xtal / 2 4 to 12 cpu clock via pre-scaler 000 f xtal * 2.5 f xtal * 16 4 prescaler vco divider1 f cpu divider2 phase comparator f xtal
AN2555 - application note modified features 17/33 1.9.1 hardware impacts port 0 configuration might be changed with regards to the new pll factor. the components on xtal1 & xtal2 (crystal and capacitors, or resonator) must be changed for the following reasons: the input frequency range is now 4 to 12 mhz it is no longer possible to use a crystal or a ceramic resonator in direct drive mode it is no longer possible to use a pll factor with a frequency generator the electrical characteristics of the main oscillator have chang ed (transconductance) 1.9.2 software impact none.
AN2555 - application note new features 18/33 2 new features 2.1 additional xperipherals some peripherals have been added to the st10f276z5. they are mapped on the x-bus and are linked to additional alternate functions of some ports of the st10f276z5. the additional xperipherals are the following: a second ssc (ssc of st10f269zx becomes ssc0, while the new one is referred to as xssc or simply ssc1). note that some re strictions and functional differences due to the xbus peculiarities are present between the standard ssc, and the new xssc. a second asc (asc0 of st10f269zx remains asc0, while the new one is referred to as xasc or simply as asc1). note that some restrictions and functional differences due to the xbus peculiarities are pres ent between the standar d asc, and the new xasc. a second pwm (pwm of st10f269zx becomes pwm0, while the new one is referred to as xpwm or simply as pwm1). note that some restrictions and functional differences due to the xbus peculiarities are present between the standard pwm, and the new xpwm. an i2c interface is added (see x-i2c or simply i2c interface). 2.1.1 hardware impacts none if the additional xperipherals are not used. 2.1.2 software impacts none if the additional peripherals are not used. as they are xperipherals, they can be enabled / disabled via the xpercon and syscon regist ers. by default, the settings of xpercon and syscon are compatible with the st10f269zx. 2.2 new multiplexer for x-interrupts the limited number of x-bus interrupt lines of the present st10 architecture, imposes some constraints on the implementation of the new fu nctionalities. in particular, the additional xperipherals xssc, xasc, xi2c and xpwm need some resources to implement interrupts and pec transfer. for this reason, a complex but very flexible multiplexed structure for the interrupt is proposed. in figure 2 the principle is represented through a simple diagram, which shows the basic structure replicated for each of the four x- interrupt vectors (xp0int, xp1int, xp2int and xp3int). it is based on a new 16-bit register xirxsel (x=0,1,2,3), divided into two bytes: higher byte (xirxsel[15:8]) interrupt enable bits lower byte (xirxsel[7:0]) interrupt flag bits when different sources submit an interrupt request, the enable bits (higher byte of xirxsel register) define a mask which controls which sources will be associated with the unique available vector. if more than one source is enabled to issue the request, the service routine has to identify the real event to be serviced. this can easily be done by checking the flag bits (lower byte of xirxsel register). note that the flag bit can provide information about events which are not currently serviced by the interrupt controller (since masked through the enable bits), allowing an effective software management also in the absence of the possibility to serve the related interrupt request: a pe riodic polling of the flag bits may be implemented inside the user application.
AN2555 - application note new features 19/33 figure 2. x-interrupt basic structure 2.2.1 hardware impact none. table 9. x-interrupt detailed mapping xp0int xp1int xp2int xp3int can1 interrupt xx can2 interrupt xx i2c receive xxx i2c transmit xxx i2c error x ssc1 receive xxx ssc1 transmit xxx ssc1 error x asc1 receive xxx asc1 transmit xxx asc1 transmit buffer xxx asc1 error x pll unlock / owd x pwm1 channel 3...0 xx xir x sel[7:0] (x = 0, 1, 2, 3) xir x sel[15:8] (x = 0, 1, 2, 3) xp x ic . ir (x = 0, 1, 2, 3) 70 15 8 it source 7 it source 6 it source 5 it source 4 it source 3 it source 2 it source 1 it source 0 enable[7:0] flag[7:0]
AN2555 - application note new features 20/33 2.2.2 software impact the xirxsel registers must be configured. if none of the new xperipherals is used, that is, if only the xperipherals already present on the st10f269zx are used, the following values must be programmed: xir0sel = 0x0100, only the can1 interrupt is enabled and will generate an interrupt to the st10 through xp0ic xir1sel = 0x0100, only the can2 interrupt is enabled and will generate an interrupt to the st10 through xp1ic xir2sel = 0x0, not used xir3sel = 0x2000, only the pll unlock interrupt is enabled and will generate an interrupt to the st10 through xp3ic. then, in the interrupt routines associated with the xpxic, the respective flags in the xirxsel register must be cleared. since the xirxsel registers are not bit addressable, a pair of registers (a pair for each xirxsel) is provided to set and clear the bits of xirxsel without risking to overwrite requests coming after reading the register and before writing it. therefore the following registers must be written to clear the flags: in the can1 interrupt routine, xir0clr (@ eb14h) = 0x0001 in the can2 interrupt routine, xir1clr (@ eb24h) = 0x0001 in the pll unlock interrupt routine, xir3clr (@ eb44h) = 0x0020 additional information on the x-interrupt multiplexer structure the figure 2: x-interrupt basic structure shows that the x-interrupt sources are connected to the interrupt request flag of the xirxsel registers and to the xpxir request flag via an and gate with the enable bit. this and gate is activated by a transition on the interrupt source line and not by the latched value in the xirxsel register. this means that: a transition on the it source line generates an interrupt to the st10 core if the source is enabled. writing to an interrupt request flag in an xirxsel register does not generate an interrupt to the st10 core. example : if xir0sel = 0x0100: can1 interrupt enabled on xp0ic interrupt to trigger by software the can1 interrupt routine with the xp0ic register, the following code must be used: xir0set = 0x0001;/* set can1 interrupt request flag in */ /* xir0sel register */ xp0ic = xp0ic | 0x0080;/*set xp0ir flag, generate an interrupt */ /* routine to the st10 */ executing only the first line only sets the flag in the xir0sel register but it is not seen by the and gate and cannot set the xp0ir flag. 2.3 programmable divider on clkout a specific register mapped on the xbus is used to choose the division factor on the clkout signal (p3.15).
AN2555 - application note new features 21/33 xclkoutdiv (e902h) xbus reset value: --00h 2.3.1 hardware impact none. 2.3.2 software impact none if only clockout is needed. when the clkout function is enab led by setting the clken bit of the syscon register, by default the cpu clock is output on p3.15. to have access to the xclkoutdiv register, and thus program the clock pre-scaling factor, the xmiscen bi t of the xpercon register and the xpen bit of the syscon register must be set. 2.4 additional port input control: xpicon register the possibility to select between ttl and cmos-like input thresholds ha s been extended to the ports 0, 1 and 5. st10f276z5: xpicon (eb26 h ) xreg reset value: --00h 2.4.1 hardware impacts none. 2.4.2 software impacts none. 1514131211109876543210 -------- div rw bit function div f clkout = f cpu / (div + 1) 1514131211109876543210 ----------p5hinp5linp1hinp1linp0hinp0lin rw rw rw rw rw rw bit function reset value pxlin port x lower byte input level selection 0: pins px.7..0 switch on standard ttl input levels 1: pins px.7..0 switch on cmos input levels 0 pxhin port x higher byte input level selection 0: pins px.15..8 switch on standard ttl input levels 1: pins px.15..8 switch on cmos input levels 0
AN2555 - application note modified registers 22/33 3 modified registers 3.1 xpercon register in the st10f276z5, new bits have been added with regards to the additional xperipherals. the xpercon register allows the xbus peripherals to be separately selected and made visible to the user by means of the co rresponding bits. if not selected ( not activated with a bit of xpercon) before the xpen bit in syscon is set, th e correspondin g address space, port pins and interrup ts are not occupied by the peripheral, and thus this peripheral is not visible and not available. st10f269zx: xpercon (f024 h / 12 h ) sfr reset value: --05h st10f276z5: xpercon (f024 h / 12 h ) sfr reset value: -005h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -----------rtcenxram2enxram1encan2encan1en rw rw rw rw rw 1514131211109876543210 ----- xmis cen xi2c en xssc en xasc en xpw men xfla shen rtce n xra m2en xra m1en can2 en can1 en rw rw rw rw rw rw rw rw rw rw rw bit number bit name function 0 can1en can1 enable bit ?0?: accesses to the can1 and its func tions are disabled (p4.5 and p4.6 pins can be used as general purpose ios) ?1?: the can1 is enabled and can be accessed. 1 can2en can2 enable bit ?0?: accesses to the can2 and its func tions are disabled (p4.4 and p4.7 pins can be used as general purpose ios) ?1?: the can2 is enabled and can be accessed. 2 xram1en xram1 enable bit ?0?: accesses to the xram1 block are disabled, external access performed. ?1?: the on-chip xram1 is enabled and can be accessed. 3 xram2en xram2 enable bit ?0?: accesses to the xram2 block are disabled, external access performed. ?1?: the on-chip xram2 is enabled and can be accessed. 4rtcen rtc enable bit ?0?: accesses to the real time clock are disabled, external access performed. ?1?: the on-chip real time clock is enabled and can be accessed. 5 xflashen xflash enable bit ?0?: accesses to the on-chip xfl ash are disabled, external access performed. ?1?: the on-chip xflash is enabled and can be accessed.
AN2555 - application note modified registers 23/33 accesses to the xperipherals are configured through 3 pairs of specific xbus configuration registers, equivalent to the external bus registers busconx and addrselx. therefore several xperipherals are sharing the same pair, with the consequence that accesses to disabled xperipherals are only re-directed to external memory if all the xperipherals sharing the same pair of registers are disabled. the xperipherals are grouped as follows: group 1: can1, can2, xasc, xssc, xi2c, xpwm, xrtc and xmisc, addr ess range 00?e800h- 00?efffh. group 2: xram1, address range 00?e000h-00?e7ffh. group 3: xram2 and xflash, address range 09?0000h-0f?ffffh. 3.1.1 hardware impacts none. 3.1.2 software impacts none if the st10f269zx software is not writing to the reserved bit. 3.2 idchip register a new field has been added inside the idchip register in order to distinguish the different peripheral options. st10f269zx: idchip (f07c h ) esfr reset value: 10dxh 6 xpwmen xpwm enable ?0?: accesses to the xpwm module are disabled, external access performed. ?1?: the on-chip xpwm module is enabled and can be accessed. 7 xascen xasc enable bit ?0?: accesses to the xasc module are disabled, external access performed. ?1?: the on-chip xasc is enabled and can be accessed. 8 xsscen xssc enable bit ?0?: accesses to the xssc module are disabled, external access performed. ?1?: the on-chip xssc is enabled and can be accessed. 9xi2cen xi 2 c enable bit ?0?: accesses to the xi2c module are disabled, external access performed. ?1?: the on-chip xi 2 c is enabled and can be accessed. 10 xmiscen xbus additional features enable bit ?0?: accesses to the additional miscellaneous features are disabled. ?1?: the additional features are enabled and can be accessed. 11...15 reserved 1514131211109876543210 chipid revid rr bit number bit name function
AN2555 - application note modified registers 24/33 st10f276z5: idchip (f07c h ) esfr reset value: 114xh 3.2.1 hardware impacts none. 3.2.2 software impacts none. 1514131211109876543210 pconf chipid revid rr r bit field function revid st10 module revision identifier (full mask set revision) ?01h?: rev. a (first main revision) ?02h?: rev. b (second main revision) ... ?0fh?: rev. p chipid st10 module identifier ?10d?: st10f269zx identifier (269d = 10dh) ?114h?: st10f276z5 identifier (276d = 114h) pconf peripheral configuration ?00?: (e) enhanced (st10f276z5) ?01?: (b) basic ?10?: (d) dedicated ?11?: reserved
AN2555 - application note new registers 25/33 4 new registers 4.1 xadrs3 register on previous st10 devices, this register was already present but its value was mask programmed. on the st10f276z5 this register has been made available to the user. it makes it possible for the user to configure the window size and start address for the accesses to the xflash and xram2 (the 2 modules are on the same xbus chip select). st10f276z5: xadrs3 (f01c h ) sfr reset value: 800bh the register functionality is the same as that of addrselx register s used for external address range selection, with some limitations: the address window can only be located in the first mbyte of addressable space, that is, in the 00?0000h-0f?ffffh range the window start address must be aligned to a range size boundary 4.1.1 hardware impacts none. 1514131211109876543210 rgsad rgsz rw rw table 10. xadrs3 register bits bit number bit name function 3..0 rgsz range size selection defines the size of the address window. 15..4 rgsad range start address defines the bits a19..a8 of the start address of the address window. table 11. definition of address area bit field rgsz selected window size relevant bit (r) of rgsad selected range start address relevant bit (r) of address (a23 - a0) 0 0 0 0 256 bytes rrrr rrrr rrrr 0000 rrrr rrrr rrrr xxxx xxxx 0 0 0 1 512 bytes rrrr rrrr rrrx 0000 rrrr rrrr rrrx xxxx xxxx ... ... ... ... 1 0 1 0 256 kbytes rrxx xxxx xxxx 0000 rrxx xxxx xxxx xxxx xxxx 1 0 1 1 512 kbytes rxxx xxxx xxxx 0000 rxxx xxxx xxxx xxxx xxxx 1 1 x x reserved
AN2555 - application note new registers 26/33 4.1.2 software impacts none if the xadrs3 register is not reprogrammed: the default value gives access to the entire xflash and xram2 modules. xadrs3 cannot be changed after executing the einit instruction. 4.2 xperemu register this register has been added as a write-only register. st10f276z5: xperemu (eb7e h ) xreg reset value: xxxxh the bit meaning is exactly the sa me as for the xpercon register. 4.2.1 hardware impacts none. 4.2.2 software impacts once the xpen bit of the syscon re gister is set and at least one of the xperiphera ls (except for memories) is activated, the xperemu register must be written with the same content as that of xpercon: this is mandatory to allow the correct emulat ion of the new set of feat ures introduc ed on the x-bus for the new st10 generation. the following instructions must be added inside the initialization routine: if (syscon.xpen && (xpercon & 0x07d3)) then { xperemu = xpercon } of course, xperemu must be prog rammed after xpercon and after syscon, in this way the final configuration for xperipherals is stored in xperemu an d used for the emulat ion hardware setup. 4.3 emulation-dedicated registers a set of four additional registers is implemented for emulation purpos es only. like xperemu, they are write-only registers. xemu0 (00?eb76h) xemu1 (00?eb78h) xemu2 (00?eb7ah) xemu3 (00?eb7ch) these registers are used by emulators. th ey have no user action on the st10f276z5. 4.3.1 hardware impact none. 1514131211109876543 210 ----- xmis cen xi2c en xss cen xas cen xpw men xflas hen xrt cen xram 2en xram 1en can 2en can 1en - - -- -wwwwwwww www
AN2555 - application note new registers 27/33 4.3.2 software impact none. on the st10f269zx, the 00?e800h to 00?ebffh address range was mapped onto external memory but it was recommended to rese rve this space for upward compatibility. 4.4 xmisc register st10f276z5: xmisc (eb46 h ) xreg reset value: 0000h 4.4.1 hardware impact none. 4.4.2 software impact none. on the st10f269zx, the can clock is the cpu clock but it is divided by 2 when calculating the time quantum. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - - vregoff canck2 canpar adcmux ------------ rw rw rw rw bit number bit name function 0 adcmux port1l adc channels enable ?0?: analog inputs on port p5.y can be converted (default configuration) ?1?: analog inputs on port p1.z can be converted. only 8 channels can be managed 1canpar can parallel mode selection ?0?: can2 is mapped on p4.4/p4.7, while can1 is mapped on p4.5/p4.6 ?1?: can1 and can2 are mapped in para llel on p4.5/p4.6. this is effective only if both can1 and can2 are enabled by setting the can1en and can2en bits in the xpercon register. if can1 is disabled, can2 remains on p4.4/p4.7 even if the canpar bit is set. 2 canck2 can clock divider by 2 disable ?0?: clock provided to can modules is cpu clock divided by 2 (mandatory when f cpu is higher than 40 mhz) ?1?: clock provided to can modules is directly cpu clock 3vregoff main voltage regulator disable in power-down mode ?0?: default value after reset and when power down is not used ?1?: main regulator is turned off when power-down mode is entered 4...15 reserved
AN2555 - application note electrical characteristics 28/33 5 electrical characteristics 5.1 dc characteristics 5.1.1 absolute maximum ratings they are the same. 5.1.2 overview of the dc characteristics the pads of the st10f276z5 have been redesigned according to the new technology and therefore the characteristics are different. user should verify the dc characteristics. ta b l e 1 2 lists the parameters that might be impacted most. table 12. dc characteristics parameter symbol st10f269zx limit values st10f276z5 limit values unit min. max. min. max. input low volt- age v il sr v ils sr -0.5 -0.5 0.2 v dd - 0.1 2.0, special thresholds -0.3 -0.3 0.8 0.3 v dd v input low voltage (rstin , ea, nmi, and rpd) v il1 sr n.a. n.a. -0.3 0.3 v dd v input low voltage (xtal1 and xtal3) v il2 sr -0.3 0.3 v dd v input high voltage v ih sr v ihs sr 0.2 v dd + 0.9 0.8 v dd - 0.2 v dd + 0.5 v dd + 0.5, special threshold 2.0 0.7 v dd v dd + 0.3 v dd + 0.3 v input high voltage (rstin , ea, nmi, and rpd) v ih1 sr 0.2 v dd + 0.9 0.8 v dd - 0.2 v dd + 0.5 v dd + 0.5, special threshold 2 0.7 v dd v dd + 0.3 v dd + 0.3 v input high voltage xtal1 v ih2 sr 0.7 v dd v dd + 0.5 0.7 v dd v dd + 0.3 v input hysteresis hys n.a. 250, special threshold -400 750 700 1400 mv input hysteresis rstin , ea , nmi v hys1 cc 750 1400 mv output low voltage v ol cc port0, port1, port 4, ale, rd , wr , bhe , clkout, rstout 0.45 / i ol = 2.4ma port6, ale, clkout, wr , ready, bhe , rd , rstout , rstin 0.4 / i ol = 8ma 0.05 / i ol = 1ma v
AN2555 - application note electrical characteristics 29/33 5.2 ac characteristics at 40 mhz as the technology is different between the two devices, the i/os also present some differences in the ac behavior. ta b l e 1 3 and ta b l e 1 4 list all the timing differences. please check carefully your design for possible impact. 5.2.1 external memory bus timings note that for high cpu clock frequencies above 40 mhz (when using the st10f276z5q3), some numbers in the timing formulas become zero or negative, that in most of the cases is not acceptable or not meaningful at all. in these cases, it is necessary to reduce the speed of the bus setting properly t a (ale extension), t c (memory cycle time wait-states) and t f (memory tri-state time). output low voltage (all other) v ol1 cc ? 0.45 / i ol = 1.6ma ? 0.4 / i ol = 4 ma 0.05 / i ol = 0,5 ma v output high voltage v oh cc 0.9v dd / i oh = -0.5 ma 2.4 / i oh = -2.4 ma port0, port1, port 4, ale, rd , wr , bhe , clkout, rstout v dd - 0.8 / i oh = -8 ma v dd -0.08 / i oh = -1 ma port6, ale, clkout, wr , ready, bhe , rd , rstout , rstin v output high voltage (all other) v oh1 cc 0.9v dd / i oh = -0.25 ma 2.4 / i oh = -1.6 ma ?v dd - 0.8 / i oh = -4 ma v dd -0.08 / i oh = -0.5 ma ?v input leakage current (port5) i oz1 cc ? 200 ? 200 na input leakage current (all other) i oz2 cc ?1? 0.5ua input leakage current (p2.0) i oz3 cc ?-? -0.5 +1 ua input leakage current (rpd) i oz4 cc ?-? 3ua overload cur- rent (p2.0) i ov2 cc ?-? -1 +5 ma table 12. dc characteristics parameter symbol st10f269zx limit values st10f276z5 limit values unit min. max. min. max.
AN2555 - application note electrical characteristics 30/33 multiplexed bus demultiplexed bus table 13. multiplexed bus timings (ns) symbol parameter st10f269zx st10f276z5 st10f269zx f cpu = 40mhz st10f276z5 f cpu = 40mhz min. max. min. max. min. max. min. max. t 6 cc address setup to ale tcl - 10.5 + t a - tcl - 11 + t a -2 + t a - 1.5 + t a - t 16 sr ale low to valid data in - 3 tcl - 19 + t a + t c - 3 tcl - 20 + t a + t c 18.5 + t a + t c - 17.5 + t a + t c - t 17 sr address/unlatche d cs to valid data in - 4 tcl - 28 + 2t a + t c - 4 tcl - 30 + 2t a + t c 22 + 2t a + t c - 20 + 2t a + t c - t 39 sr latched cs low to valid data in - 3 tcl - 19 + 2t a + t c - 3 tcl - 21 + 2t a + t c 18.5 + 2t a + t c - 16.5 + 2t a + t c - t 44 cc address float after rdcs , wrcs (with rw delay) -0-1.5-0-1.5 t 45 cc address float after rdcs , wrcs (no rw delay) -tcl- tcl + 1.5 -12.5- 14 table 14. multiplexed bus timings symbol parameter st10f269zx st10f276z5 st10f269zx f cpu = 40 mhz st10f276z5 f cpu = 40 mhz min. max. min. max. min. max. min. max. t 6 cc address setup to ale tcl - 10.5 + t a - tcl - 11 + t a -2 + t a - 1.5 + t a - t 80 cc address/unlatc hed cs setup to rd , wr (with rw delay) -2 tcl - 8.5 + 2t a -2 tcl - 12.5 + 2t a 16.5 + 2t a - 12.5 + 2t a - t 81 cc address/unlatc hed cs setup to rd , wr (no rw delay) - tcl - 8.5 + 2t a - tcl - 12 + 2t a 4 + 2t a - 0.5 + 2t a - t 16 sr ale low to valid data in -3 tcl - 19 + t a + t c -3 tcl - 20 + t a + t c 18.5 + t a + t c - 17.5 + t a + t c - t 17 sr address/unlatc hed cs to valid data in -4 tcl - 28 + 2t a + t c -4 tcl - 30 + 2t a + t c 22 + 2t a + t c - 20 + 2t a + t c -
AN2555 - application note electrical characteristics 31/33 5.2.2 hi-speed synchronous se rial interface (ssc) the maximum baudrate of the ssc in the st10f276z5 is 8 mbaud whereas it is of 10 in the st10f269zx. for cpu frequencies strictly higher than 32 mhz, the minimum value of the sscbr register (prescaler value) must not be lower than 2. t 28 cc address/unlatc hed cs hold after rd , wr 0 (no t f ) -5 + t f (t f > 0) -0 + t f -0 (no t f ) -5 + t f (t f > 0) -0 + t f - t 39 sr latched cs low to valid data in -3 tcl - 19 + 2t a + t c -3 tcl - 21 + 2t a + t c 18.5 + 2t a + t c - 16.5 + 2t a + t c - t 82 cc address setup to rdcs , wrcs (with rw delay) 2 tcl - 10.5 + 2t a -2 tcl - 11 + 2t a - 14.5 + 2t a - 14 + 2t a - table 14. multiplexed bus timings (continued) symbol parameter st10f269zx st10f276z5 st10f269zx f cpu = 40 mhz st10f276z5 f cpu = 40 mhz min. max. min. max. min. max. min. max.
AN2555 - application note revision history 32/33 6 revision history table 15. revision history date revision changes 06-july-2007 1 initial release
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