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cypress semiconductor corporation 198 champion court san jose , ca 95134 - 1709 408 - 943 - 2600 document number: 002 - 14781 rev. *b revised july 1, 2016 the following document contains information on cypress products. although the document is marked with the name broadcom , the company that originally developed the specification, cypress will continue to offer these pr oducts to new and existing customers. continuity of specifications there is no change to this document as a result of offering the device as a cypress product. any changes that have been made are the result of normal document improvements and are noted in the document history page, where supported. future revisions will occur when appropriate, and changes will be noted in a document history page. continuity of ordering part numbers cypress continues to support existing part numbers. to order these products , please use only the ordering part numbers listed in this document. for more information please visit our website at www .cypress.com or contact your local sales office for additional information about cypress pro ducts and services. our customers cypress is for true innovators C in companies both large and small. our customers are smart, aggressive, out - of - the - box thinkers who design and develop game - changing products that revolutionize their industries or create n ew industries with products and solutions that nobody ever thought of before. about cypress founded in 1982, cypress is the leader in advanced embedded system solutions for the worlds most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. cypresss programmable systems - on - chip, general - purpose microcontrollers, analog ics, wireless and usb - based connectivity solutions and reliable, high - performance memories help engineers design differentiated pro ducts and get them to market first. cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators and out - of - the - box thinkers to disrupt markets and create new product categories in record tim e. to learn more, go to www.cypress.com .
43364-ds102-r 5300 california avenue ? irvine, ca 92617 ? phone: 949-926-5000 ? fax: 949-926-5203 october 5, 2015 preliminary data sheet bcm43364 single-chip i eee 802.11 b/g/n mac/baseband/radio figure 1: bcm43364 system block diagram general description features the broadcom ? bcm43364 is a highly integrated single-chip solution and offers the lowest rbom in the industry for internet of things (iot) and a wide range of other portable devices. the chip includes a 2.4 ghz wlan ieee 802.11 b/g/n mac/baseband/ radio. in addition, it integrates a power amplifier (pa) that meets the output power requirements of most handheld systems, a low-noise amplifier (lna) for best-in-class receiver sensitivity, and an internal transmit/receive (itr) rf switch, further reducing the overall solution cost and printed circuit board area. the wlan host interface supports gspi and sdio v2.0 modes, providing a raw data transfer rate up to 200 mbps when operating in 4-bit mode at a 50 mhz bus frequency. using advanced design techniques and process technology to reduce active and idle power, the bcm43364 is designed to address the needs of highly mobile devices that require minimal power consumption and compact size. it includes a power management unit that simplifies the system power topology while maximizing battery life. ieee 802.11x key features ? single-band 2.4 ghz ieee 802.11b/g/n. ? support for 2.4 ghz broadcom turboqam ? data rates (256-qam) and 20 mhz channel bandwidth. ? integrated itr switch supports a single 2.4 ghz antenna. ? supports explicit ieee 802.11n transmit beamforming. ? tx and rx low-density parity check (ldpc) support for improved range and power efficiency. ? supports standard sdio v2.0 and gspi host interfaces. ? supports space-time block coding (stbc) in the receiver. ? integrated arm cortex-m3 processor and on-chip memory for complete wlan subsystem functionality, minimizing the need to wake up the applications processor for standard wlan functions. this allows for further minimization of power consumption, while maintaining the ability to field-upgrade with future features. on-chip memory includes 512 kb sram and 640 kb rom. ? onedriver ? software architecture for easy migration from existing embedded wlan. vddio vbat 2.4 ghz wlan tx/rx wlan host i/f wl_reg_on sdio*/spi wl_host_wake bpf clk_req ref_clk (19.2, 26, or 37.4 mhz) bcm43364
broadcom corporation 5300 california avenue irvine, ca 92617 ? 2015 by broadcom corporation all rights reserved printed in the u.s.a. broadcom ? , the pulse logo, connecting everything ? , the connecting everything logo, onedriver ? , and turboqam ? are among the trademarks of broadcom corporation and/or its affiliates in the united states, certain other countries and/or the eu. any other trademarks or trade names mentioned are the property of their respective owners. this data sheet (including, without limitation, the broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high-risk application. broadcom provides this data sheet ?as-is,? without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without limitation, the implied warranties of merchantability, fitnes s for a particular purpose, and non- infringement. features general features ? support diversity antenna. ? supports a battery voltage range from 3.0v to 4.8v with an internal switching regulator. ? programmable dynamic power management. ? 4 kbit one-time programmable (otp) memory for storing board parameters. ? can be routed on low-cost 1-x-1 pcb stack-ups. ? 74-ball wlbga package (4.87 mm 2.87 mm, 0.4 mm pitch). ? security: ? wpa and wpa2 (personal) support for powerful encryption and authentication. ? aes in wlan hardware for faster data encryption and ieee 802.11i compatibility. ? reference wlan subsystem provides cisco compatible extensions (ccx, ccx 2.0, ccx 3.0, ccx 4.0, ccx 5.0). ? reference wlan subsystem provides wi-fi protected setup (wps). ? worldwide regulatory support: global products supported with worldwide homologated design.
revision history bcm43364 preliminary data sheet broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 3 broadcom confidential revision history revision date change description 43364-ds102-r 10/05/15 updated: ? table 9: ?wlbga signal descriptions,? on page 49 ? table 12: ?i/o states,? on page 53 43364-ds101-r 08/06/15 updated: ? figure 3: ?typical power topology (1 of 2),? on page 14. ? figure 4: ?typical power topology (2 of 2),? on page 15. ? figure 22: ?74-ball wlbga ball map (bottom view),? on page 44. ? table 7: ?bcm43364 wlbga ball list ? ordered by ball number,? on page 45. ? table 8: ?bcm43364 wlbga ball list ? ordered by ball name,? on page 48. ? table 9: ?wlbga signal descriptions,? on page 49. ? table 12: ?i/o states,? on page 53. ? table 18: ?wlan 2.4 ghz receiver performance specifications,? on page 59. ? table 19: ?wlan 2.4 ghz transmitter performance specifications,? on page 62. ? table 25: ?2.4 ghz mode wlan power consumption,? on page 70. 43364-ds100-r 12/08/14 initial release
table of contents bcm43364 preliminary data sheet broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 4 broadcom confidential table of contents about this document ............................................................................................................................... ... 9 purpose and audience ........................................................................................................... ................. 9 acronyms and abbreviations..................................................................................................... .............. 9 document conventions ........................................................................................................... ................ 9 technical support ............................................................................................................................... ......... 9 section 1: overview .......................................................................................................... 10 overview ............................................................................................................................... ....................... 10 features ............................................................................................................................... ........................ 11 standards compliance ............................................................................................................................... 12 section 2: power supplies and power management ..................................................... 13 power supply topology ............................................................................................................................. 13 bcm43364 pmu features .......................................................................................................................... 13 wlan power management ........................................................................................................................ 16 pmu sequencing ............................................................................................................................... ......... 17 power-off shutdown ............................................................................................................................... ... 18 power-up/power-down/reset circuits ..................................................................................................... 18 section 3: frequency references.................................................................................... 19 crystal interface and clock generation ................................................................................................... 19 tcxo ............................................................................................................................... ............................. 20 external 32.768 khz low-power oscillator .............................................................................................. 21 section 4: wlan system interfaces................................................................................ 22 sdio v2.0 ............................................................................................................................... ...................... 22 sdio pin descriptions.......................................................................................................... ................. 22 generic spi mode ............................................................................................................................... ........ 23 spi protocol ................................................................................................................... ....................... 24 command structure .............................................................................................................. ......... 26 write.......................................................................................................................... ..................... 26 write/read ..................................................................................................................... ................ 26 read........................................................................................................................... .................... 26 status ......................................................................................................................... .................... 27 gspi host-device handshake..................................................................................................... .......... 29 boot-up sequence ............................................................................................................... ................. 29 section 5: wireless lan mac and phy .......................................................................... 32 mac features ............................................................................................................................... .............. 32 mac description ................................................................................................................ ................... 32 psm ............................................................................................................................ ................... 33
table of contents bcm43364 preliminary data sheet broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 5 broadcom confidential wep ............................................................................................................................ ................... 34 txe ............................................................................................................................ .................... 34 rxe............................................................................................................................ .................... 34 ifs............................................................................................................................ ...................... 35 tsf ............................................................................................................................ .................... 35 nav............................................................................................................................ .................... 35 mac-phy interface.............................................................................................................. .......... 35 phy description ............................................................................................................................... .......... 36 phy features................................................................................................................... ..................... 36 section 6: wlan radio subsystem ................................................................................ 38 receive path ............................................................................................................................... ................ 39 transmit path ............................................................................................................................... ............... 39 calibration ............................................................................................................................... .................... 39 section 7: cpu and global functions ............................................................................. 40 wlan cpu and memory subsystem ........................................................................................................ 40 one-time programmable memory ............................................................................................................ 40 gpio interface ............................................................................................................................... .............. 41 external coexistence interface ................................................................................................................. 41 2-wire coexistence ............................................................................................................. .................. 41 3-wire and 4-wire coexistence interfaces....................................................................................... ..... 42 jtag interface ............................................................................................................................... ............ 43 uart interface ............................................................................................................................... ............ 43 section 8: pinout and signal descriptions ..................................................................... 44 ball map ............................................................................................................................... ........................ 44 wlbga ball list in ball number order with x-y coordinates ............................................................... 45 wlbga ball list ordered by ball name .................................................................................................. 48 signal descriptions ............................................................................................................................... ..... 49 wlan gpio signals and strapping options ........................................................................................... 52 chip debug options ............................................................................................................................... .... 52 i/o states ............................................................................................................................... ...................... 53 section 9: dc characteristics .......................................................................................... 55 absolute maximum ratings ...................................................................................................................... 55 environmental ratings .............................................................................................................................. 5 6 electrostatic discharge specifications .................................................................................................... 56 recommended operating conditions and dc characteristics ............................................................. 56 section 10: wlan rf specifications .............................................................................. 58 2.4 ghz band general rf specifications ................................................................................................. 59 wlan 2.4 ghz receiver performance specifications ............................................................................ 59
table of contents bcm43364 preliminary data sheet broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 6 broadcom confidential wlan 2.4 ghz transmitter performance specifications ....................................................................... 62 general spurious emissions specifications ........................................................................................... 64 section 11: internal regulator electrical specifications ............................................... 65 core buck switching regulator ................................................................................................................ 65 3.3v ldo (ldo3p3) ............................................................................................................................... ..... 67 cldo ............................................................................................................................... ............................ 68 lnldo ............................................................................................................................... .......................... 69 section 12: system power consumption........................................................................ 70 wlan current consumption ..................................................................................................................... 70 2.4 ghz mode ................................................................................................................... .................... 70 section 13: interface timing and ac characteristics .................................................... 71 sdio default mode timing ........................................................................................................................ 71 sdio high-speed mode timing ................................................................................................................. 73 gspi signal timing ............................................................................................................................... ...... 74 jtag timing ............................................................................................................................... ................ 75 section 14: power-up sequence and timing ................................................................. 76 sequencing of reset and regulator control signals ............................................................................. 76 control signal timing diagrams................................................................................................. ........... 76 section 15: package information ..................................................................................... 77 package thermal characteristics ............................................................................................................. 77 junction temperature estimation and psi versus theta jc ................................................................... 77 section 16: mechanical information ................................................................................ 78 section 17: ordering information .................................................................................... 80
list of figures bcm43364 preliminary data sheet broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 7 broadcom confidential list of figures figure 1: bcm43364 system block diagram ......................................................................................... ........... 1 figure 2: bcm43364 block diagram ................................................................................................ ............... 11 figure 3: typical power topology (1 of 2) ....................................................................................... ................ 14 figure 4: typical power topology (2 of 2) ....................................................................................... ................ 15 figure 5: recommended oscillator configuration .................................................................................. ......... 19 figure 6: recommended circuit to use with an external dedicated tcxo .................................................... 20 figure 7: signal connections to sdio host (sd 4-bit mode) ....................................................................... ... 22 figure 8: signal connections to sdio host (sd 1-bit mode) ....................................................................... ... 23 figure 9: signal connections to sdio host (gspi mode) ........................................................................... .... 23 figure 10: gspi write protocol .................................................................................................. ...................... 24 figure 11: gspi read protocol ................................................................................................... ..................... 25 figure 12: gspi command structure............................................................................................... ................ 26 figure 13: gspi signal timing without status.................................................................................... ............. 27 figure 14: gspi signal timing with status (response delay = 0).................................................................. .28 figure 15: wlan boot-up sequence ................................................................................................ .............. 31 figure 16: wlan mac architecture ................................................................................................ ................ 33 figure 17: wlan phy block diagram............................................................................................... .............. 37 figure 18: radio functional block diagram ....................................................................................... ............. 38 figure 19: 2-wire coexistence interface to an lte ic ............................................................................ ........ 41 figure 20: 3-wire coexistence interface to an lte ic ............................................................................ ........ 42 figure 21: 4-wire coexistence interface to an lte ic ............................................................................ ........ 42 figure 22: 74-ball wlbga ball map (bottom view) ................................................................................. ....... 44 figure 23: rf port location..................................................................................................... ........................ 58 figure 24: sdio bus timing (default mode) ....................................................................................... ............ 71 figure 25: sdio bus timing (high-speed mode).................................................................................... ........ 73 figure 26: gspi timing .......................................................................................................... .......................... 74 figure 27: wlan = on ............................................................................................................ ........................ 76 figure 28: wlan = off ........................................................................................................... ....................... 76 figure 29: 74-ball wlbga mechanical information ................................................................................. ....... 78 figure 30: wlbga package keep-out areas?top view with the bumps facing down .............................. 79
list of tables bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 8 list of tables table 1: power-up/power-down/reset control signals.............................................................................. .... 18 table 2: crystal oscillator and external clock requirements and performance............................................. 20 table 3: external 32.768 khz sleep-clock specifications ......................................................................... ...... 21 table 4: sdio pin descriptions .................................................................................................. ..................... 22 table 5: gspi status field details .............................................................................................. ..................... 28 table 6: gspi registers ......................................................................................................... .......................... 29 table 7: bcm43364 wlbga ball list ? ordered by ball number................................................................. 45 table 8: bcm43364 wlbga ball list ? ordered by ball name .................................................................... 48 table 9: wlbga signal descriptions .............................................................................................. ................ 49 table 10: gpio functions and strapping options.................................................................................. ......... 52 table 11: chip debug options.................................................................................................... ..................... 52 table 12: i/o states ............................................................................................................ ............................. 53 table 13: absolute maximum ratings .............................................................................................. ............... 55 table 14: environmental ratings ................................................................................................. .................... 56 table 15: esd specifications .................................................................................................... ...................... 56 table 16: recommended operating conditions and dc characteristics ........................................................ 56 table 17: 2.4 ghz band general rf specifications................................................................................ ........ 59 table 18: wlan 2.4 ghz receiver performance specifications .................................................................... 59 table 19: wlan 2.4 ghz transmitter performance specifications ................................................................ 62 table 20: general spurious emissions specifications ............................................................................. ....... 64 table 21: core buck switching regulator (cbuck) specifications ................................................................ 65 table 22: ldo3p3 specifications ................................................................................................. ................... 67 table 23: cldo specifications ................................................................................................... ..................... 68 table 24: lnldo specifications .................................................................................................. .................... 69 table 25: 2.4 ghz mode wlan power consumption ................................................................................... .. 70 table 26: sdio bus timing parameters (default mode)............................................................................ .... 72 table 27: sdio bus timing parameters (high-speed mode)........................................................................ 7 3 table 28: gspi timing parameters ................................................................................................ .................. 74 table 29: jtag timing characteristics ........................................................................................... ................ 75 table 30: package thermal characteristics ....................................................................................... ............. 77
about this document broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 9 bcm43364 preliminary data sheet broadcom confidential about this document purpose and audience this document provides details of the functional, operational, and electrical characteristics of the broadcom ? bcm43364. it is intended for hardware design, application, and oem engineers. acronyms and abbreviations in most cases, acronyms and abbreviations are defined on first use. for a comprehensive list of acronyms and other terms used in broadcom documents, go to: http://www.broadcom.com/press/glossary.php . document conventions the following conventions may be used in this document: technical support broadcom provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, pcb layout information, and software updates through its customer support portal ( https://support.broadcom.com ). for a csp account, contact your sales or engineering support representative. in addition, broadcom provides other product support through its downloads and support site ( http://www.broadcom.com/support/ ). convention description bold user input and actions: for example, type exit , click ok, press alt+c monospace code: #include html:

command line commands and parameters: wl [-l] < > placeholders for required elements: enter your or wl [ ] indicates optional command-line parameters: wl [-l] indicates bit and byte ranges (inclusive): [0:3] or [7:0]
overview bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 10 section 1: overview overview the broadcom ? bcm43364 provides the highest level of integration for iot and wireless automation system, with integrated ieee 802.11 b/g/n. it provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. the bcm43364 is designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation. figure 2 on page 11 shows the interconnection of all the major physical blocks in the bcm43364 and their associated external interfaces, which are described in greater detail in subsequent sections.
features bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 11 figure 2: bcm43364 block diagram features the bcm43364 supports the following wlan features: ? ieee 802.11b/g/n single-band radio with an internal power amplifier, lna, and t/r switch ? on-chip wlan driver execution capable of supporting ieee 802.11 functionality ? wlan host interface options: ? sdio v2.0, including default and high-speed timing. ? gspi?up to a 50 mhz clock rate common and radio digital swreg ldox2 lpo xtal osc. bpf wlan sdio gspi jtag* arm cm3 backplane bt- wlan eci wdt otp gpio uart jtag* ram rom pmu control mac lnpphy radio ahb bus matrix cortex m3 etm jtag* sdp ram rom patch interctrl dma bus arb arm ip wd timer sw timer gpio ctrl apb sdio or gspi debug ieee 802.11a/b/g/n gpio uart 2.4 ghz 2.4 ghz pa lna power supply sleep clk xtal ahb to apb bridge ahb supported over sdio jtag supported over sdio por wl_reg_on
standards compliance bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 12 standards compliance the bcm43364 supports the following standards: ? ieee 802.11n?handheld device class (section 11) ? ieee 802.11b ? ieee 802.11g ? ieee 802.11d ? ieee 802.11h ? ieee 802.11i the bcm43364 will support the following future drafts/standards: ? ieee 802.11r ? fast roaming (between aps) ? ieee 802.11k ? resource management ? ieee 802.11w ? secure management frames ? ieee 802.11 extensions: ? ieee 802.11e qos enhancements (as per the wmm specification is already supported) ? ieee 802.11i mac enhancements ? ieee 802.11r fast roaming support ? ieee 802.11k radio resource measurement the bcm43364 supports the following security features and proprietary protocols: ? security: ?wep ? wpa personal ? wpa2 personal ?wmm ? wmm-ps (u-apsd) ?wmm-sa ? wapi ? aes (hardware accelerator) ? tkip (host-computed) ? ckip (sw support) ? proprietary protocols: ? ccxv2 ? ccxv3 ? ccxv4 ? ccxv5 ? ieee 802.15.2 coexistence compliance ? on silicon solution compliant with ieee 3-wire requirements.
power supplies and power management bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 13 section 2: power supplies and power management power supply topology one buck regulator, multiple ldo regulators, and a power management unit (pmu) are integrated into the bcm43364. all regulators are programmable via the pmu to simplify the power supply. a single vbat (3.0v to 4.8v dc maximum) and vddio supply (1.8v to 3.3v) can be used, with all additional voltages being provided by the regulators in the bcm43364. the wl_reg_on control signal is used to power up the regulators and take the respective circuit blocks out of reset. the cbuck cldo and lnldo power up when any of the reset signals are deasserted. all regulators are powered down only when wl_reg_on is deasserted. the cldo and lnldo can be turned on and off based on the dynamic demands of the digital baseband. the bcm43364 allows for an extremely low power-consumption mode by completely shutting down the cbuck, cldo, and lnldo regulators. when in this state, lpldo1 provides the bcm43364 with all required voltage, further reducing leakage currents. bcm43364 pmu features the pmu supports the following: ? vbat to 1.35vout (170 ma nominal, 370 ma maximum) core-buck (cbuck) switching regulator ? vbat to 3.3vout (250 ma nominal, 450 ma maximum 800 ma peak maximum) ldo3p3 ? 1.35v to 1.2vout (100 ma nominal, 150 ma maximum) lnldo ? 1.35v to 1.2vout (80 ma nominal, 200 ma maximum) cldo with bypass mode for deep sleep ? additional internal ldos (not externally accessible) ? pmu internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode. figure 3 on page 14 and figure 4 on page 15 show the typical power topology of the bcm43364. note: vbat should be connected to the ldo_vddbat5v and sr_vddbat5v pins of the device. note: vddio should be connected to the sys_vddio and wcc_vddio pins of the device.
broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 14 bcm43364 pmu features broadcom confidential bcm43364 preliminary data sheet figure 3: typical power topology (1 of 2) mini pmu wl rf?logen wl rf?rx lna wl rf?adc ref wl rf?tx wl rf?afe and tia wl rf?xtal internal vcoldo 80 ma (nmos) internal rxldo 10 ma (nmos) internal adcldo 10 ma (nmos) internal txldo 80 ma (pmos) internal afeldo 80 ma (nmos) lnldo (100 ma) 1.2v 1.2v 1.2v 1.2v cl ldo peak: 200 ma avg: 80 ma (bypass in deep- sleep) core buck regulator peak: 370 ma avg: 170 ma lpldo1 (5 ma) 2.2 uh 0603 1.35v 1 . 1 v 1.2v 1.2v sr_vddbat5v vdd1p35 ldo_vdd_1p5 4.7 uf 0402 sr_pvss sr_vlx o_wl_resetb wl_reg_on wcc_vddio wcc_vddio (40 ma) pmu_vss gnd sr_vbat5v vbat int_sr_vbat bcm43364 1.2v vbat: operational: 2.4v?4.8v performance: 3.0v?4.8v absolute maximum: 5.5v vddio operational: 1.8v?3.3v 600 @ 100 mhz 2.2 uf 0402 0.1 uf 0201 wlrf_xtal_ vdd1p2 wl rf?tx mixer and pa wl rf?rfpll pfd and mmd 10 ma average, > 10 ma at start-up vout_lnldo 2.2 uf 0402 vddc1 vddc2 (avs) vout_cldo 1.3v, 1.2v, or 0.95v wlan/clb/top, always on wl otp wl digital and phy wl vddm (sroms & aos) mini pmu is placed in wl radio vbat supply ball supply bump/pad ground ball ground bump/pad external to chip power switch no power switch no dedicated power switch, but internal power- down modes and block-specific power switches (320 ma) sw1 wlan reset balls
broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 15 bcm43364 pmu features broadcom confidential bcm43364 preliminary data sheet figure 4: typical power topology (2 of 2) bcm43364 1.8v, 2.5v, and 3.3v 4.7 uf 0402 ldo3p3 with back-power protection (peak 450-800 ma 200 ma average) vout_3p3 3.3v ldo_ vddbat5v vbat wlrf_pa_vdd 2.5v cap-less lnldo (10 ma) wl rf?pa (2.4 ghz) wl otp 3.3v wl rf?adc, afe, logen, lna, nmos mini-pmu ldos 6.4 ma 480 to 800 ma supply ball external to chip power switch no power switch no dedicated power switch, but internal power- down modes and block-specific power switches 1 uf 0201 wl bbpll/dfll vout_3p3 6.4 ma
wlan power management bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 16 wlan power management the bcm43364 has been designed with the stringent power consumption requirements of mobile devices in mind. all areas of the chip design are optimized to minimize power consumption. silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. additionally, the bcm43364 integrated ram is a high volatile memory with dynamic clock control. the dominant supply current consumed by the ram is leakage current only. additionally, the bcm43364 includes an advanced wlan power management unit (pmu) sequencer. the pmu sequencer provides significant power savings by putting the bcm43364 into various power management states appropriate to the operating environment and the activities that are being performed. the power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. power-up sequences are fully programmable. configurable, free-running counters (running at the 32.768 khz lpo clock) in the pmu sequencer are used to turn on/turn off individual regulators and power switches. clock speeds are dynamically changed (or gated altogether) for the current mode. slower clock speeds are used wherever possible. the bcm43364 wlan power states are described as follows: ? active mode: all wlan blocks in the bcm43364 are powered up and fully functional with active carrier sensing and frame transmission and receiving. all required regulators are enabled and put in the most efficient mode based on the load current. clock speeds are dynamically adjusted by the pmu sequencer. ? doze mode: the radio, analog domains, and most of the linear regulators are powered down. the rest of the bcm43364 remains powered up in an idle state. all main clocks (pll, crystal oscillator) are shut down to reduce active power to the minimum. the 32.768 khz lpo clock is available only for the pmu sequencer. this condition is necessary to allow the pmu sequencer to wake up the chip and transition to active mode. in doze mode, the primary power consumed is due to leakage current. ? deep-sleep mode: most of the chip, including analog and digital domains, and most of the regulators are powered off. logic states in the digital core are saved and preserved to retention memory in the always-on domain before the digital core is powered off. to avoid lengthy hardware reinitialization, the logic states in the digital core are restored to their pre-deep-sleep settings when a wake-up event is triggered by an external interrupt, a host resume through the sdio bus, or by the pmu timers. ? power-down mode: the bcm43364 is effectively powered off by shutting down all internal regulators. the chip is brought out of this mode by external logic re-enabling the internal regulators.
pmu sequencing bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 17 pmu sequencing the pmu sequencer is used to minimize system power consumption. it enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable them. resource requests can derive from several sources: clock requests from cores, the minimum resources defined in the resourcemin register, and the resources requested by any active resource request timers. the pmu sequencer maps clock requests into a set of resources required to produce the requested clocks. each resource is in one of the following four states: ? enabled ?disabled ? transition_on ? transition_off the timer value is 0 when the resource is enabled or disabled and nonzero during state transition. the timer is loaded with the time_on or time_off value of the resource when the pmu determines that the resource must be enabled or disabled. that timer decrements on each 32.768 khz pmu clock. when it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. if the time_on value is 0, the resource can transition immediately from disabled to enabled. similarly, a time_off value of 0 indicates that the resource can transition immediately from enabled to disabled. the terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. during each clock cycle, the pmu sequencer performs the following actions: ? computes the required resource set based on requests and the resource dependency table. ? decrements all timers whose values are nonzero. if a timer reaches 0, the pmu clears the resourcepending bit for the resource and inverts the resourcestate bit. ? compares the request with the current resource status and determines which resources must be enabled or disabled. ? initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents. ? initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
power-off shutdown bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 18 power-off shutdown the bcm43364 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices in the system, remain operational. when the bcm43364 is not needed in the system, vddio_rf and vddc are shut down while vddio remains powered. this allows the bcm43364 to be effectively off while keeping the i/o pins powered so that they do not draw extra current from any other devices connected to the i/o. during a low-power shutdown state, provided vddio remains applied to the bcm43364, all outputs are tristated, and most input signals are disabled. input voltages must remain within the limits defined for normal operation. this is done to prevent current paths or create loading on any digital signals in the system, and enables the bcm43364 to be fully integrated in an embedded device and to take full advantage of the lowest power-savings modes. when the bcm43364 is powered on from this state, it is the same as a normal power-up, and the device does not retain any information about its state from before it was powered down. power-up/power-down/reset circuits the bcm43364 has two signals (see table 1 ) that enable or disable the wlan circuits and the internal regulator blocks, allowing the host to control power consumption. for timing diagrams of these signals and the required power-up sequences, see section 14: ?power-up sequence and timing,? on page 76 . table 1: power-up/power-down/reset control signals signal description wl_reg_on this signal is used by the pmu to power-up the wlan section. when this pin is high, the regulators are enabled and the wlan section is out of reset. when this pin is low, the wlan section is in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming.
frequency references bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 19 section 3: frequency references an external crystal is used for generating all radio frequencies and normal operation clocking. as an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (tcxo) signal may be used. no software settings are required to differentiate between the two. in addition, a low-power oscillator (lpo) is provided for lower power mode timing. crystal interface and clock generation the bcm43364 can use an external crystal to provide a frequency reference. the recommended configuration for the crystal oscillator, including all external components, is shown in figure 5 . consult the reference schematics for the latest configuration. figure 5: recommended os cillator configuration the bcm43364 uses a fractional-n synthesizer to generate the radio frequencies, clocks, and data/packet timing so that it can operate using numerous frequency references. the frequency reference can be an external source such as a tcxo or a crystal interfaced directly to the bcm43364. the default frequency reference setting is a 37.4 mhz crystal or tcxo. the signal requirements and characteristics for the crystal interface are shown in table 2 on page 20 . note: although the fractional-n synthesizer can support many reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. contact broadcom for further details. 12 ? 27 pf 12 ? 27 pf wlrf_xtal_xon wlrf_xtal_xop c c r note : resistor value determined by crystal drive level. see reference schematics for details.
tcxo bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 20 tcxo as an alternative to a crystal, an external precision tcxo can be used as the frequency reference, provided that it meets the phase noise requirements listed in table 2 on page 20 . if the tcxo is dedicated to driving the bcm43364, it should be connected to the wlrf_xtal_xop pin through an external capacitor with value ranges from 200 pf to 1000 pf as shown in figure 6 . figure 6: recommended circuit to use with an external dedicated tcxo table 2: crystal oscillator and external clock requirements and performance parameter conditions/notes crystal external frequency reference units min. typ. max. min. typ. max. frequency ? ? 37.4 a ???? mhz crystal load capacitance ? ? 12 ? ? ? ? pf esr ? ? ? 60 ? ? ? ? input impedance (wlrf_xtal_xop) resistive ? ? ? 10k 100k ? ? capacitive ? ? ? ? ? 7 pf wlrf_xtal_xop input voltage ac-coupled analog signal ? ? ? 400 b ? 1260 mv p-p wlrf_xtal_xop input low level dc-coupled digital signal ? ? ? 0 ? 0.2 v wlrf_xtal_xop input high level dc-coupled digital signal ? ? ? 1.0 ? 1.26 v frequency tolerance initial + over temperature ? ?20 ? 20 ?20 ? 20 ppm duty cycle 37.4 mhz clock ? ? ? 40 50 60 % phase noise c, d, e (ieee 802.11 b/g) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?129 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?136 dbc/hz phase noise c, d, e (ieee 802.11n, 2.4 ghz) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?134 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?141 dbc/hz tcxo nc 200 pf ? 1000 pf wlrf_xtal_xop wlrf_xtal_xon
external 32.768 khz low-power oscillator bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 21 external 32.768 khz low-power oscillator the bcm43364 uses a secondary low-frequency sleep clock for low-power mode timing. either the internal low- precision lpo or an external 32.768 khz precision oscillator is required. the internal lpo frequency range is approximately 33 khz 30% over process, voltage, and temperature, which is adequate for some applications. however, one trade-off caused by this wide lpo tolerance is a small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons. whenever possible, the preferred approach is to use a precision external 32.768 khz clock that meets the requirements listed in table 3 on page 21 . phase noise c, d, e (256-qam) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?140 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?147 dbc/hz a. the frequency step size is approximately 80 hz. the bcm43364 does not auto-detect the reference clock frequency; the frequency is specified in the software and/or nvram file. b. to use 256-qam, a 800 mv minimum voltage is required. c. for a clock reference other than 37.4 mhz, 20 log10(f/37.4) db should be added to the limits, where f = the reference clock frequency in mhz. d. phase noise is assumed flat above 100 khz. e. the bcm43364 supports a 26 mhz reference clock sharing option. see the phase noise requirement in the table. note: the bcm43364 will auto-detect the lpo clock. if it senses a clock on the ext_sleep_clk pin, it will use that clock. if it doesn't sense a clock, it will use its own internal lpo. ? to use the internal lpo: tie ext_sleep_clk to ground. do not leave this pin floating. ? to use an external lpo: connect the external 32.768 khz clock to ext_sleep_clk. table 3: external 32.768 khz sleep-clock specifications parameter lpo clock units nominal input frequency 32.768 khz frequency accuracy 200 ppm duty cycle 30?70 % input signal amplitude 200?3300 mv, p-p signal type square wave or sine wave ? input impedance a a. when power is applied or switched off. >100 k ? <5 pf clock jitter <10,000 ppm table 2: crystal oscillator and external clock requirements and performance (cont.) parameter conditions/notes crystal external frequency reference units min. typ. max. min. typ. max.
wlan system interfaces bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 22 section 4: wlan system interfaces sdio v2.0 the bcm43364 wlan section supports sdio version 2.0. for both 1-bit (25 mbps) and 4-bit modes (100 mbps), as well as high speed 4-bit mode (50 mhz clocks?200 mbps). it has the ability to map the interrupt signal on a gpio pin. this out-of-band interrupt signal notifies the host when the wlan device wants to turn on the sdio interface. the ability to force control of the gated clocks from within the wlan chip is also provided. sdio mode is enabled using the strapping option pins. see table 10 on page 52 for details. three functions are supported: ? function 0 standard sdio function. the maximum block size is 32 bytes. ? function 1 backplane function to access the internal system-on-a-chip (soc) address space. the maximum block size is 64 bytes. ? function 2 wlan function for efficient wlan packet transfer through dma. the maximum block size is 512 bytes. sdio pin descriptions figure 7: signal connections to sdio host (sd 4-bit mode) table 4: sdio pin descriptions sd 4-bit mode sd 1-bit mode gspi mode data0 data line 0 data data line do data output data1 data line 1 or interrupt irq interrupt irq interrupt data2 data line 2 nc not used nc not used data3 data line 3 nc not used cs card select clk clock clk clock sclk clock cmd command line cmd command line di data input sd host cmd dat[3:0] clk bcm43364
generic spi mode bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 23 figure 8: signal connections to sdio host (sd 1-bit mode) generic spi mode in addition to the full sdio mode, the bcm43364 includes the option of using the simplified generic spi (gspi) interface/protocol. characteristics of the gspi mode include: ? up to 50 mhz operation ? fixed delays for responses and data from the device ? alignment to host gspi frames (16 or 32 bits) ? up to 2 kb frame size per transfer ? little-endian and big-endian configurations ? a configurable active edge for shifting ? packet transfer through dma for wlan the gspi mode is enabled using the strapping option pins. see table 10 on page 52 for details. figure 9: signal connections to sdio host (gspi mode) sd host cmd clk data irq bcm43364 sd host di sclk do irq cs bcm43364
generic spi mode bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 24 spi protocol the spi protocol supports both 16-bit and 32-bit word operation. byte endianess is supported in both modes. figure 10 and figure 11 on page 25 show the basic write and write/read commands. figure 10: gspi write protocol
generic spi mode bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 25 figure 11: gspi read protocol
generic spi mode bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 26 command structure the gspi command structure is 32 bits. the bit positions and definitions are shown in figure 12 . figure 12: gspi command structure write the host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the cs going low. the following bits are clocked out on the falling edge of the gspi clock. the device samples the data on the active edge. write/read the host reads on the rising edge of the clock requiring data from the device to be made available before the first rising-clock edge of the data. the last clock edge of the fixed delay word can be used to represent the first bit of the following data word. this allows data to be ready for the first clock edge without relying on asynchronous delays. read the read command always follows a separate write to set up the wlan device for a read. this command differs from the write/read command in the following respects: a) chip selects go high between the command/address and the data, and b) the time interval between the command/address is not fixed. 0 10 27 11 packet length - 11bits * address C 17 bits f1 f0 c a function no: 00 C func 0 01 C func 1 10 C func 2 11 C func 3 command : 0 C read 1 C write bcm_spid command structure 28 29 30 31 access : 0 C fixed address 1 C incremental address * 11h0 = 2048 bytes 0 10 27 11 packet length - 11bits * address C 17 bits f1 f0 c a function no: 00 C func 0: all spi-specific registers 01 C func 1: registers and memories belonging to other blocks in the chip (64 bytes max) 10 C func 2: dma channel 1. wlan packets up to 2048 bytes. 11 C func 3: dma channel 2 (optional). packets up to 2048 bytes. command : 0 C read 1 C write bcm_spid command structure 28 29 30 31 access : 0 C fixed address 1 C incremental address * 11h0 = 2048 bytes
generic spi mode bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 27 status the gspi interface supports status notification to the host after a read/write transaction. this status notification provides information about packet errors, protocol errors, available packets in the rx queue, etc. the status information helps reduce the number of interrupts to th e host. the status-reporting feature can be switched off using a register bit, without any timing overhead. the gspi bus timing for read/write transactions with and without status notification are as shown in figure 13 below and figure 14 on page 28 . see table 5 on page 28 for information on status-field details. figure 13: gspi signal timing without status c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits sclk mosi c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso response delay d1 c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits cs c31 c30 c1 c0 d31 d30 d1 d0 c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay d1 c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay d1 write write-read read cs sclk mosi miso cs sclk mosi
generic spi mode bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 28 figure 14: gspi signal timing with status (response delay = 0) table 5: gspi status field details bit name description 0 data not available the requested read data is not available. 1 underflow fifo underflow occurred due to current (f2, f3) read command. 2 overflow fifo overflow occurred due to current (f1, f2, f3) write command. 3 f2 interrupt f2 channel interrupt 5 f2 rx ready f2 fifo is ready to receive data (fifo empty). 7 reserved ? 8 f2 packet available packet is available/ready in f2 tx fifo. 9:19 f2 packet length length of packet available in f2 fifo c31 c0 d31 d1 d0 read data 16*n bits s0 s31 status 32 bits c31 c0 d31 d1 d0 command 32 bits read data 16*n bits s0 s31 status 32 bits c31 s0 c1 c0 d31 s31 d1 d0 command 32 bits write data 16*n bits s1 status 32 bits c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 s0 c1 c0 d31 s31 d1 d0 s1 c31 s0 c1 c0 d31 s31 d1 d0 s1 command 32 bits write write-read read miso cs sclk mosi miso cs sclk mosi miso cs sclk mosi
generic spi mode bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 29 gspi host-device handshake to initiate communication through the gspi after power-up, the host needs to bring up the wlan chip by writing to the wake-up wlan register bit. writing a 1 to this bit will start up the necessary crystals and plls so that the bcm43364 is ready for data transfer. the device can signal an interrupt to the host indicating that the device is awake and ready. this procedure also needs to be followed for waking up the device in sleep mode. the device can interrupt the host using the wlan irq line whenever it has any information to pass to the host. on getting an interrupt, the host needs to read the interrupt and/or status register to determine the cause of the interrupt and then take necessary actions. boot-up sequence after power-up, the gspi host needs to wait 50 ms for the device to be out of reset. for this, the host needs to poll with a read command to f0 address 0x14. address 0x14 contains a predefined bit pattern. as soon as the host gets a response back with the correct register content, it implies that the device has powered up and is out of reset. after that, the host needs to set the wake-up wlan bit (f0 reg 0x00 bit 7). wake-up wlan turns the pll on; however, the pll doesn't lock until the host programs the pll registers to set the crystal frequency. for the first time after power-up, the host needs to wait for the availability of the low-power clock inside the device. once it is available, the host needs to write to a pmu register to set the crystal frequency. this will turn on the pll. after the pll is locked, the chipactive interrupt is issued to the host. this indicates device awake/ ready status. see table 6 for information on gspi registers. in table 6 , the following notation is used for register access: ? r: readable from host and cpu ? w: writable from host ? u: writable from cpu table 6: gspi registers address register bit access default description x0000 word length 0 r/w/u 0 0: 16-bit word length 1: 32-bit word length endianess 1 r/w/u 0 0: little endian 1: big endian high-speed mode 4 r/w/u 1 0: normal mode. sample on spiclk rising edge, output on falling edge. 1: high-speed mode. sample and output on rising edge of spiclk (default). interrupt polarity 5 r/w/u 1 0: interrupt active polarity is low. 1: interrupt active polarity is high (default). wake-up 7 r/w 0 a write of 1 denotes a wake-up command from host to device. this will be followed by an f2 interrupt from the gspi device to host, indicating device awake status.
generic spi mode bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 30 figure 15 on page 31 shows the wlan boot-up sequence from power-up to firmware download, including the initial device power-on reset (por) evoked by the wl_reg_on signal. after initial power-up, the wl_reg_on signal can be held low to disable the bcm43364 or pulsed low to induce a subsequent reset. x0002 status enable 0 r/w 1 0: no status sent to host after a read/write. 1: status sent to host after a read/write. interrupt with status 1 r/w 0 0: do not interrupt if status is sent. 1: interrupt host even if status is sent. x0003 reserved ? ? ? ? x0004 interrupt register 0 r/w 0 requested data not available. cleared by writing a 1 to this location. 1 r 0 f2/f3 fifo underflow from the last read. 2 r 0 f2/f3 fifo overflow from the last write. 5 r 0 f2 packet available 6 r 0 f3 packet available 7 r 0 f1 overflow from the last write. x0005 interrupt register 5 r 0 f1 interrupt 6 r 0 f2 interrupt 7 r 0 f3 interrupt x0006, x0007 interrupt enable register 15:0 r/w/u 16'he0e7 particular interrupt is enabled if a corresponding bit is set. x0008 to x000b status register 31:0 r 32'h0000 same as status bit definitions x000c, x000d f1 info. register 0 r 1 f1 enabled 1 r 0 f1 ready for data transfer 13:2 r/u 12'h40 f1 maximum packet size x000e, x000f f2 info. register 0 r/u 1 f2 enabled 1 r 0 f2 ready for data transfer 15:2 r/u 14'h800 f2 maximum packet size x0014 to x0017 test read-only register 31:0 r 32'hfeedb ead this register contains a predefined pattern, which the host can read to determine if the gspi interface is working properly. x0018 to x001b test r/w register 31:0 r/w/u 32'h000000 00 this is a dummy register where the host can write some pattern and read it back to determine if the gspi interface is working properly. x001c to x001f response delay registers 7:0 r/w 0x1d = 4, other registers = 0 individual response delays for f0, f1, f2, and f3. the value of the registers is the number of byte delays that are introduced before data is shifted out of the gspi interface during host reads. note: the bcm43364 has an internal power-on reset (por) circuit. the device will be held in reset for a maximum of 3 ms after vddc and vddio have both passed the 0.6v threshold. table 6: gspi registers (cont.) address register bit access default description
generic spi mode bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 31 figure 15: wlan boot-up sequence < 1.5 ms after 15 ms 1 the reference clock is assumed to be up. access to pll registers is possible. 15 1 ms < 50 ms < 3 ms after a fixed delay following internal por going high, the device responds to host f0 (address 0x14) reads. vddio wl_reg_on vddc (from internal pmu) internal por device requests a reference clock. spi host interaction: host polls f0 (address 0x14) until it reads a predefined pattern. host sets wake-up-wlan bit and waits 15 ms 1 , the maximum time for reference clock availability. after 15 1 ms, the host programs the pll registers to set the crystal frequency. host downloads code. chip-active interrupt is asserted after the pll locks. vbat ramp time from 0v to 4.3v > 40 s 0.6v > 2 sleep clock cycles wl_irq 1 this wait time is programmable in sleep-clock increments from 1 to 255 (30 s to 15 ms).
wireless lan mac and phy bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 32 section 5: wireless lan mac and phy mac features the bcm43364 wlan mac supports features specified in the ieee 802.11 base standard, and amended by ieee 802.11n. the salient features are listed below: ? transmission and reception of aggregated mpdus (a-mpdu). ? support for power management schemes, including wmm power-save, power-save multipoll (psmp) and multiphase psmp operation. ? support for immediate ack and block-ack policies. ? interframe space timing support, including rifs. ? support for rts/cts and cts-to-self frame sequences for protecting frame exchanges. ? back-off counters in hardware for supporting multiple priorities as specified in the wmm specification. ? timing synchronization function (tsf), network allocation vector (nav) maintenance, and target beacon transmission time (tbtt) generation in hardware. ? hardware off-load for aes-ccmp, legacy wpa tkip, legacy wep ciphers, wapi, and support for key management. ? programmable independent basic service set (ibss) or infrastructure basic service set functionality ? statistics counters for mib support. mac description the bcm43364 wlan mac is designed to support high throughput operation with low-power consumption. in addition, several power-saving modes that have been implemented allow the mac to consume very little power while maintaining network-wide timing synchronization. the architecture diagram of the mac is shown in figure 16 on page 33 .
mac features bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 33 figure 16: wlan mac architecture the following sections provide an overview of the important modules in the mac. psm the programmable state machine (psm) is a microcoded engine that provides most of the low-level control to the hardware to implement the ieee 802.11 specification. it is a microcontroller that is highly optimized for flow- control operations, which are predominant in implementations of communication protocols. the instruction set and fundamental operations are simple and general, which allows algorithms to be optimized until very late in the design process. it also allows for changes to the algorithms to track evolving ieee 802.11 specifications. the psm fetches instructions from the microcode memory. it uses the shared memory to obtain operands for instructions, as a data store, and to exchange data between both the host and the mac data pipeline (via the shm bus). the psm also uses a scratch-pad memory (similar to a register bank) to store frequently accessed and temporary variables. the psm exercises fine-grained control over the hardware engines by programming internal hardware registers (ihr). these ihrs are collocated with the hardware functions they control and are accessed by the psm via the ihr bus. the psm fetches instructions from the microcode memory using an address determined by the program counter, an instruction literal, or a program stack. for alu operations, the operands are obtained from shared memory, scratch-pad memory, ihrs, or instruction literals, and the results are written into the shared memory, scratch-pad memory, or ihrs. embedded cpu interface host registers, dma engines tx-fifo 32 kb wep wep, tkip, aes txe tx a-mpdu rxe pmq psm shared memory 6 kb psm ucode memory ext- ihr ifs tsf nav ihr bus shm bus mac - phy interface rx-fifo 10 kb rx a-mpdu
mac features bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 34 there are two basic branch instructions: conditional branches and alu-based branches. to better support the many decision points in the ieee 802.11 algorithms, branches can depend on either readily available signals from the hardware modules (branch condition signals are available to the psm without polling the ihrs) or on the results of alu operations. wep the wired equivalent privacy (wep) engine encapsulates all the hardware accelerators to perform the encryption and decryption, as well as the mic computation and verification. the accelerators implement the following cipher algorithms: legacy wep, wpa tkip, and wpa2 aes-ccmp. based on the frame type and association information, the psm determines the appropriate cipher algorithm to be used. it supplies the keys to the hardware engines from an on-chip key table. the wep interfaces with the transmit engine (txe) to encrypt and compute the mic on transmit frames and the receive engine (rxe) to decrypt and verify the mic on receive frames. wapi is also supported. txe the transmit engine (txe) constitutes the transmit data path of the mac. it coordinates the dma engines to store the transmit frames in the txfifo. it interfaces with wep module to encrypt frames and transfers the frames across the mac-phy interface at the appropriate time determined by the channel access mechanisms. the data received from the dma engines are stored in transmit fifos. the mac supports multiple logical queues to support traffic streams that have different qos priority requirements. the psm uses the channel access information from the ifs module to schedule a queue from which the next frame is transmitted. once the frame is scheduled, the txe hardware transmits the frame based on a precise timing trigger received from the ifs module. the txe module also contains the hardware that allows the rapid assembly of mpdus into an a-mpdu for transmission. the hardware module aggregates the encrypted mpdus by adding appropriate headers and pad delimiters as needed. rxe the receive engine (rxe) constitutes the receive data path of the mac. it interfaces with the dma engine to drain the received frames from the rx fifo. it transfers bytes across the mac-phy interface and interfaces with the wep module to decrypt frames. the decrypted data is stored in the rx fifo. the rxe module contains programmable filters that are programmed by the psm to accept or filter frames based on several criteria such as receiver address, bssid, and certain frame types. the rxe module also contains the hardware required to detect a-mpdus, parse the headers of the containers, and disaggregate them into component mpdus.
mac features bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 35 ifs the ifs module contains the timers required to determine interframe space timing including rifs timing. it also contains multiple back-off engines required to support prioritized access to the medium as specified by wmm. the interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the phy. these timers provide precise timing to the txe to begin frame transmission. the txe uses this information to send response frames or perform transmit frame-bursting (rifs or sifs separated, as within a txop). the back-off engines (for each access category) monitor channel activity, in each slot duration, to determine whether to continue or pause the back-off counters. when the back-off counters reach 0, the txe gets notified so that it may commence frame transmission. in the event of multiple back-off counters decrementing to 0 at the same time, the hardware resolves the conflict based on policies provided by the psm. the ifs module also incorporates hardware that allows the mac to enter a low-power state when operating under the ieee power-saving mode. in this mode, the mac is in a suspended state with its clock turned off. a sleep timer, whose count value is initialized by the psm, runs on a slow clock and determines the duration over which the mac remains in this suspended state. once the timer expires, the mac is restored to its functional state. the psm updates the tsf timer based on the sleep duration, ensuring that the tsf is synchronized to the network. tsf the timing synchronization function (tsf) module maintains the tsf timer of the mac. it also maintains the target beacon transmission time (tbtt). the tsf timer hardware, under the control of the psm, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network. the tsf module also generates trigger signals for events that are specified as offsets from the tsf timer, such as uplink and downlink transmission times used in psmp. nav the network allocation vector (nav) timer module is responsible for maintaining the nav information conveyed through the duration field of mac frames. this ensures that the mac complies with the protection mechanisms specified in the standard. the hardware, under the control of the psm, maintains the nav timer and updates the timer appropriately based on received frames. this timing information is provided to the ifs module, which uses it as a virtual carrier- sense indication. mac-phy interface the mac-phy interface consists of a data path interface to exchange rx/tx data from/to the phy. in addition, there is a programming interface, which can be controlled either by the host or the psm to configure and control the phy.
phy description bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 36 phy description the bcm43364 wlan digital phy is designed to comply with ieee 802.11b/g/n single stream to provide wireless lan connectivity supporting data rates from 1 mbps to 96 mbps for low-power, high-performance handheld applications. the phy has been designed to meet specification requirements in the presence of interference, radio nonlinearity, and impairments. it incorporates efficient implementations of the filters, fft, and viterbi decoder algorithms. efficient algorithms have been designed to achieve maximum throughput and reliability, including algorithms for carrier sense/rejection, frequency/phase/timing acquisition and tracking, and channel estimation and tracking. the phy receiver also contains a robust ieee 802.11b demodulator. the phy carrier sense has been tuned to provide high throughput for ieee 802.11g/ieee 802.11b hybrid networks. phy features ? supports the ieee 802.11b/g/n single-stream standards. ? supports explicit ieee 802.11n transmit beamforming. ? supports optional greenfield mode in tx and rx. ? tx and rx ldpc for improved range and power efficiency. ? supports ieee 802.11h/d for worldwide operation. ? algorithms achieving low power, enhanced sensitivity, range, and reliability. ? automatic gain control scheme for blocking and nonblocking application scenarios for cellular applications. ? closed-loop transmit power control. ? designed to meet fcc and other regulatory requirements. ? support for 2.4 ghz broadcom turboqam data rates and 20 mhz channel bandwidth.
phy description bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 37 figure 17: wlan phy block diagram the phy is capable of fully calibrating the rf front-end to extract the highest performance. on power-up, the phy performs a full calibration suite to correct for iq mismatch and local oscillator leakage. the phy also performs periodic calibration to compensate for any temperature related drift, thus maintaining high- performance over time. a closed-loop transmit control algor ithm maintains the output power at its required level and can control tx power on a per-packet basis. filters and radio comp frequency and timing synch carrier sense, agc, and rx fsm radio control block filters and radio comp afe and radio mac interface buffers ofdm demodulate viterbi decoder tx fsm pa comp modulation and coding modulate/ spread frame and scramble fft/ifft cck/dsss demodulate descramble and deframe coex
wlan radio subsystem bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 38 section 6: wlan radio subsystem the bcm43364 includes an integrated wlan rf transceiver that has been optimized for use in 2.4 ghz wireless lan systems. it is designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 ghz unlicensed ism band. the transmit and receive sections include all on-chip filtering, mixing, and gain control functions. improvements to the radio design include shared tx/rx baseband filters and high immunity to supply noise. figure 18 shows the radio functional block diagram. figure 18: radio functional block diagram wl logen wl pll wlan bb clb voltage regulators wl pa wl pga wl tx g-mixer wl txlpf wl rx g-mixer slna wl g-lna12 wl rxlpf wl atx wl grx wl gtx wl arx wl adc wl adc wl rxlpf wl dac wl dac wl txlpf wlrf_2g_elg wlrf_2g_rf 4 ~ 6 nh 10 pf recommend q = 40
receive path bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 39 receive path the bcm43364 has a wide dynamic range, direct conversion receiver. it employs high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band. transmit path baseband data is modulated and upconverted to the 2.4 ghz ism band. a linear on-chip power amplifier is included, which is capable of delivering high output powers while meeting ieee 802.11b/g/n specifications without the need for an external pa. this pa is supplied by an internal ldo that is directly supplied by vbat, thereby eliminating the need for a separate paldo. closed-loop output power control is integrated. calibration the bcm43364 features dynamic on-chip calibration, eliminating process variation across components. this enables the bcm43364 to be used in high-volume applications because calibration routines are not required during manufacturing testing. these calibration routines are performed periodically during normal radio operation. automatic calibration examples include baseband filter calibration for optimum transmit and receive performance and loft calibration for leakage reduction. in addition, i/q calibration, r calibration, and vco calibration are performed on-chip.
cpu and global functions bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 40 section 7: cpu and global functions wlan cpu and memory subsystem the bcm43364 includes an integrated arm cortex-m3 processor with internal ram and rom. the arm cortex-m3 processor is a low-power processor that features low gate count, low interrupt latency, and low-cost debugging. it is intended for deeply embedded applications that require fast interrupt response features. the processor implements the arm architecture v7-m with support for the thumb-2 instruction set. arm cortex-m3 provides a 30% performance gain over arm7tdmi. at 0.19 w/mhz, the cortex-m3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit devices on mips/w. it supports integrated sleep modes. arm cortex-m3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced silicon area. arm cortex-m3 supports independent buses for code and data access (icode/dcode and system buses). arm cortex-m3 supports extensive debug features including real-time tracing of program execution. on-chip memory for the cpu includes 512 kb sram and 640 kb rom. one-time programmable memory various hardware configuration parameters may be stored in an internal 4096-bit one-time programmable (otp) memory, which is read by system software after a device reset. in addition, customer-specific parameters, including the system vendor id and the mac address, can be stored, depending on the specific board design. the initial state of all bits in an unprogrammed otp device is 0. after any bit is programmed to a 1, it cannot be reprogrammed to 0. the entire otp array can be programmed in a single write cycle using a utility provided with the broadcom wlan manufacturing test tools. alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. prior to otp memory programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the reference board design package. documentation on the otp development process is available on the broadcom customer support portal ( http://www.broadcom.com/support ).
gpio interface bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 41 gpio interface five general-purpose i/o (gpio) pins are available on the bcm43364 that can be used to connect to various external devices. gpios are tristated by default. subsequently, they can be programmed to be either input or output pins via the gpio control register. they can also be programmed to have internal pull-up or pull-down resistors. gpio_0 is normally used as a wl_host_wake signal. the bcm43364 supports 2-wire, 3-wire, and 4-wire coexistence configurations using gpio_1 through gpio_4. the signal functions of gpio_1 through gpio_4 are programmable to support the three coexistence configurations. external coexistence interface the bcm43364 supports 2-wire, 3-wire, and 4-wire coexistence interfaces to enable signaling between the device and an external colocated wireless device in order to manage wireless medium sharing for optimal performance. the external colocated device can be any of the following ics: gps, wimax, lte, or uwb. an lte ic is used in this section for illustration. 2-wire coexistence figure 19 shows a 2-wire lte coexistence example. the following definitions apply to the gpios in the figure: ? gpio_1: wlan_seci_tx output to an lte ic. ? gpio_2: wlan_seci_rx input from an lte ic. figure 19: 2-wire coexistence interface to an lte ic lte/ic uart_in uart_out note: wlan_seci_out and wlan_seci_in are multiplexed on the gpios. gpio_1 wlan_seci_tx wlan_seci_rx gpio_2 bcm43364
external coexistence interface bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 42 3-wire and 4-wire coexistence interfaces figure 20 and figure 21 show 3-wire and 4-wire lte coexistence examples, respectively. the following definitions apply to the gpios in the figures: ? for the 3-wire coexistence interface: ? gpio_2: wlan priority output to an lte ic. ? gpio_3: lte_rx input from an lte ic. ? gpio_4: lte_tx input from an lte ic. for the 4-wire coexistence interface: ? gpio_1: wlan priority output to an lte ic. ? gpio_2: lte frame sync input from an lte ic. this gpio applies only to the 4-wire coexistence interface. ? gpio_3: lte_rx input from an lte ic. ? gpio_4: lte_tx input from an lte ic. figure 20: 3-wire coexistence interface to an lte ic figure 21: 4-wire coexistence interface to an lte ic lte/ic gpio_2 gpio_3 gpio_4 lte_rx lte_tx wlan priority bcm43364 lte/ic gpio_1 gpio_2 gpio_3 wlan priority lte_frame_sync lte_rx gpio_4 lte_tx bcm43364
jtag interface bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 43 jtag interface the bcm43364 supports the ieee 1149.1 jtag boundary scan standard over sdio for performing device package and pcb assembly testing during manufacturing. in addition, the jtag interface allows broadcom to assist customers by using proprietary debug and characterization test tools during board bring-up. therefore, it is highly recommended to provide access to the jtag pins by means of test points or a header on all pcb designs. uart interface one uart interface can be enabled by software as an alternate function on the jtag pins. uart_rx is available on the jtag_tdi pin, and uart_tx is available on the jtag_tdo pin. the uart is primarily for debugging during development. by adding an external rs-232 transceiver, this uart enables the bcm43364 to operate as rs-232 data termination equipment (dte) for exchanging and managing data with other serial devices. it is compatible with the industry standard 16550 uart, and it provides a fifo size of 64 8 in each direction.
broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 44 pinout and signal descriptions broadcom confidential bcm43364 preliminary data sheet section 8: pinout and signal descriptions ball map figure 22 shows the 74-ball wlbga ball map. figure 22: 74-ball wlbga ball map (bottom view) abcd e fgh jk lm 1 nc nc nc nc vdd_1p2 vdd_1p2 vddb_pa wlrf_2g_ elg wlrf_2g_ rf wlrf_pa_ vdd 1 2 nc nc nc nc vdd_1p2 vdd_1p2 vss vss wlrf_lna _gnd wlrf_ge neral_gn d wlrf_pa_ gnd wlrf_vd d_ 1p35 2 3 nc nc nc vddc vss vss wlrf_gpi o wlrf_vc o_gnd wlrf_xta l_ vdd1p2 3 4 nc nc nc vssc nc vddc wlrf_afe _gnd gpio_3 wlrf_xta l_gnd wlrf_xta l_xop 4 5 nc nc sys_vddi o nc nc lpo_in nc nc vssc gpio_4 gpio_2 wlrf_xta l_xon 5 6 sr_vlx pmu_avs s vout_cld o vout_lnl do gnd wcc_vddi o wl_reg_ on gpio_1 gpio_0 sdio_dat a_0 sdio_cmd clk_req 6 7 sr_pvss sr_vddb at5v ldo_vdd1 p5 vout_3p3 ldo_vdd bat5v sdio_dat a_1 sdio_dat a_3 sdio_dat a_2 sdio_clk 7 abcd e fgh jk lm
wlbga ball list in ball number order with x-y coordinates bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 45 wlbga ball list in ball number order with x-y coordinates table 7 provides ball numbers and names in ball number order. the table includes the x and y coordinates for a top view with a (0,0) center. table 7: bcm43364 wlbga ball list ? ordered by ball number ball number ball name x coordinate y coordinate a1 nc ?1200.006 2199.996 a2 nc ?799.992 2199.996 a3 nc ?399.996 2199.996 a4 nc 0 2199.996 a5 nc 399.996 2199.996 a6 sr_vlx 799.992 2199.978 a7 sr_pvss 1199.988 2199.978 b1 nc ?1200.006 1800 b2 nc ?799.992 1800 b3 nc ?399.996 1800 b4 nc 0 1800 b5 nc 399.996 1800 b6 pmu_avss 799.992 1799.982 b7 sr_vbat5v 1199.988 1799.982 c1 nc ?1200.006 1399.995 c2 nc ?799.992 1399.986 c3 nc ?399.996 1399.995 c4 nc 0 1399.995 c5 sys_vddio 399.996 1399.986 c6 vout_cldo 799.992 1399.986 c7 ldo_vdd15v 1199.988 1399.986 d2 nc ?799.992 999.99 d3 vddc ?399.996 999.999 d4 vssc 0 999.999 d5 nc 399.996 999.99 d6 vout_lnldo 799.992 999.99 e1 nc ?1199.988 599.994 e2 vdd_1p2 ?799.992 599.994 e3 vss ?399.996 599.994 e5 nc 399.996 599.994 e6 gnd 799.992 599.994 e7 vout_3p3 1199.988 599.994 f1 vdd_1p2 ?1199.988 199.998
wlbga ball list in ball number order with x-y coordinates bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 46 f2 vdd_1p2 ?799.992 199.998 f4 nc 0 199.998 f5 lpo_in 399.996 199.998 f6 wcc_vddio 800.001 199.998 f7 ldo_vbat5v 1199.988 199.998 g1 vdd_1p2 ?1199.988 ?199.998 g2 vss ?799.992 ?199.998 g4 vddc 0 ?199.998 g5 nc 399.996 ?199.998 g6 wl_reg_on 800.001 ?199.998 h1 vddb_pa ?1199.988 ?599.994 h2 vss ?799.992 ?599.994 h3 vss ?399.996 ?599.994 h4 wlrf_afe_gnd 0 ?599.994 h5 nc 399.996 ?599.994 h6 gpio_1 800.001 ?599.994 h7 sdio_data_1 1200.006 ?599.994 j1 wlrf_2g_elg ?1199.988 ?999.99 j2 wlrf_lna_gnd ?799.992 ?999.99 j3 wlrf_gpio ?399.996 ?999.99 j5 vssc 399.996 ?999.999 j6 gpio_0 800.001 ?999.999 j7 sdio_data_3 1200.006 ?999.999 k1 wlrf_2g_rf ?1199.988 ?1399.986 k2 wlrf_general_gnd ?799.992 ?1399.986 k4 gpio_3 0 ?1399.995 k5 gpio_4 399.996 ?1399.995 k6 sdio_data_0 800.001 ?1399.995 l2 wlrf_pa_gnd ?799.992 ?1799.982 l3 wlrf_vco_gnd ?399.996 ?1799.982 l4 wlrf_xtal_gnd 0 ?1799.982 l5 gpio_2 399.996 ?1799.991 l6 sdio_cmd 800.001 ?1799.991 l7 sdio_data_2 1200.006 ?1799.991 m1 wlrf_pa_vdd ?1199.988 ?2199.978 m2 wlrf_vdd_1p35 ?799.992 ?2199.978 m3 wlrf_xtal_vdd1p2 ?399.996 ?2199.978 table 7: bcm43364 wlbga ball list ? ordered by ball number ball number ball name x coordinate y coordinate
wlbga ball list in ball number order with x-y coordinates bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 47 m4 wlrf_xtal_xop 0 ?2199.978 m5 wlrf_xtal_xon 399.996 ?2199.978 m6 clk_req 800.001 ?2199.996 m7 sdio_clk 1200.006 ?2199.996 table 7: bcm43364 wlbga ball list ? ordered by ball number ball number ball name x coordinate y coordinate
wlbga ball list ordered by ball name bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 48 wlbga ball list ordered by ball name table 8 provides the ball numbers and names in ball name order. table 8: bcm43364 wlbga ball list ? ordered by ball name ball name ball number clk_req m6 gnd e6 gpio_0 j6 gpio_1 h6 gpio_2 l5 gpio_3 k4 gpio_4 k5 ldo_vdd1p5 c7 ldo_vddbat5v f7 lpo_in f5 nc a1 nc a2 nc a3 nc a4 nc a5 nc b1 nc b2 nc b3 nc b4 nc b5 nc c1 nc c2 nc c3 nc c4 nc d2 nc d5 nc e1 nc e5 nc f4 nc g5 nc h5 pmu_avss b6 sdio_clk m7 sdio_cmd l6 sdio_data_0 k6 sdio_data_1 h7 sdio_data_2 l7 sdio_data_3 j7 sr_pvss a7 sr_vddbat5v b7 sr_vlx a6 sys_vddio c5 vdd_1p2 e2 vdd_1p2 f1 vdd_1p2 f2 vdd_1p2 g1 vddb_pa h1 vddc d3 vddc g4 vout_3p3 e7 vout_cldo c6 vout_lnldo d6 vss e3 vss g2 vss h2 vss h3 vssc d4 vssc j5 wcc_vddio f6 wl_reg_on g6 wlrf_2g_elg j1 wlrf_2g_rf k1 wlrf_afe_gnd h4 wlrf_general_gnd k2 wlrf_gpio j3 wlrf_lna_gnd j2 wlrf_pa_gnd l2 wlrf_pa_vdd m1 wlrf_vco_gnd l3 wlrf_vdd_1p35 m2 wlrf_xtal_gnd l4 wlrf_xtal_vdd1p2 m3 wlrf_xtal_xon m5 wlrf_xtal_xop m4 ball name ball number
signal descriptions bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 49 signal descriptions table 9 provides the wlbga package signal descriptions. table 9: wlbga signal descriptions signal name wlbga ball type description rf signal interface wlrf_2g_rf k1 o 2.4 ghz wlan rf output port. sdio bus interface sdio_clk m7 i sdio clock input. sdio_cmd l6 i/o sdio command line. sdio_data_0 k6 i/o sdio data line 0. sdio_data_1 h7 i/o sdio data line 1. sdio_data_2 l7 i/o sdio data line 2. also used as a strapping option (see table 12 on page 53 ). sdio_data_3 j7 i/o sdio data line 3. note: per section 6 of the sdio specification, 10 to 100 k ? pull-ups are required on the four data lines and the cmd line. this requirement must be met during all operating states by using external pull-up resistors or properly programming internal sdio host pull-ups. wlan gpio interface wlrf_gpio j3 i/o test pin. not connected in normal operation. clocks wlrf_xtal_xon m5 o xtal oscillator output. wlrf_xtal_xop m4 i xtal oscillator input. clk_req m6 o external system clock request?used when the system clock is not provided by a dedicated crystal (for example, when a shared tcxo is used). asserted to indicate to the host that the clock is required. lpo_in f5 i external sleep clock input (32.768 khz). if an external 32.768 khz clock cannot be provided, pull this pin low. no connect nc_a1 a1 i no connect. nc_a2 a2 o no connect. nc_a3 a3 i/o no connect.
signal descriptions bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 50 nc_a4 a4 i/o no connect. nc_a5 a5 i/o no connect. nc_b1 b1 i/o no connect. nc_b2 b2 i no connect. nc_b3 b3 i/o no connect. nc_b4 b4 o no connect. nc_b5 b5 i/o no connect. nc_c1 c1 i/o no connect. nc_c2 c2 o no connect. nc_c3 c3 o no connect. nc_c4 c4 i no connect. nc_d2 d2 o no connect. nc_e1 e1 i no connect. nc_f4 f4 i/o no connect. nc_g5 g5 i/o no connect. nc_h5 h5 i/o no connect. nc_e5 e5 n/a not used. do not connect to this pin. nc_d5 d5 n/a not used. do not connect to this pin. miscellaneous wl_reg_on g6 i used by pmu to power up or power down the internal regulators used by the wlan section. also, when deasserted, this pin holds the wlan section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. gnd_e6 e6 i tie pin e6 to ground. gpio_0 j6 i/o programmable gpio pins. this pin becomes an output pin when it is used as wlan_host_wake/out-of-band signal. gpio_1 h6 i/o programmable gpio pins. gpio_2 l5 i/o programmable gpio pins. gpio_3 k4 i/o programmable gpio pins. gpio_4 k5 i/o programmable gpio pins. wlrf_2g_elg j1 i connect to an external inductor. see the reference schematic for details. integrated voltage regulators sr_vddbat5v b7 i sr vbat input power supply. sr_vlx a6 o cbuck switching regulator output. see table 21 on page 65 for details of the inductor and capacitor required on this output. ldo_vddbat5v f7 i ldo vbat. ldo_vdd1p5 c7 i lnldo input. table 9: wlbga signal descriptions (cont.) signal name wlbga ball type description
signal descriptions bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 51 vout_lnldo d6 o output of low-noise lnldo. vout_cldo c6 o output of core ldo. vddb_pa h1 i connect to vout_3p3. vdd_1p2 g1 i connect to vout_lnldo. vdd_1p2 f2 i connect to vout_lnldo. vdd_1p2 f1 i connect to vout_lnldo. vdd_1p2 e2 i connect pin e2 to vout_lnldo. power supplies wlrf_xtal_vdd1p2 m3 i xtal oscillator supply. wlrf_pa_vdd m1 i power amplifier supply. wcc_vddio f6 i vddio input supply. connect to vddio. sys_vddio c5 i vddio input supply. connect to vddio. wlrf_vdd_1p35 m2 i lnldo input supply. vddc d3, g4 i core supply for wlan. vout_3p3 e7 o 3.3v output supply. see the reference schematic for details. ground vss_h2 h2 i connect to ground. vss_g2 g2 i connect to ground. vss_h3 h3 i connect to ground. vss_e3 e3 i connect to ground. pmu_avss b6 i quiet ground. sr_pvss a7 i switcher-power ground. vssc d4, j5 i core ground for wlan. wlrf_afe_gnd h4 i afe ground. wlrf_lna_gnd j2 i 2.4 ghz internal lna ground. wlrf_general_gnd k2 i miscellaneous rf ground. wlrf_pa_gnd l2 i 2.4 ghz pa ground. wlrf_vco_gnd l3 i vco/lo generator ground. wlrf_xtal_gnd l4 i xtal ground. table 9: wlbga signal descriptions (cont.) signal name wlbga ball type description
wlan gpio signals and strapping options bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 52 wlan gpio signals an d strapping options the pins listed in table 10 are sampled at power-on reset (por) to determine the various operating modes. sampling occurs a few milliseconds after an internal por or deassertion of the external por. after the por, each pin assumes the gpio or alternative function specified in the signal descriptions table. each strapping option pin has an internal pull-up (pu) or pull-down (pd) resistor that determines the default mode. to change the mode, connect an external pu resistor to vddio or a pd resistor to ground using a 10 k ? resistor or less. chip debug options the chip can be accessed for debugging via the jtag interface, multiplexed on the sdio_data_0 through sdio_data_3 (and sdio_clk) i/o depending on the bootstrap state of gpio_1 and gpio_2. table 11 shows the debug options of the device. note: refer to the reference board schematics for more information. table 10: gpio functions and strapping options pin name wlbga pin # default function description sdio_data_2 l7 1 wlan host interface select this pin selects the wlan host interface mode. the default is sdio. for gspi, pull this pin low. table 11: chip debug options jtag_sel gpio_2 gpio_1 function sdio i/o pad function 0 0 0 normal mode sdio 0 0 1 jtag over sdio jtag 0 1 1 swd over gpio_1/gpio_2 sdio
broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 53 i/o states broadcom confidential bcm43364 preliminary data sheet i/o states the following notations are used in table 12 : ? i: input signal ? o: output signal ? i/o: input/output signal ?pu = pulled up ? pd = pulled down ? nopull = neither pulled up nor pulled down table 12: i/o states name i/o keeper active mode low power state/ sleep (all power present) power-down (wl_reg_on=0) out-of-reset; (wl_reg_on=1) wl_reg_on=1 and vddios are present wl_reg_on=0 and vddios are present power rail wl_reg_on i n input; pd (pull-down can be disabled) input; pd (pull-down can be disabled) input; pd (of 200k) input; pd (200k) input; pd (200k) ? ? clk_req i/o y open drain or push-pull (programmable). active high. open drain or push-pull (programmable). active high pd open drain, active high. open drain, active high. open drain, active high. wcc_vddio sdio_data_0 i/o n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio sdio_data_1 i/o n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio sdio_data_2 i/o n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio sdio_data_3 i/o n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio sdio_cmd i/o n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio sdio_clk i n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull input wcc_vddio jtag_sel i y pd pd high-z, nopull input, pd pd input, pd wcc_vddio gpio_0 i/o y tbd active mode high-z, nopull a input, sdio oob int, nopull active mode input, nopull wcc_vddio gpio_1 i/o y tbd active mode high-z, nopull a input, pd active mode input, strap, pd wcc_vddio gpio_2 i/o y tbd active mode high-z, nopull a input, gci gpio[7], nopull active mode input, strap, nopull wcc_vddio
broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 54 i/o states broadcom confidential bcm43364 preliminary data sheet gpio_3 i/o y tbd active mode high-z, nopull a input, gci gpio[0], pu active mode input, pu wcc_vddio gpio_4 i/o y tbd active mode high-z, nopull a input, gci gpio[1], pu active mode input, pu wcc_vddio note: 1. keeper column: n = pad has no keeper. y = pad has a keeper. keeper is always active except in the power-down state. 2. if there is no keeper, and it is an input and there is nopull, then the pad should be driven to prevent leakage due to a floati ng pad (e.g., sdio_clk). 3. in the power-down state (xx_reg_on = 0): high-z; nopull => the pad is disabled because power is not supplied. 4. depending on whether the pcm interface is enabled and the configuration is master or slave mode, it can be either an output or input. 5. depending on whether the i 2 s interface is enabled and the configuration is master or slave mode, it can be either an output or input. 6. the gpio pull states for the active and low-power states are hardware defaults. they can all be subsequently programmed as pull -ups or pull-downs. 7. regarding gpio pins, the following are the pull-up and pull-down values for both 3.3v and 1.8v vddio: minimum (k ? ) typical (k ? ) maximum (k ? ) 3.3v vddio pull-downs: 51.5 44.5 38 3.3v vddio pull-ups: 37.4 39.5 44.5 1.8v vddio pull-downs: 64 83 116 1.8v vddio pull-ups: 65 86 118 a. the gpio pull states for the active and low-power states ar e hardware defaults. they can all be subsequently programmed as a pull-up or pull-down. table 12: i/o states (cont.) name i/o keeper active mode low power state/ sleep (all power present) power-down (wl_reg_on=0) out-of-reset; (wl_reg_on=1) wl_reg_on=1 and vddios are present wl_reg_on=0 and vddios are present power rail
dc characteristics bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 55 section 9: dc characteristics absolute maximum ratings note: values in this data sheet are design goals and are subject to change based on the results of device characterization. caution! the absolute maximum ratings in table 13 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. functional operation is not guaranteed under these conditions. excluding vbat, operation at the absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. table 13: absolute maximum ratings rating symbol value unit dc supply for vbat and pa driver supply vbat ?0.5 to +6.0 a a. continuous operation at 6.0v is supported. v dc supply voltage for digital i/o vddio ?0.5 to 3.9 v dc supply voltage for rf switch i/os vddio_rf ?0.5 to 3.9 v dc input supply voltage for cldo and lnldo ? ?0.5 to 1.575 v dc supply voltage for rf analog vddrf ?0.5 to 1.32 v dc supply voltage for core vddc ?0.5 to 1.32 v maximum undershoot voltage for i/o b b. duration not to exceed 25% of the duty cycle. v undershoot ?0.5 v maximum overshoot voltage for i/o b v overshoot vddio + 0.5 v maximum junction temperature t j 125 c
environmental ratings bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 56 environmental ratings the environmental ratings are shown in table 14 . electrostatic dischar ge specifications extreme caution must be exercised to prevent electrostatic discharge (esd) damage. proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. always store unused material in its antistatic packaging. recommended operating conditi ons and dc characteristics functional operation is not guaranteed outside the limits shown in table 16 , and operation outside these limits for extended periods can adversely affect long-term reliability of the device. table 14: environmental ratings characteristic value units conditions/comments ambient temperature (t a ) ?30 to +70c a a. functionality is guaranteed, but specifications require derating at extreme temperatures (see the specification tables for details). ? coperation storage temperature ?40 to +125c ? c? relative humidity less than 60 % storage less than 85 % operation table 15: esd specifications pin type symbol condition esd rating unit esd, handling reference: nqy00083, section 3.4, group d9, table b esd_hand_hbm human body model contact discharge per jedec eid/ jesd22-a114 1250 v machine model (mm) esd_hand_mm machine model contact 50 v cdm esd_hand_cdm charged device model contact discharge per jedec eia/ jesd22-c101 300 v table 16: recommended operating conditions and dc characteristics element symbol value unit minimum typical maximum dc supply voltage for vbat vbat 3.0 a ? 4.8 b v dc supply voltage for core vdd 1.14 1.2 1.26 v dc supply voltage for rf blocks in chip vddrf 1.14 1.2 1.26 v
recommended operating conditions and dc characteristics bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 57 dc supply voltage for digital i/o vddio, vddio_sd 1.71 ? 3.63 v dc supply voltage for rf switch i/os vddio_rf 3.13 3.3 3.46 v external tssi input tssi 0.15 ? 0.95 v internal por threshold vth_por 0.4 ? 0.7 v sdio interface i/o pins for vddio_sd = 1.8v: input high voltage vih 1.27 ? ?v input low voltage vil ? ?0.58 v output high voltage @ 2 ma voh 1.40 ? ?v output low voltage @ 2 ma vol ? ?0.45 v for vddio_sd = 3.3v: input high voltage vih 0.625 vddio ? ?v input low voltage vil ? ? 0.25 vddio v output high voltage @ 2 ma voh 0.75 vddio ?? v output low voltage @ 2 ma vol ? ? 0.125 vddio v other digital i/o pins for vddio = 1.8v: input high voltage vih 0.65 vddio ? ?v input low voltage vil ? ? 0.35 vddio v output high voltage @ 2 ma voh vddio ? 0.45 ? ?v output low voltage @ 2 ma vol ? ?0.45 v for vddio = 3.3v: input high voltage vih 2.00 ? ?v input low voltage vil ? ?0.80 v output high voltage @ 2 ma voh vddio ? 0.4 ? ?v output low voltage @ 2 ma vol ? ?0.40 v rf switch control output pins c for vddio_rf = 3.3v: output high voltage @ 2 ma voh vddio ? 0.4 ? ?v output low voltage @ 2 ma vol ? ?0.40 v input capacitance c in ? ? 5 pf a. the bcm43364 is functional across this range of voltages. however, optimal rf performance specified in the data sheet is guaranteed only for 3.2v < vbat < 4.8v. b. the maximum continuous voltage is 4.8v. voltages up to 6.0v for up to 10 seconds, cumulative duration over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds, cumulative duration over the lifetime of the device are allowed. c. programmable 2 ma to 16 ma drive strength. default is 10 ma. table 16: recommended operating conditions and dc characteristics (cont.) element symbol value unit minimum typical maximum
wlan rf specifications bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 58 section 10: wlan rf specifications the bcm43364 includes an integrated direct conversion radio that supports the 2.4 ghz band. this section describes the rf characteristics of the 2.4 ghz radio. unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in table 14: ?environmental ratings,? on page 56 and table 16: ?recommended operating conditions and dc characteristics,? on page 56 . functional operation outside these limits is not guaranteed. typical values apply for the following conditions: ?vbat = 3.6v. ? ambient temperature +25c. figure 23: rf port location note: values in this data sheet are design goals and may change based on device characterization results. note: all specifications apply at the chip port unless otherwise specified. tx rx c2 10 pf l1 4.7 nh c1 10 pf filter chip port antenna port bcm43364
2.4 ghz band general rf specifications bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 59 2.4 ghz band general rf specifications wlan 2.4 ghz receiver pe rformance specifications table 17: 2.4 ghz band general rf specifications item condition minimum typical maximum unit tx/rx switch time including tx ramp down ? ? 5 s rx/tx switch time including tx ramp up ? ? 2 s note: unless otherwise specified, the specifications in table 18 are measured at the chip port (for the location of the chip port, see figure 23 on page 58 ). table 18: wlan 2.4 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz rx sensitivity (8% per for 1024 octet psdu) a 1 mbps dsss ?97.5 ?99.5 ? dbm 2 mbps dsss ?93.5 ?95.5 ? dbm 5.5 mbps dsss ?91.5 ?93.5 ? dbm 11 mbps dsss ?88.5 ?90.5 ? dbm rx sensitivity (10% per for 1000 octet psdu) at wlan rf port a 6 mbps ofdm ?91.5 ?93.5 ? dbm 9 mbps ofdm ?90.5 ?92.5 ? dbm 12 mbps ofdm ?87.5 ?89.5 ? dbm 18 mbps ofdm ?85.5 ?87.5 ? dbm 24 mbps ofdm ?82.5 ?84.5 ? dbm 36 mbps ofdm ?80.5 ?82.5 ? dbm 48 mbps ofdm ?76.5 ?78.5 ? dbm 54 mbps ofdm ?75.5 ?77.5 ? dbm rx sensitivity (10% per for 4096 octet psdu). defined for default parameters: gf, 800 ns gi. 20 mhz channel spacing for all mcs rates (mixed mode) 256-qam, r = 5/6 ?67.5 ?69.5 ? dbm 256-qam, r = 3/4 ?69.5 ?71.5 ? dbm mcs7 ?71.5 ?73.5 ? dbm mcs6 ?73.5 ?75.5 ? dbm mcs5 ?74.5 ?76.5 ? dbm mcs4 ?79.5 ?81.5 ? dbm mcs3 ?82.5 ?84.5 ? dbm mcs2 ?84.5 ?86.5 ? dbm mcs1 ?86.5 ?88.5 ? dbm mcs0 ?90.5 ?92.5 ? dbm
wlan 2.4 ghz receiver performance specifications bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 60 blocking level for 3 db rx sensitivity degradation (without external filtering) 704?716 lte ? ?13 ? dbm 777?787 lte ? ?13 ? dbm 776?794 mhz cdma2000 ? ?13.5 ? dbm 815?830 lte ? ?12.5 ? dbm 816?824 cdma2000 ? ?13.5 ? dbm 816?849 lte ? ?11.5 ? dbm 824?849 wcdma ? ?11.5 ? dbm 824?849 cdma2000 ? ?12.5 ? dbm 824?849 lte ? ?11.5 ? dbm 824?849 gsm850 ? ?8 ? dbm 830?845 lte ? ?11.5 ? dbm 832?862 lte ? ?11.5 ? dbm 880?915 wcdma ? ?10 ? dbm 880?915 lte ? ?12 ? dbm 880?915 e-gsm ? ?9 ? dbm 1710?1755 wcdma ? ?13 ? dbm 1710?1755 lte ? ?14.5 ? dbm 1710?1755 cdma2000 ? ?14.5 ? dbm 1710?1785 wcdma ? ?13 ? dbm 1710?1785 lte ? ?14.5 ? dbm 1710?1785 gsm1800 ? ?12.5 ? dbm 1850?1910 gsm1900 ? ?11.5 ? dbm 1850?1910 cdma2000 ? ?16 ? dbm 1850?1910 wcdma ? ?13.5 ? dbm 1850?1910 lte ? ?16 ? dbm 1850?1915 lte ? ?17 ? dbm 1920?1980 wcdma ? ?17.5 ? dbm blocking level for 3 db rx sensitivity degradation (without external filtering) (cont.) 1920?1980 cdma2000 ? ?19.5 ? dbm 1920?1980 lte ? ?19.5 ? dbm 2300?2400 lte ? ?44 ? dbm 2500?2570 lte ? ?43 ? dbm 2570?2620 lte ? ?34 ? dbm 5g (wlan) wlan ? >?4 ? dbm maximum receive level @ 2.4 ghz @ 1, 2 mbps (8% per, 1024 octets) ?6 ? ? dbm @ 5.5, 11 mbps (8% per, 1024 octets) ?12 ? ? dbm @ 6?54 mbps (10% per, 1000 octets) ?15.5 ? ? dbm table 18: wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit
wlan 2.4 ghz receiver performance specifications bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 61 adjacent channel rejection- dsss. (difference between interfering and desired signal [25 mhz apart] at 8% per for 1024 octet psdu with desired signal level as specified in condition/ notes.) 11 mbps dsss ?70 dbm 35 ? ? db adjacent channel rejection- ofdm. (difference between interfering and desired signal (25 mhz apart) at 10% per for 1000 b octet psdu with desired signal level as specified in condition/notes.) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db 65 mbps ofdm ?61 dbm ?2 ? ? db rcpi accuracy c range ?98 dbm to ?75 dbm ?3 ? 3 db range above ?75 dbm ?5 ? 5 db return loss zo = 50 ? across the dynamic range. 10 ? ? db a. optimal rf performance, as specified in this data sheet, is guaranteed only for temperatures between ?10c and 55c. b. for 65 mbps, the size is 4096. c. the minimum and maximum values shown have a 95% confidence level. table 18: wlan 2.4 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit
wlan 2.4 ghz transmitter performance specifications bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 62 wlan 2.4 ghz transmitter performance specifications note: unless otherwise specified, the specifications in table 18 are measured at the chip port (for the location of the chip port, see figure 23 on page 58 ). table 19: wlan 2.4 ghz transmitter performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz transmitted power in cellular and wlan 5g band (at 21 dbm, 90% duty cycle, 1 mbps cck). 776?794 mhz cdma2000 ? ?167.5 ? dbm/hz 869?960 mhz cdmaone, gsm850 ? ?163.5 ? dbm/hz 1450?1495 dab ? ?154.5 ? dbm/hz 1570?1580 mhz gps ? ?152.5 ? dbm/hz 1592?1610 mhz glonass ? ?149.5 ? dbm/hz 1710?1800 dsc-1800-uplink ? ?145.5 ? dbm/hz 1805?1880 mhz gsm 1800 ? ?143.5 ? dbm/hz 1850?1910 mhz gsm 1900 ? ?140.5 ? dbm/hz 1910?1930 mhz tdscdma,lte ? ?138.5 ? dbm/hz 1930?1990 mhz gsm1900, cdmaone, wcdma ??139? dbm/hz 2010?2075 mhz tdscdma ? ?127.5 ? dbm/hz 2110?2170 mhz wcdma ? ?124.5 ? dbm/hz 2305?2370 lte band 40 ? ?104.5 ? dbm/hz 2370?2400 lte band 40 ? ?81.5 ? dbm/hz 2496?2530 lte band 41 ? ?94.5 ? dbm/hz 2530?2560 lte band 41 ? ?120.5 ? dbm/hz 2570?2690 lte band 41 ? ?121.5 ? dbm/hz 5000?5900 wlan 5g ? ?109.5 ? dbm/hz harmonic level (at 21 dbm with 90% duty cycle, 1mbps cck) 4.8-5.0 ghz 2nd harmonic ? ?26.5 ? dbm/ mhz 7.2-7.5 ghz 3rd harmonic ? ?23.5 ? dbm/ mhz 9.6-10 ghz 4th harmonic ? ?32.5 ? dbm/ mhz
wlan 2.4 ghz transmitter performance specifications bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 63 tx power at the chip port for the highest power level setting at 25c, vba = 3.6v, and spectral mask and evm compliance a, b evm does not exceed ieee 802.11b (dsss/cck) ?9 db 21 ? ? dbm ofdm, bpsk ?8 db 20.5 ? ? dbm ofdm, qpsk ?13 db 20.5 ? ? dbm ofdm, 16-qam ?19 db 20.5 ? ? dbm ofdm, 64-qam (r = 3/4) ?25 db 18 ? ? dbm ofdm, 64-qam (r = 5/6) ?27 db 17.5 ? ? dbm ofdm, 256-qam (r = 5/6) ?32 db 15 ? ? dbm tx power control dynamic range ?9??db closed loop tx power variation at highest power level setting across full temperature and voltage range. applies across 5 to 21 dbm output power range. ??1.5db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss zo = 50 4 6 ? db load pull variation for output power, evm, and adjacent channel power ratio (acpr) vswr = 2:1. evm degradation ? 3.5 ? db output power variation ? 2 ? db acpr-compliant power level ?15 ? dbm vswr = 3:1. evm degradation ? 4 ? db output power variation ? 3 ? db acpr-compliant power level ?15 ? dbm a. tx power for channel 1 and channel 11 is specified separately by nonvolatile memory parameters to ensure band-edge compliance. b. optimal rf performance, as specified in this data sheet, is guaranteed only for temperatures between ?10c and 55c. table 19: wlan 2.4 ghz transmitter performance specifications (cont.) parameter condition/notes minimum typical maximum unit
general spurious emissions specifications bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 64 general spurious emi ssions specifications table 20: general spurious emissions specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz general spurious emissions tx emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ?99 ?96 dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ?44 ?41 dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ?68 ?65 dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ?88 ?85 dbm rx/standby emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ?99 ?96 dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ?54 ?51 dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ?88 ?85 dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ?88 ?85 dbm note: the specifications in this table apply at the chip port.
internal regulator electrical specifications bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 65 section 11: internal regulator electrical specifications functional operation is not guaranteed outside of the specification limits provided in this section. core buck switching regulator note: values in this data sheet are design goals and are subject to change based on device characterization results. table 21: core buck switching regulator (cbuck) specifications specification notes min. typ. max. units input supply voltage (dc) dc voltage range inclusive of disturbances. 2.4 3.6 4.8 a v pwm mode switching frequency ccm, load > 100 ma vbat = 3.6v. ? 4 ? mhz pwm output current ? ? ? 370 ma output current limit ? ? 1400 ? ma output voltage range programmable, 30 mv steps. default = 1.35v. 1.2 1.35 1.5 v pwm output voltage dc accuracy includes load and line regulation. forced pwm mode. ?4 ? 4 % pwm ripple voltage, static measure with 20 mhz bandwidth limit. static load, max. ripple based on vbat = 3.6v, vout = 1.35v, fsw = 4 mhz, 2.2 h inductor l > 1.05 h, cap + board total-esr < 20 m ? , c out > 1.9 f, esl<200 ph ?720mvpp pwm mode peak efficiency peak efficiency at 200 ma load, inductor dcr = 200 m ? , vbat = 3.6v, vout = 1.35v ?85?% pfm mode efficiency 10 ma load current, inductor dcr = 200 m ? , vbat = 3.6v, vout = 1.35v ?77?% start-up time from power down vddio already on and steady. time from reg_on rising edge to cldo reaching 1.2v ? 400 500 s external inductor 0603 size, 2.2 h 20%, dcr = 0.2 ? 25% ?2.2?h external output capacitor ceramic, x5r, 0402, esr <30 m ? at 4 mhz, 4.7 f 20%, 10v 2.0 b 4.7 10 c f
core buck switching regulator bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 66 external input capacitor for sr_vddbatp5v pin, ceramic, x5r, 0603, esr < 30 m ? at 4 mhz, 4.7 f 20%, 10v 0.67 b 4.7 ? f input supply voltage ramp-up time 0 to 4.3v 40 ? ? s a. the maximum continuous voltage is 4.8v. voltages up to 6.0v for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. b. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. c. total capacitance includes those connected at the far end of the active load. table 21: core buck switching regul ator (cbuck) specifications (cont.) specification notes min. typ. max. units
3.3v ldo (ldo3p3) bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 67 3.3v ldo (ldo3p3) table 22: ldo3p3 specifications specification notes min. typ. max. units input supply voltage, v in min. = v o + 0.2v = 3.5v dropout voltage requirement must be met under maximum load for performance specifications. 3.1 3.6 4.8 a a. the maximum continuous voltage is 4.8v. voltages up to 6.0v for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. voltages as high as 5.0v for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. v output current ? 0.001 ? 450 ma nominal output voltage, v o default = 3.3v. ? 3.3 ? v dropout voltage at max. load. ? ? 200 mv output voltage dc accuracy includes line/load regulation. ?5 ? +5 % quiescent current no load ? 66 85 a line regulation v in from (v o + 0.2v) to 4.8v, max. load ? ? 3.5 mv/v load regulation load from 1 ma to 450 ma ? ? 0.3 mv/ma psrr v in v o + 0.2v, v o = 3.3v, c o = 4.7 f, max. load, 100 hz to 100 khz 20??db ldo turn-on time chip already powered up. ? 160 250 s external output capacitor, c o ceramic, x5r, 0402, (esr: 5 m ? ?240 m ? ), 10%, 10v 1.0 b b. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 5.64 f external input capacitor for sr_vddbata5v pin (shared with band gap) ceramic, x5r, 0402, (esr: 30m-200 m ? ), 10%, 10v. not needed if sharing vbat capacitor 4.7 f with sr_vddbatp5v. ?4.7?f
cldo bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 68 cldo table 23: cldo specifications specification notes min. typ. max. units input supply voltage, v in min. = 1.2 + 0.15v = 1.35v dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.2 ? 200 ma output voltage, v o programmable in 10 mv steps. default = 1.2.v 0.95 1.2 1.26 v dropout voltage at max. load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 13 ? a 200 ma load ? 1.24 ? ma line regulation v in from (v o + 0.15v) to 1.5v, maximum load ??5mv/v load regulation load from 1 ma to 300 ma ? 0.02 0.05 mv/ma leakage current power down ? 5 20 a bypass mode ? 1 3 a psrr @1 khz, vin 1.35v, c o = 4.7 f 20 ? ? db start-up time of pmu vddio up and steady. time from the reg_on rising edge to the cldo reaching 1.2v. ??700s ldo turn-on time ldo turn-on time when rest of the chip is up. ? 140 180 s external output capacitor, c o total esr: 5 m ? ?240 m ? 1.1 a a. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 2.2 ? f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. ?12.2f
lnldo bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 69 lnldo table 24: lnldo specifications specification notes min. typ. max. units input supply voltage, vin min. v in = v o + 0.15v = 1.35v (where v o = 1.2v) dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.1 ? 150 ma output voltage, v o programmable in 25 mv steps. default = 1.2v 1.1 1.2 1.275 v dropout voltage at maximum load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 10 12 a max. load ? 970 990 a line regulation v in from (v o + 0.15v) to 1.5v, 200 ma load ?? 5mv/v load regulation load from 1 ma to 200 ma: v in (v o + 0.12v) ? 0.025 0.045 mv/ma leakage current power-down, junction temp. = 85c ? 5 20 a output noise @30 khz, 60?150 ma load c o = 2.2 f @100 khz, 60?150 ma load c o = 2.2 f ? ? 60 35 ? psrr @1 khz, v in (v o + 0.15v), c o = 4.7 f 20 ? ? db ldo turn-on time ldo turn-on time when rest of chip is up ? 140 180 s external output capacitor, c o total esr (trace/capacitor): 5 m ? ?240 m ? 0.5 a a. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 2.2 4.7 f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. total esr (trace/capacitor): 30 m ? ?200 m ? ? 1 2.2 f nv/ hz
system power consumption bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 70 section 12: system power consumption wlan current consumption table 25 shows typical currents consumed by the bcm43364?s wlan section. 2.4 ghz mode note: the values in this data sheet are desi gn goals and are subject to change based on device characterization.unless otherwise stated, these values apply for the conditions specified in table 16: ?recommended operating conditions and dc characteristics,? on page 56 . table 25: 2.4 ghz mode wlan power consumption mode rate vbat = 3.6v, vddio = 1.8v, ta 25c vbat (ma) vio (a) sleep modes leakage (off) n/a 0.0035 0.08 sleep (idle, unassociated) a a. device is initialized in sleep mode, but not associated. n/a 0.0058 80 sleep (idle, associated, inter-beacons) b b. device is associated, and then enters power save mode (idle between beacons). rate 1 0.0058 80 ieee power save pm1 dtim1 (avg.) c c. beacon interval = 100 ms; beacon duration = 1 ms @ 1 mbps (integrated sleep + wakeup + beacon). rate 1 1.05 74 ieee power save pm1 dtim3 (avg.) d d. beacon interval = 300 ms; beacon duration = 1 ms @ 1 mbps (integrated sleep + wakeup + beacon). rate 1 0.35 86 ieee power save pm2 dtim1 (avg.) c rate 1 1.05 74 ieee power save pm2 dtim3 (avg.) d rate 1 0.35 86 active modes rx listen mode e e. carrier sense (cca) when no carrier present. n/a 37 12 rx active (at ?50dbm rssi) f f. tx output power is measured on the chip-out side; duty cycle =100%. tx active mode is measured in packet engine mode (pseudo-random data) rate 1 39 12 rate 11 40 12 rate 54 40 12 rate mcs7 41 12 tx f rate 1 @ 20 dbm 320 15 rate 11 @ 18 dbm 290 15 rate 54 @ 15 dbm 260 15 rate c7 @ 15 dbm 260 15
interface timing and ac characteristics bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 71 section 13: interface timing and ac characteristics unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in table 14 on page 56 and table 16 on page 56 . functional operation outside of these limits is not guaranteed. sdio default mode timing sdio default mode timing is shown by the combination of figure 24 and table 26 on page 72 . figure 24: sdio bus timing (default mode) note: values in this data sheet are design goals and are subject to change based on the results of device characterization. t wl t wh f pp t thl t isu t tlh t ih t odly (max) t odly (min) input output sdio_clk
sdio default mode timing bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 72 table 26: sdio bus timing a parameters (default mode) a. timing is based on cl ? 40 pf load on command and data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b. min (vih) = 0.7 vddio and max (vil) = 0.2 vddio. frequency?data transfer mode fpp 0 ? 25 mhz frequency?identification mode fod 0 ? 400 khz clock low time twl 10 ? ? ns clock high time twh 10 ? ? ns clock rise time ttlh ? ? 10 ns clock fall time tthl ? ? 10 ns inputs: cmd, dat (referenced to clk) input setup time tisu5??ns input hold time tih5??ns outputs: cmd, dat (referenced to clk) output delay time?data transfer mode todly 0 ? 14 ns output delay time?identification mode todly 0 ? 50 ns
sdio high-speed mode timing bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 73 sdio high-speed mode timing sdio high-speed mode timing is shown by the combination of figure 25 and table 27 . figure 25: sdio bus timing (high-speed mode) table 27: sdio bus timing a parameters (high-speed mode) a. timing is based on cl ? 40 pf load on command and data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b. min (vih) = 0.7 vddio and max (vil) = 0.2 vddio. frequency ? data transfer mode fpp 0 ? 50 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl7??ns clock high time twh7??ns clock rise time ttlh??3ns clock fall time tthl??3ns inputs: cmd, dat (referenced to clk) input setup time tisu6??ns input hold time tih2??ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly ? ? 14 ns output hold time toh 2.5 ? ? ns total system capacitance (each line) cl ? ? 40 pf t wl t wh f pp t thl t isu t tlh t ih t odly input output 50% vdd t oh sdio_clk
gspi signal timing bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 74 gspi signal timing the gspi device always samples data on the rising edge of the clock. figure 26: gspi timing table 28: gspi timing parameters parameter symbol minimum maximum units note clock period t1 20.8 ? ns f max = 50 mhz clock high/low t2/t3 (0.45 t1) ? t4 (0.55 t1) ? t4 ns ? clock rise/fall time t4/t5 ? 2.5 ns ? input setup time t6 5.0 ? ns setup time, simo valid to spi_clk active edge input hold time t7 5.0 ? ns hold time, spi_clk active edge to simo invalid output setup time t8 5.0 ? ns setup time, somi valid before spi_clk rising output hold time t9 5.0 ? ns hold time, spi_clk active edge to somi invalid csx to clock a a. spi_csx remains active for entire duration of gspi read/write/write_read transaction (that is, overall words for multiple word transaction). ? 7.86 ? ns csx fall to 1st rising edge clock to csx c ? ? ? ns last falling edge to csx high t4 t5 t1 t2 t 3 t7 t6 t9 t8 spi_clk spi_din spi_dout (falling edge)
jtag timing bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 75 jtag timing table 29: jtag timing characteristics signal name period output maximum output minimum setup hold tck 125 ns ? ? ? ? tdi ? ? ? 20 ns 0 ns tms ? ? ? 20 ns 0 ns tdo ? 100 ns 0 ns ? ? jtag_trst 250 ns ? ? ? ?
power-up sequence and timing bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 76 section 14: power-up sequence and timing sequencing of reset and regulator control signals the bcm43364 wl_reg_on signal allows the host to control power consumption by enabling or disabling the wlan and internal regulator blocks. these signals are described below. additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see figure 27 and figure 28 ). the timing values indicated are minimum required values; longer delays are also acceptable. control signal timing diagrams figure 27: wlan = on figure 28: wlan = off note: ? the bcm43364 has an internal power-on reset (por) circuit. the device will be held in reset for a maximum of 110 ms after vddc and vddio have both passed the por threshold (see table 16: ?recommended operating conditions and dc characteristics,? on page 56 ). wait at least 150 ms after vddc and vddio are available before initiating sdio accesses. ? vbat and vddio should not rise faster than 40 s. vbat should be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high. 32.678 khz sleep clock vbat vddio wl_reg_on 90% of vh ~ 2 sleep cycles 32.678 khz sleep clock vbat vddio wl_reg_on
package information bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 77 section 15: package information package thermal characteristics junction temperature estimation and psi versus theta jc package thermal characterization parameter psi-jt ( ? jt ) yields a better estimation of actual junction temperature (t j ) versus using the junction-to-case thermal resistance parameter theta-j c ( ? jc ). the reason for this is ? jc assumes that all the power is dissipated through the top surface of the package case. in actual applications, some of the power is dissipated through the bottom and sides of the package. ? jt takes into account power dissipated through the top, bottom, and sides of the package. the equation for calculating the device junction temperature is as follows: t j = t t + p ?? jt where: ?t j = junction temperature at steady-state condition, c ?t t = package case top center temperature at steady-state condition, c ? p = device power dissipation, watts ? ? jt = package thermal characteristics (no airflow), c/w table 30: package thermal characteristics a a. no heat sink, ta = 70c. this is an estimate based on a 4-layer pcb that conforms to eia/jesd51?7 (101.6 mm x 114.3 mm x 1.6 mm) and p = 1.2w continuous dissipation. characteristic value in still air ? ja (c/w) 53.11 ? jb (c/w) 13.14 ? jc (c/w) 6.36 ? jt (c/w) 0.04 ? jb (c/w) 14.21 maximum junction temperature t j (c) b b. absolute junction temperature limits maintained through active thermal monitoring and dynamic tx duty cycle limiting. 125 maximum power dissipation (w) 1.2
mechanical information bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 78 section 16: mechanical information figure 29 shows the mechanical drawing for the bcm43364 wlbga package. figure 29: 74-ball wlbga mechanical information
mechanical information bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 79 figure 30: wlbga package keep-out areas?top view with the bumps facing down
ordering information bcm43364 preliminary data sheet broadcom confidential broadcom ? single-chip ieee 802.11 b/g/n mac/baseband/radio october 5, 2015 ? 43364-ds102-r page 80 section 17: ordering information part number a a. add a ?t? to the end of the part number to specify ?tape and reel.? package description operating ambient temperature bcm43364kubg 74-ball wlbga halogen-free package (4.87 mm x 2.87 mm, 0.40 pitch) 2.4 ghz single-band wlan ieee 802.11n ?30c to +70c
phone: 949-926-5000 fax: 949-926-5203 e-mail: info@broadcom.com web: www.broadcom.com broadcom corporation 5300 california avenue irvine, ca 92617 ? 2015 by broadcom corporation. all rights reserved. 43364-ds102-r october 5, 2015 broadcom ? corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. bcm43364 preliminary data sheet ?

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