1. general description the 74ahc259-q100; 74ahct259-q100 is a high-speed si-gate cmos device and is pin compatible with low-power schottky ttl (l sttl). it is specified in compliance with jedec standard no. 7-a. the 74ahc259-q100; 74ahct259-q100 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. it is a multifunctional device capable of storing single-line data in ei ght addressable latches. it provides a 3-to-8 decoder and multiplexer function with active high outputs (q0 to q7). it also incorporates an active low common reset (mr ) for resetting all latches as well as an active low enable input (le ). the 74ahc259-q100; 74ahct259-q100 has four modes of operation: ? in the addressable latch mode, data on the data line (d) is written into the addressed latch. the addressed latch follows the data input with all non-addressed latches remaining in their previous states. ? in the memory mode, all latches remain in th eir previous states and are unaffected by the data or address inputs. ? in the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the data input (d) with all other outputs in the low state. ? in the reset mode, all outputs are low and unaffected by the address inputs (a0 to a2) and data input (d). when operating the 74ahc259-q100; 74ahct25 9-q100 as an address latch, changing more than 1 bit of the address could impose a transient-wrong address. therefore, only change more than 1 bit while in the memory mode. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? balanced propagation delays ? all inputs have schmitt-trigger actions ? combines demultiplexer and 8-bit latch ? serial-to-parallel capability 74ahc259-q100; 74ahct259-q100 8-bit addressable latch rev. 1 ? 22 july 2013 product data sheet
74ahc_ahct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 22 july 2013 2 of 19 nxp semiconductors 74ahc259-q100; 74ahct259-q100 8-bit addressable latch ? output from each storage bit available ? random (addressable) data entry ? easily expandable ? common reset input ? useful as a 3-to-8 active high decoder ? inputs accept voltages higher than v cc ? input levels: ? for 74ahc259-q100: cmos level ? for 74ahct259-q100: ttl level ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 3. ordering information table 1. ordering information type number package temperature range name description version 74ahc259-q100 74AHC259D-Q100 ? 40 ? c to +125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74ahc259pw-q100 ? 40 ? c to +125 ? c tssop16 plastic thin shrink sm all outline package; 16 leads; body width 4.4 mm sot403-1 74ahct259-q100 74ahct259d-q100 ? 40 ? c to +125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74ahct259pw-q100 ? 40 ? c to +125 ? c tssop16 plastic thin shrink sm all outline package; 16 leads; body width 4.4 mm sot403-1
74ahc_ahct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 22 july 2013 3 of 19 nxp semiconductors 74ahc259-q100; 74ahct259-q100 8-bit addressable latch 4. functional diagram fig 1. logic symbol fig 2. iec logic symbol mna573 d a0 a1 a2 mr le q0 q1 q2 q3 q4 q5 q6 q7 14 15 12 11 10 9 7 6 5 4 3 2 1 13 mna572 1 9,10d z9 g8 g10 c10 8r 13 15 14 0 1 2 3 1 2 0 dx 0 7 2 3 4 5 4 6 7 9 10 11 12 5 6 7 g fig 3. functional diagram mna571 8 latches 1-of-8 decoder q0 q1 q2 q3 q4 q5 q6 q7 12 11 10 9 7 6 5 4 a0 a1 a2 le mr d 13 15 14 3 2 1
74ahc_ahct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserve d. product data sheet rev. 1 ? 22 july 2013 4 of 19 nxp semiconductors 74ahc259-q100; 74ahct259-q100 8-bit addressable latch 5. pinning information 5.1 pinning 5.2 pin description fig 4. pin configuration $ + & |