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december 2010 doc id 13496 rev 2 1/25 1 l9777 low power voltage regulator features operating dc supply voltage range 5.6 v to 31 v low current consumption (110 a typ @ i out = 0) high precision output voltage (2 %) low dropout voltage vdd tracking regulator switchable on/off by vdd_en pin reset circuit sensing the output voltage down to 1 v. double reset function adjustable reset threshold external capacitor to set nmi/ reset power up delay and watchdog frequency over temperature protection wide temperature range (t j = -40 c to 150 c) short circuit proof suitable for use in automotive electronics description the l9777 is a monolithic integrated low drop regulator which can supply up to 200 ma, available in the powersso-12 package. it is designed to supply microprocessor systems under severe conditions of automotive applications and therefore equipped with additional protection functions against over load, short circuit and over temperature. of course the l9777 can also be used in other applications where a regulated voltage is required. powersso-12 (exp osed die pad) table 1. device summary order code package packing L9777A powersso-12 tray l9777b powersso-12 tray l9777b13tr powersso-12 tape and reel l9777c powersso-12 tray www.st.com
contents l9777 2/25 doc id 13496 rev 2 contents 1 block diagrams and pins configur ation . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 block diagram (option a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 option b features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 option c features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 nmi and reset driver delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 reset adjustable threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 vdd regulated voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 vdd_low (option c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 device options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 option a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 option b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 option c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 electrical and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
l9777 list of tables doc id 13496 rev 2 3/25 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. electrical and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
list of figures l9777 4/25 doc id 13496 rev 2 list of figures figure 1. block diagram (option a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. package pin configuration (options a and b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. block diagram (option b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. block diagram (option c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. package pin configuration (option c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. vcc versus output current ivcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 7. filter time between vcc and nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. reset time diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 9. filter time between nmi and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 10. reset and nmi drivers fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 11. resistor divider to adjust the under voltage threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 12. watchdog timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 13. vdd_low filter tim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. powersso-12 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 23
l9777 block diagrams and pins configuration doc id 13496 rev 2 5/25 1 block diagrams and pins configuration 1.1 block diagram (option a) figure 1. block diagram (option a) 1.2 option b features vdd can sustain short to 40 v regardless of vi battery voltage current capability of vdd scaled down to 50 ma with dropout of 1.5 v (max.) in default condition, vdd and wd functions are disabled using 2 pull down current on vdd_en and wd_en pin standby current consumption reduced to 100 a (typ.) figure 2. package pin configuration (options a and b) watchdog vi vbatt wd d c d timing nmi wd_en gnd vcc c vcc ivcc=200ma voltage reference low voltage reset start up 3r r voff + _ 1.26v reset iwd_en radj delay vdd_en vdd rnmi rreset rwd v d c timing ivdd=100ma c vdd vmuxth 10 ivdd_en vcc reset nmi d vdd_en wd wd_en vi timing vcc vdd gnd radj 1 3 2 4 5 6 10 9 8 7 11 12 pinconfa_b
block diagrams and pins configuration l9777 6/25 doc id 13496 rev 2 figure 3. block diagram (option b) figure 4. block diagram (option c) 1.3 option c features vdd can sustain short to 40 v regardless of vi battery voltage current capability of vdd scaled down to 50 ma with dro pout of 1.5v (max.) in default condition, vdd and wd functions are disabled using 2 pull down current on vdd_en and wd_en pin double reset function removed and pin reset used to detect un dervoltage condition on vdd regulated voltage (vdd_low pin) watchdog vi vbatt wd d c d timing nmi wd_en gnd vcc c vcc ivcc=200ma voltage reference low voltage reset start up 3r r voff + _ 1.26v reset iwd_en radj delay vdd_en vdd rnmi rreset rwd v d c timing ivdd= 50 ma c vdd vmuxth 10 ivdd_en watchdog vi vbatt wd d c d nmi wd_en gnd vcc c vcc ivcc=200ma voltage reference low voltage reset start up 3r r voff + _ 1.26v vdd_low iwd_en radj vdd_en vdd rnmi rvdd_low rwd v d ivdd = 50ma c vdd vmuxth 10 ivdd_en low voltage reset 300mv
l9777 block diagrams and pins configuration doc id 13496 rev 2 7/25 figure 5. package pin configuration (option c) table 2. pin description pin# i/o name function 1 o reset/vdd_low option a & b : reset output. this pin is set low if nmi output goes low for adjustable filter time option c: vdd_low output this pin is set low when undervoltage on vdd is detected 2o nmi non maskable interrupt output this pin is set low when low voltage on vcc is detected or frequency of wd signal is too low. 3i d nmi/reset power up delay. external cap on this pin sets the time response of the vcc low voltage detector and the time re sponse of the watchdog monitor. 4 i vdd_en vdd control. option a: if this pin is low vdd output voltage is not available (connect this pin to vcc or left floating to switch on vdd output voltage) option b & c: if this pin is low or left floating vdd output voltage is not available (connect this pin to vcc to switch on vdd regulator) 5i wd watchdog input. if the frequency at this input pin is too low, the nmi output is activated low 6i wd_en watchdog function enable/disable option a: if this pin is low the watchdog function is disabled, if connected to vcc or left fl oating the watchdog function is enabled. option b & c: if this pin is low or floating, the watchdog function is disabled, if connect ed to vcc the watchdog function is enabled. 7i vi input voltage block to gnd with a capacitor of value at least 100 nf vdd_low nmi d vdd_en wd wd_en vi n.c. vcc vdd gnd radj 1 3 2 4 5 6 10 9 8 7 11 12 pinconfc
block diagrams and pins configuration l9777 8/25 doc id 13496 rev 2 8i timing option a & b: reset filter time external cap on this pin sets the delay time between nmi and reset output option c: not used and should be left floating or shorted to ground. 9o vcc voltage regulator output external cap cvcc 220 nf is needed to stabilize the regulator 10 o vdd vdd output regulated voltage switched on/off by vdd_en pin. external cap cvdd=100 nf is needed to stabilize the regulator 11 gnd ground 12 i radj vcc under voltage threshold adjustment by connecting this pin to an external resistor divider vs. vcc, is possible to set the vcc under voltage threshold. if this pin is connected to gnd the under voltage threshold is set by internal circuit. table 2. pin description (continued) pin# i/o name function
l9777 absolute maximum ratings doc id 13496 rev 2 9/25 2 absolute maximum ratings table 3. absolute maximum ratings symbol parameter min. max. unit input voltage vi v vi voltage -0.3 40 v i vi current intern al limited vcc v vcc voltage -0.3 5.5 v i vcc current intern al limited nmi v nmi voltage -0.3 vcc+0.3 v i nmi current intern al limited d v d voltage -0.3 vcc+0.3 v current intern al limited radj v radj voltage -0.3 vcc+0.3 v i radj current intern al limited wd v wd voltage -0.3 vcc+0.3 v i wd current intern al limited wd_en v wd_en voltage -0.3 vcc+0.3 v i wd_en current intern al limited vdd_en v vdd_en voltage -0.3 vcc+0.3 v i vdd_en current intern al limited reset v reset voltage -0.3 vcc+0.3 v i reset current intern al limited
absolute maximum ratings l9777 10/25 doc id 13496 rev 2 timing vi + 0.3 (opt. a) 40v (opt. b) not connected (opt. c) v timing voltage -0.3 - v i timing current intern al limited vdd v vdd voltage -0.3 vi + 0.3 (opt. a) 40v (opt. b) 40v (opt. c) v i vdd current intern al limited temperature t j junction temperature -40 150 c esd voltage level v esd hbm-mil std 883c -1.5 1.5 kv table 3. absolute maximum ratings (continued) symbol parameter min. max. unit
l9777 functional description doc id 13496 rev 2 11/25 3 functional description 3.1 voltage regulator this device supply an always active 5 v regulated voltage on pin v cc with a current capability up to 200 ma. v cc voltage has an accuracy of 2% over a wide supply voltage (v i = 5.6 v to 31 v) and temperature range (t j = -40 c to 150 c). a short circuit protection to gnd is provided (see figure 6 ). by means of tracking regulator, it is available a second output regulated voltage on pin vdd with a current capability up to 50m a. this regulated output is switchable on/off by external pin vdd_en. figure 6. vcc versus output current ivcc 3.2 reset the reset circuit monitors the output voltage vcc. in case of internal reset threshold, if the output voltage stays lower than vccun for a filter time trr, then nmi goes low. this filter time depends on the distance between the vcc output and the under voltage reset threshold (vccun): this so lution increases the noise immunity of the voltage regulator be-cause the filter time between the reset event and the falling of nmi output changes according to the depth of spike on output voltage (see following picture). a minimum filter time of 1 s (trr1) is guaranteed if vcc goes down to 2.5 v and v s > 5.6 v. figure 7. filter time between vcc and nmi otherwise, in case of external reset threshold fixed by means of external resistor divider on pin radj, there is only a constant filter time (trradj) of 1 s min value. vcc vccref ivcc ishort ilim vcc nmi trr1 vcc nmi v1 trr2 vccun 2.5v
functional description l9777 12/25 doc id 13496 rev 2 in both cases, if the output voltage vcc becomes lower than 2.0v (typ) than nmi may go immediately low without any delay. the nmi low signal is guaranteed for an output voltage vcc greater than 1v. when vcc returns over vccun threshold nmi goes high with a filter time trd. this time is obtained by 127 period of an oscillator with an additional initia l time. the oscillator period is given by: where: icr = 20 a (typ) is a current internally generated, idr = 20 a (typ) is a current internally generated, vdu = 1.24 v and vdrl = 0.62 v are two typical internal thresholds, cd is the external capacitance on pin d. trd is given by: trd (s) = t0 + 127 x tosc = 0.62*10-3 + 7.874* 106 * cd (typ) where t0 is the initial ramp between 0 v and vdu as in figure 8 . figure 8. reset time diagram if nmi output goes to 0 v for filter time tresdf (which is fixed by external cap on timing pin) also the reset signal goes to 0 v. re set low signal is guaranteed for vcc > 1 v. figure 9. filter time between nmi and reset tosc vdu vdrl ? () cd ? [] irc ----------------------------------------------------------- vdu vdrl ? () cd ? [] ird ----------------------------------------------------------- + = trr < trr trd = t0 + 127 tosc tosc trd = t0 + 127 tosc tosc vdu vdrl nmi vd vcc rrun vccun reset tresdf tresdr trr < tresdf < tresdf tresdf vtiming vbgap trd = t0 + 127 tosc nmi reset < tresdf tresdf nmi reset < tresdf tresdf
l9777 functional description doc id 13496 rev 2 13/25 3.3 nmi and reset driver delay nmi and reset pins are driven by bipolar transistor with a maxi mum current capability internally limited of value respectively inmil and iresl. for this reason, when the drivers are activate d, the capacitor s present on pin nmi or reset are discharged with constant current. the waveform on output pin is a voltage ramp with a slope linearly dependent on external capacitance. the fall time needed by drivers to discharge external capacitor can be calculated in first approximation using this expression. where v is the voltage difference between 90% and 10% of total voltage swing of the transition, cext is the total pin capacitance a nd ilim is the current lim itation of the driver (iresl and inmil). figure 10. reset and nmi drivers fall time t fall v c ext ? () i lim ---------------------------- - = reset (v) time (s) 5 90% vsw 10% vsw vsw tfall vresl
functional description l9777 14/25 doc id 13496 rev 2 3.4 reset adjustable threshold the under voltage threshold value (vccun) can be set between 0.7vcc (typ.) and 0.96vcc (typ) by connecting external resistor divider to radj pin (see figure 11 ). this feature can be used with microprocessors that guarantee a safe operation with supply voltage lower than internal reset threshold. the calculation of this threshold is given by: vccun_ext = vradjth (1+r1/r2) (neglecting radj input current) where: vradjth=1.2v (typ) and vccun_ext is the reset threshold. if this features is not needed, radj pin has to be connected to gnd, in this case the internal under voltage threshold value is 0.94*vcc (typ.). figure 11. resistor divider to adjust the under voltage threshold 3.5 watchdog the watchdog input wd monitors a connected microcontroller. if pulses are missing, the output nmi is set to low. the minimum wd frequency to avoid reset event can be set with the external capacitor cd. the watchdog circuit charges and discharges the capacitor cd with the constant currents iwc and iwd, coun ting the number of oscillations as for trd delay time. if no rising edge is sensed on pi n wd between 48 oscillation periods (twop - twol, time a to b in figure 12 ), a watchdog reset is generated. to prevent this reset the microcontroller must generate a positive edge during this time window in order to reset the counter. minimum frequency of microprocessor input signal can be calculated using following equation: twop - twol = 48 * tosc = 2.976*10 6 *cd s every wd positive edge resets the counter and makes a synchronization between internal oscillator and external wd input signal. synchronization is realized changing the current from charging to discharging if rising edge is detected during rising ramp on cd (time d in figure 12 ). otherwise if rising edge is detected during falling ramp on cd, no curren t inversion is performed (time e). this operation leads to a maximum error of half oscillation pe riod on twop - twol time window. when nmi goes low for watchdog reset, the counter will go on for other 16 counts, returning to initial st ate (time b to c in figure 12 ). during this time (twol) the nmi remains low and wd edges are masked, so the twol reset time is fully guaranteed. the watchdog operation is not active only if wd_en input pin is set low. radj vcc l9777 r1 r2
l9777 functional description doc id 13496 rev 2 15/25 in this case the capacitor cd, when not used fo r vcc undervoltage condition, is pulled down to 0v by an active switch. at time f we can see that during twol reset time, wd_en pin is not sensed, so the watch- dog function can be disabled only when twol is finished. in this way a full reset time is guaranteed even in this condition. figure 12. watchdog timing waveforms 0 1 2 3 47 63 0 1 2 3 0 1 5 0 1 2 3 47 48 63 0 wd_en nmi cd 0 1 2 3 47 63 0 1 2 3 0 1 5 0 1 2 3 47 48 63 0 wd_en nmi cd twol twop wd counter twol twop wd counter counter state is incremented when t high threshold is reached he twol 48 osc twol 48 osc the watchdog disable is sensed only when twol is finisched a b c d e f vdthh vdthl 48 osc 16 osc current inversion on cap cd no current inversion reset vdthh vdthl 48 osc 16 osc current inversion on cap cd no current inversion reset tresdf filter time
vdd regulated voltage l9777 16/25 doc id 13496 rev 2 4 vdd regulated voltage l9777 provides a second regulated voltage in tracking with vcc main regulator capable to source load wit h up to 100 ma output current capability. vdd tracking regulator function is controlled by vdd_en input pin. if pin is set high vdd voltage becomes available. if pin is set low or left floating regulator is disabled. note that vdd regulator will be disable also in case of undervoltage condition on vcc main regulator, so at powe r up regulator will start up only when vcc rises over undervoltage threshold without trd power up delay time, even if vdd_en pin is set high.
l9777 vdd_low (option c) doc id 13496 rev 2 17/25 5 vdd_low (option c) vdd_low circuit monitors vdd regulated vo ltage. when vdd falls below vddun for a filter time tfvdd vdd_low output voltage is set low. vddun is a reference voltage 300 mv (t yp) lower than vcc regulated voltage. filter time tfvdd is spike dependent as trr1 for vcc regulator so the same consideration applies also in this case. figure 13. vdd_low filter tim vdd vdd_low tfvdd11 vcc vdd_low vddun - 100mv tfvdd2 vddun 2.5 v
device options l9777 18/25 doc id 13496 rev 2 6 device options 6.1 option a this is the standard configuration with vdd output capable to source up to 100 ma to an external load with low dropout (400 mv max.) and double reset function provided (nmi and reset output). note that as we can see in absolute section vdd and timing pin are capable to sustain only short to vi pin. with this option input digital pins vdd_en and wd_en are both pulled up by 5 a typ current source (minimum quiescent current is 110 a typ.). 6.2 option b with this option vdd and timing pins are both capable to sustain short to 40v regardless of vi battery voltage. to provide this feature a series diode is introduced between vi pin and vdd power pmos source. in this configuratio n current capability on vdd output is scaled down to 50 ma while dropout voltage increases to 1.5v (max). all other features are un- changed and double reset capability is maintained. in option b vdd_en and wd_en are both pulled down with 10 a typ internal current source so minimum quiescent current is reduced to 100 a typ. 6.3 option c using option c vdd is capable to sustain short to 40 v as in option b. vdd output current is scaled down to 50 ma and dropout increase up to 1.5 v (max). double reset feature is removed and reset pi n is used to monitor vdd output voltage (vdd_low pin). a spike dependent filter time similar to vcc main regulator is provided and same low voltage reset specifications applie s to bipolar output driver (vdd_low driver). for this reason timing pin is no more used and can be left floating or shorted to ground. note that nmi output pin behaves normally as in option a and becomes the main reset signal for vcc and watchdog monitor. as in option b vdd_en and wd_en are both pulled down with 10 a typ internal current source so minimum quiescent current is reduced to 100 a typ.
l9777 electrical and thermal characteristics doc id 13496 rev 2 19/25 7 electrical and thermal characteristics v i = 5.6v to 31v, t j = -40c to +150c unless otherwise specified. table 4. electrical and thermal characteristics pin symbol parameter test condition min. typ. max. unit general vcc v ccref output voltage v i = 5.6 to 31 v i vcc = 0 to 200 ma 4.9 5.00 5.1 v vcc i short short circuit current v cc = 0 v 150 250 500 ma vcc i lim1 output current limitation 210 300 600 ma vi, vcc i qs0 current consumption with watchdog not active i qs0 = i vi -i vcc option a v i =13.5 v, i vcc = 0 ma, wd_en = 0 v vdd_en = 0 v (vdd disabled) -110220 a option b v i = 13.5 v, i vcc = 0 ma, wd_en floating or low, vdd_en floating or low (vdd disabled) -100200 a option c v i = 13.5 v, i vcc = 0 ma, wd_en floating or low, vdd_en floating or low (vdd reset active) -400700a i qs200 current consumption iqs200 = i vi -i vcc v i = 13.5 v, i vcc = 200 ma -23ma vi, vcc v dp1 dropout voltage i vcc = 200 ma - 200 400 mv vcc v line1 line regulation voltage v i = 5.6 to 31 v i vcc = 0 to 200 ma -- 25 mv vcc v load1 load regulation voltage i vcc = 0 to 200 ma - - 25 mv vcc svr ripple rejection f r = 100 hz 55 - - db -t w thermal protection temperature - 150 - 190 c -t wh thermal protection temperature hysteresis --10-c nmi nmi v nmil nmi output low voltage r ext = 5 k to v cc , v cc > 1 v - - 0.4 v nmi i nmilk nmi output leakage current v nmi = 5 v - - 1 a nmi r nmi pull up internal resistance - 122550k
electrical and thermal characteristics l9777 20/25 doc id 13496 rev 2 nmi v ccun vcc under voltage threshold radj = 0 v 4.5v 0.94 vcc 0.96 vcc - radj v radjth threshold for vcc under voltage detection - 1.15 1.20 1.25 v radj v rjmuxth threshold for radj multiplexer comparator - 0.52 0.62 0.72 v dvdu nmi timing high threshold - 1.14 1.24 1.34 v d vdrl nmi timing low threshold - 0.52 0.62 0.72 v di rc charge current v i = 13.5 v v d = 0.1 v 10 20 40 a di rd discharge current v i = 13.5 v v d = 2.5 v 10 20 40 a nmi trr1 nmi spike dependent filter time in case of internal reset threshold v cc > 2 v radj = 0v 1- - s nmi trradj nmi fixed filter time in case of external reset threshold external resistor divider on radj (see figure 11 ). v cc > 2 v 12.55 s nmi trd nmi power up delay v i =13.5 v, cd=10 nf 45 80 115 ms nmi i nmil nmi limitation current - 5 - 25 ma reset (option a & b) reset v resl reset output low voltage r ext = 5 k to v cc , v cc > 1 v - - 0.4 v reset i resetlk reset output leakage current ---1 a reset i resl reset limitation current - 5 25 ma reset tresdf reset delay from nmi falling edge c timing = 2.2 nf 350 550 750 s reset t resdr reset delay from nmi rising edge ---1 s reset r reset pull up internal resistance - 122550k vdd_low (option c) vdd_low v vdd_lowl reset output low voltage r ext = 5 k to v cc , v cc > 1 v - - 0.4 v vdd_low i vdd_lowlk reset output leakage current ---1 a vdd_low i vdd_lowl reset limitation current - 5 - 25 ma vdd_low r vdd_low pull up internal resistance - 122550k table 4. electrical and thermal characteristics (continued) pin symbol parameter test condition min. typ. max. unit
l9777 electrical and thermal characteristics doc id 13496 rev 2 21/25 vdd_en vdd_en v vddthl vdd_en input low threshold --- 0.30 v cc v vdd_en v vddthh vdd_en input high threshold - 0.70 v cc --v vdd_en v vddhy vdd_en hysteresis - 200 500 800 mv vdd_en i vdd_en pull up current option a - 2.5 5 10 a vdd_en i vdd_en pull down current option b and c - 5 10 20 a vdd (option a) vdd,vcc diffvr output voltage difference between vdd and vcc i vdd =1 to 100 ma -25 - 25 mv vdd i lim2 vdd output limitation current - 110 200 400 ma vi,vdd v dp2 dropout voltage i vdd =100 ma - 200 400 mv vdd v line2 vdd line regulation voltage v i = 5.6 to 31 v i vdd = 1 to 100 ma --25mv vdd v load2 vdd load regulation voltage i vdd = 1 to 100 ma - - 25 mv vdd (option b) vdd,vcc diffvr output voltage difference between vdd and vcc i vdd = 1 to 50ma v i = 6.6 to 31v -25 - 25 mv vdd i lim2 vdd output limitation current v i = 6.6 to 31v 55 100 240 ma vi,vdd v dp2 dropout voltage i vdd = 50ma; v i = 6.6 to 31v - - 1.5 v vdd v line2 vdd line regulation voltage i vdd = 1 to 50ma v i = 6.6 to 31v - - 25 mv vdd v load2 vdd load regulation voltage i vdd = 1 to 50ma v i = 6.6 to 31v - - 25 mv table 4. electrical and thermal characteristics (continued) pin symbol parameter test condition min. typ. max. unit
electrical and thermal characteristics l9777 22/25 doc id 13496 rev 2 vdd (option c) vdd,vcc diffvr output voltage difference between vdd and vcc i vdd = 1 to 50 ma v i = 6.6 to 31 v -25 - 25 mv vdd i lim2 vdd output limitation current v i = 6.6 to 31 v 55 100 240 ma vi,vdd v dp2 dropout voltage i vdd = 50 ma; vi = 6.6 to 31 v - - 1.5 v vdd v line2 vdd line regulation voltage v i = 6.6 to 31 v i vdd = 1 to 50 ma --25mv vdd v load2 vdd load regulation voltage i vdd = 1 to 50 ma v i = 6.6 to 31 v --25mv vdd v ddun vdd undervoltage threshold v i = 6.6 to 31 v v cc - 400 v cc - 300 v cc - 200 mv vdd t fvdd vdd spike dependent undervoltage filter time vdd transition from 5 v to 4 v 1 - - s wd wd v wdthh input high voltage - - - 0.3 v cc v wd v wdthl input low voltage - 0.7 v cc --v wd v wdhy wd input hysteresis - 250 500 800 mv wd r wd pull down resistor - 15 35 80 k di wdc charge current v d = 0.1 v; v i = 13.5 v 102040 a di wdd discharge current v d = 2.5 v; v i = 13.5 v 102040 a dv dthl low threshold - 0.52 0.62 0.72 v dv dthh high threshold - 1.14 1.24 1.34 v dt wop watchdog period cd =10 nf 20 40 80 ms dt wol watchdog output low time cd =10 nf 5 10 20 ms wd_en wd_en v wentl wd_en input low voltage --- 0.30 v cc - wd_en v wenth wd_en input high voltage - 0.70 v cc --- wd_en v wenhy wd_en input hysteresis - 200 500 800 mv wd_en i wd_en pull up current option a - 2.5 5 10 a wd_en i wd_en pull down current option b and c - 5 10 20 a table 4. electrical and thermal characteristics (continued) pin symbol parameter test condition min. typ. max. unit
l9777 package information doc id 13496 rev 2 23/25 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 14. powersso-12 mechanical data and package dimensions outline and mechanical data 7392413 a 16 12 7 gauge plane 0.25 mm seating plane bottom view h x 45? d c l e e h y x b a a2 c a1 k c ddd dim. mm inch min. typ. max. min. typ. max. a 1.250 1.620 0.049 0.002 a1 0.000 0.100 0.000 0.004 a2 1.100 1.650 0.043 0.065 b 0.230 0.410 0.009 0.016 c 0.190 0.250 0.007 0.010 d (1) 4.800 5.000 0.189 0.197 e 3.800 4.000 0.150 0.157 e 0.800 0.031 h 5.800 6.200 0.228 0.244 h 0.250 0.500 0.010 0.020 l 0.400 1.270 0.016 0.050 k0?8?0?8? x 1.900 2.500 0.075 0.098 y 3.600 4.200 0.142 0.165 ddd 0.100 0.004 note: 1. d does not include mold flash or protrusions or gate burrs. mold flash potrusions or gate burrs shall not ex- ceed 0.15mm (.006inch) in total. powersso-12 (exposed pad)
revision history l9777 24/25 doc id 13496 rev 2 9 revision history table 5. revision history date revision description of changes 10-may-2007 1 initial release. 14-dec-2010 2 changed esd parameter values in ta b l e 3 . modified section 1.3: option c features on page 6 . modified section 6.3: option c on page 18 . updated table 4: electrical and thermal characteristics on page 19 . document status promoted from preliminary data to datasheet.
l9777 doc id 13496 rev 2 25/25 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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