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1 datasheet low noise, low power, 100 taps, digitally controlled potentiometer (xdcp?) x9317 the intersil x9317 is a digitally controlled potentiometer (xdcp?). the device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. the wiper position is controlled by a 3-wire interface. the potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switching network. between each element and at either end are tap points accessible to the wiper terminal. the position of the wiper element is controlled by the cs , u/d , and inc inputs. the position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. the device can be used as a three-terminal potentiometer for voltage control or as a two-termin al variable resistor for current control in a wide variety of applications. applications ?lcd bias control ? dc bias adjustment ? gain and offset trim ? laser diode bias control ? voltage regulator output control features ? solid-state potentiometer ? 3-wire serial up/down interface ? 100 wiper tap points - wiper position stored in nonvolatile memory and recalled on power-up ? 99 resistive elements - temperature compensated - end-to-end resistance range 20% ?low power cmos -v cc = 2.7v to 5.5v, and 5v 10% - standby current <5a ? high reliability - endurance, 100,000 data changes per bit - register data retention, 100 years ?r total values = 10k , 50k , 100k ?packages - 8 ld soic, tssop, and msop ? pb-free (rohs compliant) up/down counter 7-bit nonvolatile memory store and recall control circuitry one of one decoder resistor array r h u/d inc cs wiper switches hundred v cc v ss r l r w control and memory up/down (u/d ) increment (inc ) device select (cs ) v cc (supply voltage) v ss (ground) r h r w r l general detailed 0 1 2 96 97 98 99 figure 1. block diagram november 4, 2014 fn8183.9 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2004, 2005, 2008, 2009, 2012, 2014. all rights reserved intersil (and design) and xdcp are trademarks owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
x9317 2 fn8183.9 november 4, 2014 submit document feedback ordering information part number ( notes 1 , 2 , 3 )part marking v cc limits (v) r total (k ) temperature range (c) package (pb-free) pkg. dwg. # x9317wm8z dcw 5 10% 10 0 to +70 8 ld msop m8.118 x9317wm8iz dct -40 to +85 8 ld msop m8.118 x9317ws8z x9317w z 0 to +70 8 ld soic m8.15e x9317ws8iz x9317w zi -40 to +85 8 ld soic m8.15e x9317wv8z 9317w z 0 to +70 8 ld tssop m8.173 x9317wv8iz 9317w iz -40 to +85 8 ld tssop m8.173 x9317um8z dcs 50 0 to +70 8 ld msop m8.118 x9317um8iz dcr -40 to +85 8 ld msop m8.118 x9317us8z x9317u z 0 to +70 8 ld soic m8.15e x9317us8iz x9317u zi -40 to +85 8 ld soic m8.15e x9317uv8z 9317u z 0 to +70 8 ld tssop m8.173 x9317uv8iz 9317u iz -40 to +85 8 ld tssop m8.173 x9317tm8z dcn 100 0 to +70 8 ld msop m8.118 x9317tm8iz dcl -40 to +85 8 ld msop m8.118 x9317ts8z x9317t z 0 to +70 8 ld soic m8.15e x9317ts8iz x9317t zi -40 to +85 8 ld soic m8.15e x9317tv8z 9317t z 0 to +70 8 ld tssop m8.173 x9317tv8iz 9317t iz -40 to +85 8 ld tssop m8.173 x9317wm8z-2.7 dcx 2.7 to 5.5 10 0 to +70 8 ld msop m8.118 x9317wm8iz-2.7 dcu -40 to +85 8 ld msop m8.118 x9317ws8z-2.7 x9317w zf 0 to +70 8 ld soic m8.15e x9317ws8iz-2.7 x9317w zg -40 to +85 8 ld soic m8.15e x9317wv8z-2.7 9317w fz 0 to +70 8 ld tssop m8.173 x9317wv8iz-2.7 akz -40 to +85 8 ld tssop m8.173 x9317um8z-2.7 aob 50 0 to +70 8 ld msop m8.118 x9317um8iz-2.7 aoh -40 to +85 8 ld msop m8.118 x9317us8z-2.7 x9317u zf 0 to +70 8 ld soic m8.15e x9317us8iz-2.7 x9317u zg -40 to +85 8 ld soic m8.15e x9317uv8z-2.7 9317u fz 0 to +70 8 ld tssop m8.173 x9317uv8iz-2.7 9317u gz -40 to +85 8 ld tssop m8.173 x9317tm8z-2.7 dcp 100 0 to +70 8 ld msop m8.118 x9317tm8iz-2.7 dcm -40 to +85 8 ld msop m8.118 x9317ts8z-2.7 x9317t zf 0 to +70 8 ld soic m8.15e x9317ts8iz-2.7 x9317t zg -40 to +85 8 ld soic m8.15e x9317tv8z-2.7 9317t fz 0 to +70 8 ld tssop m8.173 x9317tv8iz-2.7 9317t gz -40 to +85 8 ld tssop m8.173 notes: 1. add ?t1? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec jstd-020. 3. for moisture sensitivity level (msl), please see device information page for x9317 . for more information on msl please see tech brief tb363 .
x9317 3 fn8183.9 november 4, 2014 submit document feedback pin configurations x9317 (8 ld tssop) top view x9317 (8 ld soic, 8 ld msop) top view inc r l cs v cc 1 2 3 4 8 7 6 5 u/d r w v ss r h r h v cc inc u/d 1 2 3 4 8 7 6 5 v ss cs r l r w pin descriptions soic/msop tssop symbol brief description 13inc increment toggling inc while cs is low moves the wiper either up or down. 24u/d up/down the u/d input controls the direction of the wiper movement. 35r h the high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer. 46v ss ground 57r w the wiper terminal is equivalent to the movable terminal of a mechanical potentiometer. 68 r l the low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer. 71cs chip select the device is selected when the cs input is low, and de-selected when cs is high. 82v cc supply voltage
x9317 4 fn8183.9 november 4, 2014 submit document feedback absolute maximum rating s thermal information i w (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8ma r h , r w , r l to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6v voltage on cs , inc , u/d and v cc with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1v to +7v thermal resistance (typical) ? ja (c/w) ? jc (c/w) soic package ( notes 4 , 5 ) . . . . . . . . . . . . . 115 60 msop package ( notes 4 , 5 ) . . . . . . . . . . . . 145 55 tssop package ( notes 4 , 5 ). . . . . . . . . . . . 155 49 junction temperature under bias . . . . . . . . . . . . . . . . . . . -65 ? c to +135 ? c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for ? jc , the ?case temp? location is taken at the package top center. potentiometer specifications v cc = full range. boldface limits apply across the operat ing temperature range, -40c to +85c (industrial) and 0c to +70c (commercial). symbol parameter test conditions/notes min ( note 13 ) typ ( note 9 ) max ( note 13 )unit r total end-to-end resistance toleranc e see ?ordering information? on page 2 for values -20 +20 % v rh / rl r h /r l terminal voltage v ss = 0v v ss v cc v power rating r total 10k 10 mw r w wiper resistance i w = [v(r h ) - v(r l )]/ r total , v cc = 5v 200 400 i w = [v(r h ) - v(r l )]/ r total , v cc = 2.7v 400 1000 i w wiper current ( note 10 ) see ? test circuit ? on page 5 -4.4 +4.4 ma noise ( note 12 ) ref: 1khz -120 dbv resolution 1% absolute linearity ( note 6 )v(r h ) = v cc , v(r l ) = 0v -1 +1 mi ( note 8 ) relative linearity ( note 7 )v(r h ) = v cc , v(r l ) = 0v -0.2 +0.2 mi ( note 8 ) r total temperature coefficient ( note 10 )v(r h ) = v cc , v(r l ) = 0v 300 ppm/c ratiometric temperature coefficient ( notes 10 , 11 ) 20 ppm/c c h /c l /c w ( note 10 ) potentiometer capacitances see ? equivalent circuit ? on page 5 10/10/25 pf v cc supply voltage x9317 4.5 5.5 v x9317-2.7 2.7 5.5 v
x9317 5 fn8183.9 november 4, 2014 submit document feedback dc electrical specifications v cc = 5v 10%. boldface limits apply across the operat ing temperature range, -40c to +85c (industrial) and 0c to +70c (commercial). symbol parameter test conditions min ( note 13 ) typ ( note 9 ) max ( note 13 )unit i cc1 v cc active current (increment) cs = v il , u/d = v il or v ih and inc =v il /v ih at min. t cyc r l , r h , r w not connected 80 a i cc2 v cc active current (store) (non-volatile write) cs = v ih , u/d = v il or v ih and inc = v il or v ih . r l , r h , r w not connected 400 a i sb standby supply current cs ? v ih , u/d and inc =v il r l , r h , r w not connected 5 a i li cs , inc , u/d input leakage current v in = v ss to v cc -10 +10 a v ih cs , inc , u/d input high voltage v cc x 0.7 v cc + 0.5 v v il cs , inc , u/d input low voltage -0.5 v cc x 0.1 v c in ( note 10 )cs , inc , u/d input capacitance v cc = 5v, v in = v ss , t a = +25c, f = 1mhz 10 pf endurance and data retention v cc = 5v 10%, t a = full operating temperature range. parameter min unit minimum endurance 100,000 data changes per bit data retention 100 years test circuit equivalent circuit force current test point r w c h c l r w 10pf 10pf r total c w 25pf r h r l ac conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input reference levels 1.5v ac electrical specifications v cc = 5v 10%. boldface limits apply across the operat ing temperature range, -40c to +85c (industrial) and 0c to +70c (commercial). symbol parameter min ( note 13 ) typ ( note 9 ) max ( note 13 )unit t cl cs to inc setup 50 ns t ld ( note 10 )inc high to u/d change 100 ns t di ( note 10 )u/d to inc setup 1 s t ll inc low period 960 ns t lh inc high period 960 ns t lc inc inactive to cs inactive 1 s t cphs cs deselect time (store) 10 ms t cphns ( note 10 ) cs deselect time (no store) 100 ns t iw inc to r w change 1 5 s t cyc inc cycle time 2 s
x9317 6 fn8183.9 november 4, 2014 submit document feedback power-up and down requirements the recommended power-up sequence is to apply v cc /v ss first, then the potentiometer voltages. during power-up, the data sheet parameters for the dcp do not fully apply until 1ms after v cc reaches its final value. the v cc ramp spec is always in effect. in order to prevent unwanted tap position changes, or an inadvertent store, bring the cs and inc high before or concurrently with the v cc pin on power-up. t r , t f ( note 10 ) inc input rise and fall time 500 s t pu ( note 10 ) power-up to wiper stable 5 s t r v cc ( note 10 ) v cc power-up rate 0.2 50 v/ms t wr store cycle 5 10 ms notes: 6. absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [v(r w(n)(actual) )-v(r w(n)(expected) )]/mi v(r w(n)(expected) ) = n(v(r h )-v(r l ))/99 + v(r l ), with n from 0 to 99. 7. relative linearity is a measure of the error in step size between taps = [v(r w(n+1) )-(v(r w(n) ) - mi)]/mi. 8. 1 ml = minimum increment = [v(r h )-v(r l )]/99. 9. typical values are for t a = +25c and nominal supply voltage. 10. this parameter is not 100% tested. 11. ratiometric temperature coefficient = (v(r w ) t1(n) -v(r w ) t2(n) )/[v(r w ) t1(n) (t1-t2) x 10 6 ], with t1 and t2 being 2 temperatures, and n from 0 to 99. 12. measured with wiper at tap position 99, r l grounded, using test circuit. 13. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established b y characterization and are not production tested. ac electrical specifications v cc = 5v 10%. boldface limits apply across the operat ing temperature range, -40c to +85c (industrial) and 0c to +70c (commercial). (continued) symbol parameter min ( note 13 ) typ ( note 9 ) max ( note 13 )unit
x9317 7 fn8183.9 november 4, 2014 submit document feedback ac timing typical performance characteristic cs inc u/d r w t ci t il t ih t cyc t id t di t iw mi (3) t ic t cphs t f t r 10% 90% 90% t cphns -55 -350 -300 -250 -200 -150 -100 -50 0 -45 -35 -25 -15 -5 5 15 25 35 temperature (c) ppm 45 55 65 75 85 95 105115 125 figure 2. typical total resistance temperature coefficient
x9317 8 fn8183.9 november 4, 2014 submit document feedback pin descriptions r h and r l the high (r h ) and low (r l ) terminals of the x9317 are equivalent to the fixed terminals of a mechanical potentiometer. the terminology of r l and r h references the relative position of the terminal in relation to wiper movement direction selected by the u/d input and not the voltage potential on the terminal. r w r w is the wiper terminal and is equivalent to the movable terminal of a mechanical potent iometer. the position of the wiper within the array is determined by the control inputs. the wiper terminal series resistance is typically 200 . up/down (u/d ) the u/d input controls the direction of the wiper movement and whether the counter is incremented or decremented. increment (inc ) the inc input is negative-edge triggered. toggling inc will move the wiper and either increment or decrement the counter in the direction indicated by th e logic level on the u/d input. chip select (cs ) the device is selected when the cs input is low. the current counter value is stored in nonvolatile memory when cs is returned high while the inc input is also high. after the store operation is complete, the x9317 will be placed in the low power standby mode until the device is selected once again. principles of operation there are three sections of the x9317: the control section, the nonvolatile memory, and the resist or array. the control section operates just like an up/down counter. the output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. the contents of the counter can be stored in nonvolatile memory and retained for future use. the resistor array is comprised of 99 individual resistors connected in series. electronic switches at either end of the array and between each resistor provide an electrical connection to the wiper pin, r w . the wiper acts like its mechanical equivalent and does not move beyond the first or last position. that is, the counter does not wrap around when clocked to either extreme. the electronic switches on the device operate in a ?make before break? mode when the wiper changes tap positions. if the wiper is moved several positions, multiple taps are connected to the wiper for t iw (inc to v w change). the r total value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. when the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. when power is restored, the contents of the memory are recalled and the wiper is set to the value last stored. instructions and programming the inc , u/d and cs inputs control the movement of the wiper along the resistor array. with cs set low, the device is selected and enabled to respond to the u/d and inc inputs. high-to-low transitions on inc will increment or decrement (depending on the state of the u/d input) a 7-bit counter. the output of this counter is decoded to select one of on e hundred wiper positions along the resistive array. the value of the counter is stored in nonvolatile memory whenever cs transitions high while the inc input is also high. the system may select the x9317, move the wiper and deselect the device without having to stor e the latest wiper position in nonvolatile memory. after the wiper movement is performed as previously described and once the new position is reached, the system must keep inc low while taking cs high. the new wiper position will be maintained until changed by the system or until a power-up/down cycle recalls the previously stored data. this procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments co uld be made. the adjustments might be based on user preference, system parameter changes due to temperature drift, etc. the state of u/d may be changed while cs remains low. this allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. applications information electronic digitally controlled (xdcp) potentiometers provide three powerful application advantages: 1. the variability and reliability of a solid-state potentiometer, 2. the flexibility of computer-based digital controls, and 3. the retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. mode selection cs inc u/d mode lhwiper up l l wiper down h x store wiper position to nonvolatile memory hxxstandby l x no store, return to standby l h wiper up (not recommended) l l wiper down (not recommended)
x9317 9 fn8183.9 november 4, 2014 submit document feedback basic configurations of electronic potentiometers figure 3. three terminal potentiometer; variable voltage divider figure 4. two terminal variable resistor; variable current v ref r w r h r l v ref i basic circuits figure 5. buffered reference volt age figure 6. cascading techniques figure 7. single supply inverting amplifier figure 8. voltage regulator figure 9. offset voltage adjustment figure 10. comparator with hysteresis - + +5v r 1 +v v ref v out lmc7101 v out = v w /r w r w r w r w +v +v +v x (a) (b) + - r 1 v o lmc7101 r 2 +5v 100k 100k +5v v s v o = (r2/r1)v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + - v s v o r 2 r 1 100k 10k 10k 10k +5v lmc7101 +5v v ul = {r 1 /(r 1 +r 2 )} v o (max) v ll = {r 1 /(r 1 +r 2 )} v o (min) + - v s v o r 2 r 1 } lt311a }
x9317 10 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8183.9 november 4, 2014 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change november 4, 2014 fn8183.9 added revision history converted to new template and added new intersil standards. updated ordering information to show all u parts in column for rtotal (k ) to show 50 as the value. added thermal information (tja and tjc).
x9317 11 fn8183.9 november 4, 2014 submit document feedback package outline drawing m8.118 8 lead mini small outline plastic package rev 4, 7/11 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.25 - 0.36 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 8 0.85010 seating plane a 0.65 bsc 3.00.05 4.90.15 (0.40) (1.40) (0.65) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-aa plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m
x9317 12 fn8183.9 november 4, 2014 submit document feedback package outline drawing m8.173 8 lead thin shrink small outline package (tssop) rev 2, 01/10 notes: end view detail "x" typical recommended land pattern top view b a c plane seating 0.10 c 0.10 c b a h 3.0 0.5 4.40 0.10 0.25 +0.05/-0.06 6.40 0.20 c b a 0.05 0-8 gauge plane see detail "x" 0.90 +0.15/-0.10 0.60 0.15 0.09-0.20 6 3 4 2 4 1.00 ref 0.65 1.20 max 0.25 0.05 min 0.15 max (5.65) (0.65 typ) (0.35 typ) (1.45) 1 c l pin 1 id mark 4 5 8 package body outline side view 2. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall 3. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.15 per side. 4. dimensions are measured at datum plane h. not exceed 0.15 per side. 5. dimensioning and toleranc ing per asme y14.5m-1994. 6. dimension on lead width does not include dambar protrusion. allowable protrusion shall be 0.08 mm total in excess of dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm. 7. conforms to jedec mo-153, variation ac. issue e dimensions in ( ) for reference only. 1. dimensions are in millimeters.
x9317 13 fn8183.9 november 4, 2014 submit document feedback package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise specified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side. dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view ?a typical recommended land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view ?b?

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