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advance product information this document contains information for a product under development. cirrus logic reserves the right to modify this produ ct without notice. copyright ? cirrus logic, inc. 2010 (all rights reserved) cirrus logic, inc. http://www.cirrus.com cs1500 digital power factor correction ic features & description ? digital emi noise shaping ? excellent efficiency under all load conditions ? minimal external devices required ? optimized digital loop compensation ? comprehensive safety features ? undervoltage lockout (uvlo) ? output overvoltage protection ? input current limiting ? output overpower protection ? input brownout protection ? open/short loop protection for iac & fb pins ? thermal shutdown description the cs1500 is a high-performance power factor correction (pfc) controller for universal ac input, which uses a proprietary digital algorithm for discontinuous conduction mode (dcm) with variable on-time and variable frequency control, ensuring unity power factor. the cs1500 incorporates all the safety features necessary for robust and compact pfc stages. in addition, it has burst mode control to lower the light-load/standby losses to a minimum. protection features such as ov ervoltage, overcurrent, overpower, open- and short-circuit protection, overtemperature, and brownout help protect the device during abnormal transient conditions. the digital controller optimize s the system stability and transient performance, simplifies the pfc design, reduces the external component count and bom costs. the simple design and minimum cost makes cs1500 the ideal choice for pfc up to 300 watts. pin assignments nc stby iac fb nc vdd gd gnd 1 2 3 4 8 7 6 5 8-lead soic d2 c1 d1 cs1500 c2 l b c3 q1 6 2 8 5 7 3 1 r1a r1 b r2a r2b r3 fb gd nc stby gnd vdd iac nc r ac r fb br1 ac mains regulated dc output 4 vdd jul ?10 ds849a7 jul ?$shortyear> confidential
cs1500 2 ds849a7 jul ?$shortyear> confidential table 1. pin descriptions pin name pin # i/o description nc 1, 8 - nc ? no connections stby 2in remote on/off control ? a voltage below 0.8 v shuts down the ic (not latched) and brings the device into low power consumption mode. the input has an internal 600 k pull-up resistor to the vdd pin and should be driven with an open-collector device. iac 3in rectifier voltage sense ? a current proportional to the rectified line voltage (v rect ) is fed into this pin. the current is measured with an a/d converter. fb 4in link voltage sense ? a current proportional to the output link voltage (v link ) of the pfc is fed into this pin. the current is measured with an a/d converter. gnd 5- ground ? current return for both the input signal portion of the ic and the gate driver. gd 6out gate driver output ? the totem pole stage is able to drive the power mosfet with a peak current of 0.5 a source and 1.0 a sink. the high-level voltage of this pin is clamped at v z to avoid excessive gate voltages. vdd 7in ic supply voltage ? supply voltage of both the input signal portion of the ic and the gate driver.
cs1500 ds849a7 3 jul ?$shortyear> confidential 1. characteristics and specifications 1.1 absolute maximum ratings 1.2 electrical characteristics (t a = 25o c, v dd = 13v, -40o < t j < +125o c, c l =1nf between pin gd and gnd, all voltages are measured with respect to gnd; all current are positive when flowing into the ic; unless otherwise specified). recommended v dd = 10 ? 15 v. pin symbol parameter value unit 7v dd ic supply voltage v z v 1,2,3,4,8 - analog input ma ximum voltage -0.5 to v z v 3,4 - analog input maximum current 50 ma 6v gd gate drive output voltage -0.3 to v z v 6i gd gate drive output current -1.0 / +0.5 a -p d total power dissipation @ t a =50 c 600 mw t a operating ambient temperature range 1 -40 to +125 oc -t j junction temperature operating range -40 to +125 oc -t stg storage temperature range -65 to +150 oc parameter condition symbol min typ max unit vdd supply voltage turn-on threshold voltage v dd increasing v dd(on) 8.4 8.8 9.3 v turn-off threshold voltage (uvlo) v dd decreasing v dd(off) 7.1 7.4 7.9 v uvlo hysteresis v hys -1.3-v zener voltage i dd =20ma v z 16.8 17.9 18.5 v vdd supply current start-up supply current v dd =v dd(on) i st -6880 a standby supply current stby <0.8v i sb -80112 a operating supply current c l =1nf, f sw(max) =70khz i dd -1.71.9ma pfc gate drive maximum operating frequency 6 v dd = 13v f sw(max) 62 66 70 khz minimum operating frequency 6 v dd = 13v f sw(min) 20 22 23 khz maximum duty cycle 6 v dd = 13v d max 64 66 68 % output source resistance i gd =100ma,v dd = 13v r oh -9- output sink resistance i gd = -200ma,v dd = 13v r ol -6- rising time c l =1nf,v dd = 13v t r -3260ns falling time c l =1nf,v dd = 13v t f -1530ns output voltage low state i gd = -200ma,v dd = 13v vol - 0.9 1.3 v output voltage high state i gd =100ma,v dd = 13v voh 11.3 11.8 - v
cs1500 4 ds849a7 jul ?$shortyear> confidential notes: 1. specifications guaranteed by design & characterization and correlation with statistical process controls. 2. specification are based upon a pf c system configured for ac input of 90-265 vac (sine), 45/65 hz, v link =400v, r ac =3x1.0 m , r fb =3x1.0 m , c3 = 180 f, l b = 360 h, 90 w. for other v link voltages, refer to section 4 application example. 3. detailed calculation see section 4 application example. 4. overpower protection is scaled to rated power. 5. stby is designed to be driven by an open collector. the input is internally pulled up with a 600 k resistor. 6. normal operation mode, see section 3.2. 1.3 thermal characteristics 7. the package thermal impedance is calculated in accordance with jesd 51. feedback & protection 2,3 reference current 1 25o c i ref -129- a output voltage at star tup mode 25o c, 115 vac v o(startup) -360-v output voltage at normal mode v o(nom) -400-v overvoltage protection threshold 25o c, 115 vac v ovp 415 418 421 v overvoltage protection hysteresis v ovp(hy) -4-v overpower protection threshold 2,4 25o c, 115 vac - 130 - % overpower protection recovery 2,4 25o c, 115 vac - 100 - % input brownout protection thre shold 25o c, gdrv turns off v bp(th) 62 65 69 vrms input brownout recovery threshold 25o c, gdrv turns on v br 76 80 83 vrms thermal protection 1 thermal shutdown threshold t sd 130 143 155 oc thermal shutdown hysteresis t sd(hy) -9-oc stby input 5 logic threshold low - - 0.8 v logic threshold high vdd-0.8 - - v symbol parameter value unit r ja thermal resistance (junction to ambient) 7 . 159 oc / w r jc thermal resistance (junction to case) 7 . 39 oc / w parameter condition symbol min typ max unit
cs1500 ds849a7 5 jul ?$shortyear> confidential 2. typical electrical performance 0 0.5 1 1.5 2 2.5 3 3.5 0 2 4 6 8 10 12 14 16 18 20 v dd (v) i dd (ma) c l = 1 nf f sw(max) = 70 khz t a = 25 c falling rising 7 8 9 10 11 12 13 -50 0 50 100 150 temp ( o c) v dd (v) startup uvlo 0 0.5 1 1.5 2 -50 0 50 100 150 temp ( o c) uvlo hysteresis (v) 17 17.5 18 18.5 19 -50 0 50 100 150 temp ( o c) v z (v) i dd = 20 ma figure 1. supply current s. supply vo ltage figure 2. start-up uvlo s. temp figure 3. uvlo hysteresis s. temp figure 4. vdd ener voltage s. temp
cs1500 6 ds849a7 jul ?$shortyear> confidential 385 390 395 400 405 410 415 420 425 -50 0 50 100 150 temperature (c) v link (v) ovp normal frequency (khz) min freq max freq temp ( o c) 0 10 20 30 40 50 60 70 80 90 100 -60 -40 -20 0 20 40 60 80 100 120 140 0 2 4 6 8 10 12 14 -60 -40 -20 0 40 100 120 140 gate resistor (r oh , r ol ) temp ( o c) z out (ohm) source sink v dd = 13 v i source = 100 ma i sink = 200 ma 20 60 80 -50 0 50 100 150 tem p ( o c) supply current (ma) start-up standby 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 operating v dd = 13 v c l = 1 nf f sw(max) = 70 khz start-up standby figure 5. supply current (i s i st i dd ) s. temp figure 6. minmax operating frequency s. temp figure 7. ate resistance (r oh r ol ) s. temp figure 8. ovp s. temp
cs1500 ds849a7 7 jul ?$shortyear> confidential 3. introduction figure 9. cs1500 block diagram the cs1500 digital power factor controller operates in variable on-time, variable frequency, discontinuous conduction mode (dcm). the cs1500 uses a proprietary digital algorithm to maximize the efficiency and reduce the conductive emi. the analog-to-digital converter (adc) shown in the cs1500 block diagram in figure 9 is used to sense the pfc output voltage ( v link ) and the rectified ac line voltage ( v rect ) by measuring currents through thei r respective resistors. the magnitudes of these currents are measured as a proportion of a reference current (i ref ) that functions as the reference for the adcs. the digital signal is then processed in a control algorithm which determines the behavior of the cs1500 during start-up, normal operation, and under fault conditions, such as brownout, overvoltage, overcurrent, overpower, and over-temperature conditions. ? dcm with variable on-time, variable switching fre- quency the cs1500 pfc switching frequency varies with the v rect on a cycle-by-cycle basis, and its digi tal algorithm calculates the on-time accord ingly for unity power factor. unlike traditional critical conduction mode (crm) pfc controller, cs1500 operates at its low switching frequen- cy near the zero-crossing point of the ac input voltage, even no switching at all, and it operates at its high switch- ing frequency at the peak of its ac input voltage (this is the opposite of the switchin g frequency profile for a crm pfc controller), thus cs1500 reduces switching losses especially under light-load conditions, spreads conducted emi energy peaks over a wide frequency band and in- creases overall system efficiency. ? optimized digital loop compensation the proprietary digital control engine optimizes the feed- back error signal using an adaptive control algorithm, im- proves system stability an d transient response. no external feedback error signal compensation components are required. ? overcurrent mitigation the cs1500s digital controller algorithm limits the on time of the power mosfet by the following equation: where t on is the max time that the power mosfet is turned on and v rect is the rectified line voltage. in the event of a sudden line surge or sporadic, high dv/dt line voltages, this equation may not limit the on time appro- priately. for this type of li ne disturbance, additional pro- tection mechanisms such as fusible resistors, fast-blow fuses, or other current-limiting devices are recommend- ed. ? over voltage protection under steady-state conditio ns, the voltage loop keeps pfc output voltage close to it s nominal value. under light load startup or feedback loop open conditions, the output voltage may pass the overvoltage protection threshold. the digital control engine initiates a fast response loop to shut down gate driving signal to reduce the energy deliv- ered to the output for pfc c apacitor protection. when the link voltage drop below v ovp -v ovp(hy) , pfc resumes normal operation. iac fb stby 3 4 2 cs1500 gd 6 vdd 7 nc 8 gnd 5 processor logic nc 1 pwm driver oscillator protection adc ------------------------ -
cs1500 8 ds849a7 jul ?$shortyear> confidential 3.1 pfc operating frequency one key feature of the cs1500 is its operating frequency profile. figure 10 illustrates how the frequency varies over half cycle of the line voltage in steady-state operation. when power is first applied to the cs150 0, it first examines the line voltage and adapts its operating frequency to the exposed line voltage as shown in figure 11. the operating frequency is varied in about a 2-to-1 ratio from the peak to the trough. during start-up the control algorithm limits the maximum on- time, provides nearly squar e-wave envelop current within every half line cycle by adjusting the operating frequency for fast startup behavior. figure 10. switching frequency vs. phase angle figure 11. switching frequency vs. output power figure 11 illustrates how the operating frequency (as a percentage of maximum frequency) changes with output power and the peak of the line voltage. burst mode (when p o below 5%) will be discussed in a later section. the cs1500 is designed to function as a dcm (discontinuous conduction mode) controller, however it may operate in a quasi-crm operation mode near the peak periods. for 90~265vac main input applications, pfc can be also designed in quasi-crm at a peak of 90vac and full load as shown in figure 12. figure 12. dcm and quasi-crm operation with cs1500 3.2 start-up vs. norm al operation mode cs1500 has two discrete operation modes: start-up and normal. start-up mode will be activated when v link is less than 90% of nominal value and remains active until v link reaches 100% of nominal value, as shown in figure 13. startup mode is activated duri ng initial system power-up. any v link drop to less than 90% of nominal value, such as load change, can cause the system to enter start-up mode until v link is brought back into regulation. figure 13. start-up and normal modes 3.3 burst mode burst mode is utilized to im prove system efficiency when the system output power (p o ) is < 5% of nominal. burst mode is implemented by intermittently disabling the pfc over a full half-line period cycle under light load conditions, as shown in figure 14. 0 20 40 60 80 100 120 04590135180 rectified line voltage phase (deg.) % of max switching freq. (% of max.) line voltage (% of max.) % p o max f sw max (khz) vin < 150 vac 20 70 50 60 40 40 5 burst mode 20 0 60 80 100 vin > 150 vac 46 56 dcm quasi crm dcm quasi crm dcm i lb t [ms] i ac inductor current t [ms] v link [v] 100% 90% startup mode normal mode startup mode normal mode
cs1500 ds849a7 9 jul ?$shortyear> confidential figure 14. burst modes 3.4 output power and pfc boost inductor maximum output power in normal mode is defined by the following equation: where, v in(min) , v link , and l b are user defined based on application requirements and maximum operating switching frequency f max = 70khz. is a margin factor to guarantee rated power (p o ) against tolerances and transients. is typically set to 0.9. the pfc boost inductor (lb in figure 21) value can be calculated using equation 1 as follows: where v in(min) is volts rms, v link is volts dc, and is set to 0.9. 3.5 pfc output capacitor the value of the pfc output capacitor should be chosen based upon voltage ripple and hold-up requirements. this is described in more detail in the application section 4.1.6 pfc output capacitor on page 13. to ensure system stability with the digital controller, the recommended value of the capacitor is within the range of 0.5 f / watt to 2.0 f/watt. 3.6 output feedb ack & regulation a current proportional to the pfc output voltage, v link , is supplied to the ic on pin fb and is used as a feedback control signal. this current is compared against a fixed-value internal reference current, i ref . resistor r fb (shown as r2a & r2b in figure 21) sets the feedback current and is calculated as follows: figure 15. feedback input pin model the adc is used to measur e the magnitude of the i fb current through resistor r fb . the magnitude of the i fb current is then compared to an internal reference current, i ref . by using digital loop compensation, the voltage feedback signal does not require an external compensation network. it is recommended that a ceramic capacitor of up to 2.2 nf be placed between the fb pin and t he vdd pin to filter noise in the layout. 3.7 iac signal figure 16. iac input pin model a current proportional to the ac input voltage is supplied to the ic on pin iac and is used by the pfc control algorithm. resistor r ac (shown as r1a & r1b in figure 21) sets the iac current and is calculated as follows: for optimal performance, resistor r ac , r fb should use less than 1% tolerance resistor. resistors can be separated in two v in [v] t [ms] fet v gs burst mode active v in p o [w] t [ms] pfc disable burst threshold p o v in min () () 2 v link v in min () 2 () ? 2f max l b v link --------------------------------------------------------- = [eq.1] l b v in min () () 2 v link v in min () 2 () ? 2f max p o v link --------------------------------------------------------- = [eq.2] r fb v link v dd ? i ref --------------------------- - = [eq.3] r fb i fb vdd adc v link 7 fb 4 r ac i ac iac vdd adc 7 3 v rect r ac r fb = [eq.4]
cs1500 10 ds849a7 jul ?$shortyear> confidential or more series elements if voltage breakdown or regulatory compliance is of concern. it is recommended that a ceramic capacitor of up to 2.2 nf be placed between the iac pin and the vdd pin to filter noise in the layout. 3.8 brownout protection figure 17 illustrates the brownout protection mechanism whereby the cs1500 enters standby, and upon recovery from brownout, enters normal operation mode. in order to avoid the fault trigger, a digital filter is added for line voltage detection. the measured peak of the line voltage will be clamped to a threshold (128 v) set by the ic wit hin half of a line cycle if it is higher than the threshold. it then decreases the voltage with a slew rate of 5 v / trough (8 ms). the cs1500 initiates a timer when the measured voltage falls below the lower brownout threshold. the ic asserts the brownout protection and stops the gate drive only if the timer reaches more than 56 ms, which is set by the algorithm based on minimum line frequency. during the brownout state, the device continues monitoring the input line voltage. the device exits the brownout state when the input voltage peak value exceeds the brownout upper threshold for at least 56 ms. the maximum response time of the brownout protection normally happens at light load conditions. it can be calculated by the following equation: in the brownout stat e, the pfc gate driver will restart every 3 seconds, trying to regulate v link to nominal value. figure 17. brownout sequence 3.9 overpower protection during normal operation, if the load is increased beyond the overpower threshold, the output voltage starts falling. when the output voltage is below the startup threshold voltage, the cs1500 switches to startup mode and t he output voltage will rise back again to the nominal value and will operate in normal mode if the load is reduced to a normal level. otherwise, the pfc oscillates between startup mode and normal mode and the digital engine declares the overpower condition. when the overpower protection is asserted, the ic stops gate drive, goes into a low- power state, and restarts every 3 seconds. in the case of an intermittent or minor fault, the device will continue to regulate the output voltage (v link ) to its nominal value. if the pfc remains in startup mode for longer than a given time, set by the digital controller, it senses an overload condition and initiates t he overpower protection. the cs1500 has the ability to ensure nearly constant overpower constraint over a wide range of line voltages, as shown in figure 19. figure 18. overpower protection mechanism figure 19. maximal output power vs. line voltage 3.10 overvoltage protection the overvoltage protection will trigger immediately and stop the gate drive when the current into the fb pin (i ovp ) exceeds 105% of the reference current value (i ref ). the ic resumes gate drive switching when the link voltage drops below v ovp ?v ovp(hy) . 3.11 open/short loop protection if the pfc output sense resistor r fb fails (open or short to gnd), the measured output voltage decreases at a slew rate of about 2v / s, which is determined by adc sampling rate. the ic stops the gate drive when the measured output voltage is lower than the measured li ne voltage. the ic resumes gate drive switching when the current into the fb pin becomes larger than or equal to the current into the iac pin and v link is 116.8 ms = [eq.5] t brownout 8ms 8ms 5v ------------ 128 v v bp th () ? () 56 ms ++ = 8 = 8 5 -- - 128 95 ? () 56 ++ 56 ms 56 ms start timer enter standby exit standby upper lower brownout thresholds start timer t brownout t [ms] v link [v] 100% 90% t 0 t 0 + t ovrpwr overpower startup mode normal mode startup mode startup mode normal mode normal mode v ac(rms) 90 265 p o p o(max) p o / l = l b / l = l b l < l b
cs1500 ds849a7 11 jul ?$shortyear> confidential greater than the peak of the line voltage (v rect(pk) ). the maximum response time of op en/short loop protection for r fb is about 150 s in the cs1500. if the pfc input sense resistor r ac fails (open or short to gnd), the current reference signal supplied to the ic on pin iac falls to zero. this failure is equivalent to a brownout condition and will be handled by the brownout protection mechanism described in section 3.8. 3.12 overcurrent limiting boost inductor saturation is a fatal condition for a pfc converter. to prevent inductor current saturation conditions, the ic utilizes a proprietary di gital algorithm that keeps the boost inductor current away from its saturation current. the boost inductor should be designed for full load, minimal line voltage, maximum switching frequency, and with enough margin to prevent saturation in normal operation mode. 3.13 standby (stby ) function the standby (stby ) pin provides a means by which an external signal can cause the cs1500 to enter into a non- operating, low-power state. the stby input is intended to be driven by an open-collector/open-drain device. internal to the pin, there is a pull-up resistor connected to the vdd pin as shown in figure 20. since the pull-up resistor has a high impedance, the user may need to provide a filter capacitor (up to 1000 pf) on this pin. figure 20. stby pin connection when the stby pin is not used, it is recommended that the pin be tied to vdd (pulled high). < 1 nf 600 k see text vdd stby gnd cs1500
cs1500 12 ds849a7 jul ?$shortyear> confidential 4. application example the following sections describe an example application. the example is based upon the typical connection diagram illustrated in figure 21. equations are provided to de monstrate how a user would calculate the values for the components shown in the diagram. 4.1 pfc for power supply application the following design example is for a universal main input, front-end pfc converter with the following parameters: 4.1.1 i ac and i fb sensing inputs the rectified ac input voltage (v rect ) and boosted pfc output voltage (v link ) are sensed as currents into the ic. the sensing currents are set by resistors r ac and r fb , respectively: maximum power dissipation in each sense resistor is calculated as follows (the equat ion ignores the voltage drop across r iac & r ifb ): d2 c1 d1 cs1500 c2 l b c3 q1 6 2 8 5 7 3 1 r1a r1 b r2a r2b r3 fb gd nc stby gnd vdd iac nc r ac r fb br1 ac mains regulated dc output 4 vdd figure 21. cs1500 basic application circuit v in(min) 90 vac v in(max) 265 vac v link 400 v p o 90 w r fb v link v dd ? i ref --------------------------- - = r fb 400 12 ? 129 10 6 ? --------------------------- - = r fb 3.0m = [eq.6] r ac r fb = r ac 3.0m = [eq.7] pr fb () v link 2 r fb -------------- - = pr fb () 400 2 310 6 ------------------ = pr fb () 53.3mw = [eq.8] pr ac () max 265 2 310 6 ------------------ - = pr ac () max v in max () [] 2 r ac ----------------------------- = pr ac () max 23.4mw = [eq.9]
cs1500 ds849a7 13 jul ?$shortyear> confidential 4.1.2 pfc input filter capacitor to achieve unity power factor, a dcm pfc circuit needs an input filtering circuit to bypass the high-frequency current so that the input current consists of the low-frequency portion only. there are two main factors on pfc input filter capacitor selection: its voltage ripple and phase lag, which both will worsen power factor. the filtering capacitance is proportional to p o and it is suggested as follows: use 0.47 f for tolerance. if a pi filter used for suppres sion of conducted emi is located on the dc side of the in put rectifier, the v rect sense point has to be moved to th e second capacitor. 4.1.3 pfc boost inductor the value of the inductor in normal mode can be calculated by the following equation, with = 0.9 as a derating factor to ensure the inductor is sized to guarantee dcm operation and provide a slightly higher power than required by the load: choose a 360 h inductor. is the efficiency. the inductor should be designed so that its saturation current meets the following requirement, where 0.001126 is a pre- defined threshold for the cu rrent protection algorithm: where l is the inductance in henrys. 4.1.4 pfc mosfet in normal mode, the pfc mosfet peak current is equal to the peak current in the pfc boost inductor: 4.1.5 pfc diode the pfc diode peak current in normal mode is the equal to the inductor peak current: the pfc diode average current is calculated as follows: 4.1.6 pfc output capacitor the value of the output capacitor is determined by several requirements. it must meet the voltage ripple and hold-up time requirements and the rms current in the capacitor should not exceed its rms current rating. the following equation defines t he size of the output capacitor to meet the output voltage ripple requirements: f line(min) is the minimum line frequency the design is required to support, v link is the output voltage from the pfc, v link(rip) , is the output voltage ripple requirement in volts peak-to-peak. the equation will provide the va lue of the output capacitor needed to meet the ripple requirement. for 10 v of ripple and minimum line frequency of 45 hz, the equation becomes: a second requirement that the output capacitor may be required to meet is hold-up ti me. the value of the capacitor c 1 3.3 nf w ------ - p o c 1 3.3 120 c 1 390nf 0.39 f = [eq.10] l b v in min () () 2 v link v in min () 2 () ? 2f max p o v link --------------------------------------------------------- = l b 0.9 0.95 90 2 400 90 2 () ? 27010 3 () 90 400 ------------------------------------------------------------------ - = l b 374 h = [eq.11] i lb pk () 4p o v in min () 2 ----------------------------------------------------- - = i lb pk () 3.3a = i lb pk () 490 0.9 0.95 90 2 ---------------------------------------------------- - = [eq.12] i sat 0.001126 l ------------------------ - [eq.13] i fet pk () i lb pk () = i fet pk () 3.3a = [eq.14] i dpk () i lb pk () = i dpk () 3.3a = [eq.15] i davg () p o v link ----------- - = i davg () 0.225a = i davg () 90 400 --------- - = [eq.16] [eq.17] c out rip () p o 2 f line min () v link v link rip () -------------------------------------------------------------------------------------- - = c out rip () 90 2 45 400 10 ------------------------------------------------ - 80 f u use u 100 f ==
cs1500 14 ds849a7 jul ?$shortyear> confidential needed to meet the hold-up time required is defined by the following equation: t hold is the magnitude of the hold-up time in seconds. for 10 ms of hold-up time and v link(min) of 300 v, the equation becomes: choose a 100 f capacitor. 4.1.7 overvoltage protection overvoltage protection is activated when v link exceeds 105% of the nominal value: while in overvoltage protecti on mode, gate drive output is disabled. gd output is re-enabled when v link falls below its nominal value. c out hold () 2p o t hold v link v out rip () 2 ------------------------ - ? ?? ?? 2 v link min () () 2 ? ------------------------------------------------------------------------------------------ = [eq.18] c out hold () 290 0.010 400 10 2 ------ ? ?? ?? 2 300 () 2 ? ------------------------------------------------------ 27 f == v ovp v link 1.05 = v ovp 400 1.05 = v ovp 420v = [eq.19]
cs1500 ds849a7 15 jul ?$shortyear> confidential 4.1.8 summary of component values designator value description r1a 1.5 m sfr25 axial film res - 0.4w-1% r1b 1.5 m sfr25 axial film res - 0.4w-1% r2a 1.5 m sfr25 axial film res - 0.4w-1% r2b 1.5 m sfr25 axial film res - 0.4w-1% r3 4.7 sfr25 axial film res - 0.4w-1% c1 0.47 f ecq2w474kh c2 0.47 f 50v ceramic cap - x7r c3 100 f, 450v lls2w101mela br1 4a, 600v gbu4j-bp d1 1 a, 600 v 1n4005 d2 1 a, 600 v stth1r06 lb 360 h premier magnetics q1 12 a, 500 v stp12nm50fp cs1500 pfc controller cs1500
cs1500 16 ds849a7 jul ?$shortyear> confidential 5. performance plots 0 10 20 30 40 50 60 70 80 90 100 0102030405060708090100 load (%) thd(%) vin = 230 vin = 115 load (%) efficiency 70 75 80 85 90 95 100 0 102030405060708090100110 vin=230v vin=115v figure 22. fficiency s. load typical figure 23. distortion s. load typical
cs1500 ds849a7 17 jul ?$shortyear> confidential 10 0.4 0.5 0.6 0.7 0.8 0.9 1 0 2030405060708090100 load (%) power factor vin = 115 vin = 230 figure 24. power factor s. load typical
cs1500 18 ds849a7 jul ?$shortyear> confidential figure 25. load transient ? 20% to 80% (60 ma to 240 ma), 0.8 a/ sec slew, 90 vac figure 26. load transient ? 20% to 80% (60 ma to 240 ma), 0.8 a/ sec slew, 260 vac
cs1500 ds849a7 19 jul ?$shortyear> confidential figure 27. overload ? 240 ma to 500 ma, 90 vac figure 28. overload ? 240 ma to 500 ma, 265 vac
cs1500 20 ds849a7 jul ?$shortyear> confidential 6. definitions variable definition the efficiency factor. a margin factor to guarantee rated power against tolerances and transients. f line(min) the minimum ac line frequency. i ac the current generated by v rect that flows into the iac pin. i fb the current generated by v link that flows into the fb pin. i fet(pk) the pfc mosfet peak current, which is equal to the peak current in the pfc boost inductor. i rms the magnitude of the rms current. i sat the boost inductor l b saturation current. i st the sum of the current into the iac and fb pins. i st the startup current of the chip. l b the pfc boost inductor. p o the nominal output power from the cs1500 pfc circuit. p o(max) the maximum value of the output power from the cs1500 pfc circuit. r ac the sense resistor used to measure current into the iac pin. r fb the sense resistor used to measure current into the fb pin. v in(min) the minimum specified line voltage for proper operation (volts rms). v link the magnitude of the output voltage from the pfc. v link(min) the magnitude of the output voltage from the pfc. v link(rip) v link(rip) , is the output voltage ripple re quirement in volts peak-to-peak v rect the instantaneous value of the rectified line voltage (volts).
cs1500 ds849a7 21 jul ?$shortyear> confidential 7. package drawing 8. ordering information 9. environmental, manufacturi ng, & handling information inches millimeters dim min max min max a 0.053 0.069 1.35 1.75 a1 0.004 0.010 0.10 0.25 b 0.013 0.020 0.33 0.51 c 0.007 0.010 0.19 0.25 d 0.189 0.197 4.80 5.00 e 0.150 0.157 3.80 4.00 e 0.040 0.060 1.02 1.52 h 0.228 0.244 5.80 6.20 l 0.016 0.050 0.40 1.27 0 8 0 8 jedec # ms-012 8l soic (150 mil body) package drawing d h e e b a1 a c l seating plane 1 part # temperature range package description cs1500-fsz -40 c to +125 c 8-lead soic, lead (pb) free model number peak reflow temp msl rating a a. msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. max floor life b b. stored at 30 c, 60% relative humidity. cs1500-fsz 260 c 2 365 days
cs1500 22 ds849a7 jul ?$shortyear> confidential 10.revision history revision date changes a1 apr 2009 initial advance information release. a2 jun 2009 no substantive changes. document number incremented to avoid confusion among previous, pre-released versions. a3 dec 2009 revised feature list & product de scription. revised electrical charac- teristics to include brownout & op en-loop protection. modified defini- tion table. modified data sheet format. a4 mar 2010 updated to corr espond to c1 silicon. a5 may 2010 updated performance data. a6 may 2010 updated with additional test bench data for ep level. a7 jul 2010 updated zener voltage, opp thre shold, brownout protection/recovery. updated fig.1 with new data. contacting cirrus logic support for all product questions and in quiries contact a cirrus logic sales representative. to find one nearest you go to http://www.cirrus.com important notice "advance" product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warran ty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage ("critical applications"). cirr us products are not designed, au thorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life support products or other crit- ical applications. inclusion of cirrus products in such applic ations is unders tood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purp ose, with regard to any cirrus product that is used in such a manner. if the customer or customer's customer us es or permits the use of cirrus products in criti cal applications, customer agrees, by such use, to fully indemnify cirrus, its office rs, directors, employees, distributors and other agents from any and all liability, includ- ing attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, the cirrus logic logo designs, exl core, and the exl core logo designs are trademarks of cirrus logic, in c. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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