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this is preliminary information on a new product now in dev elopment or undergoing evaluati on. details are subject to change without notice. december 2014 docid026468 rev 2 1/35 M24C16-DFCU 16-kbit serial i2c bus eeprom 4 balls csp datasheet - preliminary data features ? package: ? rohs compliant and halogen free wlcsp(ecopack2 ? ) ? compatible with all i2c bus modes ?1 mhz ?400 khz ? memory array: ? 16 kbits (2 kbytes) of eeprom ? page size: 16 bytes ? additional write lockable page(identification page) ? supply voltage range: ? 1.6 v to 5.5 v ? operating temperature range ?v cc = 1.7 v : -40c / +85c ?v cc = 1.6 v : -40c (read) / 0c (write) / +85c ? schmitt trigger inputs for noise filtering ? write ? byte write within 5 ms ? page write within 5 ms ? random and sequential read modes ? esd protection ? human body model: 4 kv ? write cycle endurance ? 4 million write cycles at 25 c ? 1.2 million write cycles at 85 c ? more than 200-years data retention wlcsp (cu) www.st.com
contents M24C16-DFCU 2/35 docid026468 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 v ss (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 write identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.4 lock identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.5 minimizing write delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 17 5.2 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.1 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2.2 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
docid026468 rev 2 3/35 M24C16-DFCU contents 3 5.2.4 read identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.5 read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.6 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 application design recommendati ons . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.1 operating supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1.3 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 error correction code (ecc x 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
list of tables M24C16-DFCU 4/35 docid026468 rev 2 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. significant address bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. device identification code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. 400 khz ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13. 1 mhz ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 14. m24c16-df cu wlcsp 4-bump package relate d mechanical data . . . . . . . . . . . . . . . . . 32 table 15. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 16. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
docid026468 rev 2 5/35 M24C16-DFCU list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. wlcsp connections ? (top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. write mode sequence (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 7. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 figure 9. maximum r bus value versus bus parasitic capacitance (c bus ) for ? an i 2 c bus at maximum frequency f c = 400 khz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10. maximum r bus value versus bus parasitic capacitance (c bus ) ? for an i 2 c bus at maximum frequency f c = 1mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 11. ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12. wlcsp 4-bump wafer-level chip-scale package out line . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 13. m24c16-df cu wlcsp 4-bump recommended land pattern . . . . . . . . . . . . . . . . . . . . . . 32
description M24C16-DFCU 6/35 docid026468 rev 2 1 description the M24C16-DFCU is a 16-kbit i2c-compatible eeprom assemb led in a four balls ultra thin chip scale package (wlcsp). the device is accessed by a simple serial i2c compatible interface running up to 1 mhz. the M24C16-DFCU memory ar ray is based on advanced true eeprom technology (electrically erasable programmable memory), organized as 128 pages of 16 bytes, with a data integrity improved with an embedded error correction code logic. the M24C16-DFCU offers an additional identification page (16 bytes) in which the st device identification can be read. this page can also be used to st ore sensitive application parameters which can be later perm anently locked in read-only mode. figure 1. logic diagram table 1. signal names signal name function direction sda serial data i/o scl serial clock input v cc supply voltage v ss ground 069 9 && 9 66 6'$ 6&/ 0&)&8
docid026468 rev 2 7/35 M24C16-DFCU description 34 figure 2. wlcsp connections (top view, marking side, with balls on the underside) 069 ^> { ^ s s ^^ ? 3,1$ 0dunlqjvlgh wrsylhz %xpsvlgh erwwrpylhz ^> ^ s s ^^ ?
signal description M24C16-DFCU 8/35 docid026468 rev 2 2 signal description 2.1 serial clock (scl) scl is an input. the signal applied on the scl input is used to strobe the data available on sda(in) and to output the data on sda(out). 2.2 serial data (sda) sda is an input/output used to transfer data in or data out of the device. sda(out) is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull-up resistor must be co nnected from serial data (sda) to v cc ( figure 9 indicates how to calculate the value of the pull-up resistor). 2.3 v ss (ground) v ss is the reference for the v cc supply voltage. 2.4 supply voltage (v cc ) 2.4.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see operating conditions in section 9: dc and ac parameters ) . in order to secure a stab le dc supply voltage, it is recommended to decouple the v cc line with a suitable ca pacitor (usually from10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instructio n, until the completion of the internal write cycle (t w ). 2.4.2 power-up conditions the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage (see operating conditions in section 9: dc and ac parameters ) and the rise time must not vary faster than 1 v/s. 2.4.3 device reset in order to prevent inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not re spond to any instruction until v cc has reached the internal reset threshold voltage. this threshold is lower than the minimum v cc operating voltage (see operating conditions in section 9: dc and ac parameters ). when v cc passes over the por threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until v cc reaches a valid and stable dc voltage within the specified [v cc (min), v cc (max)] range (see operating conditions in section 9: dc and ac parameters ).
docid026468 rev 2 9/35 M24C16-DFCU signal description 34 in a similar way, during power-down (continuous decrease in v cc ), the device must not be accessed when v cc drops below v cc (min). when v cc drops below the power-on-reset threshold voltage, the device stops resp onding to any instruction sent to it. 2.4.4 power-down conditions during power-down (continuous decrease in v cc ), the device must be in the standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress).
memory organization M24C16-DFCU 10/35 docid026468 rev 2 3 memory organization the memory is organized as shown below. figure 3. block diagram 069 &rqwuroorjlf +ljkyrowdjh jhqhudwru ,2vkliwuhjlvwhu $gguhvvuhjlvwhu dqgfrxqwhu 'dwd uhjlvwhu sdjh ;ghfrghu <ghfrghu 6&/ 6'$
docid026468 rev 2 11/35 M24C16-DFCU device operation 34 4 device operation the device supports the i 2 c protocol. this is summarized in figure 4 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a dat a transfer can only be initia ted by the bus master, which will also provide the serial clock for synchronization. the device is always a slave in all communications. figure 4. i 2 c bus protocol 6&/ 6'$ 6&/ 6'$ 6'$ 67$57 &rqglwlrq 6'$ ,qsxw 6'$ &kdqjh $,% 6723 &rqglwlrq 06% $&. 67$57 &rqglwlrq 6&/ 06% $&. 6723 &rqglwlrq
device operation M24C16-DFCU 12/35 docid026468 rev 2 4.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must prece de any data transfer instruction. the device continuously monitors (except during a writ e cycle) serial data (sda) and serial clock (scl) for a start condition. 4.2 stop condition stop is identified by a rising edge of serial da ta (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read instruction that is followed by noack can be fo llowed by a stop condition to force the device into the standby mode. a stop condition at the end of a write instruction triggers the internal write cycle. 4.3 data input during data input, the device samples serial da ta (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low. 4.4 acknowledge bit (ack) the acknowledge bit is used to indicate a succ essful byte transfer. the bus transmitter, whether it be bus master or slave device, releas es serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits.
docid026468 rev 2 13/35 M24C16-DFCU device operation 34 4.5 device addressing to start communication between the bus master and the slave device, the bus master must initiate a start conditio n. following this, the bus master s ends the device select code, shown in table 3 (on serial data (sda), most significant bit first). the 8 th bit is the read/ write bit (r w ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select co de, the device deselects itself from the bus, and goes into standby mode (therefore will not acknowle dge the device select code). table 2. device select code device type identifier (1) chip enable address b7 b6 b5 b4 b3 b2 b1 b0 when accessing the memory 1 0 1 0 a10 a9 a8 rw when accessing the identification page 1 0 1 1 x x x rw 1. the most significant bit, b7, is sent first. table 3. significant address bits memory (device type identifier = 1010b) identification page (device type identifier = 1011b) random address read write read identification page write identification page lock identification page read lock status most significant address bits b3 (1) a1 0 a1 0 xxx see chapter 5.2.4 b2 (1) a9 a9 x x x b1 (1) a8 a8 x x x address byte b7 a7 a7 0 0 1 b6 a6 a6 x x x b5 a5 a5 x x x b4 a4 a4 x x x b3 a3 a3 a3 a3 x b2 a2 a2 a2 a2 x b1 a1 a1 a1 a1 x b0 a 0 a 0 a 0 a 0 x 1. address bits defined inside the deviceselect code (see table 2 ).
device operation M24C16-DFCU 14/35 docid026468 rev 2 4.6 identification page the M24C16-DFCU offers an identification page (16 bytes) in addition to the 16-kbit memory. the identification page contains two fields: ? device identification code: the first three bytes are programmed by stmicroelectronics with the device identification code, as shown in table 4 . ? application parameters: the bytes after the de vice identification code are available for application specific data. note: if the end application does not need to read the device identification code, this field can be overwritten and used to store application-spec ific data. once the app lication-specific data are written in the identification page, the whol e identification page should be permanently locked in read-only mode. the instructions read, write and lock identification page are detailed in section 5 : table 4. device identification code address in identification page content value 00h st manufacturer code 20h 01h i 2 c family code e0h 02h memory density code 0bh(16-kbit)
docid026468 rev 2 15/35 M24C16-DFCU instructions 34 5 instructions 5.1 write operations for a write operation, the bus master sends a start condition followed by a device select code with the r/w bit reset to 0. the device acknowledges this, as shown in figure 5 , and waits for the master to send the address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condit ion immediately after a data byte ack bit (in the ?10th bit? time slot), either at the end of a byte write or a page write, the internal write cycle t w is then triggered. a stop condition at any ot her time slot does not trigger the internal write cycle. during the internal write cycle, serial data (s da) is disabled internally, and the device does not respond to any requests. after the successful completion of an internal write cycle (t w ), the device internal address counter is automatically increment ed to point to the next byte after the last modified byte. 5.1.1 byte write after the device select code and the address by tes, the bus master sends one data byte. the device replies with ack, as shown in . th e bus master shall terminate the transfer by generating a stop condition. figure 5. write mode sequence (data write enabled) $,g ^?}? ^??? ??t?]? ^o? ????? ?]v ^??? wpt?]? ^o? ????? ?]v ?]v? ?]v? wpt?]?~}v?? ^?}? ?]ve < zlt < < < < < < zlt < <
instructions M24C16-DFCU 16/35 docid026468 rev 2 5.1.2 page write the page write mode allows up to n(a) bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, a10/ a4, are the same. if more bytes ar e sent than will fit up to the end of the page, a condition known as ?roll-over? occurs. in case of roll-over, the first bytes of the page are overwritten. note: after each byte is transferred, the internal byte address counter is incremented. the transfer is terminated by the bus master generating a stop condition. 5.1.3 write identification page the identification page (16 bytes) is an additi onal page which can be written and (later) permanently locked in read-only mode. it is writ ten by issuing the write identification page instruction. this instruction us es the same protocol and format as page write (into memory array), except for the following differences: ? device type identifier = 1011b ? most significant address bits a10/a4 are don't care, except for address bit a7 which must be ?0?. least significant address bits a3/a0 define the byte location inside the identification page. if the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (noack). 5.1.4 lock identification page the lock identification page instruction (lock id) permanently locks the identification page in read-only mode. the lock id instruction is si milar to byte write (into memory array) with the following specific conditions: ? device type identifier = 1011b ? address bit a7 must be ?1?; all other address bits are don't care ? the data byte must be equal to the binary value xxxx xx1x, where x is don't care
docid026468 rev 2 17/35 M24C16-DFCU instructions 34 5.1.5 minimizing write delays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its intern al latches to the memory ce lls. the maximum write time (t w ) is shown in ac characteristics tables in section 9: dc and ac parameters , but the typical time is shorter. to make use of this, a pollin g sequence can be used by the bus master. the sequence, as shown in figure 6 , is: ? initial condition: a write cycle is in progress. ? step 1: the bus master issues a start condi tion followed by a device select code (the first byte of the new instruction). ? step 2: if the device is bu sy with the internal write cycl e, no ack will be returned and the bus master goes back to step 1. if t he device has terminated the internal write cycle, it responds with an ack, indicating th at the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). figure 6. write cycle polling flowchart using ack 1. the seven most significant bits of the device se lect code of a random read (bottom right box in the figure) must be identical to the seven most significant bi ts of the device select code of the write (polling instruction in the figure). t?]??o ]v??}p??? $,h e?? k???]}v]? ???]vp?z uu}?? ^???}v]?]}v ]?o? ]?zzta < ???v z^ ek z^ ek z^??? ^?}? ?(}??z t?]????]}v 'hylfhvhohfw zlwk5: ^v??? vz]< z^ ek 6wduw&rqglwlrq }v?]v?z t?]?}???]}v }v?]v?z zv}uz}???]}v )luvwe\whrilqvwuxfwlrq zlwk5: douhdg\ ghfrghge\wkhghylfh
instructions M24C16-DFCU 18/35 docid026468 rev 2 5.2 read operations after the successful completion of a read oper ation, the device internal address counter is incremented by one, to point to the next byte address. for the read instructions, after each byte read (data out), the device waits for an acknowledgment (data in) during the 9th bit time. if the bus master does not acknowledge during this 9th time, the device terminates t he data transfer and switches to its standby mode. figure 7. read mode sequences 5.2.1 random address read the random address read is a sequence co mposed of a truncated write sequence (to define a new address pointer value, see table 3 ) followed by a current read. therefore the random address read sequence is the sum of [start + device select code with r/w=0 + address byte] (without stop condition, as shown in figure 7 ) and [start condition + device select code with r/w=1]. the memory device acknowledges the sequence and then outputs the contents of the addressed byte. to terminate the data 6wduw 'hyvhohfw %\whdgguhvv 6wduw 'hyvhohfw 'dwdrxw $,e 'dwdrxw1 6wrs 6wduw &xuuhqw $gguhvv 5hdg 'hyvhohfw 'dwdrxw 5dqgrp $gguhvv 5hdg 6wrs 6wduw 'hyvhohfw 'dwdrxw 6htxhqwldo &xuuhqw 5hdg 6wrs 'dwdrxw1 6wduw 'hyvhohfw %\whdgguhvv 6htxhqwldo 5dqgrp 5hdg 6wduw 'hyvhohfw 'dwdrxw 6wrs $&. 5: 12$&. $&. 5: $&. $&. 5: $&. $&. $&. 12$&. 5: 12$&. $&. $&. 5: $&. $&. 5: $&. 12$&.
docid026468 rev 2 19/35 M24C16-DFCU instructions 34 transfer, the bus master does not acknowledge the last data byte and then issues a stop condition. 5.2.2 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the r/ w bit set to 1. the device acknowledges this, and outputs the byte addressed by the inter nal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition , as shown in figure 9 , without acknowledging the byte. note that the address counter value is defined by instructions accessing either the memory or the identification page. when accessing the identification page, the address counter value is loaded with the identification page byte location, when accessing the memory, it is safer to always use the random address re ad instruction (this instruction loads the address counter with the byte location to read in the memory) instead of the current address read instruction. 5.2.3 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next by te in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 9 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte ou tput. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 5.2.4 read identification page the identification page can be read by issuing a read identification page instruction. this instruction uses the same protocol and form at as the random address read (from memory array) with device type identifier defined as 10 11b. the most significant address bits a10/a4 are don't care except bit a7 which must be 0, the least significant address bits a3/a0 define the byte location inside the identification page. the number of bytes to read in the id page must not exceed the page boundary. 5.2.5 read the lock status the locked/unlocked status of the identifica tion page can be checked by transmitting a specific truncated command [id entification page write instruction plus one data byte] to the device. the device returns an acknowledge bit afte r the data byte if the identification page is unlocked, otherwise a noack bit if the identification page is locked. after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that: ? start: the truncated command is not execut ed because the start condition resets the device internal logic, ? stop: the device is then set back into standby mode by the stop condition.
instructions M24C16-DFCU 20/35 docid026468 rev 2 5.2.6 acknowledge in read mode for all read instructions, afte r each byte sent out, the device waits for an acknowledgment from the bus master during the ?9th bit? time slot. if the bus master does not send the acknowledge (the master drives sda high during the 9th bit time), the device terminates the data transfer and enters its standby mode.
docid026468 rev 2 21/35 M24C16-DFCU application design recommendations 34 6 application design recommendations 6.1 supply voltage 6.1.1 operating s upply voltage (vcc) prior to selecting the memory and issuing instructions to it, a valid and stable vcc voltage within the specified [vcc(min), vc c(max)] range must be applied (see table 6 ). this voltage must remain stable and valid unt il the end of the transmission of the instruction and, for a write instruction, un til the completion of the internal write cycle (tw). in order to secure a stable dc supply voltage, it is recommended to decouple the vcc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the vcc/vss package pins. 6.1.2 power-up conditions when the power supply is turned on, the vcc voltage has to rise continuously from 0 v up to the minimum vcc operating voltage defined in see table 6 . in order to prevent inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not respond to any instruction until vcc reaches the internal threshold voltage (this threshold is defined in the dc characteristic table 11 as vres). when vcc passes over the por threshold, the device is reset and in the following state: ? in the standby power mode ? deselected as soon as the vcc voltage has reached a st able value within the [vcc(min), vcc(max)] range (defined in table 6 ), the device is ready for operation. 6.1.3 power-down during power-down (continuous decrease in the vcc supply voltage below the minimum vcc operating voltage defined in table 6 ), the device must be in standby power mode (that is after a stop condition or after the completion of the write cycle t w if an internal write cycle is in progress). 6.2 error correctio n code (ecc x 1) the error correction code (ecc x 1) is an intern al logic function which is transparent for the i2c communication protocol. the ecc x 1 logic is implemented on each byte of the memory array. if a single bit out of the byte happens to be erroneous during a read op eration, the ecc x 1 detects this bit and replaces it with the correct value. the read re liability is therefore much improved.
initial delivery state M24C16-DFCU 22/35 docid026468 rev 2 7 initial delivery state the device is delivered as follows: ? the memory array is set to all 1s (each byte = ffh). ? identification page: the first three bytes define the device identificati on code (value defined in table 4 ). the content of the following bytes is don?t care.
docid026468 rev 2 23/35 M24C16-DFCU maximum rating 34 8 maximum rating stressing the device outside the ratings listed in table 5 may cause permanent damage to the device. these are stress ratings only, and o peration of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings symbol parameter min. max. unit ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec standard j-std-020d (for sma ll-body, sn-pb or pb assembly), the st ecopack? 7191395 specification, and the european directive on restrictions on hazardous substances (rohs directive 2011/65/eu of july 2011). c v io input or output range ?0.50 6 v i ol dc output current (sda = 0) - 5 ma v cc supply voltage ?0.50 6 v v esd electrostatic pulse (human body model) (2) 2. positive and negative pulses applied on different co mbinations of pin connections, according to aec- q100-002 (compliant with jedec std jesd22-a114, c1=100 pf, r1=1500 ? ). - 4000 v
dc and ac parameters M24C16-DFCU 24/35 docid026468 rev 2 9 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. figure 8. ac measurement i/o waveform table 6. operating conditions symbol parameter min. max. unit v cc supply voltage 1.6 1.7 5.5 v t a ambient operating temperature: read ?40 -40 85 c ambient operating temperature: write 0 -40 f c operating clock frequency @1.6 v - 400 khz operating clock frequency @1.7 v - 1000 table 7. ac measurement conditions symbol parameter min. max. unit c bus load capacitance 100 pf - scl input rise/fall time, sda input fall time - 50 ns - input levels 0.2 v cc to 0.8 v cc v - input and output timing reference levels 0.3 v cc to 0.7 v cc v table 8. inpu t parameters symbol parameter (1) 1. characterized only, not tested in production. test condition min. max. unit c in input capacitance (sda) - - 8 pf c in input capacitance (other pins) - - 6 pf z l input impedance (wc ) v in < 0.3 v cc 30 - k ? z h v in > 0.7 v cc 500 - k ? 069 9 && 9 && 9 && 9 && ,qsxwdqgrxwsxw 7lplqjuhihuhqfhohyhov ,qsxwyrowdjhohyhov
docid026468 rev 2 25/35 M24C16-DFCU dc and ac parameters 34 table 9. cycling performance symbol parameter test condition max. unit ncycle write cycle endurance t a ? 25 c, v cc (min) < v cc < v cc (max) 4,000,000 write cycles t a = 85c, v cc (min) < v cc < v cc (max) 1,000,000 table 10. memory ce ll data retention parameter test condition min. unit data retention t a = 55 c 200 years
dc and ac parameters M24C16-DFCU 26/35 docid026468 rev 2 table 11. dc characteristics symbol parameter test condition min max. unit i li input leakage current ? (scl, sda) v in = v ss or v cc, ? device in standby mode - 2a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc - 2a i cc supply current (read) f c = 400 khz, v cc = 5.5 v - 2 ma f c = 400 khz, v cc = 2.5 v - 2 f c = 400 khz, v cc = 1.8 v - 1 f c = 1 mhz, v cc = 5.5 v - 2 f c = 1 mhz, v cc = 2.5 v - 2 f c = 1 mhz, v cc = 1.8 v - 2 i cc0 supply current (write) during t w -2ma i cc1 standby supply current device not selected (1) , t = 85 c, ? v in = v ss or v cc , v cc = 1.8 v 1. the device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle t w (t w is triggered by the correct dec oding of a write instruction). -1 a device not selected (1) , t = 85 c ? v in = v ss or v cc , v cc = 2.5 v -2 device not selected (1) , t = 85 c, ? v in = v ss or v cc , v cc = 5.5 v -3 v il input low voltage (scl, sda) - ?0.45 0.3 v cc v v ih input high voltage (scl, sda) -0.7 v cc 6.5 v v ol output low voltage i ol = 2.1 ma, v cc = 2.5 v or ? i ol = 3 ma, v cc = 5.5 v -0.4 v i ol = 1 ma, v cc = 1.8 v - 0.3 v res (2) 2. characterized only, not 100% tested. internal reset threshold voltage -0.51.5v
docid026468 rev 2 27/35 M24C16-DFCU dc and ac parameters 34 table 12. 400 khz ac characteristics symbol alt. parameter min. max. unit f c f scl clock frequency - 400 khz t chcl t high clock pulse width high 600 - ns t clch t low clock pulse width low 1300 - ns t ql1ql2 (1) 1. characterized only, not tested in production. t f sda (out) fall time 20 120 ns t xh1xh2 t r input signal rise time (2) 2. there is no min. or max. value for the input signal rise and fall times. it is however recommended by the i2c specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when f c < 400 khz. (2) ns t xl1xl2 t f input signal fall time (2) (2) ns t dxch t su:dat data in set up time 100 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (3) 3. the min value for t clqx (data out hold time) offers a safe timing to bridge the undefined region of the falling edge scl. t dh data out hold time 100 - ns t clqv (4) 4. t clqv is the time (from the falling edge of scl) r equired by the sda bus line to reach either 0.3v cc or 0.7v cc , assuming that r bus c bus time constant is less than 400 ns . t aa clock low to next data valid (access time) - 900 ns t chdl t su:sta start condition setup time 600 - ns t dlcl t hd:sta start condition hold time 600 - ns t chdh t su:sto stop condition set up time 600 - ns t dhdl t buf time between stop condition and next start condition 1300 - ns t w t wr write time - 5 ms t ns (1) pulse width ignored (input filter on scl and sda) - single glitch -80ns
dc and ac parameters M24C16-DFCU 28/35 docid026468 rev 2 table 13. 1 mhz ac characteristics symbol alt. parameter min. max. unit f c f scl clock frequency 0 1 mhz t chcl t high clock pulse width high 260 - ns t clch t low clock pulse width low 500 - ns t xh1xh2 t r input signal rise time (1) 1. there is no min. or max. values for the input signal rise and fall times. however, it is recommended by the i2c specification that the input signal rise and fa ll times be more than 20 ns and less than 120 ns when f c < 1 mhz. (1) ns t xl1xl2 t f input signal fall time (1) (1) ns t ql1ql2 (2) 2. characterized only, not tested in production. t f sda (out) fall time 20 120 ns t dxch t su:dat data in setup time 50 - ns t cldx t hd:dat data in hold time 0 - ns t clqx (3) 3. to avoid spurious start and stop conditions, a mini mum delay is placed between scl=1 and the falling or rising edge of sda. t dh data out hold time 100 - ns t clqv (4) 4. t clqv is the time (from the falling edge of scl) required by the sda bus line to reach either 0.3 v cc or 0.7 v cc , assuming that the rbus cbus time constant is within the values specified in figure 9 . t aa clock low to next data valid (access time) - 450 ns t chdl t su:sta start condition setup time 250 - ns t dlcl t hd:sta start condition hold time 250 - ns t chdh t su:sto stop condition setup time 250 - ns t dhdl t buf time between stop condition and next start condition 500 - ns t w t wr write time - 5 ms t ns (2) - pulse width ignored (input filter on scl and sda) -80ns
docid026468 rev 2 29/35 M24C16-DFCU dc and ac parameters 34 figure 9. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 400 khz figure 10. maximum r bus value versus bus parasitic capacitance (c bus ) for an i 2 c bus at maximum frequency f c = 1mhz %xvolqhfdsdflwrus) %xvolqhsxooxsuhvlvwru n ,e&exv pdvwhu 0[[[ 5 exv 9 && & exv 6&/ 6'$ 5 exv ? & exv qv +huh5 exv ?& exv qv s) 7kh5[&wlphfrqvwdqw pxvwehehorzwkhqv wlphfrqvwdqwolqhuhsuhvhqwhg rqwkhohiw exv exv 069 n %xvolqhfdsdflwrus) %xvolqhsxooxsuhvlvwrun 069 ,e&exv pdvwhu 0[[[ 5 exv 9 && & exv 6&/ 6'$ +huh 5 exv ? & exv qv 5 ex v ? & ex v qv 7kh5 exv ?& exv wlphfrqvwdqw pxvwehehorzwkhqv wlphfrqvwdqwolqhuhsuhvhqwhg rqwkhohiw
dc and ac parameters M24C16-DFCU 30/35 docid026468 rev 2 figure 11. ac waveforms 6&/ 6'$2xw 6&/ 6'$,q 'dwdydolg w&/49 w&/4; w&+'+ 6wrs frqglwlrq w&+'/ 6wduw frqglwlrq :ulwhf\foh w: $,m 'dwdydolg w4/4/ 6'$,q w&+'/ 6wduw frqglwlrq w';&+ w&/'; 6'$ ,qsxw 6'$ &kdqjh w&+'+ w'+'/ 6wrs frqglwlrq 6wduw frqglwlrq w;+;+ 6&/ w&+&/ w'/&/ w&/&+ w;+;+ w;/;/ w;/;/ w&+&/
docid026468 rev 2 31/35 M24C16-DFCU package mechanical data 34 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 12. wlcsp 4-bump wafer-level chip-scale package outline 37db0(b9 :dihuedfnvlgh 6lghylhz 2ulhqwdwlrquhihuhqfh ; ddd ( ' ; < 'hwdlo$ eee = $ $ %xps $ = 'hwdlo$ 5rwdwhg? hhh = e; h ** ) h %xpsvlgh 6hdwlqjsodqh 2ulhqwdwlrq uhihuhqfh ; < t ggg0 = t fff0 = )
package mechanical data M24C16-DFCU 32/35 docid026468 rev 2 figure 13. m24c16-df cu wlcsp 4-bump recommended land pattern table 14. m24c16-df cu wlcsp 4-bump package related mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to four decimal digits. typ. min. max. typ. min. max. a 0.270 0.240 0.300 0.0106 0.0094 0.0118 a1 0.095 - - 0.0037 - - a2 0.175 - - 0.0069 - - b 0.185 - - 0.0073 - - d 0.725 - 0.745 0.0285 - 0.0293 e 0.819 - 0.839 0.0322 - 0.0330 e 0.400 - - 0.0157 - - f 0.210 - - 0.0083 - - g 0.163 - - 0.0064 - - n4 aaa 0.110 - - 0.0043 - - bbb 0.110 - - 0.0043 - - ccc 0.110 - - 0.0043 - - ddd 0.060 - - 0.0024 - - eee 0.060 - - 0.0024 - - h &/b)3b9 h [ ?e
docid026468 rev 2 33/35 M24C16-DFCU part numbering 34 11 part numbering parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st char ge. in no event, st wi ll be liable for any customer usage of these engineering samples in production. st quality has to be contacted prior to any decision to use these engineering samples to run qualification activity. table 15. ordering information scheme example: m24c16-df cu 6 t p /k device type m24 = i 2 c serial access eeprom device function c16-d = 16 kbits (2048 x 8 bits) plus identification page operating voltage f = v cc = 1.6 v to 5.5 v package cu = ultra-thin 4-bump wlcsp (1) 1. ecopack2?: rohs-compliant and free of brominated, chlorinated and antimony oxide flame retardants. device grade 6 = device tested with standard test flow over -40 to 85 c option t = tape and reel packing plating technology p = ecopack2 ? process technology /k = manufacturing technology code
revision history M24C16-DFCU 34/35 docid026468 rev 2 12 revision history table 16. document revision history date revision changes 20-jun-2014 1 initial release 04-dec-2014 2 updated: ? features on cover page. ? section 1: description . ? figure 12 ? ta ble 6 , table 14 and table 15 . added: ? note 1 on table 15 ? sentence about engineering sample on table 15 . ? figure 13
docid026468 rev 2 35/35 M24C16-DFCU 35 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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