chx2090-qdg rohs compliant ref. : dschx2090qdg0211 - 30 jul 2010 1/10 specific ations subject to change without notice united monolithic semiconductors s.a.s. route dpartementale 128 - bp46 - 91401 orsay cedex france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 12-24ghz frequency multiplier gaas monolithic microwave ic in smd leadless packag e description the chx2090- qdg is a cascadable frequency doubler monolithic circuit, which integrate an output buffer amplifier that produces a constant output power over a range of input powers. it is designed for a wide range of applications, from military to commercial communication systems. the circuit is manufactured with a p hemt process, 0.25m gate length, via holes through the substrate, air bridges and electron beam gate lithography. it is supplied in rohs compliant smd package. typical measurements main features broadband performances: 11-13ghz 13dbm output power for +14dbm input power dc bias: vd=3.5volt@id=65ma 24l-qfn4x4 smd package main characteristics tamb. = 25c symbol parameter min typ max unit fin input frequency range 11 13 ghz fout output frequency range 22 26 ghz pin input power 14 dbm pout output power for +14dbm input power 13 dbm esd protection: electrostatic discharge sensitive d evice. observe handling precautions!
chx2090-qdg 12- 24ghz frequency multiplier ref. : dschx2090qdg0211 - 30 jul 2010 2/10 specific ations subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 electrical characteristics tamb = +25c, vd = 3.5v, vg1 = -0.9v, vg2 tuned for id=65ma. symbol parameter min typ max unit fin input frequency range 11 13 ghz fout output frequency range 22 26 ghz pin input power 14 dbm pout 2fin 2fin output power for (11 < fin < 12ghz) for fin = 13ghz 12 9 dbm dbm is/fin fin level at the output for (11 < fin < 12) for fin = 13g hz -10 0 dbm dbm is/3fin 3fin level at the output -15 dbm vswrin input vswr 2.0:1 vswrout output vswr 2.5:1 vd drain voltage 3.5 v id bias current 65 75 ma absolute maximum ratings tamb.= 25c (1) symbol parameter values unit vd drain bias voltage 5v v id drain bias current 120 ma vg gate bias voltage -2 to +0.4 v tj junction temperature (2) 175 c ta operating temperature range -40 to +85 c tstg storage temperature range -55 to +155 c (1) operation of this device above anyone of these parameters may cause permanent damage. (2) thermal resistance channel to ground paddle =24 9c/w for tamb. = +85c with 3.5v & 65ma.
12-24ghz frequency multiplier chx2090-qdg ref. : dschx2090qdg0211 - 30 jul 2010 3/10 specific ations subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 typical measured performances measurements in the connector access planes, using the proposed land pattern & board 96270. bias conditions : vd = 3,5v, vg1 = -0.9v, vg2 tuned for id# 65ma. pout (2fin) & pout (fin) vs fin for pin=14 dbm pout (2fin) & pout (3fin) vs fin for pin=14 dbm pout 2fin pout fin pout 2fin pout 3fin
chx2090-qdg 12- 24ghz frequency multiplier ref. : dschx2090qdg0211 - 30 jul 2010 4/10 specific ations subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 pout (2fin) & pout (fin) vs vg1 for fin = 12 ghz, p in=14dbm & vg2= -0,7v pout (2fin) & pout (fin) vs vg2 for fin = 12 ghz, p in=14dbm & vg1= -0,9v pout 2fin pout fin pout 2fin pout fin
12-24ghz frequency multiplier chx2090-qdg ref. : dschx2090qdg0211 - 30 jul 2010 5/10 specific ations subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 chx2090-qdg drain current versus vg2, for fin=12ghz, pin=14dbm, vd=3.5v and vg1=-0.9v 40 45 50 55 60 65 70 75 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 vg2 (volt) id (ma)
chx2090-qdg 12- 24ghz frequency multiplier ref. : dschx2090qdg0211 - 30 jul 2010 6/10 specific ations subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 package outline matt tin, lead free (green) 1- nc 13- nc units mm 2- nc 14- gnd from the standard jedec mo-220 3- gnd 15- rf out pin 25 (paddle) gnd 4- rf in 16- gnd 5- gnd 17- nc 6- nc 18- nc 7- nc 19- nc 8- nc 20- vd 9- nc 21- nc 10- nc 22- vg2 11- nc 23- vg1 12- nc 24- nc
12-24ghz frequency multiplier chx2090-qdg ref. : dschx2090qdg0211 - 30 jul 2010 7/10 specific ations subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 application note the design of the motherboard has a strong impact o n the over all performance since the transition from the motherboard to the package is c omparably large. in case of the smd type packages of united monolithic semiconductors the mo therboard should be designed according to the information given in the following to achieve good performance. other configurations are also possible but can lead to di fferent results. if you need advise please contact united monolithic semiconductors for furthe r information. smd type packages of ums should allow design and fa brication of micro- and mm-wave modules at low cost. therefore, a suitable motherbo ard environment has been chosen. all tests and verifications have been performed on roge rs ro4003. this material exhibits a permittivity of 3.38 and has been used with a thick ness of 200m [8 mils] and a 1/2oz or less copper cladding. the corresponding 50ohm transmissi on line has a strip width of about 460m [approx. 18 mils]. the contact areas on the motherboard for the packag e connections should be designed according to the footprint given above. the proper via structure under the ground pad is very important in order to achieve a good rf and lifetim e performance. all tests have been done by using a grid of plenty plated through vias with a diameter of less than 300m [12 mils] and a spacing of less than 700m [28 mils] from the cen tres of two adjacent vias. the via grid should cover the whole space under the ground pad a nd the vias closest to the rf ports should be located near the edge of the pad to allow a good rf ground connection. since the vias are important for heat transfer, a proper via filling should be guaranteed during the mounting procedure to get a low thermal resistance between package and heat sink. for power devices the use of heat slugs in the motherbo ard instead of a grid of vias is recommended. for the mounting process the smd type package can b e handled as a standard surface mount component. the use of either solder or conduc tive epoxy is possible. the solder thickness after reflow should be typical 50m [2 mi ls] and the lateral alignment between the package and the motherboard should be within 50m [ 2 mils]. caution should be taken to obtain a good and reliable contact over the whole p ad areas. voids or other improper connections, in particular, between the ground pads of motherboard and package will lead to a deterioration of the rf performance and the heat dissipation. the latter effect can reduce drastically reliability and lifetime of the product .
chx2090-qdg 12- 24ghz frequency multiplier ref. : dschx2090qdg0211 - 30 jul 2010 8/10 specific ations subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 (for production, design must be adapted with regard to pcb tolerances and assembly process) basic footprint for a 24l-qfn4x4 (all units mm) (please, refer to the ums proposed footprint for op timum operation in the following proposed assembly board section) the rf ports are dc blocked on chip. the dc connect ion (vd) does not include any decoupling capacitor in package, therefore it is ma ndatory to provide a good external dc decoupling on the pc board, as close as possible to the package. smd mounting procedure the smd leadless package has been designed for high volume surface mount pcb assembly process. the dimensions and footprint requ ired for the pcb (motherboard) are given in the drawings above. for the mounting process standard techniques involv ing solder paste and a suitable reflow process can be used. for further details, see appli cation note an0017.
12-24ghz frequency multiplier chx2090-qdg ref. : dschx2090qdg0211 - 30 jul 2010 9/10 specific ations subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 proposed assembly board 96270 for the 24l-qfn4x4 products characterization. - compatible with the proposed footprint. - based on typically ro4003 / 8mils or equivalent. - using a microstrip to coplanar transition to acces s the package. - recommended for the implementation of this product on a module board.
chx2090-qdg 12- 24ghz frequency multiplier ref. : dschx2090qdg0211 - 30 jul 2010 10/10 specifi cations subject to change without notice route dpartementale 128, bp46 - 91401 orsay cedex - france tel.: +33 (0) 1 69 33 03 08 - fax: +33 (0) 1 69 33 03 09 recommended package footprint refer to the application note an0017 available at http://www.ums-gaas.com for package foot print recommendations. smd mounting procedure the smd leadless package has been designed for high volume surface mount pcb assembly process. the dimensions and footprint required for the pcb ( motherboard) are given in the drawings above. for the mounting process standard techniques involv ing solder paste and a suitable reflow process can be used. for further details, see application note an0017. recommended esd management refer to the application note an0020 available at http://www.ums-gaas.com for esd sensitivity and handling recommendations for the ums package produc ts. recommended environmental management refer to the application note an0019 available at http://www.ums-gaas.com for environmental data on ums package products. ordering information qfn 4x4 rohs compliant package: chx2090-qdg/xy stick: xy = 20 tape & reel: xy = 21 information furnished is believed to be accurate an d reliable. however united monolithic semiconductors s.a.s. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by impli cation or otherwise under any patent or patent rights of united monolithic semiconductors s.a.s. . specifications mentioned in this publication are subject to change without notice. this publication supersedes and re places all information previously supplied. united monolithic semiconductors s.a.s. products are not authorised for use as critical components in life support devices or s ystems without express written approval from united monolithic semiconductors s.a.s.
|
