d a t a sh eet product speci?cation file under integrated circuits, ic04 january 1995 integrated circuits hef4751v lsi universal divider for a complete data sheet, please also download: the ic04 locmos he4000b logic family specifications hef, hec the ic04 locmos he4000b logic package outlines/information hef, hec
january 1995 2 philips semiconductors product speci?cation universal divider hef4751v lsi description the hef4751v is a universal divider (u.d.) intended for use in high performance phase lock loop frequency synthesizer systems. it consists of a chain of counters operating in a programmable feedback mode. programmable feedback signals are generated for up to three external (fast) ? 10/11 prescaler. the system comprising one hef4751v u.d. together with prescalers is a fully programmable divider with a maximum configuration of: 5 decimal stages, a programmable mode m stage (1 m 16, non-decimal fraction channel selection), and a mode h stage (h = 1 or 2, stage for half channel offset). programming is performed in bcd code in a bit-parallel, digit-serial format. to accommodate fixed or variable frequency offset, two numbers are applied in parallel, one being subtracted from the other to produce the internal programme. the decade selection address is generated by an internal programme counter which may run continuously or on demand. two or more universal dividers can be cascaded, each extra u.d. (in slave mode) adds two decades to the system. the combination retains the full programmability and features of a single u.d. the u.d. provides a fast output signal ff at output off, which can have a phase jitter of 1 system input period, to allow fast frequency locking. the slow output signal fs at output ofs, which is jitter-free, is used for fine phase control at a lower speed. fig.1 pinning diagram. supply voltage family data, i dd limits category lsi see family specifications hef4751vp(n): 28-lead dil; plastic (sot117) hef4751vd(f): 28-lead dil; ceramic (cerdip) (sot135v) hef4751vt(d): 28-lead so; plastic (sot136a) ( ): package designator north america rating recommended operating - 0,5 to + 18 4,5 to 12,5 v
january 1995 3 philips semiconductors product speci?cation universal divider hef4751v lsi fig.2 block diagram.
january 1995 4 philips semiconductors product speci?cation universal divider hef4751v lsi this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... fig.3 the hef4751v u.d. used in a system with 3 (fast) prescalers. 1 m 16; 1 h 2; n 5 > 0; f i /f ofs = {(n 5 10 4 + n 4 10 3 + n 3 10 2 + n 2 10 + n 1 ) m + n 0 } h + n h .
january 1995 5 philips semiconductors product speci?cation universal divider hef4751v lsi fig.4 timing diagram showing programme data inputs. allocation of data input fetch period inputs a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 si 0n 0a n 0b b in 1n 1a n 1b x 2n 2a n 2b x 3n 3a n 3b x 4n 4a n 4b x 5n 5a n 5b x 6m c0 b control 1 2 channel control x allocation of data input b3 to b0 during fetch period 6 notes 1. h = high state (the more positive voltage) 2. l = low state (the less positive voltage) 3. x = state is immaterial b 3 b 2 c0 b division ratio ll 1 lh 2 hl 5 h h 10/11 b 1 b 0 1 2 channel configuration ll h=1 l h h = 2; n h =0 h h h = 2; n h =1 h l test state
january 1995 6 philips semiconductors product speci?cation universal divider hef4751v lsi programme data input (see also figs 3 and 4) the programming process is timed and controlled by input pc and pe. when the programme enable (pe) input is high; the positive edges of the programme clock (pc) signal step through the internal programme counter in a sequence of 8 states. seven states define fetch periods, each indicated by a low signal at one of the corresponding data address outputs ( od 0 to od 6 ). these data address signals may be used to address the external programme source. the data fetched from the programme source is applied to inputs a 0 to a 3 and b 0 to b 3 . when pc is low in a fetch period an internal load pulse is generated, the data is valid during this time and has to be stable. when pe is low, the programming cyclus is interrupted on the first positive edge of pc. on the next negative edge at input pc fetch period 6 is entered. data may enter asynchronously in fetch period 6. ten blocks in the u.d. need programme input signals (see fig.2). four of these (c0 b , c3, c4 and rsh) are concerned with the configuration of the u.d. and are programmed in fetch period 6. the remaining blocks (rs0 to rs4 and c1) are programmed with number p, consisting of six internal digits n 0 to n 5 . p=(n 5 10 4 + n 4 10 3 + n 3 10 2 + n 2 10 + n 1 ) m + n 0 these digits are formed by a substractor from two external numbers a and b and a borrow-in (b in ). p=a - b - b in or if this result is negative; p=a - b - b in + m 10 5 . the numbers a and b, each consisting of six four bit digits n 0a to n 5a and n 0b to n 5b , are applied in fetch period 0 to 5 to the inputs a 0 to a 3 (data a) and b 0 to b 3 (data b) in binary coded negative logic. a = (n 5a 10 4 + n 4a 10 3 + n 3a 10 2 + n 2a 10 + n 1a ) m + n 0a . b=(n 5b 10 4 + n 4b 10 3 + n 3b 10 2 + n 2b 10 + n 1b ) m + n 0b . borrow-in (b in ) is applied via input si in fetch period 0 (si = high: borrow, si = low: no borrow). counter c1 is automatically programmed with the most significant non-zero digit (n ms ) from the internal digits n 5 to n 2 of number p. the counter chain c - 2 to c1 (see fig.3) is fully programmable by the use of pulse rate feedback. rate feedback is generated by the rate selectors rs4 to rs0 and rsh, which are programmed with digits n 4 to n 0 and n h respectively. in fetch period 6 the fractional counter c3, half channel counter c4 and c0 b are programmed and configured via data b inputs. counter c3 is programmed in fetch period 6 via data a inputs in negative logic (except all high is understood as: m = 16). the counter c0 is a side steppable 10/11 counter composed of an internal part c0 b and an external part c0 a . c0 b is configured via b 3 and b 2 to a division ratio of 1 or 2 or 5 or 10/11; c0 a must have the complementary ratio 10/11 or 5/6 or 2/3 or 1 respectively. in the latter case c0 b comprises the whole c0 counter with internal feedback, c0 a is then not required. the half channel counter c4 is enabled with b 0 = high and disabled with b 0 = low. with c4 enabled, a half channel offset can be programmed with input b 1 = high, and no offset with b 1 = low. feedback to prescalers (see also figs 5 and 6) the counters c1, c0, c - 1 and c - 2 are side-steppable counters, i.e. its division ratio may be increased by one, by applying a pulse to a control terminal for the duration of one division cycle. counter c2 has 10 states, which are accessible as timing signals for the rate selectors rs1 to rs4. a rate selector, programmed with n (n 1 to n 4 in the u.d.) generates n of 10 basic timing periods an active signal. since n 9, 1 of 10 periods is always non-active. in this period rs1 transfers the output of rate selector rs0, which is timed by counter c3 and programmed with n 0 . similarly, rs0 transfers rsh output during one period of c3. rate selector rsh is timed by c4 and programmed with n h . in one of the two states of c4, if enabled, or always, if c4 is disabled, rsh transfers the low active signal at input ri to rs0. if ri is not used it must be connected to high. the feedback output signals of rs1, rs2 and rs3 are externally available as active low signals at outputs ofb 1 , ofb 2 and ofb 3 . output ofb 1 is intended for the prescaler at the highest frequency (if present), ofb 2 for the next (if present) and ofb 3 for the lowest frequency prescaler (if present). a prescaler needs a feedback signal, which is timed on one of its own division cycles in a basic timing period. the timing signal at osy is low during the last u.d. input period of a basic timing period and is suitable for timing of the feedback for the last external prescaler. the synchronization signal for a preceding prescaler is the or-function of the sync. input and sync. output of the following prescaler (all sync. signals active low).
january 1995 7 philips semiconductors product speci?cation universal divider hef4751v lsi fig.5 block diagram showing feedback to prescalers. fig.6 timing diagram showing signals occurring in fig.5.
january 1995 8 philips semiconductors product speci?cation universal divider hef4751v lsi cascading of u.d.s (see also fig. 8) a u.d. is programmed into the slave mode by the programme input data: n 2a = 11, n 2b = 10, n 3a =n 4a =n 3b =n 4b =n 5b = 0. a u.d. operating in the slave mode performs the function of two extra programmable stages c2 and c3 to a master (not slave) mode operating u.d. more slave u.d.s may be used, every slave adding two lower significant digits to the system. output ofb 3 is converted to the borrow output of the programme data subtractor, which is valid after fetch period 5. input si is the borrow input (both in master and in slave mode), which has to be valid in fetch period 0. input si has to be connected to output ofb 3 of a following slave, if not present, to low. for proper transfer of the borrow from a lower to a higher significant u.d. subtractor, the u.d.s have to be programmed sequentially in order of significance or synchronously if the programme is repeated at least the number of u.d.s in the system. rate input ri and output ofs must be connected to rate output ofb 1 and the input in of the next slave u.d. the combination thus formed retains the full programmability and features of one u.d. output (see also fig.7 ) the normal output of the u.d. is the slow output ofs, which consists of evenly spaced low pulses. this output is intended for accurate phase comparison. if a better frequency acquisition time is required, the fast output off can be used. the output frequency on off is a factor m h higher than the frequency on ofs. however, phase jitter of maximum 1 system input period occurs at off, since the division ratio of the counters preceding off are varied by slow feedback pulse trains from rate selectors following off. fig.7 timing diagram showing output pulses.
january 1995 9 philips semiconductors product speci?cation universal divider hef4751v lsi this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... fig.8 block diagram showing cascading of u.ds.
january 1995 10 philips semiconductors product speci?cation universal divider hef4751v lsi dc characteristics v ss =0 v ac characteristics v ss = 0 v; t amb =25 c; input transition times 20 ns v dd v v oh v v ol v symbol t amb ( c) - 40 + 25 + 85 min. max. min. max. min. max. output (sink) 4,75 0,4 1,6 1,4 1,1 ma current low 5 0,4 i ol 1,7 1,5 1,2 ma 10 0,5 2,9 2,7 2,2 ma output (source) 5 4,6 1,0 0,85 0,55 ma current high 5 2,5 - i oh 3,0 2,5 1,7 ma 10 9,5 3,0 2,5 1,7 ma parameter v dd v symbol min. typ. max. unit propagation delay 5 t phl 135 270 ns c l = 10 pf in ? osy 10 45 90 ns high to low output transition times high to low 5 t thl 30 60 ns c l = 50 pf 10 12 25 ns low to high 5 t tlh 45 90 ns c l = 50 pf 10 20 40 ns maximum input 5 f max 4 8 mhz d = 50% frequency; in 10 12 24 mhz c0 b ratio > 1 maximum input 5 f max 2 4 mhz d = 50% frequency; in 10 6 12 mhz c0 b ratio = 1 maximum input 5 f max 0,15 0,3 mhz frequency; pc 10 0,5 1,0 mhz v dd v typical formula for p ( m w) dynamic power where dissipation per 5 1 200 f i +? (f o c l ) v dd 2 f i = input freq. (mhz) package (p) 10 5 400 f i +? (f o c l ) v dd 2 f o = output freq. (mhz) c l = load capacitance (pf) ? (f o c l ) = sum of outputs v dd = supply voltage (v)
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