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||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| dual channel, a djustable c urrent - l imited power s witch 201 6 - 03 - 00 0 4 pt0 4 89 - 5 0 4 / 2 9 /1 6 1 pi5pd2560/2561 features ? two separate current limiting channels ? meets usb current - limiting requirement ? 7. 5 % current - limit accuracy at 2. 8 a ? adjustable current limit, 250 ma - 2. 8 a (typ) ? fast over - current response - 3. 5 s (typ) ? 44 m? high - side mosfet ? operating range: 2.5 v to 5.5 v ? 2 a maximum standby supply current ? reverse input - output voltage protection ? built - in soft - start ? 15 kv / 8 kv system - level esd capable ? device package: t dfn 3 x3 - 10 l ? ul listed C file no. e341484 ? cb certified applications ? usb ports/hubs ? digital tv ? set - to p boxes ? voip phones pin configuration t d fn 3.0 x 3.0 - 1 0 l(top view) description the pi5pd2560/2561 is dual - channel power - distribution switch intended for applications where precision current limit ing is required or heavy capacitive loads and short circuits are encountered. these devices offer a programmable current - limit threshold between 250 ma and 2. 8 a (typ) per channel via an external resistor. the power - switch rise and fall times are controlled to minimize current surges during turn on/off. each channel of the pi5pd2560/2561 device s limit the output current to a safe level by switching into a constant - current mode when the output load exceeds the current - limit threshold. the faultx logic output for each channel independently asserts low during over - current or over temperature . typical application circuit pin description pin no. pin name type description pi5pd2560 pi5pd2561 1 gnd - ground. 2 , 3 in i power i nput voltage. 4 / en1 en1 i enable input, logic low/ high turns on channel one power switch. 5 / en2 en2 i enable input, logic low/ high turns on channel two power switch. 6 /fault2 o active - low open - drain output, asserted during over - current or over - temperature condition occur on channel 2 7 ilim i external resistor used to set current - limit threshold; recommended 20 k? rilim 187 k?. 8 out 2 o power switch output for channel two 9 out 1 o power switch output for channel one 10 /fault1 o active - low open - drain output, asserted during over - current or over - temperature condition occur on chann el 1 2 1 3 4 7 8 9 10 in en 1 out1 /fault1 out2 ilim 5 6 en 2 /fault2 gnd in in o ut1 g nd /fau lt1 il im c2 0.1uf c4 in /fau lt2 r1 100k r2 100k p ow er pad o ut2 r3 c3 vin logic signal c1 e n1 e n2
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||| 201 6 - 03 - 00 0 4 pt0 4 89 - 5 0 4 / 2 9 /1 6 2 pi5pd2560/2561 dual channel, a djustable c urrent - l imited power s witch maximum ratings storage temperature ................................ ................................ ................... - 6 5 o c to +1 50 o c supply voltage to ground potential ................................ ............................ - 0. 5 v to + 6.0 v dc input voltage ................................ ................................ ...................... - 0 . 5 v to v dd + 0.5 v voltage range from in to outx ................................ ................................ .... - 0.5 v to +6.0 v control input voltage ( vinx ) ................................ ................................ ......... - 0.5 v to +6.0 v continuous total pow er dissipation (1) ................................ ................................ ....... 2400 mw continuous faultx sink current ................................ ................................ ................ 25ma power dissipation ................................ ................................ ................................ .............. 0.5w esd: hbm mode ................................ ................................ ................................ ........... 4 000v cdm mode ................................ ................................ ................................ .............. 500v esd - system level (contact/air) ................................ ................................ ............... 8kv/15kv recommended operation conditions symbol parameter conditions min typ max unit v in input voltage - 2.5 - 5.5 v v en x input voltage pi5pd2560 - 0 - 5.5 v v / en x pi5pd2561 - 0 - 5.5 v ih high - level input voltage on enx - 1.1 - - v v i l low - level input voltage on enx - - - 0.66 v i outx continuous output current per channel, outx - 0 - 2.5 a i fa u l tx continuous / faultx sink current - - - 10 ma r ilim recommended resistor limit range - 20 - 187 k ? t a operating t emperature r ange - - 40 - 85 oc note: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section s of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. the jedec high - k (2s2p) board used to derive this data was a 3in 3in, multilayer board with 1 - ounce internal power and gr ound planes and 2 - ounce copper traces on top and bottom of the board.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||| 201 6 - 03 - 00 0 4 pt0 4 89 - 5 0 4 / 2 9 /1 6 3 pi5pd2560/2561 dual channel, a djustable c urrent - l imited power s witch dc electrical characteristics v i(in) = 5.0 v; t a = - 40 c to +85 c ; unless otherwise specified. sym description test c onditions (1) min typ max unit power switch r ds(on) static drain - source on - state resis tance - - 44 70 m ? t r rise time, output v i(in) = 5. 0 v c l = 1 ? l = 100? 1 2 4 m s v i(in) = 2. 5 v 0.5 1 3 t f fall time, output v i(in) = 5. 0 v 0.3 0.5 1.0 v i(in) = 2. 5 v 0. 2 0.4 0. 6 t ios response time to short circuit v in = 5. 0 v - - 3.5 - s enable en x v ih high - level input voltage 2. 5 v v i(in) 5.5 v 1.1 - - v v il low - level input voltage 2. 5 v v i(in) 5.5 v - - 0. 6 t on turn on time c l = 1 ? l = 100? - - 5 ms t off turn off time - - 2 current limit i os current - limit threshold @ v out x = v in * 0.8 r ilim =20k ? ilim =61.9k ? ilim =100k ? oc_trip overcurrent trip threshold v in = 5 v, current ramp ( 100 a/s) on out , rilim=2 0.0 k? 2700 3160 3600 v in = 5 v, current ramp ( 100 a/s ) on out , rilim= 100 k? 450 650 800 t ios response time to short circuit v in = 5. 0 v - 3.5 - ? supply current i stb input s upply current at output disable no load on out, v en =disable t a =25c - 0.1 2 ? ss input s upply current at output enable no load o n out, v en =5. 0 v , t a =25c r ilim =20k ? ilim =100k ? rev reverse leakage current v outx =5.5v, v in =0v a =25 c - 0.01 1.0 under voltage lockout uvlo low - level input voltage v in r ising - 2.35 2.45 v hysteresis for l ow - level input voltage t a =25 c - 35 - mv /faultx flag v ol output low voltage i /faultx =1ma - - 180 mv i off o ff - state leakage v /faultx =5.5v - - 1 ? d / faultx deglitch faultx assertion or de - assertion due to over - current condition 4 9 15 m s thermal shutdown otsd2 thermal shutdown threshold - - 15 5 - c otsd thermal shutdown threshold in current - limit - - 1 3 5 - hysteresis - - 2 0 - note: pulse - testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into acc ount separately.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||| 201 6 - 03 - 00 0 4 pt0 4 89 - 5 0 4 / 2 9 /1 6 4 pi5pd2560/2561 dual channel, a djustable c urrent - l imited power s witch parameter measurement information figure1 test circuit and voltage waveforms figure2 response time to short circuit waveform typical characteristics figure 3 . typical characteristics reference schematic in o ut1 g nd /fau lt1 il im c1 0.1uf c3 channel one output in /fau lt2 r1 100k r2 100k chennel one control input /fault1 signal /fault2 signal chennel two control input p ow er pad o ut2 r3 c2 channel two output vin e n1 e n2
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||| 201 6 - 03 - 00 0 4 pt0 4 89 - 5 0 4 / 2 9 /1 6 5 pi5pd2560/2561 dual channel, a djustable c urrent - l imited power s witch typical char acteristics (continued) figure 4 . uvlo C under voltage lockout C v figure 5 . iin C supply current, output disabled C na figure 6 . iin C supply current, output enabled C a figure 7 . iin C supply current, o utput enabled C a
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||| 201 6 - 03 - 00 0 4 pt0 4 89 - 5 0 4 / 2 9 /1 6 6 pi5pd2560/2561 dual channel, a djustable c urrent - l imited power s witch typical characteristics (continued) figure 8 . mosfet rds(on) vs. junction temperature
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||| 201 6 - 03 - 00 0 4 pt0 4 89 - 5 0 4 / 2 9 /1 6 7 pi5pd2560/2561 dual channel, a djustable c urrent - l imited power s witch functional description block diagram o verview the pi5 pd2560 /256 1 are a dual - channel, current - limited power - distribution switch using n - channel mosfets for applications where short circuits or heavy capacitive loads will be encountered. this device allows the user to program the current - limit threshold betwee n 250 ma and 2.8 a (typ) p er channel via an external resistor. this device incorporates an internal charge pump and gate drive circuitry necessary to drive the n - channel mosfets. the charge pump supplies power to the driver circuit for each channel and pro vides the necessary voltage to pull the gate of the mosfet above the source. the charge pump operates from input voltages as low as 2.5 v and requires little supply current. the driver controls the gate voltage of the power swi tch. the driver incorporates circuitry that controls the rise and fall times of the output voltage to limit large current and voltage surges and provides built - in soft - start functionality. each channel of the pi5pd2560/2561 limit the output current to the programmed current - limit thre shold i os during an over - current or short - circuit event by reducing the charge pump voltage driving the n - channel mosfet and operating it in the linear range of operation. the result of limiting the output current to i os reduces the output voltage at outx because the n - channel mosfet is no longer fully enhanced. o ver - current conditions when an over - current condition is detected, the device maintains a constant output current and reduces the output voltage accordingly. the pi5pd256 0 /25 61 thermal cycles if a n overload condition is present long enough to activate thermal limiting in any of the above cases. the device turns off when the junction temperature exceeds 135c (min) while in current limit. the device remains off until the junction temperature cools 2 0c (typ) and then restarts. the pi5pd25 60 /25 61 cycles on/off until the overload is removed . / faultx response the / faultx open - drain outputs are asserted (active low) on an individual channel during an over - current or over temperatu re condition. the pi5p d2560/2561 assert the faultx signal until the fault condition is removed and the device resumes normal operation on that channel. the pi5pd2560 /25 61 are designed to eliminate false faultx reporting by using an internal delay "deglitch" circuit (9 - ms typ) f or over - current conditions without the need for external circuitry. this ensures that faultx is not accidentally asserted due to normal operation such as starting into a heavy capacitive load. the deglitch circuitry delays entering and leaving current - limi ted induced fault conditions. the faultx signal is not deglitched when the mosfet is disabled due to an over temperature condition but is deglitched after the device has cooled and begins to turn on. this unidrectional deglitch prevents faultx oscillation during an overt t emperature event.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||| 201 6 - 03 - 00 0 4 pt0 4 89 - 5 0 4 / 2 9 /1 6 8 pi5pd2560/2561 dual channel, a djustable c urrent - l imited power s witch under - v oltage lockout (uvlo) the under - voltage lockout (uvlo) circuit disables the power switch until the input voltage reaches the uvlo turn - on threshold. built - in hysteresis prevents unwanted on/off cycling due to inp ut voltage droop during turn on. e nable (enx or / enx) the logic enables control the power switches and device supply current. the supply current is reduced to less than 2a when a logic high is present on / enx or when a logic low is present on enx. a logi c low input on / enx or a logic high input on enx enables the driver, control circuits, and power switches. the enable inputs are compatible with both ttl and cmos logic levels. t hermal sense the pi5pd2560/2561 self prot ect by using two independent ther mal sensing circuits that monitor the operating temperature of the power switch and disable operation if the temperature exceeds recommended operating conditions. each channel of the pi 5pd2560/2561 operate in constant - current mode during over - current condi tions, which increases the voltage drop across the power switch. the power dissipation in the package is proportional to the voltage drop across the power switch, which increases the junction temperature during an over - current condition. the first thermal sensor (otsd) turns off the individual power switch channel when the die temperature exceeds 135c (min) and the channel is in current limit. hysteresis is built into the thermal sensor, and the switch turns on after the device has cooled approximately 20 c. the pi5pd2560/2561 also have a second ambient thermal sensor (otsd2). the ambient thermal sensor turns off both power switch channels when the die temperature exceeds 155c (min) regardless of whether the power switch channels are in current limit and w ill turn on the power switches after the device has cooled approximately 20c. the pi5pd2560/2561 continue to cycle off and on until the fault is removed. application information input and output capacitance input and output capacitance improves the perf ormance of the device; the actual capacitance should be optimized for the particular application . for all applications, a 0.1f or greater ceramic bypass capacitor between in and gnd is recommended as close to the device as possible for local noise decoupl ing. this precaution reduces ringing on the input due to power - supply transients. additional l arger input capacitance with low esr is needed on the input to reduce voltage overshoot from exceeding the absolute maximum voltage of the device during heavy tra nsient conditions. this is especially important during bench testing when long, inductive cables are used to connect the evaluation board to the bench power supply. output capacitance is not required, but placing a high - value electrolytic capacitor on the output pin is recommended when large transient currents are expected on the output. programming the current - limit threshold the over - current threshold is user programmable via an external resistor, rilim. rilim sets the current - limit threshold for both c hannels. the pi5pd2560/2561 use an internal regulation loop to provide a regulated voltage on the ilim pin. the current - limit threshold is proportional to the current sourced out of ilim. the recommended 1% resistor range for rilim is 20 k? rilim 187 k? to ensure stability of the internal regulation loop. many applications require that the minimum current limit is above a certain current level or that the maximum current limit is below a certain current level, so it is important to consider the tolerance of the over - current threshold when selecting a value for rilim. the following equations calculates the resulting overcurrent threshold for a given external resistor value (rilim). the traces routing the rilim resistor to the pi5pd256 0/2561 should be as short as possible to reduce parasitic effects on the current - limit accuracy. i os max (ma) = i os nom (ma) = i os m in (ma) = 52850v r ilim 0.957 k? 5 600 0v r ilim k? 61200 v r ilim 1.056 k?
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||| 201 6 - 03 - 00 0 4 pt0 4 89 - 5 0 4 / 2 9 /1 6 9 pi5pd2560/2561 dual channel, a djustable c urrent - l imited power s witch figure 9 . current - limit threshold vs. rilim application 1: designing above a minimum current limit some applications require that current limiting cannot occur below a certain threshold. for this example, assume that 2 a must be delivered to the load so that the minimum desired current - limit threshold is 2000 ma. use the ios equations and figure 9 to s elect rilim. i os max (ma) = 2000ma select the closest 1% resistor less than the calculated value: rilim = 25.5 k?. this sets the minim um current - limit threshold at 2 a. use the ios equations, figure 9 , and the previously calculated value for rilim to calculat e the maximum resulting current - limit threshold i os max (ma) = 2382ma the resulting maximum current - limit threshold is 2382 ma with a 25.5 k? resistor (2) i os min (ma) = r ilim ( k? ilim ( k? ? ilim ( k? ? os max (ma) = i os max (ma) = 61200 v r ilim 1.056 k? 1 1.056 61200 v i osmin ma 52850v r ilim 0.957 k? 52850v 25.5 0.957 k?
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||| 201 6 - 03 - 00 0 4 pt0 4 89 - 5 0 4 / 2 9 /1 6 10 pi5pd2560/2561 dual channel, a djustable c urrent - l imited power s witch application 2: designing below a maxim um current limit some applications require that current limiting must occur below a certain threshold. for this example, assume that the desir ed upper current - limit threshold must be below 1000 ma to protect an up - stream power supply. use the ios equations and figure 9 to select rilim. i os max (ma) = 1000ma r ilim ( k? ) = 63.16 k? select the closest 1% resistor greater than the calculated value: rilim = 63.4 k?. this sets the maximum cur rent - limit threshold at 1000 ma . use the ios equations, figure 9 , and the previously calculated value for rilim to calculate the minimum resulting current - limit threshold r ilim ( k? ) = 63.4 k? ? ? i os min (ma) = 765ma ? the resulting minimum current - limit threshold is 765 ma with a 63.4 k? resistor. accoun ting for resistor tolerance the previous sections described the selection of r ilim given certain application requirements and the importance of understanding the current - limit threshold tolerance. the analysis focused only on the pi5pd2560a/2561a performan ce and assumed an exact resistor value. however, resistors sold in quantity are not exact and are bounded by an upper and lower tolerance centered ar ound a nominal resistance. the additional r ilim resistance tolerance directly affects the current - limit thr eshold accuracy at a system level. the following table shows a process that accounts for worst - case resistor tolerance assuming 1% resistor values. step one follows the selection process outlined in the application examples above. step two determines the u pper and lower resistance bounds of the selected resistor. step three uses the upper and lower resistor bounds in the ios equations to calculate the th reshold limits. it is important to use tighter tolerance resistors, e.g. 0.5% or 0.1%, when precision cur rent limiting is desired. desired nominal current limit (ma) ideal resistor (k?) closest 1% resistor (k?) resistor tolerance actual limits 1% low (k?) 1% high(k?) ios min (ma) ios nom (ma) ios max (ma) 300 186.7 187 185.1 188.9 241.6 299.5 357.3 400 140 140 138.6 141.4 328 400 471.4 600 93.3 93.1 92.2 94 504.6 601.5 696.5 800 70 69.8 69.1 70.5 684 802.3 917.6 1000 56 56.2 55.6 56.8 859.9 996.4 1129.1 1200 46.7 46.4 45.9 46.9 1052.8 1206.9 1356.3 1400 40 40.2 39.8 40.6 1225 1393 1555.9 1600 35 3 4.8 34.5 35.1 1426.5 1609.2 1786.2 1800 31.1 30.9 30.6 31.2 1617.3 1812.3 2001.4 2000 28 28 27.7 28.3 1794.7 2000 2199.3 2200 25.5 25.5 25.2 25.8 1981 2196.1 2405.3 2400 23.3 23.2 23 23.4 2188.9 2413.8 2633 2600 21.5 21.5 21.3 21.7 2372.1 2604.7 2831. 9 2800 20 20 19.8 20.2 2560.4 2800 3034.8 i os max (ma) = r ilim ( k? os min (ma) = i os min (ma) = 52850v r ilim 0.957 k? 52850 v i osmax ma 1 0.957 61200 v r ilim 1.056 k? 61200 v 63.4 1.056 k?
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||| 201 6 - 03 - 00 0 4 pt0 4 89 - 5 0 4 / 2 9 /1 6 11 pi5pd2560/2561 dual channel, a djustable c urrent - l imited power s witch auto - retry functionality some applications require that an overcurrent condition disables the part momentarily during a fault condition and re - enables after a pre - set time. this auto - retry functionality can b e implemented with an external resistor and capacitor. during a fault condition, faultx pulls enx low disabling the part. the part is disabled when enx is pulled below the turn - off threshold, and faultx goes high impedance allowing cretry to begin charging . the part re - enables when the voltage on enx reaches the turn - on threshold, and the auto - retry time is determined by the resistor/capacitor time constant. the part will continue to cycle in this manner until the fault condition is removed. figure 10 . auto - retry functionality some applications require auto - retry functionality and the ability to enable/disable with an external logic signal. the figure below shows how an external logic signal can drive en through rfault and maintain auto - retry functiona lity. the resistor/capacitor time constant determines the auto - retry time - out period. figure 1 1 . auto - retry functionality with external en signal in o ut1 g nd /fau lt1 il im c1 0.1uf c3 in /fau lt2 r1 100k r2 100k p ow er pad o ut2 r3 20k c2 vin e n1 e n2 c3 0.22uf c2 0.22uf vou t1 vou t2 in o ut1 g nd /fau lt1 il im c1 0.1uf c3 in /fau lt2 r1 100k r2 100k p ow er pad o ut2 r3 20k c2 vin e n1 e n2 c3 0.22uf c2 0.22uf vou t1 vou t2 logic signal & drivers
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