nmos linear image sensors are self-scanning photodiode arrays designed specifically as detectors for multichannel spectroscopy. the scanning circuit is made up of n-channel mos transistors, operates at low power consumption and is easy to handle. each photodiode has a large active area, high uv sensitivity yet very low noise, delivering a high s/n even at low light levels. nmos linear image sensors also of fer excellent output linearity and wide dynamic range. the photodiodes of s3902 series have a height of 0.5 mm and are arrayed in a row at a spacing of 50 m. the photodiodes of s390 3 series also have a height of 0.5 mm but are arrayed at a spacing of 25 m. the photodiodes are available in 3 different pixel quantities fo r each series: 128 (s3902-128q), 256 (s3902-256q, s3903-256q), 512 (s3902-512q, s3903-512q) and 1024 (s3903-1024q). quartz glass is the standard w indow material. features l wide active area pixel pitch: 50 m (s3902 series) 25 m (s3903 series) pixel height: 0.5 mm l high uv sensitivity with good stability l low dark current and high saturation charge allow a long integration time and a wide dynamic range at room temperature l excellent output linearity and sensitivity spatial uniformity l lower power consumption: 1 mw max. l start pulse and clock pulses are cmos logic compatible applications l multichannel spectrophotometry l image readout system image sensor nmos linear image sensor current output, high uv sensitivity, excellent linearity, low power consumption s3902/s3903 series 0.5 mm 1.0 m 1.0 m 400 m oxidation silicon n type silicon p type silicon s3902 series: a=50 m, b=45 m s3903 series: a=25 m, b=20 m b a kmpdc0020ea ? equivalent circuit vss start st clock clock 1 2 active photodiode saturation control gate saturation control drain dummy diode dummy video active video end of scan degital shift register (mos shift register) active area structure kmpda0107ea absolute maximum ratings parameter symbol value unit input pulse ( 1, 2, st) voltage v 15 v power consumption* 1 p 1 mw operating temperature* 2 topr -40 to +65 c storage temperature tstg -40 to +85 c *1: v =5.0 v *2: no condensation 1
nmos linear image sensor s3902/s3903 series shape specifications parameter s3902- 128q s3902- 256q s3902- 512q s3903- 256q s3903- 512q s3903- 1024q unit number of pixels 128 256 512 256 512 1024 - package length 31.75 40.6 31.75 40.6 mm number of pin 22 22 - window material quartz quartz - weight 3.0 3.5 3.0 3.5 g specifications (ta=25 c) s3902 series s3903 series parameter symbol min. typ. max. min. typ. max. unit pixel pitch - - 50 - - 25 - m pixel height - - 0.5 - - 0.5 - mm spectral response range (10% of peak) 200 to 1000 200 to 1000 nm peak sensitivity wavelength p - 600 - - 600 - nm photodiode dark current* 3 i d - 0.08 0.15 - 0.04 0.08 pa photodiode capacitance* 3 cph - 4 - - 2 - pf saturation exposure* 3 * 4 esat - 180 - - 180 - m lx s saturation output charge* 3 qsat - 10 - - 5 - pc photo response non-uniformity* 5 prnu - - 3 - - 3 % *3: vb=2.0 v, v =5.0 v *4: 2856 k, tungsten lamp *5: 50% of saturation, excluding the start pixel and last pixel electrical characteristics (ta=25 c) s3902 series s3903 series parameter symbol condition min. typ. max. min. typ. max. unit high v 1, v 2 (h) - 4.5 5 10 4.5 5 10 v clock pulse ( 1, 2) voltage low v 1, v 2 (l) - 0 - 0.4 0 - 0.4 v high v s (h) - 4.5 v 1 10 4.5 v 1 10 v start pulse ( st) voltage low v s (l) - 0 - 0.4 0 - 0.4 v video bias voltage* 6 vb - 1.5 v - 3.0 v - 2.5 1.5 v - 3.0 v - 2.5 v saturation control gate voltage vscg - - 0 - - 0 - v saturation control drain voltage vscd - - vb - - vb - v clock pulse ( 1, 2) rise / fall tim e* 7 tr 1, tr 2 tf 1, tf 2 - - 20 - - 20 - ns clock pulse ( 1, 2) pulse width tpw 1, tpw 2 - 200 - - 200 - - ns start pulse ( st) rise / fall time tr s, tf s - - 20 - - 20 - ns start pulse ( 1, 2) pulse width tpw s - 200 - - 200 - - ns start pulse ( st) and clock pulse ( 2) overlap t ov - 200 - - 200 - - ns clock pulse space * 7 x 1 , x 2 - trf - 20 - - trf - 20 - - ns data rate* 8 f - 0.1 - 2000 0.1 - 2000 khz - 70 (-128 q) - - 80 (-256 q) - ns - 110 (-256 q) - - 120 (-512 q) - ns video delay time tvd 50% of saturation * 8 * 9 - 140 (-512 q) - - 160 (-1024 q) - ns - 21 (-128 q) - - 27 (-256 q) - pf - 36 (-256 q) - - 50 (-512 q) - pf clock pulse ( 1, 2) line capacitance c 5 v bias - 67 (-512 q) - - 100 (-1024 q) - pf - 12 (-128 q) - - 12 (-256 q) - pf - 20 (-256 q) - - 24 (-512 q) - pf saturation control gate (vscg) line capacitance cscg 5 v bias - 35 (-512 q) - - 45 (-1024 q) - pf - 7 (-128 q) - - 10 (-256 q) - pf - 11 (-256 q) - - 16 (-512 q) - pf video line capacitance c v 2 v bias - 20 (-512 q) - - 30 (-1024 q) - pf *6: v is input pulse voltage (refer to ? video bias voltage margin ? ) *7: trf is the clock pulse rise or fall time. a clock pulse space of ? rise time/fall time - 20 ? ns (nanoseconds) or more should be input if the clock pulse rise or fall time is longer than 20 ns. (refer to ? timing chart for driver circuit ? ) *8: vb=2.0 v, v =5.0 v * 9 : m e a su r ed wi t h c 7 883 d riv e r c ir cu i t . 2
nmos linear image sensor s3902/s3903 series dimensional outlines (unit: mm) s3902-128q, s3903-256q s3902-256q, s3903-512q 0.51 25.4 2.54 3.0 31.75 10.4 5.2 0.2 5.2 0.2 3.2 0.3 active area 6.4 0.5 0.25 10.16 1.3 0.2* chip surface * optical distance from the outer surface of the quartz window to the chip surface 0.51 25.4 2.54 3.0 active area 12.8 0.5 6.4 ?0.3 31.75 10.4 5.2 ?0.2 5.2 ?0.2 0.25 10.16 1.3 ?0.2* * optical distance from the outer surface of the quartz window to the chip surface chip surface kmpda0108eb kmpda0109eb s3902-512q, s3903-1024q 0.51 25.4 3.0 40.6 10.4 5.2 ?0.2 5.2 ?0.2 12.8 ?0.3 active area 25.6 0.5 0.25 10.16 1.3 ?0.2* * optical distance from the outer surface of the quartz window to the chip surface 2.54 chip surface kmpda0110eb nc nc nc nc nc nc nc nc nc nc end of scan 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 2 1 st vss vscg nc vscd vss active video dummy video vsub vss, vsub and nc should be grounded. kmpdc0056ea pin connection 3
nmos linear image sensor s3902/s3903 series 0.3 0.2 0.1 0 200 400 600 800 1000 1200 wavelength (nm) photo sensitivity (a/w) (ta=25 ?c) terminal input or output description 1, 2 input (cmos logic compatible) pulses for operating the mos shift register. the video data rate is equal to the clock pulse frequency since the video output signal is obtained synchronously with the rise of 2 pulse. st input (cmos logic compatible) pulse for starting the mos shift register operation. the time interval between start pulses is equal to the signal accumulation time. vss - connected to the anode of each photodiode. this should be grounded. vscg input used for restricting blooming. this should be grounded. vscd input used for restricting blooming. this should be biased at a voltage equal to the video bias voltage. active video output video output signal. connects to photodiode cathodes when the address is on. a positive voltage should be applied to the video line in order to use photodiodes with a reverse voltage. when the amplitude of 1 and 2 is 5 v, a video bias voltage of 2 v is recommended. dummy video output this has the same structure as the active video, but is not connected to photodiodes, so only spike noise is output. this should be biased at a voltage equal to the active video or left as an open-circuit when not needed. vsub - connected to the silicon substrate. this should be grounded. end of scan output (cmos logic compatible) this should be pulled up at 5 v by using a 10 k ? resistor. this is a negative going pulse that appears synchronously with the 2 timing right after the last photodiode is addressed. nc - should be grounded. 10 5 10 2 10 1 10 0 10 1 10 2 10 3 10 4 10 3 10 2 10 1 10 0 output charge (pc) exposure ( lx s) (typ. vb=2 v, v =5 v, light source: 2856 k) s3903 series s3902 series saturation exposure saturation charge kmpdb0149ea spectral response (typical example) output charge vs. e xposure kmpdb0117ea construction of image sensor the nmos image sensor consists of a scanning circuit made up of mos transistors, a photodiode array, and a switching transistor array that addresses each photodiode, all integrated onto a monolithic silicon chip. ? equivalent circuit? shows the circuit of a nmos linear image sensor. the mos scanning circuit operates at low power consump- tion and generates a scanning pulse train by using a start pulse and 2-phase clock pulses in order to turn on each ad- dress sequentially. each address switch is comprised of an nmos transistor using the photodiode as the source, the video line as the drain and the scanning pulse input section as the gate. the photodiode array operates in charge integration mode so that the output is proportional to the amount of light expo- sure (light intensity integration time). each cell consists of an active photodiode and a dummy photodiode, which are respectively connected to the active video line and the dummy video line via a switching transis- tor. each of the active photodiodes is also connected to the saturation control drain via the saturation control transistor, so that the photodiode blooming can be suppressed by grounding the saturation control gate. applying a pulse sig- nal to the saturation control gate triggers all reset. (see ? auxiliary functions?.) ? active area structure? shows the schematic diagram of the photodiode active area. this active area has a pn junction consisting of an n-type diffusion layer formed on a p-type silicon substrate. a signal charge generated by light input accumulates as a capacitive charge in this pn junction. the n-type diffusion layer provides high uv sensitivity but low dark current. 4
nmos linear image sensor s3902/s3903 series driver circuit s3902/s3903 series do not require any dc voltage supply for operation. however, the vss, vsub and all nc terminals must be grounded. a start pulse st and 2-phase clock pulses 1, 2 are needed to drive the shift register. these start and clock pulses are positive going pulses and cmos logic compatible. the 2-phase clock pulses 1, 2 can be either completely sepa- rated or complementary. however, both pulses must not be ? high ? at the same time. a clock pulse space (x 1 and x 2 in ? timing chart for driver circuit ? ) of a ? rise time/fall time - 20 ? ns or more should be input if the rise and fall times of 1, 2 are longer than 20 ns. the 1 and 2 clock pulses must be held at ? high ? at least 200 ns. since the photodiode signal is obtained at the rise of each 2 pulse, the clock pulse frequency will equal the video data rate. the amplitude of start pulse st is the same as the 1 and 2 pulses. the shift register starts the scanning at the ? high ? level of st, so the start pulse interval determines the length of signal accumulation time. the st pulse must be held ? high ? at least 200 ns and overlap with 2 at least for 200 ns. to operate the shift register correctly, 2 must change from the ? high ? level to the ? low ? level only once during ? high ? level of st. the timing chart for each pulse is shown in ? timing chart for driver cir- cuit ? . end of scan the end of scan (eos) signal appears in synchronization with the 2 timing right after the last photodiode is addressed, and the eos terminal should be pulled up at 5 v using a 10 k ? resistor. tvd tpw 1 tpw 2 tpw s st v s (h) v s (l) v 1 (h) v 1 (l) v 2 (h) v 2 (l) 1 2 end of scan st 1 2 tr s tf s tr 1 tf 1 x1 x2 t ov tf 2 tr 2 active video output kmpdc0022ea timing chart for driver circuit signal readout circuit there are two methods for reading out the signal from an nmos linear image sensor. one is a current detection method using the load resistance and the other is a current integration method using a charge amplifier. in either readout method, a positive bias must be applied to the video line because photodiode anodes of nmos linear image sensors are set at 0 v (vss). ? video bias voltage margin ? shows a typical video bias volt- age margin. as the clock pulse amplitude is higher, the video bias voltage can be set larger so the saturation charge can be increased. the rise and fall times of the video output waveform can be shortened if the video bias voltage is reduced while the clock pulse amplitude is still higher. w hen the amplitude of 1, 2 and st is 5 v, setting the video bias v oltage at 2 v is recom- mended. to obtain good linearity, using the current integration method is advised. in this method, the integration capacitance is reset to the reference voltage level immediately before each photodiode is addressed and the signal charge is then stored as an integra- tion capacitive charge when the address switch turns on. ? readout circuit example ? and ? timing chart ? show a typi- cal current integration circuit and its pulse timing chart. to en- sure stable output, the rise of a reset pulse must be delayed at least 50 ns from the fall of 2. hamamatsu provides the following driver circuits and related products (sold separately). kmpdb0043ea video bias voltage margin 4 0 6 8 10 45678 10 clock pulse amplitude (v) video bias voltage (v) 2 9 min. video bias range m ax. recommended bias product name type no. content feature c7883 high-speed driver circuit c7883g c7883 + c8225-01 high-speed operation single power supply (+15 v) operation compact c7884 precision driver circuit c7884g c7884 + c8225-01 low noise good output linearity boxcar w aveform output c7884-01 high precision driver circuit driver circuit c7884g-01 c7884-01 + c8225-01 ultra-low noise good output linearity boxcar waveform output pulse generator c8225-01 c7883, c7884 series cable a8226 c7883 to c7885 series bnc, length 1 m 5
hamamatsu photonics k.k., solid state division 1126-1 ichino-cho, higashi-ku, hamamatsu city, 435-8558 japan, telephone: (81) 53-434-3311, fax: (81) 53-434-5184, www.hamamats u.com u.s.a.: hamamatsu corporation: 360 foothill road, p.o.box 6910, bridgewater, n.j. 08807-0910, u.s.a., telephone: (1) 908-231-0 960, fax: (1) 908-231-1218 germany: hamamatsu photonics deutschland gmbh: arzbergerstr. 10, d-82211 herrsching am ammersee, germany, telephone: (49) 8152- 375-0, fax: (49) 8152-265-8 france: hamamatsu photonics france s.a.r.l.: 19, rue du saule trapu, parc du moulin de massy, 91882 massy cedex, france, teleph one: 33-(1) 69 53 71 00, fax: 33-(1) 69 53 71 10 united kingdom: hamamatsu photonics uk limited: 2 howard court, 10 tewin road, welwyn garden city, hertfordshire al7 1bw, unit ed kingdom, telephone: (44) 1707-294888, fax: (44) 1707-325777 north europe: hamamatsu photonics norden ab: smidesv ? gen 12, se-171 41 solna, sweden, telephone: (46) 8-509-031-00, fax: (46) 8-509-031-01 italy: hamamatsu photonics italia s.r.l.: strada della moia, 1 int. 6, 20020 arese, (milano), italy, telephone: (39) 02-935-81 -733, fax: (39) 02-935-81-741 information furnished by hamamatsu is believed to be reliable. however, no responsibility is assumed for possible inaccuracies or omissions. specifications are subject to change without notice. no patent rights are granted to any of the circuits described herein. type numbers of products listed inthe specification sheets or supplied as samples may have a suffix "(x)" which means tentative specifications or a suffix "(z)" which means developmental specifications. ?2010 hamamatsu photonics k.k. nmos linear image sensor s3902/s3903 series cat. no. kmpd1043e02 jun. 2010 dn readout circuit example st 2 1 vscg vss vsub nc eos eos 10 k ? +5 v +2 v + + reset 10 pf op-amp (jfet input) open dummy video active video vscd st 2 1 kmpdc0023ea 50 ns min. st 1, reset 2 kmpdc0024ea anti-blooming function if the incident light intensity is higher than the saturation charge level, even partially, a signal charge in excess of the sa turation charge cannot accumulate in the photodiode. this excessive charge flows out into the video line degrading the signal purity. to avoid this problem and maintain the signal purity, applying the same voltage as the video bias voltage to the saturation contro l drain and grounding the saturation control gate are effective. if the incident light intensity is extremely high, a positive bi as should be applied to the saturation control gate. the larger the voltage applied to the saturation control gate, the higher the functi on for suppressing the excessive saturation charge will be. however, this voltage also lowers the amount of saturation charge, so an optimum bias voltage should be selected. auxiliary functions 1) all reset in normal operation, the accumulated charge in each photodiode is reset when the signal is read out. besides this method that uses the readout line, s3902/s3903 series can reset the photodiode charge by applying a pulse to the saturation control gate. the amplitude of this pulse should be equal to the 1, 2 and st pulses and the pulse width should be longer than 5 s. when the saturation control gate is set at the ? high ? level, all photodiodes are reset to the saturation control drain potential (equal to video bias). conversely, when the saturation control gate is set at the ? low ? level (0 v), the signal charge accumulates in each photodiode without being reset. 2) dummy video s3902/s3903 series have a dummy video line to eliminate spike noise contained in the video output waveform. video signal with lower spike noise can be obtained by differential amplification applied between the active video line and dummy video line outputs. when not needed, leave this unconnected. handling precautions 1) electrostatic countermeasures nmos linear image sensors are designed to resist static electrical charges. however, take sufficient cautions and countermea- sures to prevent damage from static charges when handling the sensors. 2) window if dust or grime sticks to the surface of the light input window, it appears as a black blemish or smear on the image. before u sing the image sensor, the window surface should be cleaned. wipe off the window surface with a soft cloth, cleaning paper or cotton swab slightly moistened with organic solvent such as alcohol, and then lightly blow away with compressed air. do not rub the window with dry cloth or cotton swab as this may generate static electricity. output voltage vout is vout [ v ] = output charge [ c ] 10 10 -12 [ f ] shown in. 6 timing chart
|
