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document no. doc-15214-7 www.e2v-us.com page 1 of 21 ?2010-2015 peregrine semiconductor corp. all rights reserved. peregrine?s pe97240 is a radiation tolerant high- performance integer-n pll capable of frequency synthesis up to 5 ghz. the device is designed for commercial space applications and optimized for superior phase noise performance. the pe97240 features a selectable prescaler modulus of 5/6 or 10/11, counters and a phase comparator as shown in figure 1 . counter values are programmable through either a serial interface or directly hard-wired. the pe97240 is available in a 44-lead cqfp and is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering excellent rf performance and intrinsic radiation tolerance. product specification radiation tolerant ultracmos ? integer-n frequency synthesizer for low phase noise applications product description pe97240 features ?? frequency range ?? 5 ghz in 10/11 prescaler modulus ?? 4 ghz in 5/6 prescaler modulus ?? phase noise floor figure of merit: ?230 dbc/hz ?? low power: 75 ma @ 2.7v ?? serial or direct mode access ?? packaged in a 44-lead cqfp ?? 100 krad(si) total dose figure 1. functional diagram pe97240
page 2 of 21 ?2010-2015 peregrine semiconductor corp. all rights reserved. document no. doc-15214-7 ultracmos ? rfic solutions product specification pe97240 table 1. pin descriptions figure 3. package type 44-lead cqfp figure 2. pin configurations (top view) pin # pin name interface mode type description 1 v dd both note 1 power supply input. input may range from 2.6?2.8v. bypassing recommended. 2 r4 direct input r counter bit4 3 r5 direct input r counter bit5 4 a3 direct input a counter bit3 5 gnd both ground 6 m3 direct input m counter bit3 7 m2 direct input m counter bit2 8 m1 direct input m counter bit1 9 m0 direct input m counter bit0 10 v dd both note 1 power supply input. input may range from 2.6?2.8v. bypassing recommended. 11 gnd both ground 12 m8 direct input m counter bit8 13 m7 direct input m counter bit7 14 sclk serial input serial clock input. sdata is clocked serially into the 21-bit primary register (e_wr ?low?) or the 8-bit enhancement register (e_w r ?high?) on the rising edge of sclk. m6 direct input m counter bit6 15 sdata serial input binary serial data input. input data entered msb first. m5 direct input m counter bit5 16 s_wr serial input serial load enable input. while s_wr is ?low?, sdata can be serially clocked. primary register data is transferred to the secondar y register on s_wr or hop_wr rising edge. m4 direct input m counter bit4
page 3 of 21 document no. doc-15214-7 www.e2v-us.com ?2010-2015 peregrine semiconductor corp. all rights reserved. product specification pe97240 table 1. pin descriptions (continued) pin no. pin name interface mode type description 17 direct direct input select ?high? enables di rect mode. select ?low? enables serial mode. 18 a0 direct input a counter bit0 a1 direct input a counter bit1 e_wr serial input enhancement register write enable. while e_ wr is ?high?, sdata can be serially clocked into the enhancement register on the rising edge of sclk. 20 a2 direct input a counter bit2 21 v dd both note 1 power supply input. input may range from 2.6?2.8v. bypassing recommended. 22 pre_en direct input prescaler enable, active ?low?. when ?high?, f in bypasses the prescaler. 23 pre_5/6_sel direct input 5/6 modulus select, ac tive ?high.? when ?low,? 10/11 modulus selected. 24 v dd both note 1 power supply input. input may range from 2.6?2.8v. bypassing recommended. 25 f in both input prescaler complementary input. a 22 pf by pass capacitor should be placed as close as possible to this pin and be connected in series with a 50 resistor to ground. 26 f in both input prescaler input from the vco, 5.0 ghz max frequency. a 22 pf coupling capacitor should be placed as close as possible to this pin and be connected in shunt to a 50 ? resistor to ground. 27 gnd both ground 28 d out serial output data out. the msel signal and the raw prescaler output are available on dout through enhancement register programming. 29 c ext both output logical ?nand? of pd_ d ? and pd_ u ? terminated through an on chip, 2 k ? series resistor. connecting cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving ld. 30 ld both output lock detect and open drain logical inversion of c ext . when the loop is in lock, ld is high impedance, otherwise ld is a logic low (?0?). 31 v dd both note 1 power supply input. input may range from 2.6v to 2.8v. bypassing recommended. 32 pd_ d both output pd_ d ? is pulse down when f p leads f c 33 pd_ u both output pd_ u is pulse down when f c leads f p 34 v dd both note 1 power supply input. input may range from 2.6?2.8v. bypassing recommended. 35 v dd both note 1 power supply input. input may range from 2.6?2.8v. bypassing recommended. 36 gnd both ground 37 f r both input reference frequency input 38 v dd both note 1 power supply input. input may range from 2.6?2.8v. bypassing recommended. 39 enh serial input enhancement mode. when asserted low (?0?), enhancement register bits are functional. 40 r0 direct input r counter bit0 41 r1 direct input r counter bit1 42 r2 direct input r counter bit2 43 r3 direct input r counter bit3 44 gnd both ground 19 notes: 1. v dd pins 1, 10, 21, 24, 31, 34, 35 and 38 are connected by diodes and must be supplied with the same positive voltage level. 2. all digital input pins have 70 k ? pull-down resistors to ground.
page 4 of 21 ?2010-2015 peregrine semiconductor corp. all rights reserved. document no. doc-15214-7 ultracmos ? rfic solutions product specification pe97240 table 3. absolute maximum ratings notes: 1. human body model (mil-std-883 method 3015). 2. pin 28 is not used in normal operation. electrostatic discharge (esd) precautions when handling this ultracmos device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up immunity unlike conventional cmos devices, ultracmos devices are immune to latch-up. table 2. operating ratings parameter/condition symbol min max unit supply voltage v dd ?0.3 3.3 v voltage on any input v i ?0.3 v dd + 0.3 v dc into any input i i ?10 +10 ma dc into any output i o ?10 +10 ma storage temperature range t st ?65 +150 c esd voltage hbm 1 all pins except pin 28 1000 v esd voltage hbm 1,2 on pin 28 300 v v esd_hbm thermal resistance t jc 33.4 c/w junction temperature t j +125 c rf input power, cw 50 mhz?5 ghz p max_cw 10 dbm parameter/condition symbol min max unit supply voltage v dd 2.6 2.8 v operating ambient temperature range t a ?40 +85 ? c exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. eldrs ultracmos devices do not include bipolar minority carrier elements, and therefore do not exhibit enhanced low dose rate sensitivity. table 4. single event effects 1 see mode effective linear energy transfer (let) 2 sel 86 mev ? cm 2 /mg set 30 mev ? cm 2 /mg 3 sefi 86 mev ? cm 2 /mg seu 86 mev ? cm 2 /mg notes: 1. testing performed using serial programming mode. 2. see testing was conducted with au, ho, xe, kr, cu ion species at 0 incidence. 3. minor transients (phase errors) observed resulting in self-recovering operation without intervention.
page 5 of 21 document no. doc-15214-7 www.e2v-us.com ?2010-2015 peregrine semiconductor corp. all rights reserved. product specification pe97240 table 5. dc characteristics @ v dd = 2.7v, ?40 c < t a < +85 c, unless otherwise specified symbol parameter condition min typ max unit i dd prescaler disabled, f c = 50 mhz, f in = 500 mhz v dd = 2.6?2.8v 34 50 ma 5/6 prescaler, f c = 50 mhz, f in = 3 ghz v dd = 2.6?2.8v 72 105 ma 10/11 prescaler, f c = 50 mhz, f in = 3 ghz v dd = 2.6?2.8v 74 110 ma digital inputs: all except f r , f in , f in v ih high level input voltage v dd = 2.6?2.8v 0.7 x v dd v v il low level input voltage v dd = 2.6?2.8v 0.3 x v dd v i ih high level input current v ih = v dd = 2.8v 70 a i il low level input current v il = 0, v dd = 2.8v ?10 a reference divider input: f r i ihr high level input current v ih = v dd = 2.8v 300 a i ilr low level input current v il = 0, v dd = 2.8v ?300 a counter and phase detector outputs: pd_ d , ? pd_ u v old output voltage low i out = 6 ma 0.4 v v ohd output voltage high i out = ?3 ma v dd ? 0.4 v lock detect outputs: c ext , ld v olc output voltage low, c ext i out = 100 a 0.4 v v ohc output voltage high, c ext i out = ?100 a v dd ? 0.4 v v olld output voltage low, ld i out = 1 ma 0.4 v operational supply current
page 6 of 21 ?2010-2015 peregrine semiconductor corp. all rights reserved. document no. doc-15214-7 ultracmos ? rfic solutions product specification pe97240 table 6. ac characteristics @ v dd = 2.7v, ?40 c < t a < +85 c, unless otherwise specified symbol parameter condition min typ max unit control interface and latches (see figures 16 and 17 ) 1 f clk serial data clock frequency 2 10 mhz t clkh serial clock high time 30 ns t clkl serial clock low time 30 ns t dsu sdata set-up time after sclk rising edge 10 ns t dhld sdata hold time after sclk rising edge 10 ns t pw s_wr pulse width 30 ns t cwr sclk rising edge to s_wr rising edge 30 ns t ce sclk falling edge to e_wr transition 30 ns t wrc s_wr falling edge to sclk rising edge 30 ns t ec e_wr transition to sclk rising edge 30 ns main divider 5/6 (including prescaler) f in operating frequency 800 4000 mhz p f_in input level range external ac coupling 800 mhz?4 ghz ?5 3 7 dbm main divider 10/11 (including prescaler) f in operating frequency 800 5000 mhz p f_in input level range external ac coupling 800 mhz?<4 ghz 4?5 ghz ?5 3 2 7 7 dbm dbm main divider (prescaler bypassed) f in operating frequency 50 800 mhz p f_in input level range external ac coupling ?5 3 7 dbm reference divider f r operating frequency 100 mhz p f_r reference input power 4 single-ended input ?5 5 7 dbm phase detector f c comparison frequency 100 mhz
page 7 of 21 document no. doc-15214-7 www.e2v-us.com ?2010-2015 peregrine semiconductor corp. all rights reserved. product specification pe97240 table 6. ac characteristics @ v dd = 2.7v, ?40 c < t a < +85 c, unless otherwise specified (continued) symbol parameter condition min typical max unit ssb phase noise 5/6 prescaler (f in = 3 ghz, p f_r = +5 dbm, f c = 50 mhz, lbw = 500 khz) ? n ? phase noise 100 hz offset ?100 ?92 dbc/hz ? n ? phase noise 1 khz offset ?109 ?103 dbc/hz ? n ? phase noise 10 khz offset ?116 ?110 dbc/hz ? n ? phase noise 100 khz offset ?118 ?115 dbc/hz ssb phase noise 10/11 prescaler (f in = 3 ghz, p f_r = +5 dbm, f c = 50 mhz, lbw = 500 khz) ? n ? phase noise 100 hz offset ?98 ?91 dbc/hz ? n ? phase noise 1 khz offset ?104 ?98 dbc/hz ? n ? phase noise 10 khz offset ?111 ?107 dbc/hz ? n ? phase noise 100 khz offset ?117 ?113 dbc/hz phase noise figure of merit (fom) 6 fom flicker flicker figure of merit 5/6 prescaler ?268 ?265 dbc/hz 10/11 prescaler ?263 ?259 dbc/hz fom floor floor figure of merit 5/6 prescaler ?230 ?227 dbc/hz 10/11 prescaler ?229 ?225 dbc/hz fom flicker pn flicker = fom flicker + 20log (f in ) ? 10log (f offset ) dbc/hz fom floor pn floor = fom floor + 10log (f c ) + 20log (f in /f c ) dbc/hz fom total dbc/hz pn total = 10log (10 [pn flicker /10] + 10 [pn floor /10]) notes: 1. timing parameters are guaranteed through desi gn characterization and not tested in production. 2. f clk is verified during the functional pattern test. serial programmi ng sections of the functional pattern are clocked at 10 mhz to verify f clk specification. 3. 0 dbm minimum is recommended for improved pha se noise performance when sine-wave is applied. 4. cmos logic levels can be used to drive the reference input. if the v dd of the cmos driver matches the v dd of the pll ic, then the reference input can be dc coupled. otherwise, the reference input should be ac coupled. for sine-wave inputs, the minimum amplitude needs to be 0.5 v pp . the maximum level should be limited to prevent esd diodes at the pin input from turning on. diodes will turn on at one forward-bias diode drop above v dd or below gnd. the dc voltage at the reference input is v dd /2. 5. +2 dbm or higher is recommended for improved phase noise performance. 6. the phase noise can be separated into two normalized specif ications: a floor figure of merit and a flicker figure of merit . to accurately measure the phase noise floor without the contribution of the flicker noise, the loop bandw idth is set to 500 khz and the phase noise is measured at a frequency offset near 100 khz. the flicker noise is measured at a frequency offset 1000 hz. the formula assumes a ?10 db /decade slope versus frequency offset.
page 8 of 21 ?2010-2015 peregrine semiconductor corp. all rights reserved. document no. doc-15214-7 ultracmos ? rfic solutions product specification pe97240 figure 4. equivalent input diagram: digital input doc-69911 figure 5. equivalent input diagram: reference input doc-02126 figure 6. equivalent input diagram: main input doc-02127 r f r f r f = 15 k c eq = 4.5 pf l bw = 3 nh l bw c eq f r 37 pin 37 pin l bw 3 nh v dd reference input r f r f v dd f in 26 pin l bw 3 nh v dd f in 25 pin l bw 3 nh r f r f = 50 k c eq = 1 pf l bw = 3 nh l bw c eq 26 pin r f l bw c eq 25 pin main input v dd r f = 87 k c eq = 1 pf l bw = 3 nh r f l bw c eq digital input pin digital input
page 9 of 21 document no. doc-15214-7 www.e2v-us.com ?2010-2015 peregrine semiconductor corp. all rights reserved. product specification pe97240 figure 7. equivalent output diagram pd_ d d (pin 55) and pd_ u (pin 57) output r n r p = 33 r n = 15 c l pd_ d and pd_ u pin 32 pin 33 pin 32 or pin 33 l bw l bw l bw 3 nh v dd r p v dd c l pin 32 or pin 33 c l = 3 pf l bw = 3 nh or pull-down on pull-up on doc-02128
page 10 of 21 ?2010-2015 peregrine semiconductor corp. all rights reserved. document no. doc-15214-7 ultracmos ? rfic solutions product specification pe97240 figure 8. typical phase noise 5/6 prescaler f in = 3 ghz, v dd = 2.7v, loop bandwidth = 500 khz, +25 c figure 9. typical phase noise 10/11 prescaler f in = 3 ghz, v dd = 2.7v, loop bandwidth = 500 khz, +25 c typical performance data@ v dd = 2.6?2.8v, ?40 c < t a < +85 c, f c = 50 mhz and f in = 3 ghz phase noise (dbc/hz) frequency offset (hz) phase noise (dbc/hz) frequency offset (hz)
page 11 of 21 document no. doc-15214-7 www.e2v-us.com ?2010-2015 peregrine semiconductor corp. all rights reserved. product specification pe97240 \ 280 \ 270 \ 260 \ 250 \ 240 \ 230 \ 220 \ 40 25 85 figure ? of ? merit temperature ? (c) floor ? fom, ? 2.6v floor ? fom, ? 2.7v floor ? fom, ? 2.8v flicker ? fom, ? 2.6v flicker ? fom, ? 2.7v flicker ? fom, ? 2.8v \ 280 \ 270 \ 260 \ 250 \ 240 \ 230 \ 220 \ 50258 figure ? of ? merit reference ? power ? (dbm) floor ? fom, ?\ 40c floor ? fom, ? +25c floor ? fom, ? +85c flicker ? fom, ?\ 40c flicker ? fom, ? +25c flicker ? fom, ? +85c \ 280 \ 270 \ 260 \ 250 \ 240 \ 230 \ 220 \ 40 25 85 figure ? of ? merit temperature ? (c) floor ? fom, ? 2.6v floor ? fom, ? 2.7v floor ? fom, ? 2.8v flicker ? fom, ? 2.6v flicker ? fom, ? 2.7v flicker ? fom, ? 2.8v \ 280 \ 270 \ 260 \ 250 \ 240 \ 230 \ 220 \ 50258 figure ? of ? merit reference ? power ? (dbm) floor ? fom, ?\ 40c floor ? fom, ? +25c floor ? fom, ? +85c flicker ? fom, ?\ 40c flicker ? fom, ? +25c flicker ? fom, ? +85c typical performance data @ v dd = 2.6?2.8v, ?40 c < t a < +85 c, f c = 50 mhz and f in = 3 ghz figure 10. fom vs. reference power and temp (5/6 prescaler, v dd = 2.7v) figure 11. fom vs. reference power and temp (10/11 prescaler, v dd = 2.7v) figure 12. fom vs. temp and supply voltage (5/6 prescaler, p f_in = 2 dbm) figure 13. fom vs. temp and supply voltage (10/11 prescaler, p f_in = 2 dbm) figure 10. rf sensitivity vs. f in and temp (5/6 prescaler, v dd = 2.6v ) * figure 11. rf sensitivity vs. f in and temp (10/11 prescaler, v dd = 2.6v ) * note: * rf sensitivity is the minimum input power level required for the pll to maintain lock. operating at these levels does not guarantee the ssb phase noise performance in table 6. \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 800 1100 1300 1500 1700 1900 2100 2300 2500 2700 2900 3100 3300 3500 3700 3900 input ? sensitivity ? (dbm) operating ? frequency ? (mhz) \ 40 ? c +25 ? c +85 ? c \ 30 \ 25 \ 20 \ 15 \ 10 \ 5 0 800 1100 1300 1500 1720 1900 2100 2300 2500 2700 2900 3100 3300 3500 3700 3900 4100 4300 4500 4700 4900 input ? sensitivity ? (dbm) operating ? frequency ? (mhz) \ 40 ? c +25 ? c +85 ? c figure 14. rf sensitivity vs. f in and temp (5/6 prescaler, v dd = 2.6v)* figure 15. rf sensitivity vs. f in and temp (10/11 prescaler, v dd = 2.6v)*
page 12 of 21 ?2010-2015 peregrine semiconductor corp. all rights reserved. document no. doc-15214-7 ultracmos ? rfic solutions product specification pe97240 functional description the pe97240 consists of a prescaler, counters, a phase detector, and control logic. the dual modulus prescaler divides the vco frequency by either 5/6 or 10/11, depending on the value of the modulus select. counters ?r? and ?m? divide the reference and prescaler output, respectively, by integer values stored in a 21-bit register. an additional counter (?a?) is used in the modulus select logic. the phase-frequency detector generates up and down frequency control signals. the control logic includes a selectable chip interface. data can be written via serial bus or hardwired directly to the pins. there are also various operational and test modes and a lock detect output. figure 16. functional block diagram prescaler 5/6 or 10/11 main counter m(8:0) a(3:0) r(5:0) 20 20 r counter phase detector 6 6 13 pd_u pd_d msel prescaler enable select sdata s_wr sclk secondary 20-bit latch primary 21-bit latch input buffer pre_5/6_sel pre_en cext input buffer ld f p f c fr direct v dd gnd enh register 8-bit 8 e_wr sdata sclk enh dout f c f p msel 8 direct mode serial mode f in f in f in f in f r
page 13 of 21 document no. doc-15214-7 www.e2v-us.com ?2010-2015 peregrine semiconductor corp. all rights reserved. product specification pe97240 main counter chain normal operating mode the main counter chain divides the rf input frequency, f in , by an integer derived from the user- defined values in the ?m? and ?a? counters. it is composed of the 5/6 or 10/11 selectable modulus prescaler, modulus select logic, and 9-bit m counter. the prescaler can be set to either 5/6 or 10/11 based on the pre_5/6_sel pin. setting pre_en ?low? enables the 5/6 or 10/11 prescaler. setting pre_en ?high? allows f in to bypass the prescaler and powers down the prescaler. the output from the main counter chain, f p , is related to the vco frequency, f in , by the following equation: f p = f in / [10 x (m + 1) + a] (1) where a ? m + 1, 1 m 511 or f p = f in / [5 x (m + 1) + a] where a ? m + 1, 1 m 511 when the loop is locked, f in is related to the reference frequency, f r , by the following equation: f in = [10 x (m + 1) + a] x [f r / (r + 1)] (2) where a ? m + 1, 1 m 511 or f in = [5 x (m + 1) + a] x [f r / (r + 1)] where a ? m + 1, 1 m 511 a consequence of the upper limit on a is that in integer-n mode, to obtain contiguous channels, f in must be = 90 x [ f r / (r + 1)] with 10/11 modulus f in must be = 20 x [ f r / (r + 1)] with 5/6 modulus the a counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in m. programming the m counter with the minimum allowed value of ?1? will result in a minimum m counter divide ratio of ?2?. prescaler bypass mode setting pre_en ?high? allows f in to bypass and power down the prescaler. in this mode, the 5/6 or 10/11 prescaler and a register are not active, and the input vco frequency is divided by the m counter directly. the following equation relates f in to the reference frequency, f r : f in = (m + 1) x [f r / (r + 1)] (3) where 1 m 511 reference counter the reference counter chain divides the reference frequency, f r , down to the phase detector comparison frequency, f c . the output frequency of the 6-bit r counter is related to the reference frequency by the following equation: f c = f r / (r + 1) (4) where 0 r 63 note that programming r with ?0? will pass the reference frequency, f r , directly to the phase detector.
page 14 of 21 ?2010-2015 peregrine semiconductor corp. all rights reserved. document no. doc-15214-7 ultracmos ? rfic solutions product specification pe97240 serial interface mode while the e_wr input is ?low? and the s_wr input is ?low?, serial input data (sdata input), b 0 to b 20 , is clocked serially into the primary register on the rising edge of sclk, msb (b 0 ) first. the contents from the primary register are transferred into the secondary register on the rising edge of s_wr according to the timing diagram shown in figure 17 . data is transferred to the counters as shown in table 7 . while the e_wr input is ?high? and the s_wr input is ?low?, serial input data (sdata input), b 0 to b 7 , is clocked serially into the enhancement register on the rising edge of sclk, msb (b 0 ) first. the enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially-entered data performed on the falling edge of e_wr according to the timing diagram shown in figure 17 . after the falling edge of e_wr, the data provides control bits as shown in tables 8 and 9 with bit functionality enabled by asserting the enh input ?low?. ? direct interface mode direct interface mode is selected by setting the direct input ?high?. counter control bits are set directly at the pins as shown in table 7 . msb (first in) (last in) lsb table 7. primary register programming table 8. enhancement register programming note: * serial data clocked serially on sclk rising edge while e_ wr ?low? and captured in secondary register on s_wr rising edg e. note: * serial data clocked serially on sclk rising edge while e_wr ?high? and captured in the double buffer on e_wr falling ed ge. msb (first in) (last in) lsb interface mode enh r 5 r 4 m 8 m 7 pre_en m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 addr serial* 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 b 18 b 19 b 20 direct 1 r 5 r 4 m 8 m 7 pre_en m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 0 interface mode enh reserved reserved f p output power down counter load msel output f c output ld disable serial* 0 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 direct 0
page 15 of 21 document no. doc-15214-7 www.e2v-us.com ?2010-2015 peregrine semiconductor corp. all rights reserved. product specification pe97240 figure 17. serial interface mode timing diagram enhancement register the functions of the enhancement register bits ar e shown below with all bits active ?high?. table 9. enhancement register bit functionality note: * program to 0. bit function description bit 0 reserve* reserved. bit 1 reserve* reserved. bit 2 f p output drives the m counter output onto the d out output. bit 3 power down power down of all functions except programming interface. bit 4 counter load immediate and cont inuous load of counter programming. bit 5 msel output drives the internal dual modul us prescaler modulus select (msel) onto the d out output. bit 6 f c output drives the reference counter output onto the d out output. bit 7 ld disable disables the ld pin for quieter operation.
page 16 of 21 ?2010-2015 peregrine semiconductor corp. all rights reserved. document no. doc-15214-7 ultracmos ? rfic solutions product specification pe97240 phase detector the phase detector is triggered by rising edges from the main counter (f p ) and the reference counter (f c ). it has two outputs, namely pd_ u , and pd_ d . if the divided vco leads the divided reference in phase or frequency (f p leads f c ), pd_ d pulses ?low?. if the divided reference leads the divided vco in phase or frequency (f r leads f p ), pd_ u pulses ?low?. the width of either pulse is directly proportional to phase offset between the two input signals, f p and f c . the phase detector gain is 400 mv/radian. pd_ u and pd_ d are designed to drive an active loop filter which controls the vco tune voltage. pd_ u pulses result in an increase in vco frequency and pd_ d results in a decrease in vco frequency. a lock detect output, ld is also provided, via the pin c ext . c ext is the logical ?nand? of pd_ u and pd_ d waveforms, which is driven through a series 2 k ? resistor. connecting c ext to an external shunt capacitor provides integration. c ext also drives the input of an internal inverting comparator with an open drain output. thus ld is an ?and? function of pd_ u and pd_ d . see figure 16 for a functional block diagram of this circuit.
page 17 of 21 document no. doc-15214-7 www.e2v-us.com ?2010-2015 peregrine semiconductor corp. all rights reserved. product specification pe97240 figure 19. evaluation board layout figure 18. evaluation kit evaluation board the pe97240 evaluation board was designed to demonstrate optimal phase noise performance when using an external and stable low noise reference source. the device may be programmed serially using the usb interface board with the applications software or directly by using jumpers to set the register values. additionally, an external vco may be used for specific operating frequencies. the evaluation board consists of a four layer stack with two outer layers made of rogers 4350b ( ? r = 3.48) and two inner layers of fr406 ( ? r = 4.80). the 12 mil (0.30 mm) thick inner layers provide ground planes for the rf transmission lines. the total thickness of the board is 62 mils (1.57 mm). prt-50550
page 18 of 21 ?2010-2015 peregrine semiconductor corp. all rights reserved. document no. doc-15214-7 ultracmos ? rfic solutions product specification pe97240 figure 20. evaluation board schematic doc-50870
page 19 of 21 document no. doc-15214-7 www.e2v-us.com ?2010-2015 peregrine semiconductor corp. all rights reserved. product specification pe97240 figure 20. evaluation board schematic (continued)
page 20 of 21 ?2010-2015 peregrine semiconductor corp. all rights reserved. document no. doc-15214-7 ultracmos ? rfic solutions product specification pe97240 9.830.20 0.300.05 (x44) 0.65 (x40) 7.120.05 8.910.15 pin 1 identifier 111 3 3 3 2 12 44 2 2 4 3 r0.50 (x4) r0.25 (x4) 14.370.13 14.370.13 8.91 top view bottom view 6.50 9.830.20 figure 21. package drawing 44-lead cqfp doc-50613 1.02 1.33 10020 0.84 1.040.10 0.150.05 0.310.03 0.13 1.48 side view
page 21 of 21 document no. doc-15214-7 www.e2v-us.com ?2010-2015 peregrine semiconductor corp. all rights reserved. product specification pe97240 table 10. ordering information order code description package shipping method 97240-01* engineering samples 44-lead cqfp 40 units/tray 97240-11 flight units 44- lead cqfp 40 units/tray 97240-00 evaluation kit ev aluation kit 1/box note: * the pe97240-01 devices are es (engineering sample) prototyp e units intended for use as initial evaluation units for cus tomers of the pe97240-11 flight units. the pe97240-01 device provides the same functionality and footprint as the pe97240-11 space qualified device, and intended for engi neering evaluation only. they are tested at +25 c only and processed to a non-compliant flow (e.g. no burn-in, non-hermetic, etc). these units are non-hermetic and are not suitable for qualification, production, radiation testing or flight use. figure 22. top marking specifications 97240-xx = part number (xx will be specified by the po and/or the assembly instructions) yyww = date code, last two digits of the year and work week zzzzzzz = lot code (up to seven digits) nnnnnn = serial number of the part (up to six digits) = pin 1 indicator pe97240-xx yyww zzzzzzz nnnnnn pin 1 prt-55218 cont act info r mation: e2v ~ http://ww w.e2v-us.com ~ inquiries @e2v-us.com ad van ce inf or m at io n : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specificat ion: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine w ill n o tify c us to m e rs of th e i nt ended changes by issuing a cn f (customer n o tifi c ati o n f o rm ). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no lia bility fo r d a m ages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracm os and u tsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information

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