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BL6528 single - phase multifunction metering ic 1 / 27 v1.0 features ? h igh accuracy. l ess than 0.1% error in active energy measurement and reactive measurement over a dynamic range of 3000:1. ? h igh stability , less than 0.1%error in the output frequency fluctuation. ? m easure the active power in the positive orientation and negative orientation, transform to fast pulse output ( cf). ? m easure the reactive power transform to fast pulse output ( cf_var). ? m easure the reactive power transform to fast puls e output ( cf_va). ? m easure instantaneous irms and vrms over a dynamic range of 1500:1. ? o n - chip sag and zero - crossing detector. ? o n - chip power supply detector. ? o n - chip anti - creep protection with the programmable threshold set. ? p rovide the pulse output with programmable frequency adjustment. ? p rovide the programmable gain adjustment and phase compensation ? m easure the power factor ( pf). ? p rovide a programmable interrupt request signal ( /irq ). ? p rovide a spi /uart communication interface. ? o n - chip voltage reference of 2.5v. ? w ith 3.58mhz external crystal oscillator. ? s ingle 5v supply, 30mw(typical) interrelated patents are pending description t he BL6528 is a low cost, high accuracy, high stability, electrical energy measurement ic intended to single phase, multifunction applications. t he BL6528 incorporates two high accuracy sigma - delta adc, voltage reference, power management and digital signal processing circuit using to calculates active energy , reactive energy ,apparent energy ,irms ,vrms etc. t he bl6 528 measures line voltage, current and calculates active ,reactive ,apparent energy, power factor, line frequency, detect sag, overvoltage, overcurrent, peak, zero - crossing voltage. t he BL6528 provide access to on - chip meter registers via spi communicatio n interface. t he BL6528 provide all - digital domain offset compensation, gain adjustment, phase compensation (maximum 2.54 adjustable).
BL6528 single - phase multifunction metering ic 2 / 27 v1.0 pin configuration pin descriptions ( ssop24 ) pin symbol descriptions 1,24 at0,at1 p rogrammable digital output. s ee at_sel register section. 2 nrst r eset pin. l ogic low on this pin will hold the adcs and digital circuitry in a reset condition and clear internal registers. 3 dvdd digital power supply +5v ,provides the supply voltage for the digital circuitry. i t should be maintained at 5 v 5% for specified operation 4 avdd power supply (+5v) . p rovides the supply voltage for the circuitry. it should be maintained at 5 v 5% for specified operation. 5,6 v1p,v1n a nalog input for current channel, these inputs are fully differential voltage inputs with a maximum signal level of 660 mv , adjustable gain. 7,8 v 2n,v2p negative and positive inputs for voltage channel. these inputs pro vide a fully differential input pair. the maximum differential input voltage is 660 mv for specified operation. adjustable gain. 1 2 3 4 5 6 7 8 2 2 2 1 2 0 1 9 1 8 1 7 9 1 0 1 6 1 5 2 4 2 3 n r s t d v d d a v d d v 1 p v 1 n v 2 n v 2 p a g n d v r e f d g n d d i n / u r x d d o u t / u t x d s c l k n c s c l k o u t c l k i n n i r q n s a g z x c f _ w a t t b l 6 5 2 8 a p g a a d c d s p s p i i r m s , v r m s i p i n v p v n s c l k / c s c l k o u t c l k b a n d g a p v r e f a d c u a r t d o u t d i n p g a b l 6 5 2 8 a a g n d s s o p 2 4 1 1 1 2 1 4 1 3 s e l a t 0 c f _ v a r a t 1 p f w a t t , w a t t h r v a r , v a r h r v a , v a h r i p e a k , v p e a k s a g , z x u r x d c f _ v a r a v d d d v d d p o r / r s t d g n d c f _ w a t t i r q / i r q u t x d c l k i n 1 2 3 4 5 6 7 8 2 2 2 1 2 0 1 9 1 8 1 7 9 1 0 1 6 1 5 2 4 2 3 n r s t d v d d a v d d v 1 p v 1 n v 2 n v 2 p a g n d v r e f d g n d d i n / u r x d d o u t / u t x d s c l k n c s c l k o u t c l k i n n i r q n s a g z x c f _ w a t t b l 6 5 2 8 a s s o p 2 4 1 1 1 2 1 4 1 3 s e l a t 0 c f _ v a r a t 1 1 2 3 4 5 6 7 8 2 0 1 9 1 8 1 7 9 1 0 1 6 1 5 n r s t d v d d a v d d v 1 p v 1 n v 2 n v 2 p a g n d v r e f d g n d d i n d o u t s c l k n c s c l k o u t c l k i n n i r q n s a g z x c f _ w a t t b l 6 5 2 8 b s s o p 2 0 1 2 1 1 1 4 1 3
BL6528 single - phase multifunction metering ic 3 / 27 v1.0 9 agnd ground reference . provides the ground reference for the circuitry . 10 v ref on - chip voltage reference. the on - chip reference has a nominal value of 2. 5 v 8% and a typical temperature coefficient of 30 ppm/ . an external reference source may also be connected at this pin. t his pin should be decoupled to agnd with a 1uf ceramic capacitor. 11 dgnd d igital ground. 12 sel logic input to select spi or uart . t he default is 0, spi mode; sel=1,uart mode. 13 cf_var c alibration frequency. t he cf_var logic output gives instantaneous reactive power information. t his output is intended to use for calibration purposes. t he full - scale output frequency can be scaled by the value of cfdiv register. w hen the power is low, the pulse width is equal to 90ms. w hen the power is high and the output period less than 180ms, the pulse width equals to half of the output period. 14 cf _watt c alibration frequency. t he cf logic output gives instantaneous active power information. t his output is intended to use for calibration purposes. t he full - scale output frequency can be scaled by the value of cfdiv register. w hen the power is low, the pulse width is equal to 90ms. w hen the power is high and the output period less than 180ms, the pulse width equals to half of the output period 15 zx v oltage waveform z ero C cross output 16 nsag t his logic output goes active low when either no zero - cross are detected or a low voltage threshold is crossed for a specified duration 1 7 n irq i nterrupt request output. 1 8 clkin c lock in. an external clock can be provided at this logic input, alternatively , a crystal ( 3.58mhz) can be connected across this pin and pin17 to provide a clock source. c eramic load capacitors of between 22pf and 33pf should be used with the gate oscillator circuit. 1 9 clkout a crystal can be connected access this pin and pin16 to provide a clock source for BL6528. 20 n cs c hip select for spi interface. t his pin must be pulled low if using the spi interface. 21 sclk s erial clock input for the synchronous serial interface. a ll serial communication data are synchronized to the clock. 22 dout /utx d w hen sel=0, d ata output for spi interface. d ata is shifted out at this pin on the rising edge of sclk. t his output is normally in a high impedance state, unless it is driving data out to the serial data bus. w hen sel=1, transmit line for uart interface 23 din /urxd w hen sel=0, d ata input for spi interface. d ata is shifted in at this pin on the rising edge of sclk w hen sel=1, receive line for uart interface pin descriptions ( ssop20) pin symbol descriptions
BL6528 single - phase multifunction metering ic 4 / 27 v1.0 1 nrst r eset pin. l ogic low on this pin will hold the adcs and digital circuitry in a reset condition and clear internal registers. 2 dvdd digital power supply +5v ,provides the supply voltage for the digital circuitry. i t should be maintained at 5 v 5% for specified operation 3 avdd power supply (+5v) . p rovides the supply voltage for the circuitry. it should be maintained at 5 v 5% for specified operation. 4,5 v1p,v1n a nalog input for current channel, these inputs are fully differential voltage inputs with a maximum signal level of 660 mv , adjustable gain. 6,7 v2n,v2p negative and positive inputs for voltage channel. these inputs provide a fully differential input pair. the maximum differential input voltage is 660 mv for specified operation. adjustable gain. 8 agnd ground reference . provides the ground reference for the circuitry . 9 v ref on - chip voltage reference. the on - chip reference has a nominal value of 2. 5 v 8% and a typical temperature coefficient of 30 pp m/ . an external reference source may also be connected at this pin. t his pin should be decoupled to agnd with a 1uf ceramic capacitor. 10 dgnd d igital ground. 11 cf_watt c alibration frequency. t he cf logic output gives instantaneous active power information. t his output is intended to use for calibration purposes. t he full - scale output frequency can be scaled by the value of cfdiv register. w hen the power is low, the pulse width is equal to 90ms. w hen the power is high and the output period less than 180ms, the pulse width equals to half of the output period 12 zx v oltage waveform z ero C cross output 13 nsag t his logic output goes active low when either no zero - cross are detected or a low voltage threshold is crossed for a specified duration 14 n irq i nterrupt request output. 15 clkin c lock in. an external clock can be provided at this logic input, alternatively , a crystal ( 3.58mhz) can be connected across this pin and pin17 to provide a clock source. c eramic load capacitors of between 22pf and 33pf should be used with the gate oscillator circuit. 16 clkout a crystal can be connected access this pin and pin16 to provide a clock source for BL6528. 17 n cs c hip select for spi interface. t his pin must be pulled low if using the spi interface. 18 sclk s erial clock input for the synchronous serial interface. a ll serial communication data are synchronized to the clock. 19 dout d ata output for spi interface. d ata is shifted out at this pin on the rising edge of sclk. t his output is normally in a high impedance state, unless it is driving data out to the serial data bus. 20 din /urxd d ata input for spi interface. d ata is shifted in at this pin on the rising edge of sclk.
BL6528 single - phase multifunction metering ic 5 / 27 v1.0 absolute maximum ratio ns t = 25 parameter symbol value p ower voltage a vdd dvdd a vdd dvdd - 0.3 ~ +7 v a nalog input voltage to a gnd v 1p v 2 p - 6 ~ + 6 v digital input voltage to d gnd din sclk /cs - 0.3 ~ vdd +0.3 v d igital output voltage to d gnd cf _ w a t t c f _ v a r at0 at1 /irq dout - 0.3 ~ vdd +0.3 v operating temperature range topr - 40 ~ +85 s torage temperature range tstr - 55 ~ +150 p ower dissipation ssop24 p 8 0 mw electronic characteristic patameter a vdd = dvdd = 5v , agnd dgnd 0v, clkin=3.58mhz, t=25 parameter symbol test condition m easure pin m in value t ypical value m ax value unit m easure error on active power watt err o ver a dynamic range 3000 :1 cf 0.1 0. 3 % p hase error when pf=0.8 capacitive pf08err c urrent lead 37
BL6528 single - phase multifunction metering ic 6 / 27 v1.0 m aximum input voltage 1200 mv dc input voltage 370 k i nput signal bandwidth - 3db 14 khz g ain error e xternal 2.5v reference - 4 +4 % g ain error match e xternal 2.5v reference - 1.5 +1.5 % o n - chip reference vref vref 2. 5 v r eference error vreferr 200 mv temperature coefficient tempcoef 30 ppm/ i nput high voltage dvdd=5v 5% 2.6 v i nput low voltage dvdd=5v 5% 0.8 v o u tput high voltage dvdd=5v 5% 4 v o utput low voltage dvdd=5v 5% 1 v a nalog power avdd vavdd 4.75 5. 25 v d igital power dvdd vdvdd 4.75 5.25 v aidd iavdd avdd=5.25v 3 ma didd idvdd dvdd=5.25 2 ma theory of operation principle of energy measure i n energy measure, the power information varying with time is calculated by a direct multiplication of the voltage signal and the current signal. a ssume that the current signal and the voltage signal are cosine functions, v,i are the peak values of the volt age signal and the current signal; the phase difference between the current signal and the voltage signal is expressed as ,t hen the power is given as follows: ) cos( ) cos( ) ( ? ? ? ? wt i wt v t p
BL6528 single - phase multifunction metering ic 7 / 27 v1.0 i f =0 ? i f 0 ? p (t) is called as the instantaneous power signal. t he ideal p (t) consists of the dc component and ac component whose frequency is 2 . t he dc component is called as the average active power. t he current signal and voltage signal is converted to digital signals by high - precision adcs, then through the drop sampling filter ( sinc4), high - pass filter ( hpf) filter out the high frequency noise and dc gain, get the required current and voltage sampling data. c urrent sampling data multiplied by voltage sampling data gets instantaneous active power, then through the low pass filter ( lpf), output average active power. c urrent sampling data and voltage sampling data processed by hilbert circuit, gets instantaneous reactive power, then through low - pass filter( lpf), output average reactive power. c urrent sampling data and voltage sampling data processed by square circuit, low - pass filter( lpf1), square root circuit, get the current rms and voltage rms. a ctive power t hrough a certain time integral, get active energy. reactive power through a certain time integral, get reactive energy. ? ) 2 cos( 1 ( 2 ) ( wt vi t p ? ? ? ? ? ? ) sin( ) 2 sin( 2 ) cos( )) 2 cos( 1 ( 2 ) sin( ) sin( ) cos( ) cos( )) 2 cos( 1 ( 2 ) sin( ) sin( ) cos( ) cos( ) cos( ) cos( ) cos( ) ( ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? wt vi wt vi wt wt vi wt vi wt wt i wt v wt i wt v t p
BL6528 single - phase multifunction metering ic 8 / 27 v1.0 system block s i n c 4 a d c p g a i a p i a n h p f i a ? ? ? i a _ w a v e x 2 l p f 1 x i a r m s i a _ r m s g n i a ? i a _ r m s p h a s e i a g a i n [ 3 : 0 ] + i a r m s ? i a _ r m s o s s i n c 4 a d c p g a v p v n h p f p h a s e v ? p h c a l [ 2 3 : 1 6 ] v g a i n [ 1 1 : 8 ] s i n c 4 a d c p g a i b p i b n h p f p h a s e i b g a i n [ 7 : 4 ] l p f v ? ? ? v _ w a v e x 2 l p f 1 x v r m s v _ r m s g n v ? v _ r m s + v r m s ? v _ r m s o s i b ? ? ? i b _ w a v e x 2 l p f 1 x i b r m s i b _ r m s g n i b ? i b _ r m s + i b r m s ? i b _ r m s o s i b ? ? ? i b _ w a v e i a ? ? ? i a _ w a v e v ? ? ? v _ w a v e i b ? i b _ r m s i a ? i a _ r m s v ? v _ r m s v a v a h r p f n l t d ? ? w a _ c r e e p ? ? ? r e v p _ c r e e p + a ? a _ w a t t o s b ? b _ w a t t o s a a _ w a t t g n b b _ w a t t g n w a t t a w a _ l o s _ l c f c f d i v c f w a t t h r p w a h r n w a h r i b ? i b _ r m s i a ? i a _ r m s c o m p l i n e _ w a t t h r i b ? i b _ p e a k i a ? i a _ p e a k v ? v _ p e a k ? f r e q i b ? i b _ p k l v l i a ? i a _ p k l v l v ? v _ p k l v l ? z x t o u t s a g c y c ? s a g l v l i a i a _ c h g n v v _ c h g n i b i b _ c h g n + + + i a ? i a _ c h o s v ? v _ c h o s i b ? i b _ c h o s + v a v a g n v a ? v a o s l i n e c y c ? ? r m s _ c r e e p l p f n l t d + w a t t b w a _ l o s _ h b l 6 5 2 8 v 1 0 ? ? ? i a ? p h c a l [ 1 5 : 8 ] i b ? p h c a l [ 7 : 0 ] l p f i a ? ? ? i a _ w a v e v ? ? ? v _ w a v e n l t d ? ? v a r _ c r e e p + ? v a r o s v a r g n v a r v a r _ l o s c f c f d i v c f _ v a r v a r h r i b ? ? ? i b _ w a v e h i l b e r t 1 h i l b e r t 2
BL6528 single - phase multifunction metering ic 9 / 27 v1.0 f r o n t - e n d w a v e p r o c e s s f ront - end gain adjustment e very analog channel has a programmable gain amplifier ( pga), gain selection is achieved by the gain register ( gain), the default value of the gain register ( gain) is 00h. e very 4 - bit of the gain register used to select the current channel or voltage channe l pga. gain[3:0] used to select current a channel pga,gain[7:4] used to select voltage channel pga. f or example gain [ 3:0]: x000=1 x x001= 2x x010= 4x x011= 8x x100= 16x x101= 24x x110= 32x x111= 32x h p f h p f i a _ w a v e s i n c 4 a d c p g a i a p i a n p h a s e s i n c 4 a d c p g a v a p v a n p h a s e + + 1 7 h g a i n [ 7 : 4 ] 1 8 h p h c a l [ 1 5 : 8 ] 1 9 h i a _ c h o s 1 c h i a _ c h g n i e h v _ c h g n h p f s i n c 4 a d c p g a i b p i b n p h a s e + 1 a h i b _ c h o s 1 d h i b _ c h g n i b _ w a v e p e a k 0 3 h i b _ p e a k 3 9 h i _ p k l v l p e a k 0 4 h v _ p e a k 3 a h v _ p k l v l p e a k 0 2 h i a _ p e a k 3 9 h i _ p k l v l v _ w a v e f r e q 0 9 h f r e q 1 7 h g a i n [ 1 1 : 8 ] 1 7 h g a i n [ 3 : 0 ] 1 8 h p h c a l [ 2 3 : 1 6 ] 1 8 h p h c a l [ 7 : 0 ] 1 b h v _ c h o s s a g n s a g 3 7 h s a g c y c 3 8 h s a g l v l z x z x
BL6528 single - phase multifunction metering ic 10 / 27 v1.0 phase compensation bl652 8 provides the method of small phase error digital calibration . it will be a small time delay or advance into signal processing circuit in order to compensate for small phase error . because this compensation should be promptly , so this method applies only to 0.1 ? ~0.5 ? range of small phase error . phase calibration register ( phcal _i, phcal _v ) i s a binary 8 - bit register , corresponding to the compensation current a channel, current b channel and voltage channel phase . the default value is 00 h . bit[7] is enable bit, when bi t[7] 0,disable compensation; bit [7] 1,enable compensation. bit [6:0] used to adjust the delay time 1.1 us/1lsb . with a line frequency of 50hz, the resolution is 360 ? ? 1/900khz ? 50hz=0.0 2 ? , the adjustable range is 0 ? ~2.54 ? . ? input channel offset calibration bl652 8 contains the input channel offset calibration registers (i_chos , v _chos), these registers are in 12 - bit sign magnitude format, the default value is 000h. the offset may result from the analog input and the analog - digital conversion circuit itself . a ctive power signal process active power offset calibration bl652 8 contains the active power offset calibration ( wattos). t his register is in 12 - bit sign magnitude format, the default value is 000h. the offset can exist in the power calculations due to crosstalk between channels on the pcb and in the BL6528. the active power offset calibration allows these offsets to be removed to increase the accuracy of the measurement at low input power levels. l p f 1 + 0 a h a _ w a t t ? p o s 0 f h p w a h r ? n e g 1 0 h n w a h r a n t i - c r e e p w a t t 2 f h w a _ c r e e p 2 d h w a _ l o s [ 1 1 : 0 ] 2 5 h a _ w a t t o s 2 7 h a _ w a t t g n l p f 1 + 0 b h b _ w a t t a n t i - c r e e p w a t t 2 f h w a _ c r e e p 2 d h w a _ l o s [ 2 3 : 1 2 ] 2 6 h a _ w a t t o s 2 8 h b _ w a t t g n ? 0 e h w a t t h r ? t 1 3 h l i n e _ w a t t h r r e v p a n t i - c r e e p r e v p 3 3 h c f d i v d i g i t a l t o f r e q c f _ w a t t 3 3 h c f d i v 3 5 h l i n e c y c i a _ w a v e i b _ w a v e v _ w a v e wattos 0 ? ? r activepowe r activepowe
BL6528 single - phase multifunction metering ic 11 / 27 v1.0 acti ve power gain adjustment t he gain register ( wattgn ) is used t o adjust the active power measurement range. t his register is in 12 - bit sign magnitude format , the default value is 000h. the following formula shows how to adjust the output active power: t he minimum value that can be write to the wattgn register is 801h(hex), which represents a gain adjustment of - 50%. t he maximum value that can be write to the wattgn register is 7ffh ( hex), which represents a gain adjustment of +50%. s imilar gain calibration registers are available for current channel and voltage channel ( i_chgn , v _chgn). n o - load threshold of active power bl652 8 contains two no - load detection features that eliminate meter creep. BL6528 can set the no - load threshold on the active power (wa_creep1), this register is in 12 - bit unsigned magnitude format. t his register is used to set the active power threshold value, when the absolute value of the input power signal is le ss than this threshold, the output active power is set to zero . this can make the active power register to 0 in no - load conditions, even a small noise signal in put . t he wa_creep 2 register is used to set the active power timer thr eshold value. t he default value is 0xfff. t here have a internal time_creep register in bl6523b, when detect the cf pulse output , the time_creep register is set to the value of wa_creep 2. if not detected the cf pulse output , the time_creep register value decrease . if the time_creep register decrease to 0 , there is still no cf signal output, the bl652 8 produce a reset signal used to reset the internal energy accumulated register of cf pulse and reload the value of wa_creep 2 to the tome_creep register. the r esolution of the wa_creep_h is 4.6s / lsb, so the maxium timing anti - creep time is about 5h13m . mode [ 3 ] =1 enable timing anti - creep function. mode [ 3 ]=0 disable timing anti - creep function. active power compensation of small signal bl652 8 contains a small active power signal compensation register ( wa_los), this register is in 12 - bit sign magnitude format. t he default value is 000h ) 2 1 ( 12 wattwg power active r activepowe output ? ? ? 1 _ | | , 1 _ | | , 0 creep wa watt creep wa watt watt watt ?? ? ? ? ? ?
BL6528 single - phase multifunction metering ic 12 / 27 v1.0 r everse indicator threshold bl652 8 contains a reverse indicator threshold register(wa_revp), this register is in 12 - bit unsigne d magnitude format, when the input power signal is negative and the absolute value is greater than the power threshold the BL6528 output the revp indicator. a ctive energy calculation the relationship between power and energy can be expressed as c onversely, energy is given as the integral of power. in bl652 8 , the active power signals are accumulated in a 53 internal registers continuously to get active energy , active energy register watthr [23:0] take out this internal register [52:29] as active energy output . t his discrete time accumulation is equivalent to integration in continuous time. where: n is the discrete time - sample number; t is the sampling period ; the sampling perio d of BL6528 is 1.1 us . t he BL6528 include a interrupt ( pehf ) that is triggered w hen the active energy register(watthr) is half full. if the enable pehf bit in the interrupt mask register set to logic high , the / irq output pin goes logic low . t he BL6528 include line cycle energy register(line_watthr). t he number of cycles is written to the linecyc register, the lsb of the linecyc register is 0.1s. at the end of a line cycle accumulation cycle, the line_watthr register is updated. t he line_watthr register hold its current value until the end of the next line cycle period, when the content is replaced with the new reading. i f a new value is written to the linecyc register midway through a line cycle accumulation, the new value is not internally loa ded until the end of a line cycle period. p ositive active energy calculation a s same as active energy calculation. n egative active energy calculation a s same as active energy calculation. dt denergy power ? ? ? dt power energy } ) ( { ) ( 0 0 ? ? ? ? ? ? ? ? n t t nt p lim dt t p e
BL6528 single - phase multifunction metering ic 13 / 27 v1.0 f requency output t he BL6528 provides two energy - to - frequency conversion for calibration purpose. a fter initial calibration at manufacturing, the manufacturer or end customer is often required to verify the meter accuracy. o ne convenient way to do this is to provide an output frequency that is proportional to the re active power. t his output frequency provides a simple single - wire interface that can be optically isolated to interface to external calibration equipment. BL6528 includes two programmable ca libration frequency output pin s ( cf_watt , cf _var ). the digital - to - frequency converter s are used to generate the pulse output. the pulse output stays high for 90ms if the pulse period is longer than 180ms. i f the pulse period is shorter than 180ms, the duty cycle of de pulse output is 50%. t he maximum output frequency with ac inputs at full scale and with cfdiv=010h is approximately 0.5 khz . t he BL6528 can set the cf frequency through the cf_div register. t he default value of the cfdiv register is 0 01 h ( hex ). w hen set cfdiv[x]=1, the cf frequency is 2 (x 4) *cf cfdiv=010 h . r eactive power signal process r e active power offset calibration bl652 8 contains the reactive power offset calibration ( varos). t his register is in 12 - bit sign magnitude format, the default value is 000h. the offset can exist in the power calculations due to crosstalk between channels on the pcb and in the BL6528. the reactive power offset calibration allows these offsets to be remo ved to increase the accuracy of the measurement at low input power levels. rea ctive power gain adjustment t he gain register ( var gn ) is used t o adjust the active power measurement range. t his register is in 12 - bit sign magnitude fo rmat , the default value is 000h. the following formula shows how to adjust the output reactive power: l p f 2 l p f 2 h i l b e r t 1 h i l b e r t 2 l p f 1 2 a h v a r g n + 0 c h v a ? 1 1 h v a r h r a n t i - c r e e p v a r 3 0 h v a r _ c r e e p 2 e h v a r _ l o s 2 9 h v a r o s ? t 1 4 h l i n e _ v a r h r d t o f c f _ v a r 3 3 h c f d i v 3 5 h l i n e c y c i a _ w a v e i b _ w a v e v _ w a v e varos re re 0 ? ? r activepowe r activepowe
BL6528 single - phase multifunction metering ic 14 / 27 v1.0 t he minimum value that can be write to the vargn register is 801h(hex), which represents a gain adjustmen of - 50%. t he maximum value that can be write to the vargn register is 7ffh ( hex), which represents a gain adjustmen of +50%. n o - load threshold of reactive power bl652 8 contains two no - load detection features that eliminate meter creep. BL6528 can set the no - load t hreshold on the reactive power (var_creep1), this register is in 12 - bit unsigned magnitude format. t his register is used to set the reactive power threshold value, when the absolute value of the input power signal is less than this threshold, the output re active power is set to zero . this can make the re active power register to 0 in no - load conditions, even a small noise signal in put. t he var _creep 2 register is used to set the re active power timer threshold value. t he default value is 0xfff. t here have a internal time_creep register in bl6523b, when detect the cf _var pulse output, the time_creep register is set to the value of var _creep 2. if not detected the cf _var pulse output , the time_creep register value decreas e . if the time_creep register decrease to 0 , there is still no cf _var signal output, the BL6528 produce a reset signal used to reset the internal energy accumulated register of cf _var pulse and reload the value of var _creep2 to the tome_creep register. the resolution of the var _creep 2 is 4.6s / lsb, so the maximum timing anti - creep time is about 5h13m . mode [ 3 ] = 1 enable timing anti - creep function. mode [ 3 ] = 0 disable timing anti - creep function. rea ctive power compensation of small signal bl652 8 contains a small reactive power signal compensation register ( var_los), this register is in 12 - bit sign magnitude format. t he default value is 000h reactive energy calculation the relationship between power and energy can be expressed as in bl652 8 , the reactive power signals are accumulated in a 53 internal registers continuously to get re active energy , rea ctive energy register var hr [23:0] take out this internal register [52:29] as reactive energy output . t his discrete time accu mulation is equivalent to integration in continuous time. ) 2 vargn 1 ( re vargn 12 ? ? ? power active output 1 _ | | , 1 _ | | , 0 creep var var creep var var var var ?? ? ? ? ? ? ? ? dt t power active energy reactive ) ( re
BL6528 single - phase multifunction metering ic 15 / 27 v1.0 where: n is the discrete time - sample number; t is the sampling period ; the sampling period of BL6528 is 1.1 us . r oot mean square measurement the rms is expressed mathematically as: f or time - sampled signals: r m s offset calibration bl652 8 contains the rms offset calibration ( i_rmsos , v _rmsos). these registers are in 12 - bit sign magnitude format, the default value is 000h. the offset can exist in the rms calculations due to input noise that is integrated in the dc component of square calculation. the rms offset calibration allows these offsets to be r emoved to increase the accuracy of the measurement at low input power levels. r m s gain calibration t he gain registers ( i _ rms gn , v_rmsgn) are used to adjust the rms measurement range. b oth registers are in 12 - bit sign magnitude format , the default value is 000h. the following formula shows how to adjust the rms: } ) ( re { re 0 0 ? ? ? ? ? ? n t t nt power active lim energy active x 2 x 2 l p f 1 l p f 1 r o o t r o o t + + 0 5 h i _ r m s 0 6 h v _ r m s 2 0 h i _ r m s g n 2 1 h v _ r m s g n r m s a n t i - c r e e p 2 e h r m s _ c r e e p r m s a n t i - c r e e p 1 e h i _ r m s o s 1 f h v _ r m s o s 0 1 h i _ w a v e 0 2 h v _ w a v e 2 e h r m s _ c r e e p ? ? t rms dt t v t v 0 2 ) ( 1 ? ? ? n i rms i v n v 1 2 ) ( 1 17 2 0 2 _ ? ? ? rmsos i i i arms arms
BL6528 single - phase multifunction metering ic 16 / 27 v1.0 t he minimum value that can be write to the x_rmsgn register is 801h(hex), which represents a gain adjustment of - 50%. t he maximum value that can be write to the x_rmsgn register is 7ffh ( hex), which represents a gain adjustment of +50%. n o - load threshold of rms bl6523b can set the no - load threshold on the rms_creep register, this register is in 12 - bit unsigned magnitude fo rmat. when the value of the rms register is less than this threshold, the rms register is set to zero . this can make the rms register to 0 in no - load conditions, even a small noise signal in put . apparent power and apparent energy calculation i n BL6528, the apparent power is defined as the product of v_rms and i_rms. va i_rms v_rms t he apparent energy is given as the integral of the apparent power. t he apparent power signals are accumulated in an internal 49 - bit register, apparent energy register v ahr [23:0] take out this internal register [ 48:25] as apparent energy output . t he BL6528 include a interrupt ( vapehf ) that is triggered w hen the apparent en ergy register(vahr) is half full. if the enable v apehf bit in the interrupt mask register set to logic high , the / irq output pin goes logic low . a pparent power offset calibration bl652 8 contains the apparent power offset calibration ( vaos). t his register is in 12 - bit sign magnitude format, the default value is 000h. the offset can exist in the power calculations due to crosstalk between channels on the pcb and in the BL6528. the apparent power offset calibration allows these offsets to be remo ved to increase the accuracy of the measurement at low input power levels. ) 2 _ 1 ( 12 rmsgn x rms rms output ? ? ? 3655 . 1 2 _ | | , 3655 . 1 2 _ | | rms 0 rms ? ? ?? ? ? ? ? ? ? ? creep rms rms creep rms rms 2 c h v a g n + ? 1 2 h v a h r 0 d h v a 2 b h v a o s 0 5 h i a _ r m s 0 6 h i b _ r m s 0 7 h v _ r m s 0 a h a _ w a t t 0 b h b _ w a t t / 0 8 h p f ? t 1 5 h l i n e _ v a h r d i g i t a l t o f r e q c f _ v a 3 3 h c f d i v 3 5 h l i n e c y c
BL6528 single - phase multifunction metering ic 17 / 27 v1.0 a pparent power gain adjustment t he gain register ( va gn ) is used t o adjust the apparent power measurement range. t his register is in 12 - bit sign magnitude f ormat , the default value is 000h. the following formula shows how to adjust the output apparent power: t he minimum value that can be write to the vagn register is 801h(hex), which represents a gain adjustmen of - 50%. t he maximum value that can be write to the vagn register is 7ffh ( hex), which represents a gain adjustmen of +50%. power factor pf (watt/va) pf register is in 24 - bit sign magnitude format. p ower factor =(sign bit)* ((pf[22]2^ 1 pf[21]2^ 2 ), the r egister value of 0x7fffff(hex) corresponds to a power factor value of 1, the register value of 0x800000(hex) corresponds to a power factor of - 1, the register value of 0x400000(hex) corresponds to a power factor of 0.5. e lectric parameters monitor voltage sag detection t he BL6528 includes a sag detection features that warns the user when the absolute value of the line voltage falls below the programmable threshold for a programmable number of half line cycles. t he voltage sag feature is controlled b y two registers: saglvl and sagcyc. t hese registers control the sag voltage threshold and the sag period , respectively . t he 12 - bit saglvl register contains the amplitude that the voltage channel must fall below before sag event occurs. the sag threshold is the number of half line cycles below which the voltage channel must remain before a sag condition occurs. e ach lsb of the sagcyc register corresponds to one half line cycle period. t he default value is 0xff ( hex). a t 50hz, the maximum sag cycle time is 2.55 seconds. vaos 0 ? ? va va ) 2 vagn 1 ( va 12 0 ? ? ? va output
BL6528 single - phase multifunction metering ic 18 / 27 v1.0 zero - crossing timeout t he BL6528 includes a zero - crossing timeout feature that is designed to detect when no zero crossings are obtained over a programmable time period. t he duration of the zero - crossing timeout is program med in the 16 - bit zxtout register. t he value in the zxtout register is decremented by 1lsb every 70.5us. if a zero - crossing is obtained, the zxtout register is reloaded. i f the zxtout register reaches 0, a zero - crossing timeout event is issued. t he maximum programmable timeout period is 4.369 secs. a interrupt is associated with the zero - crossing timeout feature. i f enabled, a zero - crossing timeout event causes the external irq pin to go low. zero - crossing detection t he bl652 8 includes a zero - crossing detection on voltage channel. t he zx output pin goeshigh on positive - going edge of the voltage channel zero crossing. p eak detection t he bl652 8 continuously records the maximum value of the current and voltage channels. t he three registers that record the peak values on current channel a, current channel b, and the voltage channel , respectively , are iapeak, ibpeak, vpeak. p eak monitor t he BL6528 include an overcurrent and overvoltage feature that detects whether the absolute value of the cu rrent or voltage waveform exceeds a programmable threshold. three peak threshold register ( i_ p k lvl , v_pklvl) are used to set the current or voltage channel peak threshold, respectively . i f the BL6528 detects an overvoltage condition, the pkv bit of the in terrupt status register is set to 1. i f the pkv bit of the interrupt mask register is enable, the irq output go low. t he
BL6528 single - phase multifunction metering ic 19 / 27 v1.0 overcurrent detection feature works in the similar manner. p ower supply monitor t he BL6528 contains an on - chip power supply monitor. t h e analog supply (avdd) is continuously monitored by the bl652 8. if the supply is less than 4v 5% , the BL6528 will be reset. t his is useful to ensure correct device startup at power - up and power - down. t he power supply monitor has built in hysteresis and fil tering. t his gives a high degree of immunity to false triggering due to noisy supplies. t he power supply and decoupling for the part should be such that the ripple at avdd does not exceed 5 v ? 5% as specified for normal operation. communication interface spi interface t he spi communication packet consists of an initial byte, t he bit [ 7:6 ] of this byte dictates whether a read or a write is being issued. t he bit [ 7:6] of this byte should be set to 00 for a read operation and to 01 for a write operation. t he bit [ 5:0] of this byte is the address of the register that is to be read from or written to. this byte should be transmitted msb first. w hen this initial byte transmission is complete, the register data is either sent from the bl652 8 on the dout pin (in the case of a read) or is written to the bl652 8 din pin by the external microcontroller (in the case of a write). a ll data is sent or received msb first. t he length of the data transfer is 24 bits long. t he serial peripheral interfac e of bl652 8 uses four communication pins : sclk, din , dout and /cs. t he spi communication operates in slave mode, a clock must be provided on the sclk pin. t his clock synchronizes all communication. t he din pin is an input to the bl652 8 ; data is sampled by bl652 8 on the rising edge of sclk. t he dout pin is an output from the bl652 8 ; data is shifted out on the rising edge of sclk. t he / cs ( chip select) input must be driven low to initialize the communication and driven high at the end of the communication. d r iving the /cs input high before the completion of a data transfer ends the communication. ? spi w rite operation serial write sequence is shown in the figure. t he bit[7:6 ] of the first bytes in din is 01 ,
BL6528 single - phase multifunction metering ic 20 / 27 v1.0 indicate a write operation. t he bit[5:0] of this byte indicate the address of register. t he last three bytes is the data that will be write to the register. t he data written to the bl652 8 should be ready before the rising edge of slck. t he spi interface will shift the data in the bl65 2 8 on the rising edge of sclk. d vdd 5v 5 d gnd 0v clkin 3.58 mhz xtal 25 min type max unit t1 /cs to the rising edge of sclk 5000 ns t2 t he high pulse width of sclk 5000 ns t3 t he low pulse width of sclk 5000 ns t4 d ata setup time before the rising edge of sclk 3000 ns t5 d ata hold time after the rising edge of sclk 2000 ns t6 transmission time between two bytes 80 us t7 t he minimum time interval between two bytes of data 5000 ns t8 t he minimu hold time of /cs after the falling edge of sclk 5000 ns ? spi read operation serial write sequence is shown in the figure . t he bit[7:6 ] of the first bytes in din is 0 0, indicate a read operation. t he bit[5:0] of this byte indicate the address of register. the data written to the bl652 8 should be ready on din before the rising edge of slck. a fter the bl652 8 receive the address of register , the bl652 8 will shift out the data of the register on dout pin on the rising edge of sclk. t 6 t 5 t 4 t 8 t 7 t 7 t 3 t 3 t 2 t 2 t 1 a 5 a 2 a 4 a 1 a 3 a 0 d 7 d 6 d 5 d 4 d 0 d 0 d 7 d 6 d 5 / c s s c l k d i n
BL6528 single - phase multifunction metering ic 21 / 27 v1.0 d vdd 5v 5 d gnd 0v clkin 3.58 mhz xtal 25 min type max unit t9 t he shortest interval from the end of the read command to the start of read data read 5000 ns t10 t he shortest interval between two bytes of data 5000 ns t11 d ata setup time after the rising edge of sclk 10000 ns t12 d ata hold time after the falling edge of sclk 5000 ns uart t he BL6528 provides a universal asynchronous receiver/transmitter(uart) interface that allows the registers of BL6528 to be accessed using only two pin. t he uart interface operates at affixed baud rate of 4800bps. w hen pin12(sel) is logic high ,pin20(ncs) and pin21(sclk) are lo gic low, the BL6528 use the uart interface. a ll communication is initiated by the sending of a valid frame by the microcontroller to the BL6528. t he set of uart: 4800bps, no parity , 1 stop bit. t he format of the byte: s tart bit d0 d1 d2 d3 d4 d5 d6 d7 s to p bit t he format of the frame is shown : uart read: uart write: t 1 2 t 1 1 t 4 t 1 0 t 1 0 t 9 t 9 t 3 t 3 t 2 t 2 t 1 a 5 a 2 a 4 a 1 a 0 a 3 d 7 d 6 d 5 d 4 d 0 d 7 d 6 d 5 d 0 / c s s c l k d i n d o u t r x t x 0 x 35 addr data lsb data data msb
BL6528 single - phase multifunction metering ic 22 / 27 v1.0 uart ?? ??? 4800bps 10% ??? 73.2ms registers r egister list addr ess name exte rnal r/w inter nal r/w bit s defaul t description electric parameters register internal write 00h version r w 24 6528 a 1 h v ersion no 6528 a_ v1 01h i_wave r w 24 0 w ave register of current channel 0 2 h v_wave r w 24 0 wave register of voltage channel 03 h i_ peak r w 24 0 c urrent peak register 04 h v_peak r w 24 0 v oltage peak register 05 h i_rms r w 24 0 irms register 0 6 h v_rms r w 24 0 vrms register 0 7 h pf r w 24 0 p ower factor 0 8 h freq r w 24 0 p eriod of voltage channel 09 h watt r w 24 0 a verage active power register 0 a h var r w 24 0 a verage re active power register 0 b h va r w 24 0 a verage apparent power register 0 c h watthr r w 24 0 a ctive energy register 0 d h pwahr r w 24 0 p ositive active energy register 0e h nwahr r w 24 0 n egative active energy register 0f h varhr r w 24 0 r eactive energy register 1 0 h vahr r w 24 0 a pparent energy register 1 1 h line_ watthr r w 24 0 l ine accumulation active energy register 1 2 h line_ varhr r w 24 0 l ine accumulation reactive energy register 1 3 h line_ vahr r w 24 0 l ine accumulation apparent energy register 1 4 h status r w 16 0 i nterrupt status register 15h reversed r eversed 0 x c a a d d r r x d a t a l s b d a t a d a t a m s b t x
BL6528 single - phase multifunction metering ic 23 / 27 v1.0 calibration registers ( external write except 3ah 16h bg_ctrl r/w r 16 9333h reversed 17h gain r/w r 8 0 c hannel gain register bit[7:4] :the gain of channel voltage bit[0:4 ] :the gain of channel current 18h phcal _i r/w r 8 0 p hase calibration register(bit [7] ) are enable bit, 1.1 us/1lsb , bit[ 6 :0]:phase calibration of current 19h phcal_v r/w r 8 0 p hase calibration register(bit[7]) are enable bit, 1.1 us/1lsb , bit[6:0]:phase calibration of voltage 1ah i_chos r/w r 12 0 c urrent channel offset adjustment register 1bh v_chos r/w r 12 0 v oltage channel offset adjustment register 1ch i_chgn r/w r 12 0 c urrent channel gain adjustment register 1d h v_chgn r/w r 12 0 v oltage channel gain adjustment register 1 e h i_rmsos r/w r 12 0 c urrent rms offset calibration register 1f h v_rmsos r/w r 12 0 v oltage rms offset calibration register 2 0 h i_rmsgn r/w r 12 0 c urrent rms gain adjust register 2 1 h v_rmsgn r/w r 12 0 v oltage rms gain adjust register 2 2 h wattos r/w r 12 0 a ctive power offset correction register 2 3 h wattgn r/w r 12 0 a ctive power gain adjustment register 24 h varos r/w r 12 0 r eactive power offset correction register 2 5 h vargn r/w r 12 0 r eactive power gain adjustment register 26 h vaos r/w r 12 0 a pparent power offset correction register 27 h vagn r/w r 12 0 a pparent power gain adjustment register 28 h wa_los r/w r 12 0 a ctive power offset calibration register 2 9 h var_los r/w r 12 0 r eactive power offset calibration register 2a h wa_ creep 1 r/w r 12 02bh a ctive power no - load threshold register 2bh wa_creep2 r/w r 12 fffh a ctive power no - load timer threshold register 2ch var_crepp 1 r/w r 12 02bh reactive power no - load threshold register 2dh var_creep 2 r/w r 12 fffh reactive power no - load timer threshold register
BL6528 single - phase multifunction metering ic 24 / 27 v1.0 2eh rms_creep r/w r 12 0 rms no - load threshold register 2fh revp_cree p r/w r 12 087h r everse no - load threshold register 30h cfdiv r/w r 12 001h cf frequency divider register 31h mode r/w r 16 000h m ode register, see the mode register section 32h linecyc r/w r 12 000h line energy accumulation cycles register 33h zxtout r/w r 16 ffffh z ero - crossing timeout 34h sagcyc r/w r 8 ffh s ag line cycle register 35h saglvl r/w r 12 0 s ag voltage level 36h i_pklvl r/w r 12 fffh c urrent channel peak level threshold register 37h v_pklvl r/w r 12 fffh v oltage channel peak level threshold register 38h mask r/w r 12 0 i nterrupt mask register, see the mask register section 39h reversed reversed 3ah reversed reversed 3bh soft_nrst w / 24 w hen send 5a5a5ah to this register, reset the BL6528. s pecial register 3ch read r r 24 0 c ontains the data from the last read operation of spi 3dh write r r 24 0 c ontains the data from the last write operation of spi 3eh chksum r r 24 01d50 bh c hecksum. t he sum of register 1 6 h~3 8 value 3fh wrprot r/w r 8 0 write protection register. write 55h, it means that allows write to writable register mode register b it l ocation b it mnemonic d efault value d escription 0~1 wa hr_ se l 0 0 e nergy accumulation mode selection mode[1:0]=00, absolute energy accumulation. mode[1:0]=01,positive - only energy accumulation. mode[1:0]=10,arithmetical energy accumulation. mode[1:0]=11,reserved. 2 cf2_sel 0 cf2 output selection cf2_sel=0, cf_var pin output the pulse of reactive energy ( var_cf).
BL6528 single - phase multifunction metering ic 25 / 27 v1.0 cf2_sel=1, cf_var pin output the pulse of apparent energy ( va_cf). 3 anticreep_ sel 0 creep mode select. anticreep_sel=0, disable time creep mode; anticreep_sel=1, enable time creep mode. 4 disable_cf var 0 =0, enable cf_var output =1,disable cf_var output 5 disable _cfwa 0 =0, enable cf_wa output =1,disable cf_wa output 6 i_hpf_sel 0 =0, enable hpf of current channel =1, disable hpf of current channel 7 v_hpf_se l 0 =0, enable hpf of voltage channel =1, disable hpf of voltage channel 8 reversed 0 reversed 9~11 at0,at1 output sel 00 12~13 reversed reversed 14~15 reversed 0 reversed mode[ 11 : 9 ] is used to set the logic output function of at0~at 1 pins. mode [11 at0 output default description 000 pkia 0 =1, current channel peak has exceeded i _ pklvl 001 sag 0 =1, sag event has occurred. 010 revp 0 =1, sign of active power has changed to negative 011 pdm_i 0 o utput the current channel pdm signal 100 varehf 0 =1 , reactive energy register(varhr) is half full. 101 zx 0 v oltage channel zero crossing 110 vref_low 0 =1, indicate the reference voltage is lower than 2v 111 reversed reversed mode [11 at0 output default description 000 pkv 0 =1, voltage channel peak has exceeded v_pklvl 001 zxto 0 =1, zero - crossing overtime 010 revp_var 0 =1, sign of reactive power has changed to negative 011 pdm_v o utput the voltage channel pdm signal 100 apehf 0 =1, active energy register(watthr) is half full. 101 vapehf 0 =1, apparent energy register(vahr) is half full 110 reversed reversed 111 reversed reversed
BL6528 single - phase multifunction metering ic 26 / 27 v1.0 i nterrupt mask register( mask ) bit location interrupt flag default description 0 sag 0 enable the interrupt that sag event has occurred 1 zxto 0 enable the interrupt of zxto 2 zx 0 enable the interrupt of zx 3 pki 0 enable the interrupt of p k i 4 pkv 0 enable the interrupt of pkv 5 revp 0 enable the interrupt of revp 6 revp _var 0 enable the interrupt of revp _var 7 apehf 0 enable the interrupt of apehf 8 varehf 0 enable the interrupt of varhr 9 vapehf 0 enable the interrupt of vahr 10 vref_low 0 enable the interrupt of vref_low 11 reversed reversed i nterrupt status register ( status ) bit location interrupt flag default description 0 sag 0 i ndicates that an interrupt was caused by a s ag event 1 zxto 0 i ndicates that zero crossing has been missing on the voltage channel for the length of time specified in the zxtout register 2 zx 0 v oltage channel zero crossing 3 pki 0 c urrent channel peak has exceeded i _ pklvl 4 pkv 0 v oltage peak has exceeded v _ pkilvl 5 revp 0 i ndicates the active power has gone from positive to nega tive 6 revp _var 0 i ndicates the re active power has gone from positive to negative 7 apehf 0 i ndicates that an interrupt was caused because watthr register is more than half full 8 varehf 0 i ndicates that an interrupt was caused because warhr register is more than half full 9 vapehf 0 i ndicates that an interrupt was caused because wahr register is more than half full 1 0 vref_low 0 i ndicates that the reference voltage is lower than 2v
BL6528 single - phase multifunction metering ic 27 / 27 v1.0 11 reversed reversed

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