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copyright ? cirrus logic, inc. 2014 (all rights reserved) http://www.cirrus.com 4 in/4 out audio codec with pcm and tdm interfaces dac features ? advanced multibit delta-sigma modulator ? 24-bit resolution ? differential or single-ended outputs ? dynamic range (a-weighted) ? -109 db differential ? -105 db single-ended ? thd+n ? -90 db differential ? -88 db single ended ? 2 vrms full-scale output into 3-k ? ac load ? rail-to-rail operation adc features ? advanced multibit delta-sigma modulator ? 24-bit resolution ? differential inputs ? -105 db dynamic range (a-weighted) ? -88 db thd+n ? 2 vrms full-scale input system features ? tdm, left justified, and i2s serial inputs and outputs ? i2c host control port ? supports logic levels between 5 and 1.8 v ? supports sample rates up to 96 khz common applications ? automotive audio systems ? av, blu-ray ? disc, and dvd receivers ? audio interfaces, mixing consoles, and effects processors general description the CS4244 provides four multibit analog-to-digital and four multi-bit digital-to-analog ? - ? converters and is compatible with differential inputs and either differential or single-ended outputs. digital volume control, noise gating, and muting is provided for each dac path. a se- lectable high-pass filter is provided for the 4 adc inputs. the CS4244 supports master and slave modes and tdm, left-justified, and i2s modes. this product is available in a 40-pin qfn package in automotive (-40c to +85c) and commercial (0c to +70c) temperature grades. the cdb4244 customer demonstration board is also available for device evalu- ation and implementation suggestions. see ?ordering information? on page 64 for complete details. ain4 ( ) ain3 ( ) ain2 ( ) ain1 ( ) i 2 c control data control por t level tr anslator vl 1 .8 to 5.0 vdc rst int sdout1 ldo analog supply 2. 5 v va 5.0 vdc vdreg ser ial audio interface sdout2 aout1 () aout2 () aout3 () aout4 () ser ial clock in/ out master clock in fram e sync clock / lrck sdin1 sdin2 digital filters multi-bit ?? adc inter polation filter multi-bit ?? m odulator s channel volum e , mute , invert , noise gate dac & analog filters master volume control oct ?14 ds900f2 CS4244
ds900f2 2 CS4244 table of contents 1. pin descriptions ......................................................................................................... ................... 5 1.1 i/o pin characteristics ................................................................................................... ................... 6 2. typical connection diagram ............................................................................................... .... 7 3. characteristics and specificatio ns .......... ................. ................ ................ ................ ........... 8 recommended operating conditions ..................................................................................... 8 absolute maximum ratings ...................................................................................................... ... 8 dc electrical characteristics ................................................................................................ 9 typical current consumption ............................. ................................................................... 10 analog input characteristics (commercial grade) ...................................................... 11 analog input characteristics (automotive grad e) ....................................................... 12 adc digital filter characteristics ....................................................................................... 14 analog output characteristics (commercial grade) .................................................. 15 analog output characteristics (automotive grade) ................................................... 16 combined dac interpolation & on-chip anal og filter response .. ................ ............ 17 digital i/o characteristics ................................................................................................... .... 18 switching characteristics - serial audio interface .................................................... 19 switching specifications - cont rol port .......... ................ ............. ............. ............. ......... 21 4. applications ............................................................................................................... .................... 22 4.1 power supply decoupling, gro unding, and pcb layout ............................................................... 22 4.2 recommended powe r-up & power-down sequence ............... ...................................................... 22 4.3 i2c control port .......................................................................................................... ..................... 24 4.4 system clocking ........................................................................................................... .................. 26 4.5 serial port interface ..................................................................................................... ................... 28 4.6 internal signal path ..................................................................................................... .................. 31 4.7 reset line ................................................................................................................ ...................... 42 4.8 error reporting and interrupt behavior .................................................................................... ...... 42 5. register quick reference ................................................................................................... ..... 45 6. register descriptions ...................................................................................................... .......... 47 6.1 device i.d. a?f (address 01h?03 h) (read only) ....................................................................... 47 6.2 revision i.d. (address 05h) (read only) ................................................................................... .... 47 6.3 clock & sp select (address 06h) ........................................................................................... ........ 48 6.4 sample width select (address 07h) ......................................................................................... ...... 49 6.5 serial port control (address 08h) ......................................................................................... .......... 49 6.6 serial port data select (address 09h) ..... ................................................................................ ....... 50 6.7 adc control 1 (address 0fh) ............................................................................................... .......... 51 6.8 adc control 2 (address 10h) ............................................................................................... .......... 51 6.9 dac control 1 (address 12h) ...................... ......................................................................... .......... 52 6.10 dac control 2 (address 13h) .............................................................................................. ......... 52 6.11 dac control 3 (address 14h) .............................................................................................. ......... 53 6.12 dac control 4 (address 15h) .............................................................................................. ......... 53 6.13 volume mode (address 16h) ................................................................................................ ........ 54 6.14 master and dac1-4 volume co ntrol (address 17h, 18h, 19h, 1ah, & 1bh) ................................ 55 6.15 interrupt control (address 1eh) .......................................................................................... .......... 55 6.16 interrupt mask 1 (address 1fh) ........................................................................................... ......... 56 6.17 interrupt mask 2 (address 20h) ........................................................................................... ......... 57 6.18 interrupt notification 1 (add ress 21h) (read only) ...................................................................... 5 7 6.19 interrupt notification 2 (add ress 22h) (read only) ...................................................................... 5 8 7. adc filter plots ........................................................................................................... ................. 59 8. dac filter plots ........................................................................................................... ................. 60 9. package dimensions ........................................................................................................ ........... 62 10. ordering information ...................................................................................................... ........ 63 11. revision history .......................................................................................................... ................ 63
ds900f2 3 CS4244 list of figures figure 1.CS4244 pinout ........................................................................................................ ...................... 5 figure 2.typical connection diagram .................... ....................................................................... .............. 7 figure 3.test circuit for adc performance testing ............................................................................. ..... 13 figure 4.psrr test configuration .............................................................................................. .............. 13 figure 5.equivalent output test load .......................................................................................... ............ 16 figure 6.tdm serial audio interface timing .................................................................................... ......... 20 figure 7.pcm serial audio interface timing .................................................................................... ......... 20 figure 8.i2c control port timing .............................................................................................. ................. 21 figure 9.system level init ialization and power-up/down sequence . ...................................................... 23 figure 10.dac dc loading ...................................................................................................... ................ 24 figure 11.timing, i2c write ................................................................................................... .................... 25 figure 12.timing, i2c read .................................................................................................... ................... 25 figure 13.master mode clocking ................................................................................................ .............. 27 figure 14.tdm system clock format ............................................................................................. .......... 28 figure 15.32-bit receiver channel block ....................................................................................... ........... 28 figure 16.serial data codi ng and extraction options within the tdm streams ....................................... 29 figure 17.left justified format ............................................................................................... .................. 30 figure 18.i2s format .......................................................................................................... ....................... 30 figure 19.audio path routing ......................... ......................................................................... ................. 31 figure 20.conventional sdout (left) vs. sidechain sdout (right) configuration ................................ 32 figure 21.dac1-4 serial data source selection ................................................................................. ..... 33 figure 22.example serial data s ource selection ................................................................................ ..... 34 figure 23.adc path ............................................................................................................ ...................... 35 figure 24.single- ended to differential active input filter .................................................................... ..... 36 figure 25.single-ended to differential active input f ilter - dc coupled input sign al (va/2 centered) .... 36 figure 26.dac1-4 path ......................................................................................................... .................... 37 figure 27.de-emphasis curve ................................................................................................... ............... 38 figure 28.passive analog output filter .......... .............................................................................. ............ 38 figure 29.volume implementation fo r the dac1-4 path ........................................................................... 39 figure 30.soft ramp behavior .................................................................................................. ................ 40 figure 31.interr upt behavior and example interrupt service routine ....................................................... 44 figure 32.adc stopband rejection .............................................................................................. ............ 59 figure 33.adc transition band ................................................................................................. ............... 59 figure 34.adc transition band (detail) ........................................................................................ ............ 59 figure 35.adc passband ripple ................................................................................................. ............. 59 figure 36.adc hpf (48 khz) ..................................................................................................... ............... 59 figure 37.adc hpf (96 khz) ..................................................................................................... ............... 59 figure 38.ssm dac stopband rejection .......................................................................................... ....... 60 figure 39.ssm dac transition band ............................................................................................. .......... 60 figure 40.ssm dac transition band (detail) .................................................................................... ....... 60 figure 41.ssm dac passband ripple ............................................................................................. ........ 60 figure 42.dsm dac stopband rejection .......................................................................................... ....... 61 figure 43.dsm dac transition band ............................................................................................. .......... 61 figure 44.dsm dac transition band (detail) .................................................................................... ....... 61 figure 45.dsm dac passband ripple ............................................................................................. ........ 61 figure 46.package drawing ..................................................................................................... ................. 62
ds900f2 4 CS4244 list of tables table 1. speed modes .......................................................................................................... .................... 26 table 2. common clock frequencies ............................................................................................. .......... 26 table 3. master mode left justified and i2s clock ratios ...................................................................... .. 27 table 4. slave mode left justified and i2s clock ratios ....................................................................... ... 27 table 5. slave mode tdm clock ratios .......................................................................................... ......... 27 table 6. soft ramp rates ...................................................................................................... ................... 41 table 7. noise gate bit depth settings ........................................................................................ ............ 41 table 8. error reporting and interrupt behavior deta ils ....................................................................... .... 42
ds900f2 5 CS4244 1. pin descriptions figure 1. CS4244 pinout pin name pin # pin description sda 1 serial control data ( input/output ) - bi-directional data i/o for the i2c control port. sdinx 2,3 serial data input ( input ) - input channels serial audio data. fs/lrck 4 frame synchronization clock/left/right clock ( input/output ) - determines which channel or frame is currently active on the serial audio data line. mclk 5 master clock ( input ) -clock source for the internal logic, processing, and modulators. sclk 6 serial clock ( input /output) -serial clock for the serial data port. sdout1 7 serial data output 1 ( output ) - adc data output into a multi-slot tdm stream or ain1 and ain2 adc data output in left justified and i2s modes. vl 8 interface power ( input ) - positive power for the digital interface level shifters. gnd 9,21 ground ( input ) - ground reference for the i/o and digital, analog sections. vdreg 10 digital power ( output ) - internally generated positive power supply for digital section. ainx+ 11,13,15, 17 positive analog input ( input ) - positive input signals to the internal analog to digital converters. the full scale analog input level is specified in the analog input characteristics tables on pages 12 and 13 . ainx- 12,14,16, 18 negative analog input ( input ) - negative input signals to the internal analog to digital converters. the full scale analog input level is specified in the analog input characteristics tables on pages 12 and 13 . filt+ 19 positive voltage reference ( output ) - positive reference voltage for the internal adcs. ad0 ad2/sdout2 tsto1 va ain3+ ain4- ain3- ain2+ ain2- ain1- ain1+ filt+ sda mclk sdout1 vl gnd sdin1 sdin2 12 11 13 14 15 16 17 18 19 20 29 30 28 27 26 25 24 23 22 21 39 40 38 37 36 35 34 33 32 31 2 1 3 4 5 6 7 8 9 10 aout1+ sclk vdreg aout2+ aout2- aout3+ aout3- aout4- aout4+ vbias vref vq gnd tsto2 aout1- scl fs/lrck ad1 int rst ain4+ top-down (though package) view
ds900f2 6 CS4244 1.1 i/o pin characteristics input and output levels and associ ated power supply voltage are shown in the table below. logic levels should not exceed the corresponding power supply voltage. notes: 1. internal connection valid when device is in reset. 2. this pin has no internal pull-up or pull-down resistors. external pull-up or pull-down resistors should be added in accordance with figure 2 . va 20 analog power ( input ) - positive power for the analog sections. vq 22 quiescent voltage ( output ) - filter connection for internal quiescent voltage. vref 23 analog power reference ( input ) - return pin for the vbias cap. vbias 24 positive voltage reference ( output ) - positive reference voltage for the internal dacs. aoutx- 25,27,29, 31 negative analog output (output) - negative output signals from the internal digital to analog con- verters. the full scale analog ou tput level is specified in the analog output characteristics tables on pages 16 and 17 . aoutx+ 26,28,30, 32 positive analog output (output) - positive output signals from the internal digital to analog convert- ers. the full scale analog output level is specified in the analog output characteristics tables on pages 16 and 17 . tstox 33,34 test outputs (output) - test outputs. these pins should be left unconnected. rst 35 reset ( input ) - applies reset to the internal circuitry when pulled low. int 36 interrupt (output ) - sent to dsp to indicate an in terrupt condition has occurred. ad2/sdout2 37 i2c address bit 2/serial data output 2 ( input/output ) - sets the i2c address bit 2 at reset. func- tions as serial data out 2 for ain3 and ain4 ad c data output in left justified and i2s modes. high impedance in tdm mode. see section 4.3 i2c control port for more details concerning this mode of operation. ad1 38 i2c address bit 1 ( input ) - sets the i2c address bit 1. ad0 39 i2c address bit 0 ( input ) - sets the i2c address bit 0. scl 40 serial control port clock ( input ) - serial clock for the i2c control port. gnd - thermal pad - the thermal pad on the bottom of the device should be connected to the ground plane via an array of vias. power supply pin name i/o driver internal connections (note 1) receiver vl scl input - weak pull-down (~500k ?? 5.0 v cmos, with hysteresis sda input/output cmos/open drain weak pull-down (~500k ?? 5.0 v cmos, with hysteresis i nt output cmos/open drain (note 2) - rst input - (note 2) 5.0 v cmos, with hysteresis mclk input - weak pull-down (~500k ?? 5.0 v cmos, with hysteresis fs/lrck input/output 5.0 v cmos weak pull-down (~500k ?? 5.0 v cmos, with hysteresis sclk input/output 5.0 v cmos weak pull-down (~500k ?? 5.0 v cmos, with hysteresis sdout1 output 5.0 v cmos weak pull-down (~500k ?? sdinx input - weak pull-down (~500k ?? 5.0 v cmos, with hysteresis ad0,1 input - (note 2) 5.0 v cmos ad2/sdout2 input/output 5.0 v cmos (note 2) 5.0 v cmos
ds900f2 7 CS4244 2. typical connec tion diagram figure 2. typical connection diagram CS4244 ain4- ain3+ ain2- ain3- va filt+ ain1+ ain1- ain2+ ain4+ sdout1 vl gnd fs/lrck mclk sdin 2 sdin 1 sda vdreg sclk ad2/ sdout2 int aout1- tsto2 aout1+ tsto1 rst ad0 ad1 scl 35 aout3 - aout4 + gnd vref vq vbias aout4 - aout2 - aout3 + aout2 + 32 31 +1.8 v to +5.0 v 0. 1uf pull up or down based upon desired address *** 0.1 uf 10 uf rp (x4) 40 38 37 36 39 digital signal processor 1 3 2 6 4 5 7 8 vl 33 34 30 28 27 26 25 22 29 23 0 .1uf 10 uf +3.3 v to +5.0 v 1uf 20 24 10 uf 0 .1uf 10 9 19 21 analog output filter * analog output filter * analog output filter * an alog in pu t filter ** 11 12 14 13 an alog in pu t filter ** an alog in pu t filter ** an alog in pu t filter ** 17 18 15 16 analog output filter * 10 uf **** * see section 4.6.4 ** see section 4.6.2.2 *** see section 4.3 **** see switching specifications - control port
ds900f2 8 CS4244 3. characteristics and specifications recommended operating conditions gnd = 0 v; all voltages with respect to ground. (note 3) notes: 3. device functional operation is guaranteed within these limits. f unctionality is not guaranteed or implied outside of these limits. op eration outside of thes e limits may adversely af fect device reliability. absolute maximum ratings gnd = 0 v; all voltages with respect to ground. warning: o peration beyond these limits may result in permanent damage to the device . notes: 4. no external loads should be connected to the v dreg pin. any connection of a load to this point may result in errant operation or perf ormance degradation in the device. 5. any pin except supplies. transient currents of up to 100 ma on the analog inpu t pins will not cause scr latch-up. 6. the maximum over/under voltage is limited by the input current. parameters symbol min typ max units dc power supply analog core va 3.135 4.75 3.3 5 3.465 5.25 v v level translator vl 1.71 - 5.25 v temperature ambient operating temperatur e - power applied automotive commercial t a -40 0 - - +85 +70 ? c ? c junction temperature t j -40 - +150 ? c parameters symb ol min max units dc power supply analog core va -0.3 5.5 v level translator vl -0.3 5.5 v vdreg current (note 4) i vdreg -10 ? a inputs input current (note 5) i in -10ma analog input voltage (note 6) v ina - 0.3 va + 0.4 v logic level input voltage (note 6) v ind -0.3 vl + 0.4 v temperature ambient operating temper ature - power applied t a -55 +125 c storage temperature t stg -65 +150 c
ds900f2 9 CS4244 dc electrical characteristics gnd = 0 v; all voltages with respect to ground. notes: 7. no external loads should be connected to the vdreg pin. any connection of a load to this point may result in errant operation or performance degradation in the device. parameters min typ max units vdreg (note 7) nominal voltage output impedance - - 2.5 0.5 - - v ? filt+ nominal voltage output impedance dc current source/sink - - - va 23 - - - 1 v k ? ? a vq nominal voltage output impedance dc current source/sink - - - 0.5?va 77 - - - 0 v k ? ? a
ds900f2 10 CS4244 typical current consumption this table represents the power consumpt ion for individual circuit blocks within the CS4244. CS4244 is configured as shown in figure 2 on page 8 . va_sel = 0 for va = 3.3 vdc, 1 for va = 5.0 vdc; f s = 100 khz; mclk = 25.6 mhz; dac load is 3 k ? ; all input signals are zero (dig ital zero for sdinx inputs and ac coupled to ground for ainx inputs) . notes: 8. full-scale differential output signal. 9. current consumption incr eases with increasing f s and increasing mclk. values are based on f s of 100 khz and mclk of 25.6 mhz. current variance between speed modes is small. 10. pll is activated by setting the mclk rate bit to either 000 (operating in 256x mode) or 001 (operating in 384khz). 11. internal to the CS4244, the analog to digital conver ters are grouped together in stereo pairs. adc1 and adc2 are grouped together as are adc3 and adc4 . the adc group current draw is the current that is drawn whenever one of these groups become active. 12. to calculate total current draw for an arbitrary amount of adcs or dacs, the following equations apply: total running curren t draw from va supply = power down overhead + pll (if applicable)+ dac current draw + adc current draw where dac current draw = dac overhead + (number of dacs x dac channel) adc current draw = adc overhead + (number of active adc groups x adc group) + (number of active adc channels x adc channel) and total running current draw from v l supply = pdn overhead + (number of acti ve adc channels x adc channel) typical current [ma] (unless otherwise noted) (note 9) , (note 12) functional block va/vl i va i vl 1 reset overhead (all lines held static, rst line pulled low.) 5 0.030 0.001 3.3 0.020 0.001 2 power down overhead (all lines clocks and data lines active, rst line pulled high, all pdnx bits set high.) 5 5 0.101 3.3 5 0.101 3 pll (note 10) (current drawn resulting from pll being active. pll is active for 256x and 384x) 51 - 3.3 1 - 4 dac overhead (current drawn whenever any of the four dacs are powered up.) 550 - 3.3 45 - 5 dac channel (note 8) (current drawn per each dac powered up.) 55 - 3.3 4 - 6 adc overhead (current drawn whenever any of the four adcs are powered up.) 511 - 3.3 11 - 7 adc group (current drawn due to an adc ?group? being powered up. see (note 11) ) 52 - 3.3 2 - 8 adc channel (current drawn per each adc powered up.) 5 2 0.109 3.3 2 0.066
ds900f2 11 CS4244 analog input characteristics (commercial grade) test conditions (unless otherwise specif ied): device configured as shown in section 2. on page 8 . input sine wave: 1 khz; va_sel = 0 for va = 3.3 vdc, 1 for va = 5.0 vdc.; t a = 25 ? c; measurement bandwidth is 20 hz to 20 khz unless otherwise specified; sample rate = 48 khz; all power down adcx bits = 0. va, vref = 3.3 v va, vref = 5.0 v parameter min typ max min typ max unit dynamic range a-weighted unweighted 95 92 101 98 - - 99 96 105 102 - - db db total harmonic distortion + noise -1 dbfs -60 dbfs - - -95 -38 -89 -32 - - -88 -42 -82 -36 db db other analog characteristics interchannel gain mismatch - 0.2 - - 0.2 - db gain drift - 100 - - 100 - ppm/c offset error (note 13) high pass filter on high pass filter off - - 0.0001 0.25 - - - - 0.0001 0.25 - - % full scale % full scale interchannel isolation - 90 - - 90 - db full-scale input voltage (differential inputs) 1.58?va 1.66?va 1.74?va 1.58?va 1.66?va 1.74?va vpp input impedance - 40 - - 40 - k ? common mode rejection (differential inputs) -60- -60- db psrr (note 14) 1 khz 60 hz - - 45 20 - - - - 45 20 - - db db
ds900f2 12 CS4244 analog input characterist ics (automotive grade) test conditions (unless otherwise specif ied): device configured as shown in section 2. on page 8 . input sine wave: 1 khz; va_sel = 0 for va = 3.3 vdc, 1 for va = 5.0 vdc.; t a = -40 to +85 ? c; measurement bandwidth is 20 hz to 20 khz unless otherwise spec ified; sample ra te = 48 khz; all power down adcx bits = 0. notes: 13. ainx+ connected to ainx-. 14. valid with the recommended capacitor values on filt+ and vq. see figure 4 for test configuration. va, vref = 3.3 v va, vref = 5.0 v parameter min typ max min typ max unit dynamic range a-weighted unweighted 93 90 101 98 - - 97 94 105 102 - - db db total harmonic distortion + noise -1 dbfs -60 dbfs - - -95 -38 -87 -30 - - -88 -42 -80 -34 db db other analog characteristics interchannel gain mismatch - 0.2 - - 0.2 - db gain drift - 100 - - 100 - ppm/c offset error (note 13) high pass filter on high pass filter off - - 0.0001 0.25 - - - - 0.0001 0.25 - - % full scale % full scale interchannel isolation - 90 - - 90 - db full-scale input voltage (differential inputs) 1.58?va 1.66?va 1.74?va 1.58?va 1.66?va 1.74?va vpp input impedance - 40 - - 40 - k ? common mode rejection (differential inputs) -60- -60- db psrr (note 14) 1 khz 60 hz - - 45 20 - - - - 45 20 - - db db
ds900f2 13 CS4244 figure 3. test circuit for adc performance testing figure 4. psrr test configuration 100 k ? 4.7 uf 100 k ? 100 k ? 470 pf 634 ? 90 .9 ? analog signal + + - 100 k ? 4.7 uf 100 k ? 100 k ? 470 pf 634 ? 90 .9 ? analog signal - + - va va 2700 pf CS4244 ainx + CS4244 ainx - operational amplifier out gnd power dac analog out gnd pwr dut +vcc +vcc + - out test equipment analog generator analyzer -vcc digital out + - + - + -
ds900f2 14 CS4244 adc digital filter characteristics test conditions (unless otherwise specif ied): device configured as shown in section 2. on page 8 . input sine wave: 1 khz; va_sel = 0 for va = 3.3 vdc, 1 for va = 5.0 vdc.; me asurement bandwidth is 20 hz to 20 khz unless otherwise specified. see filter plots in section 7. on page 60 . note: 15. response is clock-dependent and will scale with fs. 16. the adc group delay is measured from the time t he analog inputs are sampled on the ainx pins to the fs/lrck transition (rising or falling) after the last bit of t hat (group of) samp le(s) has been transmitted on sdoutx. 17. the amount of time from input of half-full-scale step function until the filter output settles to 0.1% of full scale. parameter (note 15) min typ max unit passband (frequency response) to -0.1 db corner 0 - 0.4535 fs passband ripple -0.09 - 0.17 db stopband 0.6 - - fs stopband attenuation 70 - - db single-speed mode adc group delay (note 16) - 9.5/fs - s high-pass filter characteristics (48 khz fs) frequency response -3.0 db -0.13 db - - 2 11 - - hz hz phase deviation @ 20 hz - 10 - deg passband ripple -0.09 - 0.17 db filter settling time (note 17) - 25000/fs 0s double-speed mode adc group delay (note 16) - 9.5/fs - s high-pass filter characteristics (96 khz fs) frequency response -3.0 db -0.13 db - - 4 22 - - hz hz phase deviation @ 20 hz - 10 - deg passband ripple -0.15 - 0.17 db filter settling time (note 17) - 25000/fs 0s
ds900f2 15 CS4244 analog output characteris tics (commercial grade) test conditions (unless otherwise specif ied). device configured as shown in section 2. on page 8 . va_sel = 0 for va = 3.3 vdc, 1 for va = 5.0 vdc.; t a = 25 ? c; full-scale 1 khz in put sine wave; samp le rate = 48 khz; mea- surement bandwidth is 20 hz to 20 khz; specifications apply to all channels unless otherwise indicated; all power down dacx bits = 0. see (note 19) on page 17 . va, vref= 3.3 v (differential/single-ended) va, vref= 5.0 v (differential/single-ended) parameter min typ max min typ max unit dynamic performance dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 100/96 97/93 89 86 106/102 103/99 95 92 - - - - 103/99 100/96 89 86 109/105 106/102 95 92 - - - - db db db db total harmonic distortion + noise - -90/-88 -84/-82 - -90/-88 -84/-82 db full-scale output voltage 1.48?va/ 0.74?va 1.56?va/ 0.78?va 1.64?va/ 0.82?va 1.48?va/ 0.74?va 1.56?va/ 0.78?va 1.64?va/ 0.82?va vpp interchannel isolation (1 khz) - 100 - - 100 - db interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/c ac-load resistance (r l ) (note 19) 3- -3- -k ? load capacitance (c l ) (note 19) - - 100 - - 100 pf parallel dc-load resistance (note 20) 10 - - 10 - - k ? output impedance - 100 - - 100 - ? psrr (note 21) 1 khz 60 hz - - 60 60 - - - - 60 60 - - db db
ds900f2 16 CS4244 analog output characteris tics (automotive grade) test conditions (unless otherwise specif ied): device configured as shown in section 2. on page 8 . va_sel = 0 for va = 3.3 vdc, 1 for va = 5.0 vdc.; t a = -40 to +85 ? c; full-scale 1 khz input sine wave; sample rate = 48 khz; measurement bandwidth is 20 hz to 20 kh z; specifications apply to all chan nels unless otherwise indicated; all power down dacx bits = 0. see (note 19) . notes: 18. one lsb of triangular pdf dither added to data. 19. loading configuration is given in figure 5 below. figure 5. equivalent output test load 20. parallel combination of all dac dc loads. see section 4.2.3 . 21. valid with the recommended capacitor values on filt+ and vq. see figure 4 for test configuration. va, vref= 3.3 v (differential/single-ended) va, vref= 5.0 v (differential/single-ended) parameter min typ max min typ max unit dynamic performance dynamic range 18 to 24-bit a-weighted unweighted 16-bit a-weighted unweighted 98/94 95/91 87 84 106/102 103/99 95 92 - - - - 101/97 98/94 87 84 109/105 106/102 95 92 - - - - db db db db total harmonic distortion + nois e - -90/-88 -82/-80 - -90/-88 -82/-80 db full-scale output voltage 1.48?va/ 0.74?va 1.56?va/ 0.78?va 1.64?va/ 0.82?va 1.48?va/ 0.74?va 1.56?va/ 0.78?va 1.64?va/ 0.82?va vpp interchannel isolation (1 khz) - 100 - - 100 - db interchannel gain mismatch - 0.1 0.25 - 0.1 0.25 db gain drift - 100 - - 100 - ppm/c ac-load resistance (r l ) (note 19) 3- -3- -k ? load capacitance (c l ) (note 19) - - 100 - - 100 pf parallel dc-load resistance (note 20) 10 - - 10 - - k ? output impedance - 100 - - 100 - ? psrr (note 21) 1 khz 60 hz - - 60 60 - - - - 60 60 - - db db aoutx gnd 22 f v out r l c l
ds900f2 17 CS4244 combined dac interpol ation & on-chip anal og filter response test conditions (unless otherwise specified): va_sel = 0 for va = 3.3 vdc, 1 for va = 5.0 vdc. the filter charac- teristics have been normaliz ed to the sample rate (f s ) and can be referenced to the desired sample rate by multi- plying the given characteristic by f s . notes: 22. response is clock-dependent and will scale with f s . 23. for single-speed mode, the measurement bandwidth is 0.5465 f s to 3 f s . for double-speed mode, the measurement bandwidth is 0.577 f s to 1.4 f s . 24. the dac group delay is m easured from the fs/lrck transition (r ising or falling) before the first bit of a (group of) sample(s) is transmitted on the sdinx pins to the time it appears on the aoutx pins. parameter min typ max unit single-speed mode passband (note 22) to -0.05 db corner to -3 db corner 0 0 - - 0.4780 0.4996 f s f s frequency response 20 hz to 20 khz -0.01 - +0.12 db stopband 0.5465 - - f s stopband attenuation (note 23) 102 - - db dac1-4 group delay (note 24) -11/fs-s double-speed mode passband (note 22) to -0.1 db corner to -3 db corner 0 0 - - 0.4650 0.4982 f s f s frequency response 20 hz to 20 khz -0.05 - +0.2 db stopband 0.5770 - - f s stopband attenuation (note 23) 80 - - db dac1-4 group delay (note 24) -7/fs-s
ds900f2 18 CS4244 digital i/o characteristics parameters symbol min typ max units high-level input voltage (all input pins except rst )(% of vl) (vl=1.8v) v ih 75% - - v high-level input voltage (all input pins except rst )(% of vl) (vl=2.5v, 3.3v, or 5v) v ih 70% - - v low-level input voltage (all input pins except rst )(% of vl)v il --30%v high-level input voltage ( rst pin) v ih 1.2 - - v low-level input voltage ( rst pin) v il --0.3v high-level output voltage at i o =2ma (% of vl) v oh 80% - - v low-level output voltage at i o =2ma (% of vl) v ol --20%v input leakage current i in --10 ? a input capacitance - 8 - pf
ds900f2 19 CS4244 switching characteristics - serial audio interface va_sel = 0 for va = 3.3 vdc, 1 for va = 5.0 vdc. notes: 25. after applying power to the CS4244 , rst should be held low until after the power supplies and mclk are stable. 26. mclk must be synchronous to and scale with f s . 27. the sclk frequency must remain less than or equal to the mclk frequency. for this reason, sclk may range from 256x to 512x only in single speed mode. in double speed mode, 256x is the only ratio supported. 28. the msb of ch1 is always aligned with the seco nd sclk rising edge following fs/lrck rising edge. 29. where ?n? is equal to the mclk to lrck ratio (set by the master clock rate register bits), i.e. in 256x mode, n = 256, in 512x mode, n = 512, etc. parameters symbol min max units rst pin low pulse width (note 25) 1 -ms mclk frequency (note 26) 7.68 25.6 mhz mclk duty cycle 45 55 % sclk duty cycle 45 55 % input sample rate (fs/lrck pin) single-speed mode double-speed mode f s f s 30 60 50 100 khz khz sclk falling edge to sdoutx valid (vl = 1.8 v) t dh2 -31ns sclk falling edge to sdoutx valid (vl = 2.5 v) t dh2 -22ns sclk falling edge to sdoutx valid (vl = 3.3 v or 5 v) t dh2 -17ns tdm slave mode sclk frequency (note 27) 256x 512x f s fs/lrck high time pulse (note 28) t lpw 1/f sclk (n-1)/f sclk (note 29) ns fs/lrck rising edge to sclk rising edge t lcks 5-ns sdinx setup time befo re sclk rising edge t ds 3-ns sdinx hold time after sclk rising edge t dh1 5-ns pcm slave mode sclk frequency 32x 64x f s fs/lrck duty cycle 45 55 % fs/lrck edge to sclk rising edge t lcks 5-ns sdinx setup time befo re sclk rising edge t ds 3-ns sdinx hold time after sclk rising edge t dh1 5-ns pcm master mode sclk frequency 64x 64x f s fs/lrck duty cycle 45 55 % fs/lrck edge to sclk rising edge t lcks 5-ns sdinx setup time befo re sclk rising edge t ds 5-ns sdinx hold time after sclk rising edge (vl=1.8v) t dh1 11 - ns sdinx hold time after sclk rising edge (vl=2.5v, 3.3v, or 5v) t dh1 10 - ns
ds900f2 20 CS4244 figure 6. tdm serial audio interface timing sdout1 (output ) sdinx (input ) t ds sclk (input ) fs/lrck (input ) msb t dh1 msb-1 t lcks t dh2 msb msb-1 t dh2 t lpw ~ ~ ~ t ds msb t dh1 t dh2 msb-1 t lcks fs/lrck (input /output ) sclk (input /output ) sdinx (input) sdoutx (output ) msb msb-1 figure 7. pcm serial audio interface timing
ds900f2 21 CS4244 switching specificat ions - control port test conditions (unless otherwis e specified): inputs: logic 0 = gnd = 0 v, logic 1 = vl; sda load capacitance equal to maxi- mum value of c b specified below (note 30) . notes: 30. all specifications are valid for the signals at the pins of the CS4244 with th e specified load capacitance. 31. 2 ms + (3000/mclk). see section 4.2.1 . 32. data must be held for sufficient ti me to bridge the transition time, t f , of scl. parameters sy mbol min max unit scl clock frequency f scl - 550 khz reset rising edge to start t irs (note 31) -ns bus free time between transmissions t buf 1.3 - s start condition hold time (prior to first clock pulse) t hdst 0.6 - s clock low time t low 1.3 - s clock high time t high 0.6 - s setup time for repeated start condition t sust 0.6 - s sda input hold time from scl falling (note 32) t hddi 00.9s sda output hold time from scl falling t hddo 0.2 0.9 s sda setup time to scl rising t sud 100 - ns rise time of scl and sda t r -300ns fall time scl and sda t f -300ns setup time for stop condition t susp 0.6 - s sda bus load capacitance c b -400pf sda pull-up resistance r p 500 - ? t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl t irs rst figure 8. i2c control port timing
ds900f2 22 CS4244 4. applications 4.1 power supply decoupling, grounding, and pcb layout as with any high-resolution converter, the CS4244 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. figure 2 shows the recommended power ar- rangements, with va connected to clea n supplies. vdreg, which powers the digital circuitry, is generated internally from an on-chip regulator from the va supply . the vdreg pin provides a connection point for the decoupling capacitors, as shown in figure 2 . extensive use of power and ground planes, ground plan e fill in unused areas and surface mount decoupling capacitors are recommended. decoupling capacitors shou ld be as near to the pins of the CS4244 as pos- sible. the low value ceramic capacitor should be the nearest to the pin and should be mounted on the same side of the board as the CS4244 to minimize inductance effects. all signals, especially clocks, should be kept away from the filt+, vbias, and vq pins in order to avoid unwanted coupling into the modulators. the filt+, vbias, and vq decoupling capacitors, parti cularly the 0.1 f, must be positioned to minimize the electrical path from their respective pins and gnd.va_sel for optimal heat dissipation from the package, it is re commended that the area directly under the device be filled with copper and tied to the ground plan e. the use of vias co nnecting the topside ground to the back- side ground is also recommended. 4.2 recommended power-up & power-down sequence the initialization and power-up/down sequence flow chart is shown in figure 9 . for the CS4244 reset is defined as all lines held static, rst line is pulled low. power down is defined as all lines (excluding mclk) held static, rst line is high, all pdnx bits are ?1?. running is defined as rst line high, all pdnx bits are ?0?. 4.2.1 power-up the CS4244 enters a reset state upon the initial ap plication of va and vl. when these power supplies are initially applied to the device, the audio outputs, aoutxx, are clamped to vq which is initially low. additionally, the interpolation and decimation filters, delta-sigma modulators and control port registers are all reset and the internal voltage reference, multi-bit digital-to-analog and analog-to-digital converters and low-pass filters are powered down. the device remains in the reset state until the rst pin is brought high. once rst is brought high, the control port address is latc hed after 2 ms + (3000/mclk). until this latching transition is complete, the device will not respond to i2c reads or writ es, but the i2c bus may still be used during this time. once the latching transition is complete, the address is latched and the control port is accessible. at this point and the desired register se ttings can be loaded per the interface descriptions de- tailed in the section 4.3 i2c control port . to ensure specified performance and timing, the va_sel must be set to ?0? for va = 3.3 vdc and ?1? for va = 5.0 vdc before audio output begins. after the rst pin is brought high and mclk is applied, th e outputs begin to ramp with vq towards the nominal quiescent voltage. vq will ch arge to va/2 upon initia l power up. the time that it takes to charge up to va/2 is governed by the size of the capacitor attached to the vq pin. with the capacitor value shown in the typical connection diagram, the charge time will be approxima tely 250 ms. the gradual voltage ramping allows time for the external dc-blocking capacitors to charge to vq, effectively blocking the qui- escent dc voltage. once fs/lrck is valid, mclk occurrences are counted over one f s period to deter- mine the mclk/f s ratio. with mclk valid and any of the pdnx bits cleared, the internal voltage references will transition to their nominal voltage. power is applied to the d/a converters and filters, and the analog outputs are un-clamped from the quiescen t voltage, vq. afterwards, normal operation begins.
ds900f2 23 CS4244 4.2.2 power-down to prevent audio transients at power-down, the dc-blocking capacitors must fully discharge before turn- ing off the power. in order to do this in a controlle d manner, it is recommended that all the converters be muted to start the sequence . next, set pdnx for all converters to 1 to power them down internally. then, fs/lrck and sclk can be removed if desired. finally, the ?vq ramp? bit in the "dac control 4" register must be set to ?1? for a period of 50 ms before applying reset or removing power or mclk. during this time, voltage on vq and the audio outputs discharge gradually to gnd. if power is removed before this 50 ms time period has passed, a transient will occur an d a slight click or pop ma y be heard. there is no minimum time for a power cycle. powe r may be re-applied at any time. it is important to note that all clocks should be applied and removed in the order specified in figure 9 . if mclk is removed or applied before rst has been pulled low, audible pops, clicks and/or distortion can result. if either sclk or fs/lrck is removed or applied before all pdnx bits are set to 1, audible pops, clicks and/or distortion can result. note: timings are approximate and based upon the nominal value of the passive components specified in the ?typical connection diagram? on page 8 . see section 4.6.5.2 for volume ramp behavior. figure 9. system level initialization and power-up/down sequence 4.2.3 dac dc loading figure 10 shows the analog output configuration during power-up, with the aoutx pins clamped to vq to prevent pops and clicks. thus any dc loads (rl x ) on the output pins will be in parallel when the switch- es are closed. these dc lo ads will pull the vq voltage down towards ground. if the parallel combination of all dc loads exceeds the specification shown in the analog output characteristics tables on pages 16 system operational system unpowered set all pdn dac & adc bits stop sclk, fs/lrck, sdinx set vq_ramp bit remove vl, va, and mclk set mute adcx bits clear rst dacx fully operational adc data available on sdoutx 2 ms + (3000/mclk) 50 ms apply vl , va, and mclk clear pdn dacx & adcx bits start sclk, fs/lrck, sdinx write all required configuration settings to control port clear mute dacx bits clear mute adcx bits set rst vcm ready (>90% of typical) i 2 c address captured & control port ready 250 ms write va_sel bit (in 0fh) appropriately for va delay dependent on dac mute / unmute behavior set mute dacx bits delay dependent on dac mute / unmute behavior 2 ms + (3000 /mclk ) 250 m s
ds900f2 24 CS4244 and 17 , the vq voltage will never rise to its minimum op erating voltage. if the vq voltage never rises above this minimum operating voltag e, the device will not finish the power-up sequence and normal op- eration will not begin. also note that any aoutx pin(s) with a dc load must remain powe red up (pdn dacx = 0) to keep the vq net at its nominal voltage during normal operat ion, otherwise clipping may occur on the outputs. note that the load capacitors (cl x ) are also in parallel during power-up. the amount of total capacitance on the vq net during power-up will affect the amount of time it takes for the vq voltage to rise to its nom- inal operating voltage after va power is applied. the ti me period can be calculated using the time constant given by the internal series resistor and the load capacitors. figure 10. dac dc loading 4.3 i2c control port all device configuration is achieved via the i2c control port registers as described in the switching specifi- cations - control port table. the operation via the control port may be completely asynchronous with respect to the audio sample rates. however, to avoid potential interference problems, the i2c pins should remain static if no operation is required. t he CS4244 acts as an i2c slave device. sda is a bidirectional data line. data is clocked into and out of the devi ce by the clock, scl. the ad0 and ad1 pins form the two least significant bits of the ch ip address and should be connected through a resistor to vl or gnd as desired. the sdout2 pin is used to set the ad2 bit by connecting a resistor from the sd- out2 pin to vl or to gnd. the state of these pins are sensed after the CS4244 is released from reset. ~140k va vq net ~140 k s1 rl 1+ cl 1+ aout1+ rl 1- cl 1- aout1- s2 rl 2+ cl 2+ aout2+ rl 2- cl 2- aout2- s3 rl 3+ cl 3+ aout3+ rl 3- cl 3- aout3- s4 rl 4+ cl 4+ aout4+ rl 4- cl 4- aout4- external vq capacitor
ds900f2 25 CS4244 the signal timings for a read and write cycle are shown in figure 11 and figure 12 . a start condition is de- fined as a falling transition of sda while the clock is high. a stop conditi on is a rising transition while the clock is high. all other transitions of sda occur wh ile the clock is low. the first byte sent to the CS4244 after a start condition consists of a 7- bit chip address field and a r/w bit (high for a read, low for a write). the upper 4 bits of the 7-bit address field are fixed at 0010. to communicate with a CS4244 , the chip address field, which is the first byte sent to the CS4244 , should match 0010 followed by the settings of the adx pins. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte is the memory address pointer (map) which selects the register to be read or wr itten. if the operation is a read, the contents of the register pointed to by the map will be output. setting the au to increment bit in map allows successive reads or writes of consecut ive registers. each byte is separated by an acknowledge bit. the ack bit is output from the CS4244 after each input byte is read, and is input to the CS4244 from the microcontroller after each trans- mitted byte. since the read operation can not set the map, an abort ed write operation is used as a preamble. as shown in figure 12 , the write operation is aborted after the acknowledge for the map byte by sending a stop con- dition. the following pseudocode illustrates an aborted wr ite operation followed by a read operation. send start condition. send 0010xxx0 (chip address & write operation). receive acknowledge bit. send map byte, auto increment off. receive acknowledge bit. send stop condition, aborting write. send start condition. send 0010xxx1 (chip address & read operation). receive acknowledge bit. receive byte, contents of selected register. send acknowledge bit. send stop condition. setting the auto increment bit in th e map allows successive reads or wr ites of consecutiv e registers. each byte is separated by an acknowledge bit. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 0 0 1 0 ad2 ad1 ad0 0 sda incr 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n figure 11. timing, i2c write scl chip address (write) map byte data data +1 start ack stop ack ack ack 0 0 1 0 ad2 ad1 ad0 0 sda chip address (read) start incr 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop 0 0 1 0 ad2 ad1 ad0 1 figure 12. timing, i2c read
ds900f2 26 CS4244 4.3.1 memory address pointer (map) the map byte comes after the address byte and selects the register to be read or written. refer to the pseudocode above for implementation details. 4.3.1.1 map increment (incr) the CS4244 has map auto-increment ca pability enabled by the incr bit (the msb) of the map. if incr is set to ?0?, map will stay constant for successive i2c reads or writes. if incr is set to ?1?, map will auto- increment after each byte is read or written, allo wing block reads or writes of successive registers. 4.4 system clocking the CS4244 will operate at sa mpling frequencies from 30 khz to 100 k hz. this range is divided into two speed modes as shown in table 1 . the serial port clocking must be changed while all pd nx bits are set. if the clocking is changed otherwise, the device will enter a mute state, see section 4.8 on page 43 . 4.4.1 master clock the ratio of the mclk frequency to the sample rate must be an integer. the fs/lrck frequency is equal to f s , the frequency at which all of the slots of the tdm stream or channels in left justified or i2s formats are clocked into or out of the device. the speed mode and master clock rate bits configure the device to generate the proper clocks in master mode and receive t he proper clocks in slave mode. table 2 illus- trates several standard audio sample rates and the required mclk and fs/lrck frequencies. the CS4244 has an internal fixed ratio pll. this pll is activated when the ?mclk rate[2:0]? bits in the "clock & sp sel." register are set to either 000 or 001, corresponding to 256x or 384x. when in either of these two modes, the pll will activate to adjust the frequency of the in coming mclk to ensure that the internal state machines oper ate at a nominal 24.576 mhz rate. as is shown in the typical current con- sumption table, activation of the pll will increa se the power consumption of the CS4244. note: 33. 128x and 192x ratios valid only in left justified or i2s formats. mode sampling frequency single-speed 30-50 khz double-speed 60-100 khz table 1. speed modes fs/lrck (khz) mclk (mhz) 128x (note 33) 192x (note 33) 256x 384x 512x 32 - - 8.1920 12.2880 16.3840 44.1 - - 11.2896 16.9344 22.5792 48 - - 12.2880 18.4320 24.5760 64 8.1920 12.2880 16.3840 - - 88.2 11.2896 16.9344 22.5792 - - 96 12.2880 18.4320 24.5760 - - mode dsm ssm table 2. common clock frequencies
ds900f2 27 CS4244 4.4.2 master mode clock ratios as a clock master, fs/lrck and sclk will operate as outputs interna lly derived from mclk. fs/lrck is equal to f s and sclk is equal to 64x f s as shown in figure 13 . tdm format is not supported in master mode. the resulting valid master mode clock ratios are shown in table 3 below. 4.4.3 slave mode clock ratios in slave mode, sclk and fs/lrck operate as inpu ts. the fs/lrck clock frequency must be equal to the sample rate, f s , and must be synchronously derived fr om the supplied master clock, mclk. the serial bit clock, sclk, must be synchronously de rived from the master clock, mclk, and be equal to 512x, 256x, 128x, 64x, 48x or 32x f s , depending on the desired format and speed mode. refer to table 4 and table 5 for required clock ratios. note: 34. for all cases, the sclk fr equency must be less than or equal to the mclk frequency. ssm dsm mclk/f s 256x, 384x, 512x 128x, 192x, 256x sclk/f s 64x 64x table 3. master mode left justified and i2s clock ratios ssm dsm mclk/f s 256x, 384x, 512x 128x, 192x, 256x sclk/f s 32x, 48x, 64x, 128x 32x, 48x, 64x table 4. slave mode left justified and i2s clock ratios (note 34) ssm dsm mclk/f s 256x, 384x, 512x 512x 256x sclk/f s 256x 512x 256x table 5. slave mode tdm clock ratios 512 256 8 4 00 01 00 01 fs/lrck sclk 000 001 010 x2 1.5 1 mclk speed m ode bits mclk rate bits x2 pll active figure 13. master mode clocking
ds900f2 28 CS4244 4.5 serial port interface the serial port interface format is selected by the serial port format register bits. the tdm format is avail- able in slave mode only. 4.5.1 tdm mode the serial port of the CS4244 supports the tdm inte rface format with varying bit depths from 16 to 24 as shown in figure 15 . data is clocked out of the adc on the fallin g edge of sclk and clocked into the dac on the rising edge. as indicated in figure 15 , tdm data is received most significant bit (msb) first, on the second rising edge of the sclk occurring after a fs/lrck rising edge. all data is valid on the rising edge of sclk. all bits are transmitted on the fallin g edge of sclk. each slot is 32 bits wide, with the va lid data sample left jus- tified within the slot. valid data lengths are 16, 18, 20, or 24 bits. fs/lrck identifies the start of a new frame and is equal to the sample rate, f s . as shown in figure 14 , fs/lrck is sampled as valid on the rising sclk edge preceding the most significant bit of the first data sample and must be held valid for at least 1 sclk period. the structure in which the serial data is coded into the tdm slots is shown in figure 16 . sdout2 is un- used in tdm mode and is placed in a high-impedan ce state. when using a 48 khz sample rate with a 24.576 mhz mclk and sclk, a 16 slot tdm structure can be realized. when using a 48 khz sample rate with 12.288 mhz sclk and 24.576 mhz mclk, or a 96 khz sample rate with a 24.576 mhz mclk and sclk, an 8 slot tdm structure can be realized. the data that is coded into the tdm slots is extracted into the appropriate signal path via the settings in the control port. please refer to section 4.6.1 routing the serial data within the signal paths for more details. sclk sdinx & sdout1 channel 1 channel 2 channel n-1 channel n fs/lrck frame (n 16) figure 14. tdm system clock format msb 32-bit channel block lsb 24-bit audio word 8-bit zero pad -1 -2 -3 -4 -5 -6 -7 +1 +2 +3 figure 15. 32-bit re ceiver channel block
ds900f2 29 CS4244 sdin1 input data 1.1 [31:8] x [7:0] input data 1.2 [31:8] x [7:0] input data 1.3 [31:8] x [7:0] input data 1.4 [31:8] x [7:0] input data 1.5 [31:8] x [7:0] input data 1.6 [31:8] x [7:0] input data 1.7 [31:8] x [7:0] input data 1.8 [31:8] x [7:0] sdin2 input data 2.1 [31:8] x [7:0] input data 2.2 [31:8] x [7:0] input data 2.3 [31:8] x[7:0] input data 2.4 [31:8] x [7:0] input data 2.5 [31:8] x [7:0] input data 2.6 [31:8] x[7:0] input data 2.7 [31:8] x[7:0] input data 2.8 [31:8] x[7:0] sdout1 adc1 data[31:8] 0's [7:0] adc2 data [31:8] 0's [7:0] adc3 data [31:8] 0's [7:0] adc4 data[31:8] 0's [7:0] sdout1 with sidechain adc1 data[31:8] 0's [7:0] adc2 data [31:8] 0's [7:0] adc3 data [31:8] 0's [7:0] adc4 data [31:8] 0's [7:0] mclk = 12.288/24.576mhz fs/lrck = 48/96khz sclk = 12.288/24.576mhz slot 1 [31:0] slot 2 [31:0] slot 3 [31:0] slot 4 [31:0] slot 5 [31:0] slot 6 [31:0] slot 7 [31:0] slot 8 [31:0] 0's [31:0] 0's [31:0] 0's [31:0] 0's [31:0] output data (sdin2 slot 1) output data (sdin2 slot 2) output data (sdin2 slot 3) output data (sdin2 slot 4) sdin1 input data 1.1 [31:8] x [7:0] input data 1.4 [31:8] x [7:0] input data 1.5 [31:8] x [7:0] input data 1.8 [31:8] x [7:0] input data 1.9 [31:8] x [7:0] input data 1.12 [31:8] x [7:0] input data 1.13 [31:8] x [7:0] input data 1.16 [31:8] x [7:0] sdin2 input data 2.1 [31:8] x [7:0] input data 2.4 [31:8] x [7:0] input data 2.5 [31:8] x [7:0] input data 2.8 [31:8] x [7:0] input data 2.9 [31:8] x [7:0] input data 2.12 [31:8] x [7:0] input data 2.13 [31:8] x [7:0] input data 2.16 [31:8] x [7:0] sdout1 adc1 data [31:8] 0's [7:0] adc4 data [31:8] 0's [7:0] sdout1 with sidechain adc1 data [31:8] 0's [7:0] adc4 data [31:8] 0's [7:0] mclk = 24.576mhz fs/lrck = 48khz 0's [31:0] output data (sdin2 slot 1) sclk = 24.576mhz slot 1 [31:0] ? ? slot 4 [31:0] slot 5 [31:0] ? ? slot 8 [31:0] slot 9 [31:0] slot 13 [31:0] ? ? slot 16 [31:0] 0's [31:0] 0's [31:0] 0's [31:0] 0's [31:0] 0's [31:0] ? ? slot 12 [31:0] output data (sdin2 slot 12) output data (sdin2 slot 4) output data (sdin2 slot 5) output data (sdin2 slot 8) output data (sdin2 slot 9) figure 16. serial data coding and extraction options within the tdm streams
ds900f2 30 CS4244 4.5.2 left justified and i2s modes the serial port of the CS4244 support s the left justified and i2s interf ace formats with valid bit depths of 16, 18, 20, or 24 bits for the sdoutx pins and 24 bits for the sdinx pins. all data is valid on the rising edge of sclk. data is clocked out of the adc on the fallin g edge of sclk and clocked into the dac on the rising edge. in master mode each slot is 32 bits wide. in left justified mode (see figure 17 ) the data is received or transmitted most significant bit (msb) first, on the first rising edge of the sclk occurring after a fs/lrck edge. the left channel is received or trans- mitted while fs/lrck is logic high. in i2s mode (see figure 18 ) the data is received or transmitted most significant bit (msb) first, on the sec- ond rising edge of the sclk occurring after a fs/lrck edge. the left channel is received or transmitted while fs/lrck is logic low. the ain1 and ain2 signals are transmitted on the sd out1 pin; the ain3 and ain4 signals are transmit- ted on the sdout2 pin. the data on the sdin1 pin is routed to aout1 and aout2; the data on the sdin2 pin is routed to aout3 and aout4. fs/lrck sclk msb lsb msb lsb aout 1 or 3 left channel right channel sdoutx sdinx aout 2 or 4 msb ain 1 or 3 ain 2 or 4 figure 17. left justified format fs/lrck sclk msb lsb msb lsb aout 1 or 3 left channel right channel sdoutx sdinx aout 2 or 4 msb ain 1 or 3 ain 2 or 4 figure 18. i2s format
ds900f2 31 CS4244 4.6 internal signal path the CS4244 device includes two paths in which audio da ta can be routed. the analog input path, shown in yellow, allows up to four analog si gnals to be combined into a single tdm stream on the sdout1 pin or output as stereo pairs on the sdout1 and sdout2 pi ns. the dac1-4 path, highlighted in blue, converts serial audio data to analog audio data. 4.6.1 routing the serial data within the signal paths 4.6.1.1 adc signal routing in tdm mode, the CS4244 is designed to load the firs t four slots of the tdm stream on the sdout1 pin with the internal adc data. additionally, in order to mi nimize the number of sdout lines that must be run to the system controller in a mult iple ic application, the sdout data for up to 4 devices can be loaded into a single tdm stream by side chaini ng the devices together, as shown in figure 20 . to enable the sidechain feature, the ?sdo chain? bit in the "sp control" register must be set. i 2 c control data control port level translator vl 1 .8 to 5.0 vdc rst int sdout1 ldo analog supply 2.5 v va 5.0 vdc vd 2. 5 vdc serial audio inter face sdout2 ser ial clock in/ out master clock in fram e sync clock / lrck sdin1 sdin2 ain4 ( ) ain3 ( ) ain2 ( ) ain1 ( ) digital filter s multi-bit ?? adc aout1 () aout2 () aout3 () aout4 () interpolation filter multi-bit ?? m odulators channel volume , mute, invert , noise gate dac & analog filters master volume contr ol figure 19. audio path routing
ds900f2 32 CS4244 in left justified or i2s mode, the CS4244 transmit s the ain1 and ain2 signals on the sdout1 pin and the ain3 and ain4 signals on the sdout2 pin. 4.6.1.2 dac1-4 signal routing in tdm mode, the ?dac1-4 source[2:0]? bits in the "sp data sel." register advise the CS4244 where data for the dac1-4 path is located within the incoming tdm streams. details for this register and the bit settings can be found in figures 21 and 22 . in left justified or i2s mode, the CS4244 routes the data on the sdin1 pin to dac1 and dac2 and the data on the sdin2 pin to dac3 and dac4. device d sdin2 sdout1 sdin1 x x device a sdin2 sdout1 sdin1 x x x device b sdin2 sdout1 sdin1 x x x device c sdin2 sdout1 sdin1 x x x dsp x adc data from device a is loaded into the first 4 slots of the 16 slot tdm stream going out of sdout1 pin of device a. the last 12 slots are all coded as ? 0's?. the adc data of device b is coded into the first four slots of the output tdm stream, followed by the first 12 slots of the tdm stream coming in on sdin2, placing the adc data from device a into slots 5-8 of the outgoing tdm stream. the adc data of device c is coded into the first four slots of the output tdm stream, followed by the first 12 slots of the tdm stream coming in on sdin2, placing the adc data from device b into slots 5-8 and the adc data from device a into slots 9-12 of the outgoing tdm stream. the adc data of device d is coded into the first four slots of the output tdm stream, followed by the first 12 slots of the tdm stream coming in on sdin2, placing the adc data from device c into slots 5-8, the adc data from device b into slots 9-12, and the adc data from device a into slots 13-16 of the outgoing tdm stream. device d sdin2 sdout1 sdin1 x x device a sdin2 sdout1 sdin1 x x x device b sdin2 sdout1 sdin1 x x x device c sdin2 sdout1 sdin1 x x x dsp x each of the device?s adc data is reflected in the tdm stream on sdout1 and then routed to the system controller. note: this diagram shows the configuration for 16 slot tdm streams. if 8 slot tdm streams are used, two separate serial data lines wi ll need to be connected from the dsp. one would carry the serial data for devices c&d and the other would carry the serial data for devices a &b figure 20. conventional sdout (left) vs . sidechain sdout (right) configuration
ds900f2 33 CS4244 dac1-4 source [2:0] dac1-4 data is in: 000 slots 1-4 of sdin1 001 slots 5-8 of sdin1 010 slots 9-12 of sdin1 011 slots 13-16 of sdin1 100 slots 1-4 of sdin2 101 slots 5-8 of sdin2 110 slots 9-12 of sdin2 111 slots 13-16 of sdin2 sdin1 sdin2 fs/lrck = 48/96khz mclk = 12.288/24.576mhz sclk = 12.288/24.576mhz slot 1 [31:0] slot 2 [31:0] slot 3 [31:0] slot 4 [31:0] slot 5 [31:0] slot 6 [31:0] slot 7 [31:0] slot 8 [31:0] slot 1 [31:0] slot 2 [31:0] slot 3 [31:0] slot 4 [31:0] slot 5 [31:0] slot 6 [31:0] slot 7 [31:0] slot 8 [31:0] sdin1 sdin2 mclk = 24.576mhz fs/lrck = 48khz sclk = 24.576mhz ? ?? ?? ? slot 8 [31:0] slot 9 [31:0] slot 8 [31:0] slot 9 [31:0] slot 1 [31:0] slot 1 [31:0] slot 4 [31:0] slot 5 [31:0] slot 4 [31:0] slot 5 [31:0] ? ? slot 13 [31:0] slot 12 [31:0] slot 13 [31:0] slot 16 [31:0] slot 16 [31:0] slot 12 [31:0] figure 21. dac1-4 serial data source selection
ds900f2 34 CS4244 111 slots 13-16 of sdin2 101 slots 5-8 of sdin2 110 slots 9-12 of sdin2 011 slots 13-16 of sdin1 100 slots 1-4 of sdin2 001 slots 5-8 of sdin1 010 slots 9-12 of sdin1 dac1-4 source [2:0] dac1-4 data is in: 000 slots 1-4 of sdin1 sdin1 sdin2 mclk = 12.288/24.576mhz fs/lrck = 48/96khz sclk = 12.288/24.576mhz slot 1 [31:0] slot 2 [31:0] slot 3 [31:0] slot 4 [31:0] slot 5 [31:0] slot 6 [31:0] slot 7 [31:0] slot 8 [31:0] dac1 [23:0] x dac2 [23:0] x dac3 [23:0] x dac4 [23:0] x x x x x xx xx xxxx figure 22. example serial data source selection
ds900f2 35 CS4244 4.6.2 adc path 4.6.2.1 analog inputs ainx+ and ainx- are line-level differe ntial analog inputs. the analog input pins do not self-bias and must be externally biased to va/2 to avoid clipping of th e input signal. the full-scale analog input levels are scaled according to va and can be found in the analog input characteristics tables on pages 12 and 13 . the adc output data is in two?s complement binary fo rmat. for inputs above positive full scale or below negative full scale, the adc will output 7fffffh or 800000h, respectively, and cause the adc overflow bit in the interrupt notification 1 register to be set to a ?1?. 4.6.2.2 active adc input filter the analog modulator samples the input at 6.144 mhz (internal mclk = 12.288 mhz). the digital filter will reject signals within the stopband of the filter. however, there is no rejection for input signals which are multiples of the digital passband frequency (n ? 6.144 mhz), where n = 0,1,2,... refer to figure 24 for a recommended analog input filter th at will attenuate any noise energy at 6.144 mhz, in addition to pro- viding the optimum source impedance for the modulator s. the use of capacitors that have a large voltage coefficient (such as general-purpos e ceramics) must be avoided since these can degrade signal linearity. i 2 c control data control por t level translator vl 1 .8 to 5.0 vdc rst int sdout1 ldo analog supply 2.5 v va 5.0 vdc vd 2. 5 vdc ser ial audio inter face sdout2 serial clock in/ out master clock in frame sync clock / lrck sdin1 sdin2 ain4 ( ) ain3 ( ) ain2 ( ) ain1 ( ) digital filters multi-bit ?? adc aout1 () aout2 () aout3 () aout4 () inter polation filter multi-bit ?? modulators channel volum e , mute, invert , noise gate dac & analog filters master volume control figure 23. adc path
ds900f2 36 CS4244 4.6.2.3 adc hpf the adc path contains an optional hpf which can be enabled or disa bled for all four adcs via the ?en- able hpf? bit in the "adc control 1" register . the hpf should only be disabled when the dc component of the input signal needs to be preserved in the di gital output data. the hpf characteristics are given in the adc digital filter characteristics table and plotted in section 7 . the analog input characteristics ta- bles on pages 12 and 13 specify the dc offset error when the hpf is enabled or disabled. the following figure shows how the recommended si ngle-ended to differential active input filter ( figure 24 ) can be modified to allow for dc coupled inputs when the hpf is disabled. note that the volt- age swing should not exceed the a dc full-scale input specification. va + + - - 22 ? f 100 k ? 100 k ? 100 k ? 100 k ? 0.01 ? f22 ? f 470 pf 470 pf c0g c0g 634 ? 634 ? 634 ? 91 ? 91 ? 2700 pf c0g ainx+ ainx- adc1-4 * place close to ainx pins * figure 24. single-ended to diff erential active input filter va + + - - 100 k ? 100 k ? 100 k ? 0.01 ? f 22 ? f 470 pf 470 pf c0g c0g 634 ? 634 ? 634 ? 91 ? 91 ? 2700 pf c0g ainx+ ainx- adc1-4 * place close to ainx pins * figure 25. single-ended to differential active input filter - dc coupled input signal (va/2 centered)
ds900f2 37 CS4244 4.6.3 dac1-4 path the aout1-4 signals are driven by the data placed in to the dac1-4 path. this data can be placed into the dac1-4 path via the dac1-4 data source settings in the control port. these settings allow the input source to be selected from any of the up to 32 sl ots of data on the incoming tdm streams on sdin1 and sdin2. the dac1-4 path also includes individual channel mute s. separate volume controls are available for each channel, along with a master volume control that simultaneously atte nuates all four channels. the master volume attenuation is added to any channel attenuation that is applied. 4.6.3.1 de-emphasis filter the CS4244 includes on-chip digital de-emphasis for 32 , 44.1, and 48 khz sample rates. it is not support- ed for 96 khz or for any settings in double-speed mode . the filter response is adjusted to be appropriate for a particular base rate by the base rate advisory bits. this filter response, shown in figure 27 , will vary if these bits are not set appropriately for the given base rate. the frequency response of the de-emphasis curve scales proportionally with changes in sample rate, f s . please see section 6.9.2 dac1-4 de-em- phasis for de-emphasis control. the de-emphasis f eature is included to accommodate audio record ings that utilize 50/15 ? s pre-emphasis equalization as a means of noise reduction. i 2 c control data contr ol port level tr anslator vl 1 .8 to 5.0 vdc rst int sdout1 ldo analog supply 2. 5 v va 5.0 vdc vd 2.5 vdc ser ial audio interface sdout2 ser ial clock in/out master clock in fr ame sync clock / lrck sdin1 sdin2 aout1 () aout2 () aout3 () aout4 () interpolation filter multi-bit ?? m odulator s channel volume , mute , invert , noise gate dac & analog filters master volume contr ol ain4 ( ) ain3 ( ) ain2 ( ) ain1 ( ) digital filters multi-bit ?? adc figure 26. dac1-4 path
ds900f2 38 CS4244 de-emphasis is only availa ble in single-speed mode. 4.6.4 analog outputs the recommended differential passive output filter is shown below. the filter has a flat frequency re- sponse in the audio band while rejecting as much si gnal energy outside of the audio band as possible. the filter has a single-pole high-pass filter to ac-c ouple the output signal to the load and a single-pole low-pass filter to attenuate high-f requency energy resulting from t he CS4244 dac?s noise shaping func- tion. gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 27. de-emphasis curve dac1-4 aoutx+ 22 f 1500 pf 470 ? 47 k ? c0g aoutx- 22 f 1500 pf 470 ? 47 k ? c0g figure 28. passive analog output filter
ds900f2 39 CS4244 4.6.5 volume control the CS4244 includes a volume cont rol for the dac1-4 signal path. the implementation details for the vol- ume control and other associated peripheries for dac1-4 is shown in figure 29 below. digital volume steps, adjustable noise gating, muting, and soft ramping are provided on each dac channel. 4.6.5.1 mute behavior each dac channel volume is controlled by the sum (i n db) of the individual channel volume and the mas- ter volume registers. the channel and master volume control registers have a range of +6 db to -90 db with a nominal resolution of 6.02 / 16 db per each bit, which is approximately 0.4 db. the sum of the two volume settings is limited to a ra nge of +6 db to -90 db. any volume setting below this range will result in infinite attenuation thus muting the channel. a dac channel may alternatively be muted by using t he mute register bits, the power down bits, or the noise gate feature. for any case when the mute eng ages (volume is less than -90 db, power down bit is set, mute bit is set, or noise gate is engaged), the CS4244 will mute the channel immediately or soft-ramp the volume down at a rate specified by the mute delay[1:0] bits depending on the settings of the dac1- 4 att. bit in the "dac control 3" register . this behavior also applies when unmuting a channel. 4.6.5.2 soft ramp the CS4244 soft ramp feature (enabled using the dac1-4 att. bit) is activated on mute and unmute tran- sitions as well as any normal volume register changes. to avoid any potential audible artifacts due to the soft ramping, the volume control algorithm implements the ramping function differently based upon how the user attempts to control the volume. if the user changes the volume in distant discrete steps such as what would happen if a button were pressed on a user interface to temporarily add attenuation to or mute a channel, then the volume is ramped from the current setting to the new setting at a constant rate set by the mute delay[1:0] bits. alternatively, if the user controls the volume through a knob or slider interface, a volume envelope is sam- pled at a slow, not-necessarily uniform rate (typically 1-20 hz) and sent to the CS4244. in this case the ramping algorithm detects a short su ccession of volume changes attempting to track the volume envelope and dynamically adjusts the soft-ramp rate. if the CS4244 were to use a constant ramp rate between the volume changes it re ceives, its output volume envelope may either lag behind the user-generated envelope if the ramp rate is set too low (possibly not reaching the peaks and dulling the enve lope) or the output volume envelo pe may cause a stair-case effect resulting in audible zipper noise if the ramp rate is set too high. by instead adapting the soft-ramp rate to fit the envelope given by the incoming volume samp les, the envelope lag time is limited and the zipper 1 0 noise gate soft ramp 0 1 x dacx data + dacx volume register setting master volume register setting interpolation filter modulator dac limiter (+6 to -90 db) inv dacx dac1-4 noise gate threshold mute dacx dac1-4 att aoutx figure 29. volume implementation for the dac1-4 path
ds900f2 40 CS4244 noise is avoided. in this mode the soft ramp algorit hm linearly interpolates the volume between the volume changes. there is a lag of one volume change samp le since two samples are required to calculate the first ramp rate. see figure 30 for the soft ramp diagram. on the first volume sample received, the CS4244 only detects the possible beginning of a volume envelope sequence and resets an envelope counter. the volume starts ramping to the new volume setting at a constant rate controlled by the mute delay[1:0] setting. if the envelope counter times out before a new volume sample is received, the next received sample is treated in the same way as the previous sample and t he ramp rate is kept constant. in this way, as long as the volume samples are distant from each other by more than the envelope counter time out, the rate is kept constant resulting in the soft-ramp b ehavior described in the button-press example. however if the next volume sample is received before the envelope counter times out, then it is assumed to be part of a volume envelope sequence. the envelope counter is reset and as long as new samples are received in succession before a time out occurs, the sequence is continued. starting at the second volume sample of an envelope sequence, the ra mp rate is adjusted using the equation shown in figure 30 . two control parameters allow the user to limit the ramp-rate ran ge to achieve optimum effect. the min delay[2:0] setting limits the maximum ramp rate; higher values will introdu ce more lag in the envelope tracking while providing a smoother ramp. the max delay[2:0] setting limits the minimum ramp rate; lower values will permit closer tracki ng of the envelope but may re-introduce zipper noise. the default val- ues of these registers are recommended as a starting po int. it is possible to disable the volume envelope user: change volume or mute register wait state envelope counter running envelope counter timed out? yes no reset envelope counter limit ramp rate reset envelope counter ramp rate = mute_delay changes volume between time setting volume current - setting volume new rate ramp ? min_delay max_delay figure 30. soft ramp behavior
ds900f2 41 CS4244 tracking and always produce a constant ramp rate. to accomplish this, set the min delay[2:0] and max delay[2:0] values to match the mute delay[1:0] setting. the envelope counter time out period which defines the boundary between the two soft-ramping behav- iors depends on the base rate. it is equal to approximately 100,000/fs. the mute delay[1:0] , min delay[2:0] , and max delay[2:0] bits specify a delay equal to a multiple of the base period between volume steps of 6.02 / 64 db, which is approximately 0.1 db. this is the internal resolution of the volume control engine. consequen tly the soft-ramp rate can be expressed in ms/db as shown in table 6 . table 6. soft ramp rates full-scale ramp is 96 db (-90 db to +6 db) 4.6.5.3 noise gate the CS4244 is equipped with a noise gate feature that mutes the output if the signal drops below a given bit depth for 8192 samples. while the enabling or disa bling of the noise gate feature is done for the entire dac1-4 output path, each of the chann els within the path have separate monitoring circuitry that will trig- ger the noise gate function independe ntly of the other channels. for in stance, if the noise gate were en- abled for and one of the channels were to exhibit a pattern of more than 8192 samples of either all ?1?s? or all ?0?s?, the output for that particular ch annel would be muted (and subsequently unmuted), inde- pendently of the other channels. to enable the noise gate feature, set the dac1-4 ng[2:0] bits to the desired bit depth. the available bit depth settings are shown in table 7 . fs = 48 khz or 96 khz (base = 48 khz) fs = 32 khz or 64 khz (base = 32 khz) ramp rate time to ramp to full scale (ms) time to ramp 6 db (ms) ms/db time to ramp to full scale (ms) time to ramp 6 db (ms) ms/db 1 x base 21.33 1.33 0.22 32 2 0.33 2 x base 42.67 2.67 0.44 64 4 0.66 4 x base 85.33 5.33 0.89 128 8 1.33 8 x base 170.67 10.67 1.77 256 16 2.66 16 x base 341.33 21.33 3.54 512 32 5.32 32 x base 682.67 42.67 7.09 1024 64 10.63 64 x base 1365.33 85.33 14.17 2048 128 21.26 128 x base 2730.67 170.67 28.35 4096 256 42.52 dac1-4 ng[2:0] setting channel is muted after ?x? bits 000 upper 13 bits (-72 db) 001 upper 14 bits (-78 db) 010 upper 15 bits (-82 db) 011 upper 16 bits (-90 db) 100 upper 17 bits (-94 db) 101 upper 18 bits (-102 db) 110 upper 24 bits (-138 db) 111 noise gate disabled table 7. noise gate bit depth settings
ds900f2 42 CS4244 when the upper ?x? bits, as dictated by the dac1-4 ng [2:0] settings, are either all ?1?s? or all ?0?s? for 8192 consecutive samples, the noise gate will engage for that channel. setting these bits to ?111? will disable the noise gate feature. if the noise gate feature engages , it will transition into and out of mute as dictated by the dac1-4 att. bit in the "dac control 3" register . 4.7 reset line the reset line of the CS4244 is used to place the device into a reset condition. in th is condition, all of the values of the CS4244 control port are set to their defa ult values. this mode of o peration is the lowest power mode of operation for the CS4244 and should be used whenever the device is not operating in order to save power. during the power up and power down sequence, it is often necessary for the CS4244 devices to be placed into (and taken out of) reset at a different mom ent in time than the amplifiers to which they are con- nected in order to minimize audible clicks and pops du ring the sequence. for this reason, it is advisable to run separate reset lines for each type of device, i.e. one reset line fo r the CS4244 devices and one for the amplifier devices. 4.8 error reporting and interrupt behavior the CS4244 is equipped with a suite of error reporting and protection. the types of errors that are detected, the notification method for these errors, and the steps needed to clear the errors are detailed in table 8 . it is important to note that the interr upt notification bits for all of the errors are triggered on the edge of the occurrence of the event. they are not level-triggered and therefore do not indicate the presence of an error in real time. this means that, a ?1? in the error?s respective field inside the interrupt notification register only indicates that the error has occurred since the last time the register was cleared and not necessarily that the error is currently occurring. table 8. error reporting and interrupt behavior details note: 35. this error is provided to aid in trouble shooting during software development. entry into the test mode of the device may cause permanent damage to the device and should not be done intentionally. name of error event(s) that caused the error outputs muted upon occurrence? all pdnx bits must be set and then cleared to resume normal operation? disallowed test mode entry (note 35) device has entered test mode due to an errant i2c write. no no serial port error fs/ lrck, or sclk has become invalid. yes yes clocking error the speed mode which the device is receiving is different than the speed mode set in the speed mode bits, or the pll is unlocked from input signal. yes yes adcx overflow adc inputs are larger than the permitted full scale signal. no no (normal operation will continue but audible distortion will occur.) dacx clip dac output level is larger than the available rail voltage. no no normal operation will continue but audible distortion will occur.
ds900f2 43 CS4244 4.8.1 interrupt masking an occurrence of any of the errors mentioned above will caus e the interrupt line to engage in order to no- tify the system controller that an error has occurred. if it is preferred that the error not cause the interrupt line to engage, this error can be masked in its respective mask register. it is important to note that, in the event of an error, the interrupt noti fication bit for the respective erro r will reflect the occurrence of the event, regardless of the setting of the mask bit. setting the mask bit only prevents the interrupt pin from being flagged upon the occurrence. 4.8.2 interrupt line operation as mentioned previously, the interr upt line of the CS4244 will be pulled low or high (depending on the set- tings of the ?int pin[1:0]? bits in the "interrupt control" register ) after an interrupt condition occurs, pro- vided that the event is not masked in the mask regi ster. if the CS4244?s interrupt line is to be connected onto a single bus with other devices, it is advisable to use it in the open drain mode of operation. if no other devices are conn ected to the interrupt line, it may be us ed in the cmos mode of operation. when used in the open drain configurati on, it is necessary to connect a pu ll-up resistor to this net, which will ensure a known state on the net when no error is present. please refer to the typical connection diagram for the appropriate pull-up resistor value. 4.8.3 error reporting and clearing in the event of an error, the interrupt line will be engaged - provided the mask bit for that error is not set. when the interrupt notification registers are read to determine the source of the error, the mask bit for whichever error occurred will be set automatically by the CS4244. the system controller should begin to take corrective action to clear th e error. once the error has been cleared, the system controller should clear the mask bit in the appropriate mask register to ensure that a subsequent occurrence of the error will cause the interrupt line to engage appropriately. this behavior is detailed in figure 31 on page 45 .
ds900f2 44 CS4244 user: mask bit(s) set to 0 unmasked error occurs status register bit changes to ?1? and int pin set to active level user: read status registers (see status bit(s) = ?1?) mask bit(s) of corresponding status bit(s) set to ?1? are any errors still occurring? yes no status register bit(s) set to ? 1? user: read status registers (see all status bits = ?0?) all status register bits cleared int pin set to inactive level user: takes corrective action new unmasked error new unmasked error new unmasked error new unmasked error new unmasked error new unmasked error figure 31. interrupt behavior and example interrupt service routine
ds900f2 45 CS4244 5. register qu ick reference default values are shown below the bit names . ad function 7 6 5 4 3 2 1 0 (read only bits are shown in italics) 01h device id a & b dev. id a[3:0] dev. id b[3:0] p48 0 1 0 0 0 0 1 0 02h device id c & d dev. id c[3:0] dev. id d[3:0] p48 0 0 1 1 0 1 0 0 03h device id e & f dev. id e[3:0] dev. id f[3:0] p48 0 0 0 0 0 0 0 0 04h variant id reserved [3:0] reserved [3:0] 0 0 0 0 0 0 0 0 05h revision id alpha rev. id[3:0] numeric rev. id[3:0] p48 xx x x xxxx 06h clock & sp sel. base rate[1:0] speed mode[1:0] mclk rate[2:0] reserved p49 0 0 0 0 0 1 0 0 07h sample width sel. sdoutx sw[1:0] input sw[1:0] reserved[1:0] reserved[1:0] p50 1 1 1 1 1 1 1 1 08h sp control inv sclk reserved[2:0] sp format[1:0] sdo chain mstr/slv p50 0 1 0 0 1 0 0 0 09h sp data sel. reserved reserved dac1-4 source[2:0] reserved[2:0] p51 0 0 0 0 0 0 0 1 0ah reserved reserved[7:0] 1 1 1 1 1 1 1 1 0bh reserved reserved[7:0] 1 1 1 1 1 1 1 1 0ch reserved reserved[7:0] 1 1 1 1 1 1 1 1 0dh reserved reserved[7:0] 1 1 1 1 1 1 1 1 0eh reserved reserved reserved[2:0] reserved[3:0] 0 0 0 0 0 0 0 0 0fh adc control 1 reserved reserved va_sel enable hpf inv. adc4 inv. adc3 inv. adc2 inv. adc1 p52 1 1 0 0 0 0 0 0 10h adc control 2 mute adc4 mute adc3 mute adc2 mute adc1 pdn adc4 pdn adc3 pdn adc2 pdn adc1 p52 1 1 1 1 1 1 1 1 11h reserved reserved[2:0] reserved reserved reserved reserved reserved 1 1 1 0 0 0 0 0 12h dac control 1 dac1-4 ng[2:0] dac1-4 de reserved reserved reserved p53 1 1 1 0 0 0 0 0 13h dac control 2 reserved[2:0] reserved inv. dac4 in v. dac3 inv. dac2 inv. dac1 p53 1 1 1 0 0 0 0 0 14h dac control 3 reserved dac1-4 att. reserved reserved mute dac4 mute dac3 mute dac2 mute dac1 p54 1 0 1 1 1 1 1 1 15h dac control 4 vq ramp reserved[1:0] reserved pdn da c4 pdn dac3 pdn dac2 pdn dac1 p54 0 0 0 1 1 1 1 1
ds900f2 46 CS4244 16h volume mode mute delay[1:0] min delay[2:0] max delay[2:0] p55 1 0 0 0 0 1 1 1 17h master volume master volume[7:0] p56 0 0 0 1 0 0 0 0 18h dac1 volume dac1 volume[7:0] p56 0 0 0 1 0 0 0 0 19h dac2 volume dac2 volume[7:0] p56 0 0 0 1 0 0 0 0 1ah dac3 volume dac3 volume[7:0] p56 0 0 0 1 0 0 0 0 1bh dac4 volume dac4 volume[7:0] p56 0 0 0 1 0 0 0 0 1ch reserved reserved[7:0] 0 0 0 1 0 0 0 0 1dh reserved reserved[3:0] reserved[3:0] 1 0 1 1 1 0 1 0 1eh interrupt control int mode int pin[1:0] reserved reserved reserved reserved reserved p56 0 1 0 0 0 0 0 0 1fh interrupt mask 1 mask tst mode err mask sp err mask clk err reserved mask adc4 ovfl mask adc3 ovfl mask adc2 ovfl mask adc1 ovfl p57 0 0 0 1 0 0 0 0 20h interrupt mask 2 reserved reserved reserved reserved mask dac4 clip mask dac3 clip mask dac2 clip mask dac1 clip p58 0 0 1 0 0 0 0 0 21h interrupt notification 1 tst mod e sp err clk err reserved adc4 ovfl adc3 ovfl adc2 ovfl adc1 ovfl p58 x x x x x x x x 22h interrupt notification 2 reserved reserved reserved reserved dac4 cl ip dac3 clip dac2 clip dac1 clip p59 x x x x x x x x ad function 7 6 5 4 3 2 1 0 (read only bits are shown in italics)
ds900f2 47 CS4244 6. register descriptions all registers are read/write unless other wise stated. all ?reserved? bits must maintain their default state. default values are shaded. 6.1 device i.d. a?f (address 01h?03h) (read only) 6.1.1 device i.d. (read only) device i.d. code for the CS4244. example:. 6.2 revision i.d. (address 05h) (read only) 6.2.1 alpha revision (read only) CS4244 alpha (silicon) revision level. 6.2.2 numeric revision (read only) CS4244 numeric (metal) revision level. note: the alpha and numeric revision i.d. are used to form the complete device revision i.d. example: a0, a1, b0, b1, b2, etc. 76543210 dev. id a[3:0] dev. id b[3:0] 76543210 dev. id c[3:0] dev. id d[3:0] 76543210 dev. id e[3:0] dev. id f[3:0] dev. id a[3:0] dev. id b[3:0] dev. id c[3:0] dev. id d[3:0] dev. id e[3:0] dev. id f[3:0] part number 4h 2h 3h 4h 0h 0h CS4244 76543210 arevid3 arevid2 arevid1 arevid0 nrevid3 nrevid2 nrevid1 nrevid0 arevid[3:0] alpha revision level ah a ... ... nrevid[3:0] numeric revision level 0h 0 ... ...
ds900f2 48 CS4244 6.3 clock & sp select (address 06h) 6.3.1 base rate advisory advises the CS4244 of the base rate of the incoming base rate. this allows fo r the de-emphasis filters to be adjusted appropriately. the CS4244 includes on -chip digital de-emphasis for 32, 44.1, and 48 khz base rates. it is not supported for 96 khz or for any settings in double speed mode. 6.3.2 speed mode sets the speed mode in which the CS4244 will operate.. 6.3.3 master clock rate sets the rate at which the master clock is entering the CS4244. settings are given in ?x? multiplied by the incoming sample rate, as mclk must scale directly with incoming sample rate. 76543210 base rate[1:0] speed mode[1:0 ] mclk rate[2:0] reserved base rate base rate is: 00 48 khz 01 44.1 khz 10 32 khz 11 reserved speed mode speed mode is: 00 single speed mode 01 double speed mode 10 reserved 11 auto detect (slave mode only) mclk rate mclk is: 000 256xf s in single speed mode or 128xf s in double speed mode 001 384xf s in single speed mode or 192xf s in double speed mode 010 512xf s in single speed mode or 256xf s in double speed modex 011 reserved 100 reserved 101 reserved 110 reserved 111 reserved
ds900f2 49 CS4244 6.4 sample width select (address 07h) 6.4.1 output sample width these bits set the width of the samples placed into the outgoing sdoutx streams. note: bits wider than the output samp le width setting are cleared within the sdoutx data stream. 6.4.2 input sample width these bits set the width of the samples coming into the CS4244 through the sdinx tdm streams. note: in left justified or i2s mode, the inpu t sample width is fixed to 24 bits. 6.5 serial port control (address 08h) 6.5.1 invert sclk when set, this bit inverts the polarity of the sclk signal. 6.5.2 serial port format sets the format of both the incoming serial da ta signals and outgoing serial data signals. 76543210 sdoutx sw[1:0] input sw[1:0 ] reserved[1:0] reserved[1:0] output sw sample width is: 00 16 bits 01 18 bits 10 20 bits 11 24 bits input sw sample width is: 00 16 bits 01 18 bits 10 20 bits 11 24 bits 76543210 inv sclk reserved[2:0] sp fo rmat[1:0] sdo chain master/ slave inv sclk sclk is: 0 not inverted 1 inverted sp format format is: 00 left justified 01 i2s 10 tdm (slave mode only) 11 reserved
ds900f2 50 CS4244 6.5.3 serial data output sidechain setting this bit enables the sdout1 side chain feature. in this mode , the samples from multiple devices can be coded into one tdm stream. see section 4.6.2 adc path for details. 6.5.4 master/slave setting this bit places the CS4244 in master mode, clearing it places it in slave mode. note: i2s and left justified are the only serial port forma ts available if the CS4244 is in master mode. 6.6 serial port data select (address 09h) 6.6.1 dac1-4 data source sets which portion of data is to be routed to the dac1-4 data paths. sdo chain sidechain is: 0 disabled 1 enabled master/slave CS4244 is in: 0 slave mode 1master mode 76543210 reserved reserved dac1-4 source[2:0] reserved[2:0] dac1-4 source data is routed into the dac1-4 path from: 000 slots 1-4 of the tdm stream on sdin1 001 slots 5-8 of the tdm stream on sdin1 010 slots 9-12 of the tdm stream on sdin1 011 slots 13-16 of the tdm stream on sdin1 100 slots 1-4 of the tdm stream on sdin2 101 slots 5-8 of the tdm stream on sdin2 110 slots 9-12 of the tdm stream on sdin2 111 slots 13-16 of the tdm stream on sdin2
ds900f2 51 CS4244 6.7 adc control 1 (address 0fh) 6.7.1 va select scales internal operational voltages appropriately fo r va level. configuring this bit appropriately for the va voltage level used in the app lication is imperative to ensure proper operation of the device. 6.7.2 enable high-pass filter enables high-pass filter for the adc path. 6.7.3 inv. adcx inverts the polarity of the adcx signal. 6.8 adc control 2 (address 10h) 6.8.1 mute adcx mutes the adcx signal 6.8.2 power down adcx powers down the adcx path. 76543210 reserved reserved va_sel enable hpf inv. adc4 inv. adc3 inv. adc2 inv. adc1 va_sel must be set when va is: 0 3.3 vdc 15vdc enable hpf high pass filter is: 0 disabled 1 enabled inv. adcx adcx polarity is: 0 not inverted 1 inverted 76543210 mute adc4 mute adc3 mute_adc2 mute adc1 pdn adc4 pdn adc3 pdn adc2 pdn adc1 mute adcx adc is: 0 not muted 1 muted pdn adcx adc is: 0 powered up 1 powered down
ds900f2 52 CS4244 6.9 dac control 1 (address 12h) 6.9.1 dac1-4 noise gate this sets the bit depth at which the noise ga te feature should engage for the dac1-4 path. 6.9.2 dac1-4 de-emphasis enables or disables de-emphasis for the dac1-4 path. see section 4.6.3.1 for details. the CS4244 in- cludes on-chip digital de-emphasis for 32, 44.1, and 48 khz base rates. it is not supported for 96 khz or for any settings in double-speed mode. 6.10 dac control 2 (address 13h) 6.10.1 inv. dacx inverts the polarity of the dacx signal. 76543210 dac1-4 ng dac1-4 de reserved reserved reserved dac1-4 ng[2:0] noise gate is set at: [b] 000 upper 13 bits (72 db) 001 upper 14 bits (78 db) 010 upper 15 bits (84 db) 011 upper 16 bits (90 db) 100 upper 17 bits (96 db) 101 upper 18 bits (102 db) 110 upper 24 bits (138 db) 111 noise gate disabled dac1-4 de de-emphasis is: 0 disabled 1 enabled 76543210 reserved[2:0] reserved inv. dac4 inv. dac3 inv. dac2 inv. dac1 inv. dacx dacx polarity is: 0 not inverted 1 inverted
ds900f2 53 CS4244 6.11 dac control 3 (address 14h) 6.11.1 dac1-4 attenuation sets the mode of attenuatio n used for the dac1-4 path. note: please see section 4.6.5 volume control for more details regarding the attenuation modes. 6.11.2 mute dacx mutes the dacx signal. 6.12 dac control 4 (address 15h) 6.12.1 vq ramp ramps common mode voltage ?vq? down to ground. this bit needs to be set before asserting reset pin. 6.12.2 power down dacx powers down the dacx path. 76543210 reserved dac1-4 att reserved reserved mute dac4 mute dac3 mute dac2 mute dac1 dac1-4 att attenuation events happen: 0 on a soft ramp 1 immediately mute dacx dacx is: 0 not muted 1 muted 76543210 vq ramp reserved[1:0] reserved pdn dac4 pdn dac3 pdn dac2 pdn dac1 vq ramp effect: 0 vq is set at nominal level (va/2) 1 vq is ramped from nominal level to ground. pdn dacx dacx is: 0 powered up 1 powered down
ds900f2 54 CS4244 6.13 volume mode (address 16h) 6.13.1 mute delay sets the delay between the volume steps during muti ng and unmuting of a signal when attenuation mode is set to soft ramp. each step of the ramp is equal to 6.02 / 64 db ~= 0.094 db. settings are given as ?x? times the base period. 6.13.2 minimum delay sets the minimum delay before each volume transiti on. settings are given in ?x? times the base period. see section 4.6.5 volume control for more details regarding the operation of the volume control. 6.13.3 maximum delay sets the maximum delay before the volume transition. se ttings are given in ?x? times the base period. see section 4.6.5 volume control for more details regarding the operation of the volume control. 76543210 mute delay[1:0] min de lay[2:0] max delay[2:0] mute delay delay is: 00 1x 01 4x 10 16x 11 64x min delay minimum delay is: 000 1x 001 2x 010 4x 011 8x 100 16x 101 32x 110 64x 111 128x max delay maximum delay is: 000 1x 001 2x 010 4x 011 8x 100 16x 101 32x 110 64x 111 128x
ds900f2 55 CS4244 6.14 master and dac1-4 volume contro l (address 17h, 18h, 19h, 1ah, & 1bh) 6.14.1 x volume control sets the level of the x volume control. each volume step equals 6.02 / 16 db ~= 0.38 db. see section 4.6.5.1 on page 40 for the muting behavior of these volume registers. 6.15 interrupt control (address 1eh) 6.15.1 int mode sets the behavior mode of the interrupt registers of t he device. in the default configuration, if the interrupt notification registers are read and any error is found to have occurred since the last clearing of that reg- ister, the device will automatically se t the corresponding mask bit in the appropriate mask re gister. in the nondefault configuration, mask bits are not set automatically. 6.15.2 interrupt pin polarity sets the output mode of the interrupt pin. 76543210 x volume[7:0] x volume x volume is: [db] 00000000 +6.02 00001111 +0.38 00010000 0 00010001 -0.38 00011000 -3.01 ... ... 11111110 -89.55 (most total attenuation before mute) 11111111 -89.92 (least total attenuation before unmute) 76543210 int mode int pol [1:0] reserved res erved reserved reserved reserved int mode upon the reading of an error out of the interrupt notification bits, the CS4244 will: 0 automatically set the corresponding mask bit. 1 not set the corresponding mask bit. int pol output mode of the interrupt pin is: 00 active high 01 active low 10 active low/open drain 11 reserved
ds900f2 56 CS4244 6.16 interrupt mask 1 (address 1fh) 6.16.1 test mode error interrupt mask controls whether a test mode error event flags the interrupt pin. a test mode error occurs when an inad- vertent i2c write places th e device in test mode. 6.16.2 serial port error interrupt mask controls whether the interrupt pin if flagged when any of the following parameters are changed without first powering down the device (i.e., setting all power down adcx and power down dacx bits): ? serial port format: sp format[1:0] ? speed mode: speed mode (in slave mode, changing the mclk/f s ratio without powering down the device, flags this error and the clocking error. in master mode, changing mclk frequency without the device being powered down does not flag this or the clocking error since mclk/f s does not change.) ? master/slave: mstr/slv 6.16.3 clocking error interrupt mask allows or prevents a clocking error even t from flagging the interrupt pin. see section 4.8 for details. 6.16.4 adcx overflow interrupt mask allows or prevents an adcx overflow event from flagging the interrupt pin. 76543210 mask tst mode err mask sp err mask clk err reserved mask adc4 ovfl mask adc3 ovfl mask adc2 ovfl mask adc1 ovfl masktstmod err in the event of a test mode error event, interrupt pin will: 0 be flagged 1 not be flagged mask sp err in the event of a serial po rt error event, interrupt pin will: 0 be flagged 1 not be flagged mask clk err in the event of a clocking error event, interrupt pin will: 0 be flagged 1 not be flagged mask adcx ovfl in the event of an adcx overflow event, interrupt pin will: 0 be flagged 1 not be flagged
ds900f2 57 CS4244 6.17 interrupt mask 2 (address 20h) 6.17.1 dacx clip interrupt mask allows or prevents a dacx clip even t from flagging the interrupt pin. 6.18 interrupt notifi cation 1 (address 21h) (read only) 6.18.1 test mode error a test mode error has occurred since the last cl earing of the interrupt notification register. 6.18.2 serial port error a serial port error has occurred since the last clearing of the interrupt notification register. 6.18.3 clocking error a clocking error has occurred since the last clea ring of the interrupt notification register. 6.18.4 adcx overflow an adcx overflow has occurred since the last cl earing of the interrupt notification register. 76543210 reserved reserved reserved reserved mask dac4 clip mask dac3 clip mask dac2 clip mask dac1 clip mask dacx clip in the event of a dacx clip event, interrupt pin will: 0 be flagged 1 not be flagged 76543210 tst mode err sp err clk err reserved adc4 ovfl adc3 ovfl adc2 ovfl adc1 ovfl tstmod err since the last clearing of the interrupt notification register, a test mode error: 0 has not occurred 1 has occurred sp err since the last clearing of the interrupt notification register, a serial port error: 0 has not occurred 1 has occurred clk err since the last clearing of the interrupt notification register, a clocking error: 0 has not occurred 1 has occurred adcx ovfl since the last clearing of the interrupt notification register, a adcx overflow error: 0 has not occurred 1 has occurred
ds900f2 58 CS4244 6.19 interrupt notifi cation 2 (address 22h) (read only) 6.19.1 dacx clip a dacx clip has occurred since the last cleari ng of the inte rrupt notification register. 76543210 reserved reserved reserved reserved dac4 clip dac3 clip dac2 clip dac1 clip dacx clip since the last clearing of the interrupt notification register, a dacx clip error: 0 has not occurred 1 has occurred
ds900f2 59 CS4244 7. adc filter plots 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 frequency (normalized to fs) amplitude (db) stopband rejection 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 frequency (normalized to fs) amplitude (db) a sto a d 0.6 figure 32. adc stopband rejectio n figure 33. adc transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency (normalized to fs) amplitude (db) transition band (detail) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 frequency (normalized to fs) amplitude (db) passband ripple figure 34. adc transition band (detail) figure 35. adc passband ripple 0 2 4 6 8 10 12 14 16 18 20 ?3 ?2.5 ?2 ?1.5 ?1 ?0.5 0 frequency (hz) amplitude (db) high pass filter response (fs 48khz) 0 2 4 6 8 10 12 14 16 18 20 ?3 ?2.5 ?2 ?1.5 ?1 ?0.5 0 frequency (hz) amplitude (db) g ass te espo se ( s 96 ) figure 36. adc hpf (48 khz) figure 37. adc hpf (96 khz)
ds900f2 60 CS4244 8. dac filter plots figure 38. ssm dac stopba nd rejection figure 39. ssm dac transition band figure 40. ssm dac transition band (detail) figure 41. ssm dac passband ripple
ds900f2 61 CS4244 figure 42. dsm dac stopba nd rejection figure 43. dsm dac transition band figure 44. dsm dac transition band (detail) figure 45. dsm dac passband ripple
ds900f2 62 CS4244 9. package dimensions figure 46. package drawing notes: 1. dimensioning and tolerance per asme y4.5m - 1994. 2. dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm from the terminal tip. inches millimeters note dim min nom max min nom max a 0.0315 0.0354 0.0354 0.8 0.85 0.9 1 a1 0 0.0014 0.002 0 0.035 0.05 1 b 0.0078 0.0098 0.011 0.2 0.25 0.3 1,2 d 0.2362 bsc 6 bsc 1 d2 0.1594 0.1614 0.1634 4 4.1 4.2 1 e 0.2362 bsc 6 bsc 1 e2 0.1594 0.1614 0.1634 4 4.1 4.2 1 e 0.0197 bsc 0.5 bsc 1 l 0.0118 0.0177 0.0197 0.3 0.45 0.5 1 jedec #: mo-220 controlling dimension is millimeters. e b a a1 pin #1 identifier ? 0.50 ? 0.10 laser marking e 2.00 ? ref d2 l pin ? #1 ? corner 2.00 ? ref e2 d 40l qfn (6 ? 6 mm body) package drawing
ds900f2 63 CS4244 10.ordering information 11.revision history product description package pb-free grade temp range container order# CS4244 4 in/4 out codec 40-qfn yes commercial 0 to +70c rail CS4244-cnz tape and reel CS4244-cnzr automotive -40 to +85c rail CS4244-dnz tape and reel CS4244-dnzr cdb4244 CS4244 evaluation board - - - - cdb4244 release changes f1 mar ?12 ? updated the commercial temperature ranges from -40 to +85c to 0 to +70c and the automotive temperature ranges from -40 to +105c to -40 to +85c in the following sections: ?general description? on page 1 , ?recommended operating conditions? on page 9 , ?analog input characteristics (automotive grade)? on page 13 , ?adc digital filter characteristics? on page 15 , ?analog output characteristics (automotive grade)? on page 17 , and section 10. orde ring information . ? updated psrr specification in the analog input characteristics (commercial grade) and analog input characteristics (automotive grade) tables. ? removed note about adc cm bits in the analog input characteristics (commercial grade) and analog input characteristics (automotive grade) tables. ? removed t a test condition from ?adc digital filter characteristics? on page 15 . ? added analog input pins must be externally biased to section 4.6.2.1 . ? changed adc cm bits to reserved in section 5 and section 6.6 . ? changed part number for automotive grade in section 10. ordering information from enz to dnz. f2 oct ?14 ? updated dimensions and figure in section 9. package dimensions . (data sheet change only; no change has been made to the physical device.) contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com . important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual propert y rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve potential risks of death, per sonal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not designed, au thorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life su pport products or other crit- ical applications. inclus ion of cirrus products in such appl ications is understood to be full y at the customer?s risk and cir- rus disclaims and makes no warranty, expres s, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or custom- er?s customer uses or permits the use of cirrus products in cr itical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any a nd all liability, including at- torneys? fees and costs, that may result fr om or arise in connection with these uses. cirrus logic, cirrus and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names i n this document may be trademarks or service marks of their respective owners. blu-ray disc is a registered trademark of sony kabushiki kaisha corporation.

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