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| cyrf89135 proc? - embedded cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-86331 rev. ** revised april 3, 2013 proc? - embedded proc? ? embedded features single device, two functions ? 8-bit flash based mcu function and 2.4-ghz wirelessusb? nl radio transceiver function in a single device rf attributes ? wide operating range: 1.9 v to 3.6 v ? 2.4-ghz wirelessusb nl transceiver function ? operates in the 2.4-ghz ism band (2.402 ghz?2.479 ghz) ? 1-mbps over-the-air data rate ? receive sensitivity typical: ?87 dbm ? 1 a typical current consumption in sleep state ? closed-loop frequency synthesis ? supports frequency-hopping spread spectrum ? on-chip packet framer with 64-byte first in first out (fifo) data buffer ? built-in auto-retry-acknowledge protocol simplifies usage ? built-in cyclic redundancy check (crc), forward error correction (fec), data whitening ? additional outputs for interrupt request (irq) generation ? digital readout of received signal strength indication (rssi) mcu attributes ? powerful harvard-architecture processor ? m8c cpu ? up to 4 mips with 24 mhz internal clock, external crystal resonator or clock signal ? low power at high speed temperature range: 0 c to +70 c flexible on-chip memory ? 32 kb flash/2 kb sram ? 50,000 flash erase/write cycles ? partial flash updates ? flexible protection modes ? in-system serial programming (issp) precision, programmable clocking ? internal main oscillator (imo): 6/12/24 mhz 5% ? internal low-speed oscillator (ilo) at 32 khz for watchdog and sleep timers ? precision 32 khz oscillator for optional external crystal programmable pin configurations ? up to 35 general-purpose i/os (gpios) ? dual mode gpio: all gpios support digital i/o and analog inputs ? 25-ma sink current on each gpio ? 120 ma total sink current on all gpios ? pull-up, high z, open-drain modes on all gpios ? cmos drive mode ?5 ma source current on ports 0 and 1 and 1 ma on port 2 ? 20 ma total source current on port 1. ? configurable input threshold for port 1. versatile analog system ? low-dropout voltage regulator for all analog resources ? high power supply rejection ratio (psrr) comparator ? 8 to 10-bit incremental analog-to-digital converter (adc) additional system resources ? i 2 c slave: ? selectable to 50 khz, 100 khz, or 400 khz ? spi master and slave: configurable 46.9 khz to 12 mhz ? three 16-bit timers ? watchdog and sleep timers ? integrated supervisory circuit ? emulated e2prom using flash memory complete development tools ? free development tool (psoc designer?) ? full-featured, in-cir cuit emulator (ice) and programmer ? full-speed emulation ? complex breakpoint structure ? 128 kb trace memory package option ? 68-pin 8mm 8mm 1.0 mm qfn
cyrf89135 document number: 001-86331 rev. ** page 2 of 41 logical block diagram system bus cpu core (m8c) srom 32k flash system resources por and lvd port 1 port 0 sleep and watchdog port 2 prog. ldo sram 2048 bytes interrupt controller psoc core digital clocks rst_n fifo pkt xtalo synthesizer brclk xtali v out v dd_io v in ant xtal osc x vco lna + bpf gfsk modulator ldo linear regulator pa image rej . mxr. spi registers framer antb gfsk demodulator pwr/ reset wirelessusb-nl system i2c slave internal voltage references system resets spi master/ slave three 16 bit timers port 3 port 4 pwr sys (regulator) 6/12/24 mhz internal main oscillator internal low speed oscillator (ilo multiple clock sources cyrf89135 document number: 001-86331 rev. ** page 3 of 41 contents psoc ? functional overview ............................................ 4 psoc core .................................................................. 4 10 bit adc ................................................................... 4 spi ............................................................................... 5 i2c slave ..................................................................... 5 wirelessusb nl system ............................................. 5 transmit power control ............................................... 6 power-on and register initialization sequence ........... 6 getting started .................................................................. 7 development kits ........................................................ 7 training ....................................................................... 7 cypros consultants .................................................... 7 solutions library .......................................................... 7 technical support ....................................................... 7 development tools .......................................................... 8 psoc designer software subsystems ........................ 8 designing with psoc designer ....................................... 9 select user modules ................................................... 9 configure user modules .............................................. 9 organize and connect ................................................ 9 generate, verify, and debug ....................................... 9 pinouts ............................................................................ 10 pin definitions ................................................................ 10 absolute maximum ratings .......................................... 13 operating temperature .................................................. 13 electrical specifications ? psoc core ......................... 14 dc chip-level specifications .................................... 15 dc gpio specifications ............................................ 16 analog dc mux bus specifications ........................... 18 dc low power comparator specifications ............... 18 comparator user module electr ical specifications ... 18 adc electrical specifications .................................... 19 dc por and lvd specifications .............................. 20 dc programming specifications ............................... 21 dc i2c specifications ............................................... 22 dc reference buffer specifications .......................... 22 ac chip-level specifications .................................... 23 ac gpio specifications ............................................ 24 ac comparator specifications .................................. 25 ac external clock specifications .............................. 25 ac programming specifications ................................ 26 ac i2c specifications ................................................ 27 electrical specifications ? rf section ......................... 30 packaging information ................................................... 34 thermal impedances ................................................. 35 capacitance on crystal pins ..................................... 35 solder reflow specifications ..................................... 35 development tool selection .. .............. .............. ........... 36 software .................................................................... 36 development kits ...................................................... 36 evaluation tools ........................................................ 36 device programmers ................................................. 36 ordering information ...................................................... 37 ordering code definitions ......................................... 37 acronyms ........................................................................ 38 reference documents .................................................... 38 document conventions ................................................. 38 units of measure ....................................................... 38 numeric naming ........................................................ 39 glossary .......................................................................... 39 document history page ................................................. 40 sales, solutions, and legal information ...................... 41 worldwide sales and design support ....................... 41 products .................................................................... 41 psoc solutions ......................................................... 41 cyrf89135 document number: 001-86331 rev. ** page 4 of 41 psoc ? functional overview the psoc family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (mcu)-based components with one, low cost single-chip programmable component. a psoc device includes configurable analog and digital blocks, and programmable interconnect. this architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the architecture for this device family, as shown in the logical block diagram on page 2 , consists of three main areas: the core wirelessusb nl system system resources. a common, versatile bus allows connection between i/o and the analog system. psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo and ilo. the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a 4-mips, 8-bit harvard-architecture microprocessor. system resources provide addit ional capability, such as a configurable i 2 c slave and spi master-slave communication interface and various system resets supported by the m8c. 10 bit adc the adc on proc-emb is an independent block with a state machine interface to control accesses to the block. the adc is housed together with the temperature sensor core and can be connected to this or the analog mux bus. as a default operation, the adc is connected to the temperature sensor diodes to give digital values of the temperature. the adc user module contains an integrator block and one comparator with positive and negative input set by the muxes. the input to the integrator stage comes from the analog global input mux or the temperature sensor with an input voltage range of 0 v to 1.3 v, where 1.3 v is 72% of full scale. interface block command/ status adc temp diodes v in system bus temp sensor/ adc interface to the m8 c ( processor ) core cyrf89135 document number: 001-86331 rev. ** page 5 of 41 spi the serial peripheral interconnect (spi) 3-wire protocol uses both edges of the clock to enable synchronous communication without the need for stringent setup and hold requirements. figure 1. basic spi configuration a device can be a master or slave. a master outputs clock and data to the slave device and inputs slave data. a slave device inputs clock and data from the master device and outputs data for input to the master. together, the master and slave are essentially a circular shift register, where the master generates the clocking and initiates data transfers. a basic data transfer occurs when the master sends eight bits of data, along with eight clocks. in any transfer, both master and slave transmit and receive simultaneously. if the master only sends data, the received data from the slave is ignored. if the master wishes to receive data from the slave, the master must send dummy bytes to generate the clocking for the slave to send data back. i 2 c slave the i 2 c slave enhanced communications block is a serial-to-parallel processor, designed to interface the proc-emb device to a two-wire i 2 c serial communications bus. to eliminate the need for excessive cpu intervention and overhead, the block provides i 2 c-specific support for status detection and generation of framing bits. by default, the i 2 c slave enhanced module is firmware compatible with the previous generation of i 2 c slave functionality. however, this module provides new features that are configurable to implement significant flexibility for both internal and external interfacing. figure 2. i 2 c block diagram the basic i2c features include slave, transmitter, and receiver operation byte processing for low cpu overhead interrupt or pollin g cpu interface support for clock rates of up to 400 khz 7- or 10-bit addressing (through firmware support) smbus operation (through firmware support) enhanced features of the i 2 c slave enhanced module include: support for 7-bit hardware address compare flexible data buffering schemes a ?no bus stalling? operating mode a low power bus monitoring modethe i 2 c block controls the data (sda) and the clock (scl) to the external i 2 c interface through direct connections to two dedicated gpio pins. when i 2 c is enabled, these gpio pins are not available for general purpose use. the encore v lv cpu firmware interacts with the block through i/o register reads and writes, and firmware synchronization is implemented through polling and/or interrupts. wirelessusb nl system wirelessusb nl, optimized to operate in the 2.4-ghz ism band, is cypress's third generation of 2.4-ghz low-power rf technology. wirelessusb nl implements a gaussian frequency-shift keying (gfsk) radio using a differentiated single-mixer, closed-loop modulation design that optimizes power efficiency and interference immunity. closed-loop modulation effectively eliminates the problem of frequency drift, enabling wirelessusb nl to transmit up to 255-byte payloads without repeatedly having to pay power penalties for re-locking the phase-locked loop (pll) as in open-loop designs among the advantages of wirelessusb nl are its fast lock times and channel switching, along with the ability to transmit larger payloads. use of longer payload packets, compared to multiple short payload packets, can reduce overhead, improve overall power efficiency, and help alleviate spectrum crowding. mosi miso sclk data is output by both the master and slave on one edge of the clock. data is registered at the input of both devices on the opposite edge of the clock. spi block registers sysclk data_out data_in clk_in clk_out int ss_ sclk mosi, miso sclk mosi, miso configuration[7:0] control[7:0] transmit[7:0] receive[7:0] i2c core i2c basic configuration i2c_cfg i2c_scr i2c_dr plus features hw addr cmp buffer module cpu port buffer ctl 32 byte ram i2c plus slave i2c_addr sda_out scl_in sysclk i2c_en to/from gpio pins standby scl_out sda_in i2c_xstat i2c_xcfg i2c_buf i2c_bp i2c_cp mcu_cp mcu_bp system bus cyrf89135 document number: 001-86331 rev. ** page 6 of 41 combined with cypress?s controller, wirelessusb nl also provides the lowest bill of materials (bom) cost solution for sophisticated pc peripheral applications such as wireless keyboards and mice, as well as best-in-class wireless perfor- mance in other demanding applications. such as toys, remote controls, fitness, automation, presenter tools, and gaming. with proc-emb 68-pin qfn, the wirelessusb nl transceiver can add wireless capability to a wide variety of applications. the wirelessusb nl is a fully-integrated cmos rf transceiver, gfsk data modem, and packet framer, optimized for use in the 2.4-ghz ism band. it contains transmit, receive, rf synthesizer, and digital modem functions, with few external components. the transmitter supports digital power control. the receiver uses extensive digital processing for excellent overall performance, even in the presence of interference and transmitter impairments. the product transmits gfsk data at approximately 0-dbm output power. sigma-delta pll delivers high-quality dc-coupled transmit data path. the low-if receiver architecture produces good selectivity and image rejection, with typical sensitivity of ?87 dbm or better on most channels. sensitivity on channels that are integer multiples of the crystal reference oscillator frequency (12 mhz) may show approximately 5 db degradation. digital rssi values are available to monitor channel quality. on-chip transmit and receive fifo registers are available to buffer the data transfer with mcu. over-the-air data rate is always 1 mbps even when connected to a slow, low-cost mcu. built-in crc, fec, data whitening, and automatic retry/acknowledge are all available to simplify and optimize performance for individual applications. for more details on the radio?s implementation details and timing requriements, please go through the wirelessusb nl datasheet in www.cypress.com . figure 3. wirelessusb nl logic block diagram miso rst_n clk mosi spi_ss pkt xtalo synthesizer brclk xtali v out v dd_io v in ant xtal osc x vco lna + bpf gfsk modulator ldo linear regulator pa image rej. mxr. spi registers framer antb gfsk demodulator gnd gnd pwr/ reset v dd1 ...v dd7 cyrf89135 document number: 001-86331 rev. ** page 7 of 41 transmit power control the following table lists recommended settings for register 9 for short-range applications, where reduced transmit rf power is a desirable trade off for lower current. power-on and register initialization sequence for proper initialization at power up, v in must ramp up at the minimum overall ramp rate no slower than shown by t vin specification in the following figure. during this time, the rst_n line must track the v in voltage ramp-up profile to within approximately 0.2 v. since most mcu gpio pins automatically default to a high-z condition at power up, it only requires a pull-up resistor. when power is stable and the mcu por releases, and mcu begins to execute instructions, rst_n must then be pulsed low as shown in figure 13 , followed by writing reg[27 = 0x4200. during or after this spi transaction, the state machine status can be read to confirm framer_st = 1, indicating a proper initialization. additional system resources system resources, some of which have been previously listed, provide additional capability useful to complete systems. additional resources include low voltage detection and power on reset. the following statements describe the merits of each system resource: low-voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced power-on reset (por) circuit eliminates the need for a system supervisor. the 3.6 v maximum input, 1.8, 2.5, or 3 v selectable output, low dropout regulator (ldo) provides regulation for i/os. a register controlled bypass mode enables the user to disable the ldo. a register-controlled bypass mode allows the user to disable the ldo regulator. getting started the quickest way to understand t he proc-emb silicon is to read this datasheet and then use the psoc designer integrated development environment (ide). this datasheet is an overview of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in depth information, along with detailed programming details, see the technical reference manual for the encore-v lv. for up-to-date ordering, packaging, and electrical specification information, see the latest psoc device datasheets on the web at www.cypress.com/psoc . development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics a nd skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. table 1. transmit power control power setting description typical transmit power (dbm) register 9 pa0 - highest power +1 0x1820 pa2 - high power 0 0x1920 pa4 - high power ?3 0x1a20 pa8 - low power ?7.5 0x1c20 pa12 - lower power ?11.2 0x1e20 cyrf89135 document number: 001-86331 rev. ** page 8 of 41 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application requirements. psoc designer software accelerates system design and time to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modul es) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical us er interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (dacs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this lets you to use more than 100 percent of psoc?s resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also lets you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-se nsitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a base unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation. cyrf89135 document number: 001-86331 rev. ** page 9 of 41 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed-function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. the psoc development process is: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules?. user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pwm user module configures one or more digital psoc blocks, one for each eight bits of resolution. using these parameters, you can establish the pulse width and duty cycle. configure the parameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. all of the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. organize and connect build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate configuration files? step. this causes psoc designer to generate source code that automatically configures the device to your specification and provides the software for the system. the generated code provides apis with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. a complete code development en vironment lets you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (accessed by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full-speed. psoc designer debugging capabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. the interface lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. cyrf89135 document number: 001-86331 rev. ** page 10 of 41 pinouts the CYRF89135-68LTXC proc-emb device is available in a 68-pin qfn package, which is illustrated in the following table. every port pin (labeled with a ?p?) is capable of digital i/o and connection to the common analog bus. however, v dd , and xres are not capable of digital i/o. figure 4. 68-pin qfn pinout pin definitions this table gives the pin definitions. [1, 2] pin no. pin name description 1 test2 reserved for factory test. do not connect. 2 test3 reserved for factory test. do not connect. 3 vdd core power supply voltage. connect all vdd pins to vout pin 4 p0[4] analog i/o, digital i/o, vref 5 p0[6] analog i/o, digital i/o 6 vin unregulated input voltage to the on-chip low drop out (ldo) voltage regulator. 7 vdd core power supply voltage. connect all vdd pins to vout pin. 8 ocdo ocd odd data io, nc 9 ocde ocd even data output, nc 10 p0[7] analog i/o, digital i/o,spi clk 11 p0[5] analog i/o, digital i/o test2 test3 vdd p0[4] p0[6] vin vdd ocdo ocde p0[7] p0[5] p0[3] fifo p0[1] vin ocdoe p2[7] p2[5] pkt rst_n p2[3] p2[1] p4[1] p3[7] spi_ss p3[5] p3[3] p3[1] clk mosi miso p1[7] p1[5] vdd p1[6] vdd p1[4] p1[2] p1[0] test1 nc xtali xtalo vdd gnd p1[1] vout p1[3] vin hclk cclk p0[2] p0[0] p2[6] p2[4] p2[2] p2[0] vdd p4[2] ant p4[0] p3[6] antb p3[4] p3[2] p3[0] vdd xres 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 cyrf89135 68-pin qfn notes 1. connect all vdd pin to vout pin. 2. each of the ant and antb pins much be dc grounded, 20 k ? or less. cyrf89135 document number: 001-86331 rev. ** page 11 of 41 12 p0[3] analog i/o, digital i/o, integrating input 13 fifo fifo status indicator bit 14 p0[1] analog i/o, digital i/o, integrating input 15 vin unregulated input voltage to the on-chip low drop out (ldo) voltage regulator. 16 ocdoe ocd mode direction pin, nc 17 p2[7] analog i/o, digital i/o 18 p2[5] analog i/o, digital i/o, xtal out 19 p2[3] analog i/o, digital i/o, xtal in 20 p2[1] analog i/o, digital i/o 21 p4[1] analog i/o, digital i/o 22 p3[7] analog i/o, digital i/o 23 spi_ss enable input for spi, active low. also used to bring device out of sleep state. 24 p3[5] analog i/o, digital i/o 25 p3[3] analog i/o, digital i/o 26 pkt transmit/receive packet status indicator bit 27 p3[1] analog i/o, digital i/o 28 clk clock input for spi interface 29 mosi data input for the spi bus 30 miso data output (tristate when not active) 31 p1[7] digital i/o, analog i/o, i2c scl, spi ss 32 rst_n rst_n low: chip shutdown to conserve power. register values lost rst_n high: turn on chip, registers restored to default value 33 p1[5] digital i/o, anal og i/o, i2c sda, spi miso 34 vdd core power supply voltage. connect all vdd pins to vout pin. 35 cclk ocd cpu clk output, nc 36 hclk ocd high speed clk, nc 37 vin unregulated input voltage to the on-chip low drop out (ldo) voltage regulator 38 p1[3] digital i/o, analog i/o, spi clk 39 vout 1.8 v output from on-chip ldo. connect to all vdd pins, do not connect to external loads. 40 p1[1] digital i/o, analog i/o, tc clk, i2c scl, spi mosi 41 gnd ground pin 42 vdd core power supply voltage. connect all vdd pins to vout pin. 43 xtalo output of the crystal oscillator gain block 44 xtali input to the crystal oscillator gain block 45 nc no connect 46 test1 reserved for factory test. do not connect. 47 p1[0] analog i/o, digital i/o, tc data, i2c sda 48 p1[2] analog i/o, digital i/o 49 p1[4] analog i/o, digital i/o, ext clk 50 vdd core power supply voltage. connect all vdd pins to vout pin. pin definitions (continued) this table gives the pin definitions. [1, 2] pin no. pin name description cyrf89135 document number: 001-86331 rev. ** page 12 of 41 51 p1[6] analog i/o, digital i/o 52 xres active high external reset with internal pull down 53 vdd core power supply voltage. connect all vdd pins to vout pin. 54 p3[0] analog i/o, digital i/o 55 p3[2] analog i/o, digital i/o 56 p3[4] analog i/o, digital i/o. 57 antb differential rf input/output. 58 p3[6] analog i/o, digital i/o. 59 p4[0] analog i/o, digital i/o. 60 ant differential rf input/output. 61 p4[2] analog i/o, digital i/o. 62 vdd core power supply voltage. connect all vdd pins to vout pin. 63 p2[0] analog i/o, digital i/o 64 p2[2] analog i/o, digital i/o 65 p2[4] analog i/o, digital i/o 66 p2[6] analog i/o, digital i/o 67 p0[0] analog i/o, digital i/o 68 p0[2] analog i/o, digital i/o pin definitions (continued) this table gives the pin definitions. [1, 2] pin no. pin name description cyrf89135 document number: 001-86331 rev. ** page 13 of 41 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature table 2. absolute maximum ratings symbol description conditions min typ max units t stg storage temperature higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 85 c degrades reliability. ?55 25 125 c v in ? 1.9 ? 3.63 v v dd supply voltage ? ?0.5 ? 1.98 v v io dc input voltage ? ?0.5 ? vdd + 0.5 v v ioz [3] dc voltage applied to tristate ? ?0.5 ? vdd + 0.5 v i mio maximum current into any port pin ? ?25 ? 50 ma esd electrostatic discharge voltage human body model esd i) rf pins (ant, antb) ii) analog pins (xtali, xtalo) iii) remaining pins 500 500 2000 ? ? v lu latch-up current in accordance with jesd78 standard ? ? 140 ma table 3. operating temperature symbol description conditions min typ max units t a ambient temperature ? 0 ? 70 c note 3. port1 pins are hot-swap capable with i/o configur ed in high-z mode, and pin input voltage above v in . cyrf89135 document number: 001-86331 rev. ** page 14 of 41 electrical specifications ? psoc core this section presents the dc and ac electrical specifications of the cyrf89435-68ltxc psoc device. for the latest electrical specifications, confirm that you have the mo st recent datasheet by visiting the web at http://www.cypress.com/psoc . figure 5. voltage versus cpu frequency 3.6 v 750 khz 24 mhz cpu frequency vin voltage 1.9 v 3 mhz v a l i d o p e r a t i n g r e g i o n cyrf89135 document number: 001-86331 rev. ** page 15 of 41 dc chip-level specifications the following table lists guaranteed maximum and minimum s pecifications for the entire voltage and temperature ranges. table 4. dc chip level specifications symbol description conditions min typ max units vdd [4, 5] supply voltage see table titled dc por and lvd specifications on page 20. 1.71 ? 3.6 v i dd24 supply current, imo = 24 mhz conditions are vdd ? 3.0 v, t a = 25 c, cpu = 24 mhz no i2c/spi ? 2.9 4.0 ma i dd12 supply current, imo = 12 mhz conditions are vdd ? 3.0 v, t a = 25 c, cpu = 12 mhz no i2c/spi ? 1.7 2.6 ma i dd6 supply current, imo = 6 mhz conditions are vdd ? 3.0 v, t a = 25 c, cpu = 6 mhz no i2c/spi ? 1.2 1.8 ma i sb1 standby current with por, lvd, and sleep timer vdd ? 3.0v, t a = 25 c, i/o regulator turned off ? 1.1 1.5 ? a i sb0 deep sleep current vdd ? 3.0 v, t a = 25 c, i/o regulator turned off ? 0.1 ? ? a notes 4. if powering down in standby sleep mode, to properly detect and recover from a v in brown out condition any of the following actions must be taken: bring the device out of sleep before powering down. assure that v in falls below 100 mv before powering back up. set the no buzz bit in the osc_cr0 register to keep the voltage monitoring circuit powered during sleep. increase the buzz rate to assure that the falling edge of v in is captured. the rate is configured through the pssdc bits in the slp_cfg register. for the referenced registers, refer to the cy8c20x36 technical reference manual . in deep sleep mode, additional low power voltage monitoring circuitry allows v in brown out conditions to be detected for edge rates slower than 1v/ms. 5. always greater than 50 mv above v ppor1 voltage for falling supply. 6. always greater than 50 mv above v ppor2 voltage for falling supply. 7. always greater than 50 mv above v ppor3 voltage for falling supply. cyrf89135 document number: 001-86331 rev. ** page 16 of 41 dc gpio specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 2.4 v to 3.0 v and 0 c ? t a ? 70 c, or 1.9 v to 2.4 v and 0 c ? t a ????? c, respectively. typical parameters apply to 3.3 v at 25 c and are for design guidance only. table 5. 2.4 v to 3.0 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 or 4 pins i oh < 10 ? a, maximum of 10 ma source current in all i/os v in ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 or 4 pins i oh = 0.2 ma, maximum of 10 ma source current in all i/os v in ? 0.40 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh < 10 ? a, maximum of 10 ma source current in all i/os v in ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 2 ma, maximum of 10 ma source current in all i/os v in ? 0.50 ? ? v v oh5a high output voltage port 1 pins with ldo enabled for 1.8 v out i oh < 10 ? a, v in > 2.4 v, maximum of 20 ma source current in all i/os 1.50 1.80 2.10 v v oh6a high output voltage port 1 pins with ldo enabled for 1.8 v out i oh = 1 ma, v in > 2.4 v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage iol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ??0.75v v il input low voltage ? ? ? 0.72 v v ih input high voltage ? 1.40 ? v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent temp = 25 ? c 0.50 1.70 7 pf v illvt2.5 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.7 ? ? v v ihlvt2.5 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.2 ? v cyrf89135 document number: 001-86331 rev. ** page 17 of 41 table 6. 1.9 v to 2.4 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 or 4 pins i oh = 10 ? a, maximum of 10 ma source current in all i/os v in ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 or 4 pins i oh = 0.5 ma, maximum of 10 ma source current in all i/os v in ? 0.50 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 100 ? a, maximum of 10 ma source current in all i/os v in ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 2 ma, maximum of 10 ma source current in all i/os v in ? 0.50 ? ? v v ol low output voltage i ol = 5 ma, maximum of 20 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ??0.40v v il input low voltage ? ? ? 0.30 v in v v ih input high voltage ? 0.65 v in ??v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent temp = 25 c 0.50 1.70 7 pf cyrf89135 document number: 001-86331 rev. ** page 18 of 41 analog dc mux bus specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc low power compar ator spec ifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. comparator user module electrical specifications the following table lists the guaranteed maximum and minimum spec ifications. unless stated otherwise, the specifications are fo r the entire device voltage and temperature operating range: 0 c ? t a ? 70 c, 1.9 v ? v in ? 3.6 v. table 7. dc analog mux bus specifications symbol description conditions min typ max units r sw switch resistance to common analog bus ? ? ? 800 ? r gnd resistance of initialization switch to gnd ? ? ? 800 ? the maximum pin voltage for measuring r sw and r gnd is 1.8 v. table 8. dc comparator specifications symbol description conditions min typ max units v lpc low power comparator (lpc) common mode maximum voltage limited to v in 0.0?1.8v i lpc lpc supply current ? ? 10 40 ? a v oslpc lpc voltage offset ? ? 3 30 mv table 9. comparator user module electrical specifications symbol description conditions min typ max units t comp comparator response time 50 mv overdrive ? 70 100 ns offset valid from 0.2 v to (v in ? 0.2 v) ? 2.5 30 mv current average dc current, 50 mv overdrive ? 20 80 a psrr supply voltage > 2 v power supply rejection ratio ? 80 ? db supply voltage < 2 v power supply rejection ratio ? 40 ? db input range ? 0 ? 1.5 v cyrf89135 document number: 001-86331 rev. ** page 19 of 41 adc electrical specifications table 10. adc user module electrical specifications symbol description conditions min typ max units input v in input voltage range ? 0 ? vrefadc v c iin input capacitance ???5pf r in input resistance equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution 1/(500ff data clock) 1/(400ff data clock) 1/(300ff data clock) ? reference v refadc adc reference voltage ?1.14?1.26v conversion rate f clk data clock source is chip?s internal main oscillator. see ac chip-level specifications for accuracy 2.25 ? 6 mhz s8 8-bit sample rate data cl ock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ? 23.43 ? ksps s10 10-bit sample rate data clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ? 5.85 ? ksps dc accuracy res resolution can be set to 8-, 9-, or 10-bit 8 ? 10 bits dnl differential nonlinearity ? ?1 ? +2 lsb inl integral nonlinearity ? ?2 ? +2 lsb e offset offset error 8-bit resolution 0 3.20 19.20 lsb 10-bit resolution 0 12.80 76.80 lsb e gain gain error for any resolution ?5 ? +5 %fsr power i adc operating current ? ? 2.10 2.60 ma psrr power supply rejection ratio psrr (vin > 3.0 v) ?24?db psrr (vin < 3.0 v) ?30?db cyrf89135 document number: 001-86331 rev. ** page 20 of 41 dc por and lvd specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 11. dc por and lvd specifications symbol description conditions min typ max units v por1 2.36 v selected in psoc designer porlev[1:0] = 00b, hpor = 1 v in must be greater than or equal to 1.9 v during startup, reset from the xres pin, or reset from watchdog. ?2.362.41v v por2 2.60 v selected in psoc designer porlev[1:0] = 01b, hpor = 1 ?2.602.66 v por3 2.82 v selected in psoc designer porlev[1:0] = 10b, hpor = 1 ?2.822.95 v lvd0 2.45 v selected in psoc designer ? 2.40 2.45 2.51 v v lvd1 2.71 v selected in psoc designer 2.64 [8] 2.71 2.78 v lvd2 2.92 v selected in psoc designer 2.85 [9] 2.92 2.99 v lvd3 3.02 v selected in psoc designer 2.95 [10] 3.02 3.09 v lvd4 3.13 v selected in psoc designer 3.06 3.13 3.20 v lvd5 1.90 v selected in psoc designer 1.84 1.90 2.32 notes 8. always greater than 50 mv above v ppor1 voltage for falling supply. 9. always greater than 50 mv above v ppor2 voltage for falling supply. 10. always greater than 50 mv above v ppor3 voltage for falling supply. cyrf89135 document number: 001-86331 rev. ** page 21 of 41 dc programming specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 12. dc programming specifications symbol description conditions min typ max units vin supply voltage for flash write operations ? 1.91 ? 3.6 v i ddp supply current during programming or verify ? ? 5 25 ma v ilp input low voltage during programming or verify see the appropriate dc gpio specifications on page 16 ? ? v il v v ihp input high voltage during programming or verify see the appropriate dc gpio specifications on page 16 v ih ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 0.2 ma i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 1.5 ma v olp output low voltage during programming or verify ? ? + 0.75 v v ohp output high voltage during programming or verify see appropriate dc gpio specifications on page 16 . for v in > 3 v use v oh4 in table 3 on page 13. v oh ? vin v flash enpb flash write endurance erase/write cycles per block 50,000 ? ? ? flash dr flash data retention following maximum flash write cycles; ambient temperature of 55 c 20 ? ? years cyrf89135 document number: 001-86331 rev. ** page 22 of 41 dc i 2 c specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3, 2.4 v to 3.0 v and 0 c ? t a ? 70 c, or 1.9 v to 2.4 v and 0 c ? t a ? 70 c, respectively. typical parameters apply to 3.3 v at 25 c and are for design guidance only. dc reference buffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 2.4 v to 3.0 v and 0 c ? t a ? 70 c, or 1.9 v to 2.4 v and 0 c ? t a ? 70 c, respectively. typical parameters apply to 3.3 v at 25 c and are for design guidance only. table 13. dc i 2 c specifications symbol description conditions min typ max units v ili2c input low level 3.1 v vin 3.6 v ? ? 0.25 vin v 2.5 v vin 3.0 v ? ? 0.3 vin v 1.9 v vin 2.4 v ? ? 0.3 vin v v ihi2c input high level 1.9 v vin 3.6 v 0.65 vin ? ? v table 14. dc reference buffer specifications symbol description conditions min typ max units v ref reference buffer output 1.9 v to 3.6 v 1 ? 1.05 v v refhi reference buffer output 1.9 v to 3.6 v 1.2 ? 1.25 v cyrf89135 document number: 001-86331 rev. ** page 23 of 41 ac chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 15. ac chip-level specifications symbol description conditions min typ max units f imo24 imo frequency at 24 mhz setting ? 22.8 24 25.2 mhz f imo12 imo frequency at 12 mhz setting ? 11.4 12 12.6 mhz f imo6 imo frequency at 6 mhz setting ? 5.7 6.0 6.3 mhz f cpu cpu frequency ? 0.75 ? 25.20 mhz f 32k1 ilo frequency ? 19 32 50 khz f 32k_u ilo untrimmed frequency ? 13 32 82 khz dc imo duty cycle of imo ? 40 50 60 % dc ilo ilo duty cycle ? 40 50 60 % sr power_up power supply slew rate vin slew rate during power-up ? ? 250 v/ms t xrst external reset pulse width at power-up after supply voltage is valid 1 ? ? ms t xrst2 external reset pulse width after power-up applies after part has booted 10 ? ? ? s t os startup time of eco ? ? 1 ? s t jit_imo n = 32 6 mhz imo cycle-to-cycle jitter (rms) ? 0.7 6.7 ns 6 mhz imo long term n (n = 32) cycle-to-cycle jitter (rms) ? 4.3 29.3 ns 6 mhz imo period jitter (rms) ? 0.7 3.3 ns 12 mhz imo cycle-to-cycle jitter (rms) ? 0.5 5.2 ns 12 mhz imo long term n (n = 32) cycle-to-cycle jitter (rms) ? 2.3 5.6 ns 12 mhz imo period jitter (rms) ? 0.4 2.6 ns 24 mhz imo cycle-to-cycle jitter (rms) ? 1.0 8.7 ns 24 mhz imo long term n (n = 32) cycle-to-cycle jitter (rms) ? 1.4 6.0 ns 24 mhz imo period jitter (rms) ? 0.6 4.0 ns cyrf89135 document number: 001-86331 rev. ** page 24 of 41 ac gpio specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 6. gpio timing diagram table 16. ac gpio specifications symbol description conditions min typ max units f gpio gpio operating frequency normal strong mode port 0, 1 0 0 ? ? 6 mhz for 1.9 v cyrf89135 document number: 001-86331 rev. ** page 26 of 41 ac programming specifications figure 7. ac waveform the following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. sclk ( p1[ 1]) t rsclk t fsclk sdata (p1[0]) t ssclk t hsclk t dsclk table 19. ac programming specifications symbol description conditions min typ max units t rsclk rise time of sclk ? 1 ? 20 ns t fsclk fall time of sclk ? 1 ? 20 ns t ssclk data setup time to falling edge of sclk ? 40 ? ? ns t hsclk data hold time from falling edge of sclk ? 40 ? ? ns f sclk frequency of sclk ? 0 ? 8 mhz t eraseb flash erase time (block) ? ? ? 18 ms t write flash block write time ? ? ? 25 ms t dsclk3 data out delay from falling edge of sclk 3.0 ? v in ? 3.6 ? ? 85 ns t dsclk2 data out delay from falling edge of sclk 1.9 ? v in ? 3.0 ? ? 130 ns t xrst3 external reset pulse width after power-up required to enter programming mode when coming out of sleep 300 ? ? ? s t xres xres pulse length ? 300 ? ? ? s t vddwait v dd stable to wait-and-poll hold off ? 0.1 ? 1 ms t vddxres v dd stable to xres assertion delay ? 14.27 ? ? ms t poll sdata high pulse time ? 0.01 ? 200 ms t acq ?key window? time after a v dd ramp acquire event, based on 256 ilo clocks. ? 3.20 ? 19.60 ms t xresini ?key window? time after an xres event, based on 8 ilo clocks ? 98 ? 615 ? s cyrf89135 document number: 001-86331 rev. ** page 27 of 41 ac i 2 c specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 8. definition for timing for fast/standard mode on the i 2 c bus table 20. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units min max min max f scl scl clock frequency 0 100 0 400 khz t hd;sta hold time (repeated) start condition. after this period, the first clock pulse is generated 4.0 ? 0.6 ? s t low low period of the scl clock 4.7 ? 1.3 ? s t high high period of the scl clock 4.0 ? 0.6 ? s t su;sta setup time for a repeated start condition 4.7 ? 0.6 ? s t hd;dat data hold time 0 3.45 0 0.90 s t su;dat data setup time 250 ? 100 [11] ? ns t su;sto setup time for stop condition 4.0 ? 0.6 ? s t buf bus free time between a stop and start condition 4.7 ? 1.3 ? s t sp pulse width of spikes are suppressed by the input filter ? ? 0 50 ns note 11. a fast-mode i 2 c-bus device can be used in a standard mode i 2 c-bus system, but the requirement t su;dat ? 250 ns must then be met. this automatically be the case if the device does not stretch the low period of the scl signal. if such device does stretch t he low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is released. cyrf89135 document number: 001-86331 rev. ** page 28 of 41 figure 9. spi master mode 0 and 2 figure 10. spi master mode 1 and 3 table 21. spi master ac specifications symbol description conditions min typ max units f sclk sclk clock frequency v in ? ? 2.4 v vin < 2.4 v ? ? ? ? 6 3 mhz mhz dc sclk duty cycle ? ? 50 ? % t setup miso to sclk setup time vin ? 2.4 v vin < 2.4 v 60 100 ? ? ? ? ns ns t hold sclk to miso hold time ? 40 ? ? ns t out_val sclk to mosi valid time ? ? ? 40 ns t out_high mosi high time ? 40 ? ? ns 1/f sclk t low t high t out_h t hold t setup t out_su msb lsb spi master, modes 0 and 2 sclk (mode 0) sclk (mode 2) miso (input) mosi (output) 1/f sclk t high t low t out_h t hold t setup sclk (mode 1) sclk (mode 3) miso (input) mosi (output) spi master, modes 1 and 3 t out_su msb msb lsb lsb cyrf89135 document number: 001-86331 rev. ** page 29 of 41 figure 11. spi slave mode 0 and 2 figure 12. spi slave mode 1 and 3 table 22. spi slave ac specifications symbol description conditions min typ max units f sclk sclk clock frequency ? ? ? 4 mhz t low sclk low time ? 42 ? ? ns t high sclk high time ? 42 ? ? ns t setup mosi to sclk setup time ? 30 ? ? ns t hold sclk to mosi hold time ? 50 ? ? ns t ss_miso ss high to miso valid ? ? ? 153 ns t sclk_miso sclk to miso valid ? ? ? 125 ns t ss_high ss high time ? 50 ? ? ns t ss_clk time from ss low to first sclk ? 2/sclk ? ? ns t clk_ss time from last sclk to ss high ? 2/sclk ? ? ns t clk_ss t ss_high 1/f sclk t low t high t out_h t hold t setup t ss_miso t ss_clk msb lsb spi slave, modes 0 and 2 /ss sclk (mode 0) sclk (mode 2) miso (output) mosi (input) t clk_ss 1/f sclk t high t low t sclk_miso t out_h t hold t setup t ss_clk /ss sclk (mode 1) sclk (mode 3) miso (output) mosi (input) spi slave, modes 1 and 3 t ss_miso msb msb lsb lsb cyrf89135 document number: 001-86331 rev. ** page 30 of 41 electrical specifications ? rf section symbol description min typ max units test condition and notes supply voltage v in dc power supply voltage range 1.9 ? 3.6 vdc input to v in pins current consumption i dd_tx2 current consumption ? tx ? 18.5 ? ma transmit power pa2. i dd_tx12 ? 13.7 ? ma transmit power pa12. i dd_rx current consumption ? rx ? 18 ? ma i dd_idle1 current consumption ? idle ? 1.1 ? ma i dd_slpx current consumption ? sleep ? 1 ? a temperature = +25 c. using firmware sleep patch. register 27 = 0x1200, for v in 3.00 vdc only i dd_slpr ? 8 ? a temperature = +25 c; using firmware sleep patch register 27 = 0x4200. i dd_slph ? 38 ? a temperature = +70 c ?c? grade part; using firmware sleep patch register 27 = 0x4200 v ih logic input high 0.8 vin ? 1.2 vin v v il logic input low 0 ? 0.8 v i _leak_in input leakage current ? ? 10 a v oh logic output high 0.8 vin ? ? v i oh = 100 a source v ol logic output low ? ? 0.4 v i ol = 100 a sink i _leak_out output leakage current ? ? 10 a miso in tristate t _rise_out rise/fall time (spi miso) ? 8 25 ns 7 pf cap. load t _rise_in rise/fall time (spi mosi) ? ? 25 ns t r_spi clk rise, fall time (spi) ? ? 25 n s requirement for error-free register reading, writing. f _op operating frequency range 2400 ? 2482 mhz usage on-the-air is subject to local regulatory agency restrictions regarding operating frequency. v swr_i antenna port mismatch (z 0 = 50 ? ) ? <2:1 ? vswr receive mode. measured using lc matching circuit vswr _o ? <2:1 ? vswr transmit mode. measured using lc matching circuit receive section measured using lc matching circuit for ber ? 0.1% rxs base receiver sensitivity (fec off) ? ?87 ? dbm room temperature only 0-ppm crystal frequency error. rxs temp ? ?84 ? dbm over temperature; 0-ppm crystal frequency error. cyrf89135 document number: 001-86331 rev. ** page 31 of 41 rxs ppm ? ?84 ? dbm room temperature only 80-ppm total frequency error ( 40-ppm crystal frequency error, each end of rf link) rxs temp+ppm ? ?80 ? dbm over temperature; 80-ppm total frequency error ( 40-ppm crystal frequency error, each end of rf link) r xmax-sig maximum usable signal ?20 0 ? dbm room temperature only ts data (symbol) rate ? 1 ? s minimum carrier/interference ratio for ber ? 0.1%. room temperature only. ci _cochannel co-channel interference ? +9 ? db ?60-dbm desired signal ci _1 adjacent channel interference, 1-mhz offset ? +6 ? db ?60-dbm desired signal ci _2 adjacent channel interference, 2-mhz offset ? ?12 ? db ?60-dbm desired signal ci _3 adjacent channel interference, 3-mhz offset ? ?24 ? db ?67-dbm desired signal obb out-of-band blocking ? ? ?27 ? dbm 30 mhz to 12.75 ghz measured with acx bf2520 ceramic filter on ant. pin. ?67-dbm desired signal, ber ? 0.1%. room temperature only. transmit section measured using a lc matching circuit p avh rf output power ? +1 ? dbm pa0 (pa_gn = 0, reg9 = 0x1820). room temperature only p avl ? ?11.2 ? dbm pa12 (pa_gn = 12, reg9 = 0x1e20). room temperature only. txp fx2 second harmonic ? ?45 ? dbm measured using a lc matching circuit. room temperature only. txp fx3 third and higher harmonics ? ?? ?45 ? dbm measured using a lc matching circuit. room temperature only. modulation characteristics df1 avg ? 263 ? khz modulation pattern: 11110000... df2 avg ? 255 ? khz modulation pattern: 10101010... in-band spurious emission ibs_2 2-mhz offset ? ? ?20 dbm ibs_3 3-mhz offset ? ? ?30 dbm ibs_4 ? 4-mhz offset ? ?? ?30 ? dbm rf vco and pll section f step channel (step) size ? 1 ? mhz electrical specificatio ns ? rf section (continued) symbol description min typ max units test condition and notes cyrf89135 document number: 001-86331 rev. ** page 32 of 41 figure 13. power-on and re gister programming sequence after register initialization, cyrf89435 68-pin qfn is ready to transmit or receive. l 100k ssb phase noise ?75 ? dbc/hz 100-khz offset l 1m ?105 ? dbc/hz 1-mhz offset df x0 crystal oscillator frequency error ?40 ? +40 ppm relative to 12-mhz crystal reference frequency t hop rf pll settling time ? 100 150 s settle to within 30 khz of final value. autocal off. t hop_ac ? 250 350 s settle to within 30 khz of final value. autocal on. ldo voltage regulator section v do dropout voltage ? 0.17 0.3 v measured during receive state electrical specificatio ns ? rf section (continued) symbol description min typ max units test condition and notes v in rst_n brclk spi_ss clock unstable clock stable spi activity t rsu t rpw t cmin (not drawn to scale) write reg[27]= 0x4200 t vin table 23. initialization timing requirements timing parameter min max unit notes t rsu ? 30 / 150 ms 30 ms reset setup time necessary to ensure complete reset for vin=6.5mv/s, 150 ms reset setup time necessary to ensure complete reset for vin=2mv/s t rpw 1 10 s reset pulse width necessary to ensure complete reset t cmin 3 ? ms minimum recommended crystal oscillator and apll settling time t vin ? 6.5 / 2 mv/s maximum ramp time for v in , measured from 0 to 100% of final voltage. for example, if v in = 3.3 v, the max ramp time is 6.5 3.3 = 21.45 ms. if v in = 1.9 v, the max ramp time = 6.5 1.9 = 12.35 ms.reset setup time necessary to ensure complete reset for vin=6.5mv/sreset setup time necessary to ensure complete reset for vin=6.5mv/sreset setup time nece ssary to ensure complete reset for vin=6.5mv/s cyrf89135 document number: 001-86331 rev. ** page 33 of 41 figure 14. initialization flowchart table 24. spi timing requirements timing parameter min max unit notes t sss 20 ? ns setup time from assertion of spi_ss to clk edge t ssh 200 ? ns hold time required deassertion of spi_ss t sckh 20 ? ns clk minimum high time t sckl 20 ? ns clk minimum low time t sck 83 ? ns maximum clk clock is 12 mhz t ssu 10 ? ns mosi setup time t shd 10 ? ns mosi hold time t ss_su 10 ? ns before spi_ss enable, clk hold low time requirement t ss_hd 200 ? ns minimum spi inactive time t sdo ? 35 ns miso setup time, ready to read t sdo1 ? 5 ns if miso is configured as tristate, miso assertion time t sdo2 ? 250 ns if miso is configured as tristate, miso deassertion time t1 min_r50 350 ? ns when reading register 50 (fifo) t1 min 83 ? ns when writing register 50 (fifo), or reading/writing any registers other than register 50. initialize cyrf89135 at power-up mcu generates negative- going rst_n pulse wait crystal enable time initialize registers, beginning with reg[27] initialization done rst_n pulls up along with vin cyrf89135 document number: 001-86331 rev. ** page 34 of 41 packaging information this section illustrates the packaging specifications for the cy rf89135-68ltxc psoc device, along with the thermal impedances for each package. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress. com/design/mr10161 . figure 15. 68-pin qfn (8 8 1.0 mm) lt68 5.7 5.7 e-pad (sawn type) package outline, 001-09618 important notes for information on the preferred dimensions for mounting qfn packages, see the following application note at http://www.amkor.com/products/notes_papers/mlfappnote.pdf . pinned vias for thermal conduction are not required for the low power psoc device. 001-09618 *e cyrf89135 document number: 001-86331 rev. ** page 35 of 41 thermal impedances capacitance on crystal pins solder reflow specifications ta b l e 2 7 shows the solder reflow temperature limits that must not be exceeded. table 25. thermal impedances per package package typical ? ja [12] typical ? jc 68-pin qfn [13] 29 c/w 23 c/w table 26. typical package capacitance on crystal pins package package capacitance 68-pin qfn 3.3 pf table 27. solder reflow specifications package maximum peak temperature (t c ) maximum time above t c ? 5 c 68-pin qfn 240 c 260 c notes 12. t j = t a + power ? ja . 13. to achieve the thermal impedance specified for the qfn package, the center thermal pad must be soldered to the pcb ground pl ane. cyrf89135 document number: 001-86331 rev. ** page 36 of 41 development tool selection software psoc designer? at the core of the psoc development software suite is psoc designer. utilized by thousands of psoc developers, this robust software has been facilitating psoc designs for over half a decade. psoc designer is available free of charge at http://www.cypress.com . psoc programmer flexible enough to be used on the bench in development, yet suitable for factory programming, psoc programmer works either as a standalone programming application or it can operate directly from psoc designer. psoc programmer software is compatible with both psoc ice-cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com. development kits all development kits are sold at the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. psoc designer supports the advance emulation features also. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66a family cat-5 adapter mini-eval programming board 110 ~ 240 v power supply, euro-plug adapter imagecraft c compiler (registration required) issp cable 2 cy8c29466a-24pxi 28-pdip chip samples evaluation tools all evaluation tools are sold at the cypress online store. cy8ckit-002 - miniprog 3 the cy8ckit-002 - miniprog 3 kit enables the user to program psoc devices via the miniprog3 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit usb 2.0 cable to connect it to pc cy8ckit-006 psoc ? 3 lcd segment drive evaluation kit cypress?s psoc programmable system-on-chip architecture gives you the freedom to not only imagine revolutionary new products, but the capability to also get those products to market faster than anyone else.the ability to drive a 5v display on 0.5v of input and the ability to drive multiple displays on one psoc device can translate to the ultimate in design freedom, lower bom costs and new product differentiators with this easy to use evaluation kit.the kit contains: psoc 3 lcd segment drive evaluation board 9v battery 12v wall power supply miniprog3 programmer / debugger usb cable (to connect miniprog3 to the pc) kit stand quick start guide kit cd, which includes: psoc creator, psoc programmer, projects and documentation device programmers firmware needs to be downloaded to proc-emb device only at 3.3 v using miniprog3 programmer. this programmer kit can be purchased from cypress store using part#?cy8ckit-002-miniprog3?. it is small, compact programmer which connects pc via a usb 2.0 cable (provided along with cy8ckit-002? note: miniprog1 programmer should not be used as it does not support programming at 3.3 v. cyrf89135 document number: 001-86331 rev. ** page 37 of 41 ordering information the following table lists the CYRF89135-68LTXC psoc devices' key package features and ordering codes. ordering code definitions table 28. psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) capsense blocks digital i/o pins analog inputs xres pin adc 68-pin (8 8 1 mm) qfn CYRF89135-68LTXC 32 2048 0 35 35 yes no temperature range: c = commercial pb-free package type: lt = qfn package pin count: 68 = 68 pins part number: 135 = proc - embeeded family code: 89 = wireless marketing code: rf = radio frequency company id: cy = cypress rf cy 135 -68lt c x 89 cyrf89135 document number: 001-86331 rev. ** page 38 of 41 acronyms reference documents in-system serial programming (issp) protocol for 20xx6 ( an2026c ) host sourced serial programming for 20xx6 devices ( an59389 ) document conventions units of measure table 29. acronyms used in this document acronym description ac alternating current adc analog-to-digital converter api application programming interface cmos complementary metal oxide semiconductor cpu central processing unit dac digital-to-analog converter dc direct current eop end of packet fsr full scale range gpio general purpose input/output gui graphical user interface i 2 c inter-integrated circuit ice in-circuit emulator idac digital analog converter current ilo internal low speed oscillator imo internal main oscillator i/o input/output issp in-system serial programming lcd liquid crystal display ldo low dropout (regulator) lsb least-significant bit lvd low voltage detect mcu micro-controller unit mips mega instructions per second miso master in slave out mosi master out slave in msb most-significant bit ocd on-chip debugger por power on reset ppor precision power on reset psrr power supply rejection ratio pwrsys power system psoc ? programmable system-on-chip slimo slow internal main oscillator sram static random access memory snr signal to noise ratio qfn quad flat no-lead scl serial i2c clock sda serial i2c data sdata serial issp data spi serial peripheral interface ss slave select ssop shrink small outline package tc test controller usb universal serial bus wlcsp wafer level chip scale package xtal crystal table 30. units of measure symbol unit of measure c degree celsius db decibels ff femtofarad g gram hz hertz kb 1024 bytes kbit 1024 bits khz kilohertz ksps kilo samples per second k ? kilohm mhz megahertz m ? megaohm ? a microampere ? f microfarad ? h microhenry ? s microsecond ? w microwatt ma milliampere ms millisecond mv millivolt na nanoampere nf nanofarad ns nanosecond nv nanovolt w ohm pa picoampere pf picofarad pp peak-to-peak ppm parts per million ps picosecond sps samples per second s sigma: one standard deviation v volt w watt cyrf89135 document number: 001-86331 rev. ** page 39 of 41 numeric naming hexadecimal numbers are represented with all letters in uppercas e with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pr efix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). nu mbers not indicated by an ?h?, ?b?, or 0x are decimal. glossary crosspoint connection connection between any gpio combination via analog multiplexer bus. differential non-linearity ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one lsb apart. differential non-linearity is a measure of the worst case deviation from the ideal 1 lsb step. hold time hold time is the time following a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct. i 2 c it is a serial multi-master bus used to connect low speed peripherals to mcu. integral nonlinearity it is a term describing the maximum deviation between the ideal output of a dac/adc and the actual output level. latch-up current current at which the latch-up test is conducted according to jesd78 standard (at 125 degree celsius) power supply rejection ratio (psrr) the psrr is defined as th e ratio of the change in supply voltage to the corresponding change in output voltage of the device. scan the conversion of all sensor capacitances to digital values. setup time period r equired to prepare a device, machine, proc ess, or system for it to be ready to function. signal-to-noise ratio the ratio between a capacitive finger signal and system noise. spi serial peripheral interface is a synchronous serial data link standard. cyrf89135 document number: 001-86331 rev. ** page 40 of 41 document history page document title: cyrf89135, proc? - embedded document number: 001-86331 revision ecn orig. of change submission date description of change ** 3924802 akhl 04/03/2013 new silicon document. document number: 001-86331 rev. ** revised april 3, 2013 page 41 of 41 psoc designer? is a trademark and psoc? and capsense? are registered trademarks of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cyrf89135 ? cypress semiconductor corporation, 2013. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 |
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